4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq) __attribute__((always_inline));
87 static inline uint32_t
88 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
89 __attribute__((always_inline));
92 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, uint32_t *rss_hash)
94 __attribute__((always_inline));
96 static inline uint32_t
97 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
98 __attribute__((always_inline));
103 * Verify or set magic value in CQE.
112 check_cqe_seen(volatile struct mlx5_cqe *cqe)
114 static const uint8_t magic[] = "seen";
115 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
119 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
120 if (!ret || (*buf)[i] != magic[i]) {
122 (*buf)[i] = magic[i];
130 * Check whether CQE is valid.
135 * Size of completion queue.
140 * 0 on success, 1 on failure.
143 check_cqe(volatile struct mlx5_cqe *cqe,
144 unsigned int cqes_n, const uint16_t ci)
146 uint16_t idx = ci & cqes_n;
147 uint8_t op_own = cqe->op_own;
148 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
149 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
151 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
152 return 1; /* No CQE. */
154 if ((op_code == MLX5_CQE_RESP_ERR) ||
155 (op_code == MLX5_CQE_REQ_ERR)) {
156 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
157 uint8_t syndrome = err_cqe->syndrome;
159 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
160 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
162 if (!check_cqe_seen(cqe))
163 ERROR("unexpected CQE error %u (0x%02x)"
165 op_code, op_code, syndrome);
167 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
168 (op_code != MLX5_CQE_REQ)) {
169 if (!check_cqe_seen(cqe))
170 ERROR("unexpected CQE opcode %u (0x%02x)",
179 * Return the address of the WQE.
182 * Pointer to TX queue structure.
184 * WQE consumer index.
189 static inline uintptr_t *
190 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
192 ci &= ((1 << txq->wqe_n) - 1);
193 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
197 * Manage TX completions.
199 * When sending a burst, mlx5_tx_burst() posts several WRs.
202 * Pointer to TX queue structure.
205 txq_complete(struct txq *txq)
207 const unsigned int elts_n = 1 << txq->elts_n;
208 const unsigned int cqe_n = 1 << txq->cqe_n;
209 const unsigned int cqe_cnt = cqe_n - 1;
210 uint16_t elts_free = txq->elts_tail;
212 uint16_t cq_ci = txq->cq_ci;
213 volatile struct mlx5_cqe *cqe = NULL;
214 volatile struct mlx5_wqe_ctrl *ctrl;
217 volatile struct mlx5_cqe *tmp;
219 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
220 if (check_cqe(tmp, cqe_n, cq_ci))
224 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
225 if (!check_cqe_seen(cqe))
226 ERROR("unexpected compressed CQE, TX stopped");
229 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
230 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
231 if (!check_cqe_seen(cqe))
232 ERROR("unexpected error CQE, TX stopped");
238 if (unlikely(cqe == NULL))
240 ctrl = (volatile struct mlx5_wqe_ctrl *)
241 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
242 elts_tail = ctrl->ctrl3;
243 assert(elts_tail < (1 << txq->wqe_n));
245 while (elts_free != elts_tail) {
246 struct rte_mbuf *elt = (*txq->elts)[elts_free];
247 unsigned int elts_free_next =
248 (elts_free + 1) & (elts_n - 1);
249 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
253 memset(&(*txq->elts)[elts_free],
255 sizeof((*txq->elts)[elts_free]));
257 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
258 /* Only one segment needs to be freed. */
259 rte_pktmbuf_free_seg(elt);
260 elts_free = elts_free_next;
263 txq->elts_tail = elts_tail;
264 /* Update the consumer index. */
266 *txq->cq_db = htonl(cq_ci);
270 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
271 * the cloned mbuf is allocated is returned instead.
277 * Memory pool where data is located for given mbuf.
279 static struct rte_mempool *
280 txq_mb2mp(struct rte_mbuf *buf)
282 if (unlikely(RTE_MBUF_INDIRECT(buf)))
283 return rte_mbuf_from_indirect(buf)->pool;
288 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
289 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
290 * remove an entry first.
293 * Pointer to TX queue structure.
295 * Memory Pool for which a Memory Region lkey must be returned.
298 * mr->lkey on success, (uint32_t)-1 on failure.
300 static inline uint32_t
301 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
304 uint32_t lkey = (uint32_t)-1;
306 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
307 if (unlikely(txq->mp2mr[i].mp == NULL)) {
308 /* Unknown MP, add a new MR for it. */
311 if (txq->mp2mr[i].mp == mp) {
312 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
313 assert(htonl(txq->mp2mr[i].mr->lkey) ==
315 lkey = txq->mp2mr[i].lkey;
319 if (unlikely(lkey == (uint32_t)-1))
320 lkey = txq_mp2mr_reg(txq, mp, i);
325 * Ring TX queue doorbell.
328 * Pointer to TX queue structure.
331 mlx5_tx_dbrec(struct txq *txq)
333 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
335 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
336 htonl(txq->qp_num_8s),
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
344 memcpy(dst, (uint8_t *)data, 16);
345 txq->bf_offset ^= (1 << txq->bf_buf_size);
352 * Pointer to TX queue structure.
354 * CQE consumer index.
357 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
359 volatile struct mlx5_cqe *cqe;
361 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
366 * DPDK callback for TX.
369 * Generic pointer to TX queue structure.
371 * Packets to transmit.
373 * Number of packets in array.
376 * Number of packets successfully transmitted (<= pkts_n).
379 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
381 struct txq *txq = (struct txq *)dpdk_txq;
382 uint16_t elts_head = txq->elts_head;
383 const unsigned int elts_n = 1 << txq->elts_n;
388 volatile struct mlx5_wqe_v *wqe = NULL;
389 unsigned int segs_n = 0;
390 struct rte_mbuf *buf = NULL;
393 if (unlikely(!pkts_n))
395 /* Prefetch first packet cacheline. */
396 tx_prefetch_cqe(txq, txq->cq_ci);
397 tx_prefetch_cqe(txq, txq->cq_ci + 1);
398 rte_prefetch0(*pkts);
399 /* Start processing. */
401 max = (elts_n - (elts_head - txq->elts_tail));
405 volatile rte_v128u32_t *dseg = NULL;
410 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
412 uint8_t cs_flags = 0;
413 #ifdef MLX5_PMD_SOFT_COUNTERS
414 uint32_t total_length = 0;
419 segs_n = buf->nb_segs;
421 * Make sure there is enough room to store this packet and
422 * that one ring entry remains unused.
425 if (max < segs_n + 1)
431 wqe = (volatile struct mlx5_wqe_v *)
432 tx_mlx5_wqe(txq, txq->wqe_ci);
433 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
435 rte_prefetch0(*pkts);
436 addr = rte_pktmbuf_mtod(buf, uintptr_t);
437 length = DATA_LEN(buf);
438 ehdr = (((uint8_t *)addr)[1] << 8) |
439 ((uint8_t *)addr)[0];
440 #ifdef MLX5_PMD_SOFT_COUNTERS
441 total_length = length;
443 assert(length >= MLX5_WQE_DWORD_SIZE);
444 /* Update element. */
445 (*txq->elts)[elts_head] = buf;
446 elts_head = (elts_head + 1) & (elts_n - 1);
447 /* Prefetch next buffer data. */
449 volatile void *pkt_addr;
451 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
452 rte_prefetch0(pkt_addr);
454 /* Should we enable HW CKSUM offload */
456 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
457 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
459 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
461 * Start by copying the Ethernet header minus the first two
462 * bytes which will be appended at the end of the Ethernet
465 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
466 length -= MLX5_WQE_DWORD_SIZE;
467 addr += MLX5_WQE_DWORD_SIZE;
468 /* Replace the Ethernet type by the VLAN if necessary. */
469 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
470 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
472 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
474 &vlan, sizeof(vlan));
475 addr -= sizeof(vlan);
476 length += sizeof(vlan);
478 /* Inline if enough room. */
479 if (txq->max_inline != 0) {
480 uintptr_t end = (uintptr_t)
481 (((uintptr_t)txq->wqes) +
482 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
483 uint16_t max_inline =
484 txq->max_inline * RTE_CACHE_LINE_SIZE;
488 * raw starts two bytes before the boundary to
489 * continue the above copy of packet data.
491 raw += MLX5_WQE_DWORD_SIZE - 2;
492 room = end - (uintptr_t)raw;
493 if (room > max_inline) {
494 uintptr_t addr_end = (addr + max_inline) &
495 ~(RTE_CACHE_LINE_SIZE - 1);
496 uint16_t copy_b = ((addr_end - addr) > length) ?
500 rte_memcpy((void *)raw, (void *)addr, copy_b);
503 pkt_inline_sz += copy_b;
505 assert(addr <= addr_end);
508 * 2 DWORDs consumed by the WQE header + 1 DSEG +
509 * the size of the inline part of the packet.
511 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
513 dseg = (volatile rte_v128u32_t *)
515 (ds * MLX5_WQE_DWORD_SIZE));
516 if ((uintptr_t)dseg >= end)
517 dseg = (volatile rte_v128u32_t *)
520 } else if (!segs_n) {
527 * No inline has been done in the packet, only the
528 * Ethernet Header as been stored.
530 dseg = (volatile rte_v128u32_t *)
531 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
534 /* Add the remaining packet as a simple ds. */
535 naddr = htonll(addr);
536 *dseg = (rte_v128u32_t){
538 txq_mp2mr(txq, txq_mb2mp(buf)),
551 * Spill on next WQE when the current one does not have
552 * enough room left. Size of WQE must a be a multiple
553 * of data segment size.
555 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
556 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
557 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
558 ((1 << txq->wqe_n) - 1);
560 dseg = (volatile rte_v128u32_t *)
562 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
569 length = DATA_LEN(buf);
570 #ifdef MLX5_PMD_SOFT_COUNTERS
571 total_length += length;
573 /* Store segment information. */
574 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
575 *dseg = (rte_v128u32_t){
577 txq_mp2mr(txq, txq_mb2mp(buf)),
581 (*txq->elts)[elts_head] = buf;
582 elts_head = (elts_head + 1) & (elts_n - 1);
591 /* Initialize known and common part of the WQE structure. */
592 wqe->ctrl = (rte_v128u32_t){
593 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
594 htonl(txq->qp_num_8s | ds),
598 wqe->eseg = (rte_v128u32_t){
602 (ehdr << 16) | htons(pkt_inline_sz),
604 txq->wqe_ci += (ds + 3) / 4;
605 #ifdef MLX5_PMD_SOFT_COUNTERS
606 /* Increment sent bytes counter. */
607 txq->stats.obytes += total_length;
610 /* Take a shortcut if nothing must be sent. */
611 if (unlikely(i == 0))
613 /* Check whether completion threshold has been reached. */
614 comp = txq->elts_comp + i + j;
615 if (comp >= MLX5_TX_COMP_THRESH) {
616 volatile struct mlx5_wqe_ctrl *w =
617 (volatile struct mlx5_wqe_ctrl *)wqe;
619 /* Request completion on last WQE. */
621 /* Save elts_head in unused "immediate" field of WQE. */
622 w->ctrl3 = elts_head;
625 txq->elts_comp = comp;
627 #ifdef MLX5_PMD_SOFT_COUNTERS
628 /* Increment sent packets counter. */
629 txq->stats.opackets += i;
631 /* Ring QP doorbell. */
633 txq->elts_head = elts_head;
638 * Open a MPW session.
641 * Pointer to TX queue structure.
643 * Pointer to MPW session structure.
648 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
650 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
651 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
652 (volatile struct mlx5_wqe_data_seg (*)[])
653 tx_mlx5_wqe(txq, idx + 1);
655 mpw->state = MLX5_MPW_STATE_OPENED;
659 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
660 mpw->wqe->eseg.mss = htons(length);
661 mpw->wqe->eseg.inline_hdr_sz = 0;
662 mpw->wqe->eseg.rsvd0 = 0;
663 mpw->wqe->eseg.rsvd1 = 0;
664 mpw->wqe->eseg.rsvd2 = 0;
665 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
666 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
667 mpw->wqe->ctrl[2] = 0;
668 mpw->wqe->ctrl[3] = 0;
669 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
670 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
671 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
672 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
673 mpw->data.dseg[2] = &(*dseg)[0];
674 mpw->data.dseg[3] = &(*dseg)[1];
675 mpw->data.dseg[4] = &(*dseg)[2];
679 * Close a MPW session.
682 * Pointer to TX queue structure.
684 * Pointer to MPW session structure.
687 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
689 unsigned int num = mpw->pkts_n;
692 * Store size in multiple of 16 bytes. Control and Ethernet segments
695 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
696 mpw->state = MLX5_MPW_STATE_CLOSED;
701 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
702 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
706 * DPDK callback for TX with MPW support.
709 * Generic pointer to TX queue structure.
711 * Packets to transmit.
713 * Number of packets in array.
716 * Number of packets successfully transmitted (<= pkts_n).
719 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
721 struct txq *txq = (struct txq *)dpdk_txq;
722 uint16_t elts_head = txq->elts_head;
723 const unsigned int elts_n = 1 << txq->elts_n;
728 struct mlx5_mpw mpw = {
729 .state = MLX5_MPW_STATE_CLOSED,
732 if (unlikely(!pkts_n))
734 /* Prefetch first packet cacheline. */
735 tx_prefetch_cqe(txq, txq->cq_ci);
736 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
737 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
738 /* Start processing. */
740 max = (elts_n - (elts_head - txq->elts_tail));
744 struct rte_mbuf *buf = *(pkts++);
745 unsigned int elts_head_next;
747 unsigned int segs_n = buf->nb_segs;
748 uint32_t cs_flags = 0;
751 * Make sure there is enough room to store this packet and
752 * that one ring entry remains unused.
755 if (max < segs_n + 1)
757 /* Do not bother with large packets MPW cannot handle. */
758 if (segs_n > MLX5_MPW_DSEG_MAX)
762 /* Should we enable HW CKSUM offload */
764 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
765 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
766 /* Retrieve packet information. */
767 length = PKT_LEN(buf);
769 /* Start new session if packet differs. */
770 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
771 ((mpw.len != length) ||
773 (mpw.wqe->eseg.cs_flags != cs_flags)))
774 mlx5_mpw_close(txq, &mpw);
775 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
776 mlx5_mpw_new(txq, &mpw, length);
777 mpw.wqe->eseg.cs_flags = cs_flags;
779 /* Multi-segment packets must be alone in their MPW. */
780 assert((segs_n == 1) || (mpw.pkts_n == 0));
781 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
785 volatile struct mlx5_wqe_data_seg *dseg;
788 elts_head_next = (elts_head + 1) & (elts_n - 1);
790 (*txq->elts)[elts_head] = buf;
791 dseg = mpw.data.dseg[mpw.pkts_n];
792 addr = rte_pktmbuf_mtod(buf, uintptr_t);
793 *dseg = (struct mlx5_wqe_data_seg){
794 .byte_count = htonl(DATA_LEN(buf)),
795 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
796 .addr = htonll(addr),
798 elts_head = elts_head_next;
799 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
800 length += DATA_LEN(buf);
806 assert(length == mpw.len);
807 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
808 mlx5_mpw_close(txq, &mpw);
809 elts_head = elts_head_next;
810 #ifdef MLX5_PMD_SOFT_COUNTERS
811 /* Increment sent bytes counter. */
812 txq->stats.obytes += length;
816 /* Take a shortcut if nothing must be sent. */
817 if (unlikely(i == 0))
819 /* Check whether completion threshold has been reached. */
820 /* "j" includes both packets and segments. */
821 comp = txq->elts_comp + j;
822 if (comp >= MLX5_TX_COMP_THRESH) {
823 volatile struct mlx5_wqe *wqe = mpw.wqe;
825 /* Request completion on last WQE. */
826 wqe->ctrl[2] = htonl(8);
827 /* Save elts_head in unused "immediate" field of WQE. */
828 wqe->ctrl[3] = elts_head;
831 txq->elts_comp = comp;
833 #ifdef MLX5_PMD_SOFT_COUNTERS
834 /* Increment sent packets counter. */
835 txq->stats.opackets += i;
837 /* Ring QP doorbell. */
838 if (mpw.state == MLX5_MPW_STATE_OPENED)
839 mlx5_mpw_close(txq, &mpw);
841 txq->elts_head = elts_head;
846 * Open a MPW inline session.
849 * Pointer to TX queue structure.
851 * Pointer to MPW session structure.
856 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
858 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
859 struct mlx5_wqe_inl_small *inl;
861 mpw->state = MLX5_MPW_INL_STATE_OPENED;
865 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
866 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
869 mpw->wqe->ctrl[2] = 0;
870 mpw->wqe->ctrl[3] = 0;
871 mpw->wqe->eseg.mss = htons(length);
872 mpw->wqe->eseg.inline_hdr_sz = 0;
873 mpw->wqe->eseg.cs_flags = 0;
874 mpw->wqe->eseg.rsvd0 = 0;
875 mpw->wqe->eseg.rsvd1 = 0;
876 mpw->wqe->eseg.rsvd2 = 0;
877 inl = (struct mlx5_wqe_inl_small *)
878 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
879 mpw->data.raw = (uint8_t *)&inl->raw;
883 * Close a MPW inline session.
886 * Pointer to TX queue structure.
888 * Pointer to MPW session structure.
891 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
894 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
895 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
897 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
899 * Store size in multiple of 16 bytes. Control and Ethernet segments
902 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
903 mpw->state = MLX5_MPW_STATE_CLOSED;
904 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
905 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
909 * DPDK callback for TX with MPW inline support.
912 * Generic pointer to TX queue structure.
914 * Packets to transmit.
916 * Number of packets in array.
919 * Number of packets successfully transmitted (<= pkts_n).
922 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
925 struct txq *txq = (struct txq *)dpdk_txq;
926 uint16_t elts_head = txq->elts_head;
927 const unsigned int elts_n = 1 << txq->elts_n;
932 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
933 struct mlx5_mpw mpw = {
934 .state = MLX5_MPW_STATE_CLOSED,
937 if (unlikely(!pkts_n))
939 /* Prefetch first packet cacheline. */
940 tx_prefetch_cqe(txq, txq->cq_ci);
941 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
942 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
943 /* Start processing. */
945 max = (elts_n - (elts_head - txq->elts_tail));
949 struct rte_mbuf *buf = *(pkts++);
950 unsigned int elts_head_next;
953 unsigned int segs_n = buf->nb_segs;
954 uint32_t cs_flags = 0;
957 * Make sure there is enough room to store this packet and
958 * that one ring entry remains unused.
961 if (max < segs_n + 1)
963 /* Do not bother with large packets MPW cannot handle. */
964 if (segs_n > MLX5_MPW_DSEG_MAX)
968 /* Should we enable HW CKSUM offload */
970 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
971 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
972 /* Retrieve packet information. */
973 length = PKT_LEN(buf);
974 /* Start new session if packet differs. */
975 if (mpw.state == MLX5_MPW_STATE_OPENED) {
976 if ((mpw.len != length) ||
978 (mpw.wqe->eseg.cs_flags != cs_flags))
979 mlx5_mpw_close(txq, &mpw);
980 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
981 if ((mpw.len != length) ||
983 (length > inline_room) ||
984 (mpw.wqe->eseg.cs_flags != cs_flags)) {
985 mlx5_mpw_inline_close(txq, &mpw);
987 txq->max_inline * RTE_CACHE_LINE_SIZE;
990 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
992 (length > inline_room)) {
993 mlx5_mpw_new(txq, &mpw, length);
994 mpw.wqe->eseg.cs_flags = cs_flags;
996 mlx5_mpw_inline_new(txq, &mpw, length);
997 mpw.wqe->eseg.cs_flags = cs_flags;
1000 /* Multi-segment packets must be alone in their MPW. */
1001 assert((segs_n == 1) || (mpw.pkts_n == 0));
1002 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1003 assert(inline_room ==
1004 txq->max_inline * RTE_CACHE_LINE_SIZE);
1005 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1009 volatile struct mlx5_wqe_data_seg *dseg;
1012 (elts_head + 1) & (elts_n - 1);
1014 (*txq->elts)[elts_head] = buf;
1015 dseg = mpw.data.dseg[mpw.pkts_n];
1016 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1017 *dseg = (struct mlx5_wqe_data_seg){
1018 .byte_count = htonl(DATA_LEN(buf)),
1019 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1020 .addr = htonll(addr),
1022 elts_head = elts_head_next;
1023 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1024 length += DATA_LEN(buf);
1030 assert(length == mpw.len);
1031 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1032 mlx5_mpw_close(txq, &mpw);
1036 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1037 assert(length <= inline_room);
1038 assert(length == DATA_LEN(buf));
1039 elts_head_next = (elts_head + 1) & (elts_n - 1);
1040 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1041 (*txq->elts)[elts_head] = buf;
1042 /* Maximum number of bytes before wrapping. */
1043 max = ((((uintptr_t)(txq->wqes)) +
1046 (uintptr_t)mpw.data.raw);
1048 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1051 mpw.data.raw = (volatile void *)txq->wqes;
1052 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1053 (void *)(addr + max),
1055 mpw.data.raw += length - max;
1057 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1060 mpw.data.raw += length;
1062 if ((uintptr_t)mpw.data.raw ==
1063 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1064 mpw.data.raw = (volatile void *)txq->wqes;
1067 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1068 mlx5_mpw_inline_close(txq, &mpw);
1070 txq->max_inline * RTE_CACHE_LINE_SIZE;
1072 inline_room -= length;
1075 mpw.total_len += length;
1076 elts_head = elts_head_next;
1077 #ifdef MLX5_PMD_SOFT_COUNTERS
1078 /* Increment sent bytes counter. */
1079 txq->stats.obytes += length;
1083 /* Take a shortcut if nothing must be sent. */
1084 if (unlikely(i == 0))
1086 /* Check whether completion threshold has been reached. */
1087 /* "j" includes both packets and segments. */
1088 comp = txq->elts_comp + j;
1089 if (comp >= MLX5_TX_COMP_THRESH) {
1090 volatile struct mlx5_wqe *wqe = mpw.wqe;
1092 /* Request completion on last WQE. */
1093 wqe->ctrl[2] = htonl(8);
1094 /* Save elts_head in unused "immediate" field of WQE. */
1095 wqe->ctrl[3] = elts_head;
1098 txq->elts_comp = comp;
1100 #ifdef MLX5_PMD_SOFT_COUNTERS
1101 /* Increment sent packets counter. */
1102 txq->stats.opackets += i;
1104 /* Ring QP doorbell. */
1105 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1106 mlx5_mpw_inline_close(txq, &mpw);
1107 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1108 mlx5_mpw_close(txq, &mpw);
1110 txq->elts_head = elts_head;
1115 * Translate RX completion flags to packet type.
1120 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1123 * Packet type for struct rte_mbuf.
1125 static inline uint32_t
1126 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1129 uint8_t flags = cqe->l4_hdr_type_etc;
1131 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1134 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1135 RTE_PTYPE_L3_IPV4) |
1137 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1138 RTE_PTYPE_L3_IPV6) |
1140 MLX5_CQE_RX_IPV4_PACKET,
1141 RTE_PTYPE_INNER_L3_IPV4) |
1143 MLX5_CQE_RX_IPV6_PACKET,
1144 RTE_PTYPE_INNER_L3_IPV6);
1148 MLX5_CQE_L3_HDR_TYPE_IPV6,
1149 RTE_PTYPE_L3_IPV6) |
1151 MLX5_CQE_L3_HDR_TYPE_IPV4,
1157 * Get size of the next packet for a given CQE. For compressed CQEs, the
1158 * consumer index is updated only once all packets of the current one have
1162 * Pointer to RX queue.
1165 * @param[out] rss_hash
1166 * Packet RSS Hash result.
1169 * Packet size in bytes (0 if there is none), -1 in case of completion
1173 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1174 uint16_t cqe_cnt, uint32_t *rss_hash)
1176 struct rxq_zip *zip = &rxq->zip;
1177 uint16_t cqe_n = cqe_cnt + 1;
1180 /* Process compressed data in the CQE and mini arrays. */
1182 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1183 (volatile struct mlx5_mini_cqe8 (*)[8])
1184 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1186 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1187 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1188 if ((++zip->ai & 7) == 0) {
1190 * Increment consumer index to skip the number of
1191 * CQEs consumed. Hardware leaves holes in the CQ
1192 * ring for software use.
1197 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1198 uint16_t idx = rxq->cq_ci + 1;
1199 uint16_t end = zip->cq_ci;
1201 while (idx != end) {
1202 (*rxq->cqes)[idx & cqe_cnt].op_own =
1203 MLX5_CQE_INVALIDATE;
1206 rxq->cq_ci = zip->cq_ci;
1209 /* No compressed data, get next CQE and verify if it is compressed. */
1214 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1215 if (unlikely(ret == 1))
1218 op_own = cqe->op_own;
1219 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1220 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1221 (volatile struct mlx5_mini_cqe8 (*)[8])
1222 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1225 /* Fix endianness. */
1226 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1228 * Current mini array position is the one returned by
1231 * If completion comprises several mini arrays, as a
1232 * special case the second one is located 7 CQEs after
1233 * the initial CQE instead of 8 for subsequent ones.
1235 zip->ca = rxq->cq_ci & cqe_cnt;
1236 zip->na = zip->ca + 7;
1237 /* Compute the next non compressed CQE. */
1239 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1240 /* Get packet size to return. */
1241 len = ntohl((*mc)[0].byte_cnt);
1242 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1245 len = ntohl(cqe->byte_cnt);
1246 *rss_hash = ntohl(cqe->rx_hash_res);
1248 /* Error while receiving packet. */
1249 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1256 * Translate RX completion flags to offload flags.
1259 * Pointer to RX queue structure.
1264 * Offload flags (ol_flags) for struct rte_mbuf.
1266 static inline uint32_t
1267 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1269 uint32_t ol_flags = 0;
1270 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1271 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1273 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1274 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1275 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1277 PKT_RX_IP_CKSUM_GOOD);
1278 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1279 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1280 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1281 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1282 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1284 PKT_RX_L4_CKSUM_GOOD);
1285 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1287 TRANSPOSE(cqe->l4_hdr_type_etc,
1288 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1289 PKT_RX_IP_CKSUM_GOOD) |
1290 TRANSPOSE(cqe->l4_hdr_type_etc,
1291 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1292 PKT_RX_L4_CKSUM_GOOD);
1297 * DPDK callback for RX.
1300 * Generic pointer to RX queue structure.
1302 * Array to store received packets.
1304 * Maximum number of packets in array.
1307 * Number of packets successfully received (<= pkts_n).
1310 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1312 struct rxq *rxq = dpdk_rxq;
1313 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1314 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1315 const unsigned int sges_n = rxq->sges_n;
1316 struct rte_mbuf *pkt = NULL;
1317 struct rte_mbuf *seg = NULL;
1318 volatile struct mlx5_cqe *cqe =
1319 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1321 unsigned int rq_ci = rxq->rq_ci << sges_n;
1322 int len; /* keep its value across iterations. */
1325 unsigned int idx = rq_ci & wqe_cnt;
1326 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1327 struct rte_mbuf *rep = (*rxq->elts)[idx];
1328 uint32_t rss_hash_res = 0;
1336 rep = rte_mbuf_raw_alloc(rxq->mp);
1337 if (unlikely(rep == NULL)) {
1338 ++rxq->stats.rx_nombuf;
1341 * no buffers before we even started,
1342 * bail out silently.
1346 while (pkt != seg) {
1347 assert(pkt != (*rxq->elts)[idx]);
1349 rte_mbuf_refcnt_set(pkt, 0);
1350 __rte_mbuf_raw_free(pkt);
1356 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1357 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1360 rte_mbuf_refcnt_set(rep, 0);
1361 __rte_mbuf_raw_free(rep);
1364 if (unlikely(len == -1)) {
1365 /* RX error, packet is likely too large. */
1366 rte_mbuf_refcnt_set(rep, 0);
1367 __rte_mbuf_raw_free(rep);
1368 ++rxq->stats.idropped;
1372 assert(len >= (rxq->crc_present << 2));
1373 /* Update packet information. */
1374 pkt->packet_type = 0;
1376 if (rss_hash_res && rxq->rss_hash) {
1377 pkt->hash.rss = rss_hash_res;
1378 pkt->ol_flags = PKT_RX_RSS_HASH;
1381 ((cqe->sop_drop_qpn !=
1382 htonl(MLX5_FLOW_MARK_INVALID)) ||
1383 (cqe->sop_drop_qpn !=
1384 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1386 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1387 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1388 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1390 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1394 rxq_cq_to_pkt_type(cqe);
1396 rxq_cq_to_ol_flags(rxq, cqe);
1398 if (cqe->l4_hdr_type_etc &
1399 MLX5_CQE_VLAN_STRIPPED) {
1400 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1401 PKT_RX_VLAN_STRIPPED;
1402 pkt->vlan_tci = ntohs(cqe->vlan_info);
1404 if (rxq->crc_present)
1405 len -= ETHER_CRC_LEN;
1409 DATA_LEN(rep) = DATA_LEN(seg);
1410 PKT_LEN(rep) = PKT_LEN(seg);
1411 SET_DATA_OFF(rep, DATA_OFF(seg));
1412 NB_SEGS(rep) = NB_SEGS(seg);
1413 PORT(rep) = PORT(seg);
1415 (*rxq->elts)[idx] = rep;
1417 * Fill NIC descriptor with the new buffer. The lkey and size
1418 * of the buffers are already known, only the buffer address
1421 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1422 if (len > DATA_LEN(seg)) {
1423 len -= DATA_LEN(seg);
1428 DATA_LEN(seg) = len;
1429 #ifdef MLX5_PMD_SOFT_COUNTERS
1430 /* Increment bytes counter. */
1431 rxq->stats.ibytes += PKT_LEN(pkt);
1433 /* Return packet. */
1439 /* Align consumer index to the next stride. */
1444 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1446 /* Update the consumer index. */
1447 rxq->rq_ci = rq_ci >> sges_n;
1449 *rxq->cq_db = htonl(rxq->cq_ci);
1451 *rxq->rq_db = htonl(rxq->rq_ci);
1452 #ifdef MLX5_PMD_SOFT_COUNTERS
1453 /* Increment packets counter. */
1454 rxq->stats.ipackets += i;
1460 * Dummy DPDK callback for TX.
1462 * This function is used to temporarily replace the real callback during
1463 * unsafe control operations on the queue, or in case of error.
1466 * Generic pointer to TX queue structure.
1468 * Packets to transmit.
1470 * Number of packets in array.
1473 * Number of packets successfully transmitted (<= pkts_n).
1476 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1485 * Dummy DPDK callback for RX.
1487 * This function is used to temporarily replace the real callback during
1488 * unsafe control operations on the queue, or in case of error.
1491 * Generic pointer to RX queue structure.
1493 * Array to store received packets.
1495 * Maximum number of packets in array.
1498 * Number of packets successfully received (<= pkts_n).
1501 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)