4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
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15 * the documentation and/or other materials provided with the
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
72 static __rte_always_inline int
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci);
76 static __rte_always_inline void
77 txq_complete(struct txq *txq);
79 static __rte_always_inline uint32_t
80 txq_mp2mr(struct txq *txq, struct rte_mempool *mp);
82 static __rte_always_inline void
83 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe);
85 static __rte_always_inline uint32_t
86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
88 static __rte_always_inline int
89 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
90 uint16_t cqe_cnt, uint32_t *rss_hash);
92 static __rte_always_inline uint32_t
93 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
98 * Verify or set magic value in CQE.
107 check_cqe_seen(volatile struct mlx5_cqe *cqe)
109 static const uint8_t magic[] = "seen";
110 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
114 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
115 if (!ret || (*buf)[i] != magic[i]) {
117 (*buf)[i] = magic[i];
125 * Check whether CQE is valid.
130 * Size of completion queue.
135 * 0 on success, 1 on failure.
138 check_cqe(volatile struct mlx5_cqe *cqe,
139 unsigned int cqes_n, const uint16_t ci)
141 uint16_t idx = ci & cqes_n;
142 uint8_t op_own = cqe->op_own;
143 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
144 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
146 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
147 return 1; /* No CQE. */
149 if ((op_code == MLX5_CQE_RESP_ERR) ||
150 (op_code == MLX5_CQE_REQ_ERR)) {
151 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
152 uint8_t syndrome = err_cqe->syndrome;
154 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
155 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
157 if (!check_cqe_seen(cqe))
158 ERROR("unexpected CQE error %u (0x%02x)"
160 op_code, op_code, syndrome);
162 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
163 (op_code != MLX5_CQE_REQ)) {
164 if (!check_cqe_seen(cqe))
165 ERROR("unexpected CQE opcode %u (0x%02x)",
174 * Return the address of the WQE.
177 * Pointer to TX queue structure.
179 * WQE consumer index.
184 static inline uintptr_t *
185 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
187 ci &= ((1 << txq->wqe_n) - 1);
188 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
192 * Return the size of tailroom of WQ.
195 * Pointer to TX queue structure.
197 * Pointer to tail of WQ.
203 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
206 tailroom = (uintptr_t)(txq->wqes) +
207 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
213 * Copy data to tailroom of circular queue.
216 * Pointer to destination.
220 * Number of bytes to copy.
222 * Pointer to head of queue.
224 * Size of tailroom from dst.
227 * Pointer after copied data.
230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
231 void *base, size_t tailroom)
236 rte_memcpy(dst, src, tailroom);
237 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
239 ret = (uint8_t *)base + n - tailroom;
241 rte_memcpy(dst, src, n);
242 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
248 * Manage TX completions.
250 * When sending a burst, mlx5_tx_burst() posts several WRs.
253 * Pointer to TX queue structure.
256 txq_complete(struct txq *txq)
258 const unsigned int elts_n = 1 << txq->elts_n;
259 const unsigned int cqe_n = 1 << txq->cqe_n;
260 const unsigned int cqe_cnt = cqe_n - 1;
261 uint16_t elts_free = txq->elts_tail;
263 uint16_t cq_ci = txq->cq_ci;
264 volatile struct mlx5_cqe *cqe = NULL;
265 volatile struct mlx5_wqe_ctrl *ctrl;
268 volatile struct mlx5_cqe *tmp;
270 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
271 if (check_cqe(tmp, cqe_n, cq_ci))
275 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
276 if (!check_cqe_seen(cqe))
277 ERROR("unexpected compressed CQE, TX stopped");
280 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
281 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
282 if (!check_cqe_seen(cqe))
283 ERROR("unexpected error CQE, TX stopped");
289 if (unlikely(cqe == NULL))
291 txq->wqe_pi = ntohs(cqe->wqe_counter);
292 ctrl = (volatile struct mlx5_wqe_ctrl *)
293 tx_mlx5_wqe(txq, txq->wqe_pi);
294 elts_tail = ctrl->ctrl3;
295 assert(elts_tail < (1 << txq->wqe_n));
297 while (elts_free != elts_tail) {
298 struct rte_mbuf *elt = (*txq->elts)[elts_free];
299 unsigned int elts_free_next =
300 (elts_free + 1) & (elts_n - 1);
301 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
305 memset(&(*txq->elts)[elts_free],
307 sizeof((*txq->elts)[elts_free]));
309 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
310 /* Only one segment needs to be freed. */
311 rte_pktmbuf_free_seg(elt);
312 elts_free = elts_free_next;
315 txq->elts_tail = elts_tail;
316 /* Update the consumer index. */
318 *txq->cq_db = htonl(cq_ci);
322 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
323 * the cloned mbuf is allocated is returned instead.
329 * Memory pool where data is located for given mbuf.
331 static struct rte_mempool *
332 txq_mb2mp(struct rte_mbuf *buf)
334 if (unlikely(RTE_MBUF_INDIRECT(buf)))
335 return rte_mbuf_from_indirect(buf)->pool;
340 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
341 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
342 * remove an entry first.
345 * Pointer to TX queue structure.
347 * Memory Pool for which a Memory Region lkey must be returned.
350 * mr->lkey on success, (uint32_t)-1 on failure.
352 static inline uint32_t
353 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
356 uint32_t lkey = (uint32_t)-1;
358 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
359 if (unlikely(txq->mp2mr[i].mp == NULL)) {
360 /* Unknown MP, add a new MR for it. */
363 if (txq->mp2mr[i].mp == mp) {
364 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
365 assert(htonl(txq->mp2mr[i].mr->lkey) ==
367 lkey = txq->mp2mr[i].lkey;
371 if (unlikely(lkey == (uint32_t)-1))
372 lkey = txq_mp2mr_reg(txq, mp, i);
377 * Ring TX queue doorbell.
380 * Pointer to TX queue structure.
382 * Pointer to the last WQE posted in the NIC.
385 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
387 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
388 volatile uint64_t *src = ((volatile uint64_t *)wqe);
391 *txq->qp_db = htonl(txq->wqe_ci);
392 /* Ensure ordering between DB record and BF copy. */
398 * DPDK callback to check the status of a tx descriptor.
403 * The index of the descriptor in the ring.
406 * The status of the tx descriptor.
409 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
411 struct txq *txq = tx_queue;
412 const unsigned int elts_n = 1 << txq->elts_n;
413 const unsigned int elts_cnt = elts_n - 1;
417 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
419 return RTE_ETH_TX_DESC_FULL;
420 return RTE_ETH_TX_DESC_DONE;
424 * DPDK callback to check the status of a rx descriptor.
429 * The index of the descriptor in the ring.
432 * The status of the tx descriptor.
435 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
437 struct rxq *rxq = rx_queue;
438 struct rxq_zip *zip = &rxq->zip;
439 volatile struct mlx5_cqe *cqe;
440 const unsigned int cqe_n = (1 << rxq->cqe_n);
441 const unsigned int cqe_cnt = cqe_n - 1;
445 /* if we are processing a compressed cqe */
447 used = zip->cqe_cnt - zip->ca;
453 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
454 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
458 op_own = cqe->op_own;
459 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
460 n = ntohl(cqe->byte_cnt);
465 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
467 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
469 return RTE_ETH_RX_DESC_DONE;
470 return RTE_ETH_RX_DESC_AVAIL;
474 * DPDK callback for TX.
477 * Generic pointer to TX queue structure.
479 * Packets to transmit.
481 * Number of packets in array.
484 * Number of packets successfully transmitted (<= pkts_n).
487 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
489 struct txq *txq = (struct txq *)dpdk_txq;
490 uint16_t elts_head = txq->elts_head;
491 const unsigned int elts_n = 1 << txq->elts_n;
496 unsigned int max_inline = txq->max_inline;
497 const unsigned int inline_en = !!max_inline && txq->inline_en;
500 volatile struct mlx5_wqe_v *wqe = NULL;
501 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
502 unsigned int segs_n = 0;
503 struct rte_mbuf *buf = NULL;
506 if (unlikely(!pkts_n))
508 /* Prefetch first packet cacheline. */
509 rte_prefetch0(*pkts);
510 /* Start processing. */
512 max = (elts_n - (elts_head - txq->elts_tail));
515 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
516 if (unlikely(!max_wqe))
519 volatile rte_v128u32_t *dseg = NULL;
522 unsigned int sg = 0; /* counter of additional segs attached. */
525 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
526 uint16_t tso_header_sz = 0;
528 uint8_t cs_flags = 0;
530 #ifdef MLX5_PMD_SOFT_COUNTERS
531 uint32_t total_length = 0;
536 segs_n = buf->nb_segs;
538 * Make sure there is enough room to store this packet and
539 * that one ring entry remains unused.
542 if (max < segs_n + 1)
546 if (unlikely(--max_wqe == 0))
548 wqe = (volatile struct mlx5_wqe_v *)
549 tx_mlx5_wqe(txq, txq->wqe_ci);
550 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
552 rte_prefetch0(*(pkts + 1));
553 addr = rte_pktmbuf_mtod(buf, uintptr_t);
554 length = DATA_LEN(buf);
555 ehdr = (((uint8_t *)addr)[1] << 8) |
556 ((uint8_t *)addr)[0];
557 #ifdef MLX5_PMD_SOFT_COUNTERS
558 total_length = length;
560 if (length < (MLX5_WQE_DWORD_SIZE + 2))
562 /* Update element. */
563 (*txq->elts)[elts_head] = buf;
564 /* Prefetch next buffer data. */
567 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
568 /* Should we enable HW CKSUM offload */
570 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
571 const uint64_t is_tunneled = buf->ol_flags &
573 PKT_TX_TUNNEL_VXLAN);
575 if (is_tunneled && txq->tunnel_en) {
576 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
577 MLX5_ETH_WQE_L4_INNER_CSUM;
578 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
579 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
581 cs_flags = MLX5_ETH_WQE_L3_CSUM |
582 MLX5_ETH_WQE_L4_CSUM;
585 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
586 /* Replace the Ethernet type by the VLAN if necessary. */
587 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
588 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
589 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
593 /* Copy Destination and source mac address. */
594 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
596 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
597 /* Copy missing two bytes to end the DSeg. */
598 memcpy((uint8_t *)raw + len + sizeof(vlan),
599 ((uint8_t *)addr) + len, 2);
603 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
604 MLX5_WQE_DWORD_SIZE);
605 length -= pkt_inline_sz;
606 addr += pkt_inline_sz;
609 tso = buf->ol_flags & PKT_TX_TCP_SEG;
611 uintptr_t end = (uintptr_t)
612 (((uintptr_t)txq->wqes) +
616 uint8_t vlan_sz = (buf->ol_flags &
617 PKT_TX_VLAN_PKT) ? 4 : 0;
618 const uint64_t is_tunneled =
621 PKT_TX_TUNNEL_VXLAN);
623 tso_header_sz = buf->l2_len + vlan_sz +
624 buf->l3_len + buf->l4_len;
626 if (is_tunneled && txq->tunnel_en) {
627 tso_header_sz += buf->outer_l2_len +
629 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
631 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
633 if (unlikely(tso_header_sz >
634 MLX5_MAX_TSO_HEADER))
636 copy_b = tso_header_sz - pkt_inline_sz;
637 /* First seg must contain all headers. */
638 assert(copy_b <= length);
639 raw += MLX5_WQE_DWORD_SIZE;
641 ((end - (uintptr_t)raw) > copy_b)) {
642 uint16_t n = (MLX5_WQE_DS(copy_b) -
645 if (unlikely(max_wqe < n))
648 rte_memcpy((void *)raw,
649 (void *)addr, copy_b);
652 pkt_inline_sz += copy_b;
654 * Another DWORD will be added
655 * in the inline part.
657 raw += MLX5_WQE_DS(copy_b) *
658 MLX5_WQE_DWORD_SIZE -
662 wqe->ctrl = (rte_v128u32_t){
663 htonl(txq->wqe_ci << 8),
664 htonl(txq->qp_num_8s | 1),
675 /* Inline if enough room. */
676 if (inline_en || tso) {
677 uintptr_t end = (uintptr_t)
678 (((uintptr_t)txq->wqes) +
679 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
680 unsigned int inline_room = max_inline *
681 RTE_CACHE_LINE_SIZE -
683 uintptr_t addr_end = (addr + inline_room) &
684 ~(RTE_CACHE_LINE_SIZE - 1);
685 unsigned int copy_b = (addr_end > addr) ?
686 RTE_MIN((addr_end - addr), length) :
689 raw += MLX5_WQE_DWORD_SIZE;
690 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
692 * One Dseg remains in the current WQE. To
693 * keep the computation positive, it is
694 * removed after the bytes to Dseg conversion.
696 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
698 if (unlikely(max_wqe < n))
703 htonl(copy_b | MLX5_INLINE_SEG);
706 MLX5_WQE_DS(tso_header_sz) *
708 rte_memcpy((void *)raw,
709 (void *)&inl, sizeof(inl));
711 pkt_inline_sz += sizeof(inl);
713 rte_memcpy((void *)raw, (void *)addr, copy_b);
716 pkt_inline_sz += copy_b;
719 * 2 DWORDs consumed by the WQE header + ETH segment +
720 * the size of the inline part of the packet.
722 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
724 if (ds % (MLX5_WQE_SIZE /
725 MLX5_WQE_DWORD_SIZE) == 0) {
726 if (unlikely(--max_wqe == 0))
728 dseg = (volatile rte_v128u32_t *)
729 tx_mlx5_wqe(txq, txq->wqe_ci +
732 dseg = (volatile rte_v128u32_t *)
734 (ds * MLX5_WQE_DWORD_SIZE));
737 } else if (!segs_n) {
740 /* dseg will be advance as part of next_seg */
741 dseg = (volatile rte_v128u32_t *)
743 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
748 * No inline has been done in the packet, only the
749 * Ethernet Header as been stored.
751 dseg = (volatile rte_v128u32_t *)
752 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
755 /* Add the remaining packet as a simple ds. */
756 naddr = htonll(addr);
757 *dseg = (rte_v128u32_t){
759 txq_mp2mr(txq, txq_mb2mp(buf)),
772 * Spill on next WQE when the current one does not have
773 * enough room left. Size of WQE must a be a multiple
774 * of data segment size.
776 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
777 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
778 if (unlikely(--max_wqe == 0))
780 dseg = (volatile rte_v128u32_t *)
781 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
782 rte_prefetch0(tx_mlx5_wqe(txq,
783 txq->wqe_ci + ds / 4 + 1));
790 length = DATA_LEN(buf);
791 #ifdef MLX5_PMD_SOFT_COUNTERS
792 total_length += length;
794 /* Store segment information. */
795 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
796 *dseg = (rte_v128u32_t){
798 txq_mp2mr(txq, txq_mb2mp(buf)),
802 elts_head = (elts_head + 1) & (elts_n - 1);
803 (*txq->elts)[elts_head] = buf;
805 /* Advance counter only if all segs are successfully posted. */
811 elts_head = (elts_head + 1) & (elts_n - 1);
814 /* Initialize known and common part of the WQE structure. */
816 wqe->ctrl = (rte_v128u32_t){
817 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
818 htonl(txq->qp_num_8s | ds),
822 wqe->eseg = (rte_v128u32_t){
824 cs_flags | (htons(buf->tso_segsz) << 16),
826 (ehdr << 16) | htons(tso_header_sz),
829 wqe->ctrl = (rte_v128u32_t){
830 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
831 htonl(txq->qp_num_8s | ds),
835 wqe->eseg = (rte_v128u32_t){
839 (ehdr << 16) | htons(pkt_inline_sz),
843 txq->wqe_ci += (ds + 3) / 4;
844 /* Save the last successful WQE for completion request */
845 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
846 #ifdef MLX5_PMD_SOFT_COUNTERS
847 /* Increment sent bytes counter. */
848 txq->stats.obytes += total_length;
850 } while (i < pkts_n);
851 /* Take a shortcut if nothing must be sent. */
852 if (unlikely((i + k) == 0))
854 txq->elts_head = (txq->elts_head + i + j) & (elts_n - 1);
855 /* Check whether completion threshold has been reached. */
856 comp = txq->elts_comp + i + j + k;
857 if (comp >= MLX5_TX_COMP_THRESH) {
858 /* Request completion on last WQE. */
859 last_wqe->ctrl2 = htonl(8);
860 /* Save elts_head in unused "immediate" field of WQE. */
861 last_wqe->ctrl3 = txq->elts_head;
864 txq->elts_comp = comp;
866 #ifdef MLX5_PMD_SOFT_COUNTERS
867 /* Increment sent packets counter. */
868 txq->stats.opackets += i;
870 /* Ring QP doorbell. */
871 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
876 * Open a MPW session.
879 * Pointer to TX queue structure.
881 * Pointer to MPW session structure.
886 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
888 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
889 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
890 (volatile struct mlx5_wqe_data_seg (*)[])
891 tx_mlx5_wqe(txq, idx + 1);
893 mpw->state = MLX5_MPW_STATE_OPENED;
897 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
898 mpw->wqe->eseg.mss = htons(length);
899 mpw->wqe->eseg.inline_hdr_sz = 0;
900 mpw->wqe->eseg.rsvd0 = 0;
901 mpw->wqe->eseg.rsvd1 = 0;
902 mpw->wqe->eseg.rsvd2 = 0;
903 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
904 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
905 mpw->wqe->ctrl[2] = 0;
906 mpw->wqe->ctrl[3] = 0;
907 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
908 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
909 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
910 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
911 mpw->data.dseg[2] = &(*dseg)[0];
912 mpw->data.dseg[3] = &(*dseg)[1];
913 mpw->data.dseg[4] = &(*dseg)[2];
917 * Close a MPW session.
920 * Pointer to TX queue structure.
922 * Pointer to MPW session structure.
925 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
927 unsigned int num = mpw->pkts_n;
930 * Store size in multiple of 16 bytes. Control and Ethernet segments
933 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
934 mpw->state = MLX5_MPW_STATE_CLOSED;
939 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
940 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
944 * DPDK callback for TX with MPW support.
947 * Generic pointer to TX queue structure.
949 * Packets to transmit.
951 * Number of packets in array.
954 * Number of packets successfully transmitted (<= pkts_n).
957 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
959 struct txq *txq = (struct txq *)dpdk_txq;
960 uint16_t elts_head = txq->elts_head;
961 const unsigned int elts_n = 1 << txq->elts_n;
967 struct mlx5_mpw mpw = {
968 .state = MLX5_MPW_STATE_CLOSED,
971 if (unlikely(!pkts_n))
973 /* Prefetch first packet cacheline. */
974 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
975 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
976 /* Start processing. */
978 max = (elts_n - (elts_head - txq->elts_tail));
981 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
982 if (unlikely(!max_wqe))
985 struct rte_mbuf *buf = *(pkts++);
986 unsigned int elts_head_next;
988 unsigned int segs_n = buf->nb_segs;
989 uint32_t cs_flags = 0;
992 * Make sure there is enough room to store this packet and
993 * that one ring entry remains unused.
996 if (max < segs_n + 1)
998 /* Do not bother with large packets MPW cannot handle. */
999 if (segs_n > MLX5_MPW_DSEG_MAX)
1003 /* Should we enable HW CKSUM offload */
1005 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1006 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1007 /* Retrieve packet information. */
1008 length = PKT_LEN(buf);
1010 /* Start new session if packet differs. */
1011 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1012 ((mpw.len != length) ||
1014 (mpw.wqe->eseg.cs_flags != cs_flags)))
1015 mlx5_mpw_close(txq, &mpw);
1016 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1018 * Multi-Packet WQE consumes at most two WQE.
1019 * mlx5_mpw_new() expects to be able to use such
1022 if (unlikely(max_wqe < 2))
1025 mlx5_mpw_new(txq, &mpw, length);
1026 mpw.wqe->eseg.cs_flags = cs_flags;
1028 /* Multi-segment packets must be alone in their MPW. */
1029 assert((segs_n == 1) || (mpw.pkts_n == 0));
1030 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1034 volatile struct mlx5_wqe_data_seg *dseg;
1037 elts_head_next = (elts_head + 1) & (elts_n - 1);
1039 (*txq->elts)[elts_head] = buf;
1040 dseg = mpw.data.dseg[mpw.pkts_n];
1041 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1042 *dseg = (struct mlx5_wqe_data_seg){
1043 .byte_count = htonl(DATA_LEN(buf)),
1044 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1045 .addr = htonll(addr),
1047 elts_head = elts_head_next;
1048 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1049 length += DATA_LEN(buf);
1055 assert(length == mpw.len);
1056 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1057 mlx5_mpw_close(txq, &mpw);
1058 elts_head = elts_head_next;
1059 #ifdef MLX5_PMD_SOFT_COUNTERS
1060 /* Increment sent bytes counter. */
1061 txq->stats.obytes += length;
1065 /* Take a shortcut if nothing must be sent. */
1066 if (unlikely(i == 0))
1068 /* Check whether completion threshold has been reached. */
1069 /* "j" includes both packets and segments. */
1070 comp = txq->elts_comp + j;
1071 if (comp >= MLX5_TX_COMP_THRESH) {
1072 volatile struct mlx5_wqe *wqe = mpw.wqe;
1074 /* Request completion on last WQE. */
1075 wqe->ctrl[2] = htonl(8);
1076 /* Save elts_head in unused "immediate" field of WQE. */
1077 wqe->ctrl[3] = elts_head;
1080 txq->elts_comp = comp;
1082 #ifdef MLX5_PMD_SOFT_COUNTERS
1083 /* Increment sent packets counter. */
1084 txq->stats.opackets += i;
1086 /* Ring QP doorbell. */
1087 if (mpw.state == MLX5_MPW_STATE_OPENED)
1088 mlx5_mpw_close(txq, &mpw);
1089 mlx5_tx_dbrec(txq, mpw.wqe);
1090 txq->elts_head = elts_head;
1095 * Open a MPW inline session.
1098 * Pointer to TX queue structure.
1100 * Pointer to MPW session structure.
1105 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1107 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1108 struct mlx5_wqe_inl_small *inl;
1110 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1114 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1115 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1116 (txq->wqe_ci << 8) |
1118 mpw->wqe->ctrl[2] = 0;
1119 mpw->wqe->ctrl[3] = 0;
1120 mpw->wqe->eseg.mss = htons(length);
1121 mpw->wqe->eseg.inline_hdr_sz = 0;
1122 mpw->wqe->eseg.cs_flags = 0;
1123 mpw->wqe->eseg.rsvd0 = 0;
1124 mpw->wqe->eseg.rsvd1 = 0;
1125 mpw->wqe->eseg.rsvd2 = 0;
1126 inl = (struct mlx5_wqe_inl_small *)
1127 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1128 mpw->data.raw = (uint8_t *)&inl->raw;
1132 * Close a MPW inline session.
1135 * Pointer to TX queue structure.
1137 * Pointer to MPW session structure.
1140 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1143 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1144 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1146 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1148 * Store size in multiple of 16 bytes. Control and Ethernet segments
1151 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1152 mpw->state = MLX5_MPW_STATE_CLOSED;
1153 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1154 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1158 * DPDK callback for TX with MPW inline support.
1161 * Generic pointer to TX queue structure.
1163 * Packets to transmit.
1165 * Number of packets in array.
1168 * Number of packets successfully transmitted (<= pkts_n).
1171 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1174 struct txq *txq = (struct txq *)dpdk_txq;
1175 uint16_t elts_head = txq->elts_head;
1176 const unsigned int elts_n = 1 << txq->elts_n;
1182 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1183 struct mlx5_mpw mpw = {
1184 .state = MLX5_MPW_STATE_CLOSED,
1187 * Compute the maximum number of WQE which can be consumed by inline
1190 * - 1 control segment,
1191 * - 1 Ethernet segment,
1192 * - N Dseg from the inline request.
1194 const unsigned int wqe_inl_n =
1195 ((2 * MLX5_WQE_DWORD_SIZE +
1196 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1197 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1199 if (unlikely(!pkts_n))
1201 /* Prefetch first packet cacheline. */
1202 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1203 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1204 /* Start processing. */
1206 max = (elts_n - (elts_head - txq->elts_tail));
1210 struct rte_mbuf *buf = *(pkts++);
1211 unsigned int elts_head_next;
1214 unsigned int segs_n = buf->nb_segs;
1215 uint32_t cs_flags = 0;
1218 * Make sure there is enough room to store this packet and
1219 * that one ring entry remains unused.
1222 if (max < segs_n + 1)
1224 /* Do not bother with large packets MPW cannot handle. */
1225 if (segs_n > MLX5_MPW_DSEG_MAX)
1230 * Compute max_wqe in case less WQE were consumed in previous
1233 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1234 /* Should we enable HW CKSUM offload */
1236 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1237 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1238 /* Retrieve packet information. */
1239 length = PKT_LEN(buf);
1240 /* Start new session if packet differs. */
1241 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1242 if ((mpw.len != length) ||
1244 (mpw.wqe->eseg.cs_flags != cs_flags))
1245 mlx5_mpw_close(txq, &mpw);
1246 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1247 if ((mpw.len != length) ||
1249 (length > inline_room) ||
1250 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1251 mlx5_mpw_inline_close(txq, &mpw);
1253 txq->max_inline * RTE_CACHE_LINE_SIZE;
1256 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1257 if ((segs_n != 1) ||
1258 (length > inline_room)) {
1260 * Multi-Packet WQE consumes at most two WQE.
1261 * mlx5_mpw_new() expects to be able to use
1264 if (unlikely(max_wqe < 2))
1267 mlx5_mpw_new(txq, &mpw, length);
1268 mpw.wqe->eseg.cs_flags = cs_flags;
1270 if (unlikely(max_wqe < wqe_inl_n))
1272 max_wqe -= wqe_inl_n;
1273 mlx5_mpw_inline_new(txq, &mpw, length);
1274 mpw.wqe->eseg.cs_flags = cs_flags;
1277 /* Multi-segment packets must be alone in their MPW. */
1278 assert((segs_n == 1) || (mpw.pkts_n == 0));
1279 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1280 assert(inline_room ==
1281 txq->max_inline * RTE_CACHE_LINE_SIZE);
1282 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1286 volatile struct mlx5_wqe_data_seg *dseg;
1289 (elts_head + 1) & (elts_n - 1);
1291 (*txq->elts)[elts_head] = buf;
1292 dseg = mpw.data.dseg[mpw.pkts_n];
1293 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1294 *dseg = (struct mlx5_wqe_data_seg){
1295 .byte_count = htonl(DATA_LEN(buf)),
1296 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1297 .addr = htonll(addr),
1299 elts_head = elts_head_next;
1300 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1301 length += DATA_LEN(buf);
1307 assert(length == mpw.len);
1308 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1309 mlx5_mpw_close(txq, &mpw);
1313 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1314 assert(length <= inline_room);
1315 assert(length == DATA_LEN(buf));
1316 elts_head_next = (elts_head + 1) & (elts_n - 1);
1317 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1318 (*txq->elts)[elts_head] = buf;
1319 /* Maximum number of bytes before wrapping. */
1320 max = ((((uintptr_t)(txq->wqes)) +
1323 (uintptr_t)mpw.data.raw);
1325 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1328 mpw.data.raw = (volatile void *)txq->wqes;
1329 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1330 (void *)(addr + max),
1332 mpw.data.raw += length - max;
1334 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1340 (volatile void *)txq->wqes;
1342 mpw.data.raw += length;
1345 mpw.total_len += length;
1347 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1348 mlx5_mpw_inline_close(txq, &mpw);
1350 txq->max_inline * RTE_CACHE_LINE_SIZE;
1352 inline_room -= length;
1355 elts_head = elts_head_next;
1356 #ifdef MLX5_PMD_SOFT_COUNTERS
1357 /* Increment sent bytes counter. */
1358 txq->stats.obytes += length;
1362 /* Take a shortcut if nothing must be sent. */
1363 if (unlikely(i == 0))
1365 /* Check whether completion threshold has been reached. */
1366 /* "j" includes both packets and segments. */
1367 comp = txq->elts_comp + j;
1368 if (comp >= MLX5_TX_COMP_THRESH) {
1369 volatile struct mlx5_wqe *wqe = mpw.wqe;
1371 /* Request completion on last WQE. */
1372 wqe->ctrl[2] = htonl(8);
1373 /* Save elts_head in unused "immediate" field of WQE. */
1374 wqe->ctrl[3] = elts_head;
1377 txq->elts_comp = comp;
1379 #ifdef MLX5_PMD_SOFT_COUNTERS
1380 /* Increment sent packets counter. */
1381 txq->stats.opackets += i;
1383 /* Ring QP doorbell. */
1384 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1385 mlx5_mpw_inline_close(txq, &mpw);
1386 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1387 mlx5_mpw_close(txq, &mpw);
1388 mlx5_tx_dbrec(txq, mpw.wqe);
1389 txq->elts_head = elts_head;
1394 * Open an Enhanced MPW session.
1397 * Pointer to TX queue structure.
1399 * Pointer to MPW session structure.
1404 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1406 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1408 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1410 mpw->total_len = sizeof(struct mlx5_wqe);
1411 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1412 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1413 (txq->wqe_ci << 8) |
1414 MLX5_OPCODE_ENHANCED_MPSW);
1415 mpw->wqe->ctrl[2] = 0;
1416 mpw->wqe->ctrl[3] = 0;
1417 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1418 if (unlikely(padding)) {
1419 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1421 /* Pad the first 2 DWORDs with zero-length inline header. */
1422 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1423 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1424 htonl(MLX5_INLINE_SEG);
1425 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1426 /* Start from the next WQEBB. */
1427 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1429 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1434 * Close an Enhanced MPW session.
1437 * Pointer to TX queue structure.
1439 * Pointer to MPW session structure.
1442 * Number of consumed WQEs.
1444 static inline uint16_t
1445 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1449 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1452 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1453 mpw->state = MLX5_MPW_STATE_CLOSED;
1454 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1460 * DPDK callback for TX with Enhanced MPW support.
1463 * Generic pointer to TX queue structure.
1465 * Packets to transmit.
1467 * Number of packets in array.
1470 * Number of packets successfully transmitted (<= pkts_n).
1473 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1475 struct txq *txq = (struct txq *)dpdk_txq;
1476 uint16_t elts_head = txq->elts_head;
1477 const unsigned int elts_n = 1 << txq->elts_n;
1480 unsigned int max_elts;
1482 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1483 unsigned int mpw_room = 0;
1484 unsigned int inl_pad = 0;
1486 struct mlx5_mpw mpw = {
1487 .state = MLX5_MPW_STATE_CLOSED,
1490 if (unlikely(!pkts_n))
1492 /* Start processing. */
1494 max_elts = (elts_n - (elts_head - txq->elts_tail));
1495 if (max_elts > elts_n)
1497 /* A CQE slot must always be available. */
1498 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1499 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1500 if (unlikely(!max_wqe))
1503 struct rte_mbuf *buf = *(pkts++);
1504 unsigned int elts_head_next;
1508 unsigned int do_inline = 0; /* Whether inline is possible. */
1510 unsigned int segs_n = buf->nb_segs;
1511 uint32_t cs_flags = 0;
1514 * Make sure there is enough room to store this packet and
1515 * that one ring entry remains unused.
1518 if (max_elts - j < segs_n + 1)
1520 /* Do not bother with large packets MPW cannot handle. */
1521 if (segs_n > MLX5_MPW_DSEG_MAX)
1523 /* Should we enable HW CKSUM offload. */
1525 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1526 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1527 /* Retrieve packet information. */
1528 length = PKT_LEN(buf);
1529 /* Start new session if:
1530 * - multi-segment packet
1531 * - no space left even for a dseg
1532 * - next packet can be inlined with a new WQE
1534 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1537 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1538 if ((segs_n != 1) ||
1539 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1541 (length <= txq->inline_max_packet_sz &&
1542 inl_pad + sizeof(inl_hdr) + length >
1544 (mpw.wqe->eseg.cs_flags != cs_flags))
1545 max_wqe -= mlx5_empw_close(txq, &mpw);
1547 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1548 if (unlikely(segs_n != 1)) {
1549 /* Fall back to legacy MPW.
1550 * A MPW session consumes 2 WQEs at most to
1551 * include MLX5_MPW_DSEG_MAX pointers.
1553 if (unlikely(max_wqe < 2))
1555 mlx5_mpw_new(txq, &mpw, length);
1557 /* In Enhanced MPW, inline as much as the budget
1558 * is allowed. The remaining space is to be
1559 * filled with dsegs. If the title WQEBB isn't
1560 * padded, it will have 2 dsegs there.
1562 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1563 (max_inline ? max_inline :
1564 pkts_n * MLX5_WQE_DWORD_SIZE) +
1566 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1569 /* Don't pad the title WQEBB to not waste WQ. */
1570 mlx5_empw_new(txq, &mpw, 0);
1571 mpw_room -= mpw.total_len;
1574 length <= txq->inline_max_packet_sz &&
1575 sizeof(inl_hdr) + length <= mpw_room &&
1578 mpw.wqe->eseg.cs_flags = cs_flags;
1580 /* Evaluate whether the next packet can be inlined.
1581 * Inlininig is possible when:
1582 * - length is less than configured value
1583 * - length fits for remaining space
1584 * - not required to fill the title WQEBB with dsegs
1587 length <= txq->inline_max_packet_sz &&
1588 inl_pad + sizeof(inl_hdr) + length <=
1590 (!txq->mpw_hdr_dseg ||
1591 mpw.total_len >= MLX5_WQE_SIZE);
1593 /* Multi-segment packets must be alone in their MPW. */
1594 assert((segs_n == 1) || (mpw.pkts_n == 0));
1595 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1596 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1600 volatile struct mlx5_wqe_data_seg *dseg;
1603 (elts_head + 1) & (elts_n - 1);
1605 (*txq->elts)[elts_head] = buf;
1606 dseg = mpw.data.dseg[mpw.pkts_n];
1607 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1608 *dseg = (struct mlx5_wqe_data_seg){
1609 .byte_count = htonl(DATA_LEN(buf)),
1610 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1611 .addr = htonll(addr),
1613 elts_head = elts_head_next;
1614 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1615 length += DATA_LEN(buf);
1621 /* A multi-segmented packet takes one MPW session.
1622 * TODO: Pack more multi-segmented packets if possible.
1624 mlx5_mpw_close(txq, &mpw);
1629 } else if (do_inline) {
1630 /* Inline packet into WQE. */
1633 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1634 assert(length == DATA_LEN(buf));
1635 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1636 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1637 mpw.data.raw = (volatile void *)
1638 ((uintptr_t)mpw.data.raw + inl_pad);
1639 max = tx_mlx5_wq_tailroom(txq,
1640 (void *)(uintptr_t)mpw.data.raw);
1641 /* Copy inline header. */
1642 mpw.data.raw = (volatile void *)
1644 (void *)(uintptr_t)mpw.data.raw,
1647 (void *)(uintptr_t)txq->wqes,
1649 max = tx_mlx5_wq_tailroom(txq,
1650 (void *)(uintptr_t)mpw.data.raw);
1651 /* Copy packet data. */
1652 mpw.data.raw = (volatile void *)
1654 (void *)(uintptr_t)mpw.data.raw,
1657 (void *)(uintptr_t)txq->wqes,
1660 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1661 /* No need to get completion as the entire packet is
1662 * copied to WQ. Free the buf right away.
1664 elts_head_next = elts_head;
1665 rte_pktmbuf_free_seg(buf);
1666 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1667 /* Add pad in the next packet if any. */
1668 inl_pad = (((uintptr_t)mpw.data.raw +
1669 (MLX5_WQE_DWORD_SIZE - 1)) &
1670 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1671 (uintptr_t)mpw.data.raw;
1673 /* No inline. Load a dseg of packet pointer. */
1674 volatile rte_v128u32_t *dseg;
1676 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1677 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1678 assert(length == DATA_LEN(buf));
1679 if (!tx_mlx5_wq_tailroom(txq,
1680 (void *)((uintptr_t)mpw.data.raw
1682 dseg = (volatile void *)txq->wqes;
1684 dseg = (volatile void *)
1685 ((uintptr_t)mpw.data.raw +
1687 elts_head_next = (elts_head + 1) & (elts_n - 1);
1688 (*txq->elts)[elts_head] = buf;
1689 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1690 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1691 rte_prefetch2((void *)(addr +
1692 n * RTE_CACHE_LINE_SIZE));
1693 naddr = htonll(addr);
1694 *dseg = (rte_v128u32_t) {
1696 txq_mp2mr(txq, txq_mb2mp(buf)),
1700 mpw.data.raw = (volatile void *)(dseg + 1);
1701 mpw.total_len += (inl_pad + sizeof(*dseg));
1704 mpw_room -= (inl_pad + sizeof(*dseg));
1707 elts_head = elts_head_next;
1708 #ifdef MLX5_PMD_SOFT_COUNTERS
1709 /* Increment sent bytes counter. */
1710 txq->stats.obytes += length;
1713 } while (i < pkts_n);
1714 /* Take a shortcut if nothing must be sent. */
1715 if (unlikely(i == 0))
1717 /* Check whether completion threshold has been reached. */
1718 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1719 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1720 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1721 volatile struct mlx5_wqe *wqe = mpw.wqe;
1723 /* Request completion on last WQE. */
1724 wqe->ctrl[2] = htonl(8);
1725 /* Save elts_head in unused "immediate" field of WQE. */
1726 wqe->ctrl[3] = elts_head;
1728 txq->mpw_comp = txq->wqe_ci;
1731 txq->elts_comp += j;
1733 #ifdef MLX5_PMD_SOFT_COUNTERS
1734 /* Increment sent packets counter. */
1735 txq->stats.opackets += i;
1737 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1738 mlx5_empw_close(txq, &mpw);
1739 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1740 mlx5_mpw_close(txq, &mpw);
1741 /* Ring QP doorbell. */
1742 mlx5_tx_dbrec(txq, mpw.wqe);
1743 txq->elts_head = elts_head;
1748 * Translate RX completion flags to packet type.
1753 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1756 * Packet type for struct rte_mbuf.
1758 static inline uint32_t
1759 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1762 uint16_t flags = ntohs(cqe->hdr_type_etc);
1764 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1767 MLX5_CQE_RX_IPV4_PACKET,
1768 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1770 MLX5_CQE_RX_IPV6_PACKET,
1771 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1772 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1773 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1774 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1778 MLX5_CQE_L3_HDR_TYPE_IPV6,
1779 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1781 MLX5_CQE_L3_HDR_TYPE_IPV4,
1782 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1788 * Get size of the next packet for a given CQE. For compressed CQEs, the
1789 * consumer index is updated only once all packets of the current one have
1793 * Pointer to RX queue.
1796 * @param[out] rss_hash
1797 * Packet RSS Hash result.
1800 * Packet size in bytes (0 if there is none), -1 in case of completion
1804 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1805 uint16_t cqe_cnt, uint32_t *rss_hash)
1807 struct rxq_zip *zip = &rxq->zip;
1808 uint16_t cqe_n = cqe_cnt + 1;
1812 /* Process compressed data in the CQE and mini arrays. */
1814 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1815 (volatile struct mlx5_mini_cqe8 (*)[8])
1816 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1818 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1819 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1820 if ((++zip->ai & 7) == 0) {
1821 /* Invalidate consumed CQEs */
1824 while (idx != end) {
1825 (*rxq->cqes)[idx & cqe_cnt].op_own =
1826 MLX5_CQE_INVALIDATE;
1830 * Increment consumer index to skip the number of
1831 * CQEs consumed. Hardware leaves holes in the CQ
1832 * ring for software use.
1837 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1838 /* Invalidate the rest */
1842 while (idx != end) {
1843 (*rxq->cqes)[idx & cqe_cnt].op_own =
1844 MLX5_CQE_INVALIDATE;
1847 rxq->cq_ci = zip->cq_ci;
1850 /* No compressed data, get next CQE and verify if it is compressed. */
1855 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1856 if (unlikely(ret == 1))
1859 op_own = cqe->op_own;
1860 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1861 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1862 (volatile struct mlx5_mini_cqe8 (*)[8])
1863 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1866 /* Fix endianness. */
1867 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1869 * Current mini array position is the one returned by
1872 * If completion comprises several mini arrays, as a
1873 * special case the second one is located 7 CQEs after
1874 * the initial CQE instead of 8 for subsequent ones.
1876 zip->ca = rxq->cq_ci;
1877 zip->na = zip->ca + 7;
1878 /* Compute the next non compressed CQE. */
1880 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1881 /* Get packet size to return. */
1882 len = ntohl((*mc)[0].byte_cnt);
1883 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1885 /* Prefetch all the entries to be invalidated */
1888 while (idx != end) {
1889 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1893 len = ntohl(cqe->byte_cnt);
1894 *rss_hash = ntohl(cqe->rx_hash_res);
1896 /* Error while receiving packet. */
1897 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1904 * Translate RX completion flags to offload flags.
1907 * Pointer to RX queue structure.
1912 * Offload flags (ol_flags) for struct rte_mbuf.
1914 static inline uint32_t
1915 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1917 uint32_t ol_flags = 0;
1918 uint16_t flags = ntohs(cqe->hdr_type_etc);
1922 MLX5_CQE_RX_L3_HDR_VALID,
1923 PKT_RX_IP_CKSUM_GOOD) |
1925 MLX5_CQE_RX_L4_HDR_VALID,
1926 PKT_RX_L4_CKSUM_GOOD);
1927 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1930 MLX5_CQE_RX_L3_HDR_VALID,
1931 PKT_RX_IP_CKSUM_GOOD) |
1933 MLX5_CQE_RX_L4_HDR_VALID,
1934 PKT_RX_L4_CKSUM_GOOD);
1939 * DPDK callback for RX.
1942 * Generic pointer to RX queue structure.
1944 * Array to store received packets.
1946 * Maximum number of packets in array.
1949 * Number of packets successfully received (<= pkts_n).
1952 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1954 struct rxq *rxq = dpdk_rxq;
1955 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1956 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1957 const unsigned int sges_n = rxq->sges_n;
1958 struct rte_mbuf *pkt = NULL;
1959 struct rte_mbuf *seg = NULL;
1960 volatile struct mlx5_cqe *cqe =
1961 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1963 unsigned int rq_ci = rxq->rq_ci << sges_n;
1964 int len = 0; /* keep its value across iterations. */
1967 unsigned int idx = rq_ci & wqe_cnt;
1968 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1969 struct rte_mbuf *rep = (*rxq->elts)[idx];
1970 uint32_t rss_hash_res = 0;
1978 rep = rte_mbuf_raw_alloc(rxq->mp);
1979 if (unlikely(rep == NULL)) {
1980 ++rxq->stats.rx_nombuf;
1983 * no buffers before we even started,
1984 * bail out silently.
1988 while (pkt != seg) {
1989 assert(pkt != (*rxq->elts)[idx]);
1993 rte_mbuf_raw_free(pkt);
1999 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2000 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2003 rte_mbuf_raw_free(rep);
2006 if (unlikely(len == -1)) {
2007 /* RX error, packet is likely too large. */
2008 rte_mbuf_raw_free(rep);
2009 ++rxq->stats.idropped;
2013 assert(len >= (rxq->crc_present << 2));
2014 /* Update packet information. */
2015 pkt->packet_type = 0;
2017 if (rss_hash_res && rxq->rss_hash) {
2018 pkt->hash.rss = rss_hash_res;
2019 pkt->ol_flags = PKT_RX_RSS_HASH;
2022 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2023 pkt->ol_flags |= PKT_RX_FDIR;
2024 if (cqe->sop_drop_qpn !=
2025 htonl(MLX5_FLOW_MARK_DEFAULT)) {
2026 uint32_t mark = cqe->sop_drop_qpn;
2028 pkt->ol_flags |= PKT_RX_FDIR_ID;
2030 mlx5_flow_mark_get(mark);
2033 if (rxq->csum | rxq->csum_l2tun) {
2034 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2035 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2037 if (rxq->vlan_strip &&
2038 (cqe->hdr_type_etc &
2039 htons(MLX5_CQE_VLAN_STRIPPED))) {
2040 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2041 PKT_RX_VLAN_STRIPPED;
2042 pkt->vlan_tci = ntohs(cqe->vlan_info);
2044 if (rxq->crc_present)
2045 len -= ETHER_CRC_LEN;
2048 DATA_LEN(rep) = DATA_LEN(seg);
2049 PKT_LEN(rep) = PKT_LEN(seg);
2050 SET_DATA_OFF(rep, DATA_OFF(seg));
2051 PORT(rep) = PORT(seg);
2052 (*rxq->elts)[idx] = rep;
2054 * Fill NIC descriptor with the new buffer. The lkey and size
2055 * of the buffers are already known, only the buffer address
2058 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2059 if (len > DATA_LEN(seg)) {
2060 len -= DATA_LEN(seg);
2065 DATA_LEN(seg) = len;
2066 #ifdef MLX5_PMD_SOFT_COUNTERS
2067 /* Increment bytes counter. */
2068 rxq->stats.ibytes += PKT_LEN(pkt);
2070 /* Return packet. */
2076 /* Align consumer index to the next stride. */
2081 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2083 /* Update the consumer index. */
2084 rxq->rq_ci = rq_ci >> sges_n;
2086 *rxq->cq_db = htonl(rxq->cq_ci);
2088 *rxq->rq_db = htonl(rxq->rq_ci);
2089 #ifdef MLX5_PMD_SOFT_COUNTERS
2090 /* Increment packets counter. */
2091 rxq->stats.ipackets += i;
2097 * Dummy DPDK callback for TX.
2099 * This function is used to temporarily replace the real callback during
2100 * unsafe control operations on the queue, or in case of error.
2103 * Generic pointer to TX queue structure.
2105 * Packets to transmit.
2107 * Number of packets in array.
2110 * Number of packets successfully transmitted (<= pkts_n).
2113 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2122 * Dummy DPDK callback for RX.
2124 * This function is used to temporarily replace the real callback during
2125 * unsafe control operations on the queue, or in case of error.
2128 * Generic pointer to RX queue structure.
2130 * Array to store received packets.
2132 * Maximum number of packets in array.
2135 * Number of packets successfully received (<= pkts_n).
2138 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2147 * DPDK callback for rx queue interrupt enable.
2150 * Pointer to Ethernet device structure.
2151 * @param rx_queue_id
2155 * 0 on success, negative on failure.
2158 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2160 #ifdef HAVE_UPDATE_CQ_CI
2161 struct priv *priv = mlx5_get_priv(dev);
2162 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2163 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2164 struct ibv_cq *cq = rxq_ctrl->cq;
2165 uint16_t ci = rxq->cq_ci;
2168 ibv_mlx5_exp_update_cq_ci(cq, ci);
2169 ret = ibv_req_notify_cq(cq, 0);
2176 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2181 * DPDK callback for rx queue interrupt disable.
2184 * Pointer to Ethernet device structure.
2185 * @param rx_queue_id
2189 * 0 on success, negative on failure.
2192 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2194 #ifdef HAVE_UPDATE_CQ_CI
2195 struct priv *priv = mlx5_get_priv(dev);
2196 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2197 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2198 struct ibv_cq *cq = rxq_ctrl->cq;
2199 struct ibv_cq *ev_cq;
2203 ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2204 if (ret || ev_cq != cq)
2207 ibv_ack_cq_events(cq, 1);
2214 WARN("unable to disable interrupt on rx queue %d",