4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
72 static __rte_always_inline int
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci);
76 static __rte_always_inline void
77 txq_complete(struct txq *txq);
79 static __rte_always_inline uint32_t
80 txq_mp2mr(struct txq *txq, struct rte_mempool *mp);
82 static __rte_always_inline void
83 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe);
85 static __rte_always_inline uint32_t
86 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
88 static __rte_always_inline int
89 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
90 uint16_t cqe_cnt, uint32_t *rss_hash);
92 static __rte_always_inline uint32_t
93 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
98 * Verify or set magic value in CQE.
107 check_cqe_seen(volatile struct mlx5_cqe *cqe)
109 static const uint8_t magic[] = "seen";
110 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
114 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
115 if (!ret || (*buf)[i] != magic[i]) {
117 (*buf)[i] = magic[i];
125 * Check whether CQE is valid.
130 * Size of completion queue.
135 * 0 on success, 1 on failure.
138 check_cqe(volatile struct mlx5_cqe *cqe,
139 unsigned int cqes_n, const uint16_t ci)
141 uint16_t idx = ci & cqes_n;
142 uint8_t op_own = cqe->op_own;
143 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
144 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
146 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
147 return 1; /* No CQE. */
149 if ((op_code == MLX5_CQE_RESP_ERR) ||
150 (op_code == MLX5_CQE_REQ_ERR)) {
151 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
152 uint8_t syndrome = err_cqe->syndrome;
154 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
155 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
157 if (!check_cqe_seen(cqe))
158 ERROR("unexpected CQE error %u (0x%02x)"
160 op_code, op_code, syndrome);
162 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
163 (op_code != MLX5_CQE_REQ)) {
164 if (!check_cqe_seen(cqe))
165 ERROR("unexpected CQE opcode %u (0x%02x)",
174 * Return the address of the WQE.
177 * Pointer to TX queue structure.
179 * WQE consumer index.
184 static inline uintptr_t *
185 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
187 ci &= ((1 << txq->wqe_n) - 1);
188 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
192 * Return the size of tailroom of WQ.
195 * Pointer to TX queue structure.
197 * Pointer to tail of WQ.
203 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
206 tailroom = (uintptr_t)(txq->wqes) +
207 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
213 * Copy data to tailroom of circular queue.
216 * Pointer to destination.
220 * Number of bytes to copy.
222 * Pointer to head of queue.
224 * Size of tailroom from dst.
227 * Pointer after copied data.
230 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
231 void *base, size_t tailroom)
236 rte_memcpy(dst, src, tailroom);
237 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
239 ret = (uint8_t *)base + n - tailroom;
241 rte_memcpy(dst, src, n);
242 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
248 * Manage TX completions.
250 * When sending a burst, mlx5_tx_burst() posts several WRs.
253 * Pointer to TX queue structure.
256 txq_complete(struct txq *txq)
258 const uint16_t elts_n = 1 << txq->elts_n;
259 const uint16_t elts_m = elts_n - 1;
260 const unsigned int cqe_n = 1 << txq->cqe_n;
261 const unsigned int cqe_cnt = cqe_n - 1;
262 uint16_t elts_free = txq->elts_tail;
264 uint16_t cq_ci = txq->cq_ci;
265 volatile struct mlx5_cqe *cqe = NULL;
266 volatile struct mlx5_wqe_ctrl *ctrl;
269 volatile struct mlx5_cqe *tmp;
271 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
272 if (check_cqe(tmp, cqe_n, cq_ci))
276 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
277 if (!check_cqe_seen(cqe))
278 ERROR("unexpected compressed CQE, TX stopped");
281 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
282 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
283 if (!check_cqe_seen(cqe))
284 ERROR("unexpected error CQE, TX stopped");
290 if (unlikely(cqe == NULL))
292 txq->wqe_pi = ntohs(cqe->wqe_counter);
293 ctrl = (volatile struct mlx5_wqe_ctrl *)
294 tx_mlx5_wqe(txq, txq->wqe_pi);
295 elts_tail = ctrl->ctrl3;
296 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
298 while (elts_free != elts_tail) {
299 struct rte_mbuf *elt = (*txq->elts)[elts_free & elts_m];
300 struct rte_mbuf *elt_next =
301 (*txq->elts)[(elts_free + 1) & elts_m];
305 memset(&(*txq->elts)[elts_free & elts_m],
307 sizeof((*txq->elts)[elts_free & elts_m]));
309 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
310 /* Only one segment needs to be freed. */
311 rte_pktmbuf_free_seg(elt);
315 txq->elts_tail = elts_tail;
316 /* Update the consumer index. */
318 *txq->cq_db = htonl(cq_ci);
322 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
323 * the cloned mbuf is allocated is returned instead.
329 * Memory pool where data is located for given mbuf.
331 static struct rte_mempool *
332 txq_mb2mp(struct rte_mbuf *buf)
334 if (unlikely(RTE_MBUF_INDIRECT(buf)))
335 return rte_mbuf_from_indirect(buf)->pool;
340 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
341 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
342 * remove an entry first.
345 * Pointer to TX queue structure.
347 * Memory Pool for which a Memory Region lkey must be returned.
350 * mr->lkey on success, (uint32_t)-1 on failure.
352 static inline uint32_t
353 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
356 uint32_t lkey = (uint32_t)-1;
358 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
359 if (unlikely(txq->mp2mr[i].mp == NULL)) {
360 /* Unknown MP, add a new MR for it. */
363 if (txq->mp2mr[i].mp == mp) {
364 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
365 assert(htonl(txq->mp2mr[i].mr->lkey) ==
367 lkey = txq->mp2mr[i].lkey;
371 if (unlikely(lkey == (uint32_t)-1))
372 lkey = txq_mp2mr_reg(txq, mp, i);
377 * Ring TX queue doorbell.
380 * Pointer to TX queue structure.
382 * Pointer to the last WQE posted in the NIC.
385 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
387 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
388 volatile uint64_t *src = ((volatile uint64_t *)wqe);
391 *txq->qp_db = htonl(txq->wqe_ci);
392 /* Ensure ordering between DB record and BF copy. */
398 * DPDK callback to check the status of a tx descriptor.
403 * The index of the descriptor in the ring.
406 * The status of the tx descriptor.
409 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
411 struct txq *txq = tx_queue;
415 used = txq->elts_head - txq->elts_tail;
417 return RTE_ETH_TX_DESC_FULL;
418 return RTE_ETH_TX_DESC_DONE;
422 * DPDK callback to check the status of a rx descriptor.
427 * The index of the descriptor in the ring.
430 * The status of the tx descriptor.
433 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
435 struct rxq *rxq = rx_queue;
436 struct rxq_zip *zip = &rxq->zip;
437 volatile struct mlx5_cqe *cqe;
438 const unsigned int cqe_n = (1 << rxq->cqe_n);
439 const unsigned int cqe_cnt = cqe_n - 1;
443 /* if we are processing a compressed cqe */
445 used = zip->cqe_cnt - zip->ca;
451 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
452 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
456 op_own = cqe->op_own;
457 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
458 n = ntohl(cqe->byte_cnt);
463 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
465 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
467 return RTE_ETH_RX_DESC_DONE;
468 return RTE_ETH_RX_DESC_AVAIL;
472 * DPDK callback for TX.
475 * Generic pointer to TX queue structure.
477 * Packets to transmit.
479 * Number of packets in array.
482 * Number of packets successfully transmitted (<= pkts_n).
485 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
487 struct txq *txq = (struct txq *)dpdk_txq;
488 uint16_t elts_head = txq->elts_head;
489 const uint16_t elts_n = 1 << txq->elts_n;
490 const uint16_t elts_m = elts_n - 1;
495 unsigned int max_inline = txq->max_inline;
496 const unsigned int inline_en = !!max_inline && txq->inline_en;
499 volatile struct mlx5_wqe_v *wqe = NULL;
500 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
501 unsigned int segs_n = 0;
502 struct rte_mbuf *buf = NULL;
505 if (unlikely(!pkts_n))
507 /* Prefetch first packet cacheline. */
508 rte_prefetch0(*pkts);
509 /* Start processing. */
511 max_elts = (elts_n - (elts_head - txq->elts_tail));
512 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
513 if (unlikely(!max_wqe))
516 volatile rte_v128u32_t *dseg = NULL;
519 unsigned int sg = 0; /* counter of additional segs attached. */
522 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
523 uint16_t tso_header_sz = 0;
525 uint8_t cs_flags = 0;
527 uint16_t tso_segsz = 0;
528 #ifdef MLX5_PMD_SOFT_COUNTERS
529 uint32_t total_length = 0;
534 segs_n = buf->nb_segs;
536 * Make sure there is enough room to store this packet and
537 * that one ring entry remains unused.
540 if (max_elts < segs_n)
544 if (unlikely(--max_wqe == 0))
546 wqe = (volatile struct mlx5_wqe_v *)
547 tx_mlx5_wqe(txq, txq->wqe_ci);
548 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
550 rte_prefetch0(*(pkts + 1));
551 addr = rte_pktmbuf_mtod(buf, uintptr_t);
552 length = DATA_LEN(buf);
553 ehdr = (((uint8_t *)addr)[1] << 8) |
554 ((uint8_t *)addr)[0];
555 #ifdef MLX5_PMD_SOFT_COUNTERS
556 total_length = length;
558 if (length < (MLX5_WQE_DWORD_SIZE + 2))
560 /* Update element. */
561 (*txq->elts)[elts_head & elts_m] = buf;
562 /* Prefetch next buffer data. */
565 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
566 /* Should we enable HW CKSUM offload */
568 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
569 const uint64_t is_tunneled = buf->ol_flags &
571 PKT_TX_TUNNEL_VXLAN);
573 if (is_tunneled && txq->tunnel_en) {
574 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
575 MLX5_ETH_WQE_L4_INNER_CSUM;
576 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
577 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
579 cs_flags = MLX5_ETH_WQE_L3_CSUM |
580 MLX5_ETH_WQE_L4_CSUM;
583 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
584 /* Replace the Ethernet type by the VLAN if necessary. */
585 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
586 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
587 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
591 /* Copy Destination and source mac address. */
592 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
594 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
595 /* Copy missing two bytes to end the DSeg. */
596 memcpy((uint8_t *)raw + len + sizeof(vlan),
597 ((uint8_t *)addr) + len, 2);
601 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
602 MLX5_WQE_DWORD_SIZE);
603 length -= pkt_inline_sz;
604 addr += pkt_inline_sz;
607 tso = buf->ol_flags & PKT_TX_TCP_SEG;
609 uintptr_t end = (uintptr_t)
610 (((uintptr_t)txq->wqes) +
614 uint8_t vlan_sz = (buf->ol_flags &
615 PKT_TX_VLAN_PKT) ? 4 : 0;
616 const uint64_t is_tunneled =
619 PKT_TX_TUNNEL_VXLAN);
621 tso_header_sz = buf->l2_len + vlan_sz +
622 buf->l3_len + buf->l4_len;
623 tso_segsz = buf->tso_segsz;
625 if (is_tunneled && txq->tunnel_en) {
626 tso_header_sz += buf->outer_l2_len +
628 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
630 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
632 if (unlikely(tso_header_sz >
633 MLX5_MAX_TSO_HEADER))
635 copy_b = tso_header_sz - pkt_inline_sz;
636 /* First seg must contain all headers. */
637 assert(copy_b <= length);
638 raw += MLX5_WQE_DWORD_SIZE;
640 ((end - (uintptr_t)raw) > copy_b)) {
641 uint16_t n = (MLX5_WQE_DS(copy_b) -
644 if (unlikely(max_wqe < n))
647 rte_memcpy((void *)raw,
648 (void *)addr, copy_b);
651 pkt_inline_sz += copy_b;
653 * Another DWORD will be added
654 * in the inline part.
656 raw += MLX5_WQE_DS(copy_b) *
657 MLX5_WQE_DWORD_SIZE -
661 wqe->ctrl = (rte_v128u32_t){
662 htonl(txq->wqe_ci << 8),
663 htonl(txq->qp_num_8s | 1),
674 /* Inline if enough room. */
675 if (inline_en || tso) {
676 uintptr_t end = (uintptr_t)
677 (((uintptr_t)txq->wqes) +
678 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
679 unsigned int inline_room = max_inline *
680 RTE_CACHE_LINE_SIZE -
682 uintptr_t addr_end = (addr + inline_room) &
683 ~(RTE_CACHE_LINE_SIZE - 1);
684 unsigned int copy_b = (addr_end > addr) ?
685 RTE_MIN((addr_end - addr), length) :
688 raw += MLX5_WQE_DWORD_SIZE;
689 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
691 * One Dseg remains in the current WQE. To
692 * keep the computation positive, it is
693 * removed after the bytes to Dseg conversion.
695 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
697 if (unlikely(max_wqe < n))
702 htonl(copy_b | MLX5_INLINE_SEG);
705 MLX5_WQE_DS(tso_header_sz) *
707 rte_memcpy((void *)raw,
708 (void *)&inl, sizeof(inl));
710 pkt_inline_sz += sizeof(inl);
712 rte_memcpy((void *)raw, (void *)addr, copy_b);
715 pkt_inline_sz += copy_b;
718 * 2 DWORDs consumed by the WQE header + ETH segment +
719 * the size of the inline part of the packet.
721 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
723 if (ds % (MLX5_WQE_SIZE /
724 MLX5_WQE_DWORD_SIZE) == 0) {
725 if (unlikely(--max_wqe == 0))
727 dseg = (volatile rte_v128u32_t *)
728 tx_mlx5_wqe(txq, txq->wqe_ci +
731 dseg = (volatile rte_v128u32_t *)
733 (ds * MLX5_WQE_DWORD_SIZE));
736 } else if (!segs_n) {
739 /* dseg will be advance as part of next_seg */
740 dseg = (volatile rte_v128u32_t *)
742 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
747 * No inline has been done in the packet, only the
748 * Ethernet Header as been stored.
750 dseg = (volatile rte_v128u32_t *)
751 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
754 /* Add the remaining packet as a simple ds. */
755 naddr = htonll(addr);
756 *dseg = (rte_v128u32_t){
758 txq_mp2mr(txq, txq_mb2mp(buf)),
771 * Spill on next WQE when the current one does not have
772 * enough room left. Size of WQE must a be a multiple
773 * of data segment size.
775 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
776 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
777 if (unlikely(--max_wqe == 0))
779 dseg = (volatile rte_v128u32_t *)
780 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
781 rte_prefetch0(tx_mlx5_wqe(txq,
782 txq->wqe_ci + ds / 4 + 1));
789 length = DATA_LEN(buf);
790 #ifdef MLX5_PMD_SOFT_COUNTERS
791 total_length += length;
793 /* Store segment information. */
794 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
795 *dseg = (rte_v128u32_t){
797 txq_mp2mr(txq, txq_mb2mp(buf)),
801 (*txq->elts)[++elts_head & elts_m] = buf;
803 /* Advance counter only if all segs are successfully posted. */
812 /* Initialize known and common part of the WQE structure. */
814 wqe->ctrl = (rte_v128u32_t){
815 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
816 htonl(txq->qp_num_8s | ds),
820 wqe->eseg = (rte_v128u32_t){
822 cs_flags | (htons(tso_segsz) << 16),
824 (ehdr << 16) | htons(tso_header_sz),
827 wqe->ctrl = (rte_v128u32_t){
828 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
829 htonl(txq->qp_num_8s | ds),
833 wqe->eseg = (rte_v128u32_t){
837 (ehdr << 16) | htons(pkt_inline_sz),
841 txq->wqe_ci += (ds + 3) / 4;
842 /* Save the last successful WQE for completion request */
843 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
844 #ifdef MLX5_PMD_SOFT_COUNTERS
845 /* Increment sent bytes counter. */
846 txq->stats.obytes += total_length;
848 } while (i < pkts_n);
849 /* Take a shortcut if nothing must be sent. */
850 if (unlikely((i + k) == 0))
852 txq->elts_head += (i + j);
853 /* Check whether completion threshold has been reached. */
854 comp = txq->elts_comp + i + j + k;
855 if (comp >= MLX5_TX_COMP_THRESH) {
856 /* Request completion on last WQE. */
857 last_wqe->ctrl2 = htonl(8);
858 /* Save elts_head in unused "immediate" field of WQE. */
859 last_wqe->ctrl3 = txq->elts_head;
862 txq->elts_comp = comp;
864 #ifdef MLX5_PMD_SOFT_COUNTERS
865 /* Increment sent packets counter. */
866 txq->stats.opackets += i;
868 /* Ring QP doorbell. */
869 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
874 * Open a MPW session.
877 * Pointer to TX queue structure.
879 * Pointer to MPW session structure.
884 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
886 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
887 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
888 (volatile struct mlx5_wqe_data_seg (*)[])
889 tx_mlx5_wqe(txq, idx + 1);
891 mpw->state = MLX5_MPW_STATE_OPENED;
895 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
896 mpw->wqe->eseg.mss = htons(length);
897 mpw->wqe->eseg.inline_hdr_sz = 0;
898 mpw->wqe->eseg.rsvd0 = 0;
899 mpw->wqe->eseg.rsvd1 = 0;
900 mpw->wqe->eseg.rsvd2 = 0;
901 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
902 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
903 mpw->wqe->ctrl[2] = 0;
904 mpw->wqe->ctrl[3] = 0;
905 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
906 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
907 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
908 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
909 mpw->data.dseg[2] = &(*dseg)[0];
910 mpw->data.dseg[3] = &(*dseg)[1];
911 mpw->data.dseg[4] = &(*dseg)[2];
915 * Close a MPW session.
918 * Pointer to TX queue structure.
920 * Pointer to MPW session structure.
923 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
925 unsigned int num = mpw->pkts_n;
928 * Store size in multiple of 16 bytes. Control and Ethernet segments
931 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
932 mpw->state = MLX5_MPW_STATE_CLOSED;
937 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
938 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
942 * DPDK callback for TX with MPW support.
945 * Generic pointer to TX queue structure.
947 * Packets to transmit.
949 * Number of packets in array.
952 * Number of packets successfully transmitted (<= pkts_n).
955 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
957 struct txq *txq = (struct txq *)dpdk_txq;
958 uint16_t elts_head = txq->elts_head;
959 const uint16_t elts_n = 1 << txq->elts_n;
960 const uint16_t elts_m = elts_n - 1;
966 struct mlx5_mpw mpw = {
967 .state = MLX5_MPW_STATE_CLOSED,
970 if (unlikely(!pkts_n))
972 /* Prefetch first packet cacheline. */
973 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
974 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
975 /* Start processing. */
977 max_elts = (elts_n - (elts_head - txq->elts_tail));
978 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
979 if (unlikely(!max_wqe))
982 struct rte_mbuf *buf = *(pkts++);
984 unsigned int segs_n = buf->nb_segs;
985 uint32_t cs_flags = 0;
988 * Make sure there is enough room to store this packet and
989 * that one ring entry remains unused.
992 if (max_elts < segs_n)
994 /* Do not bother with large packets MPW cannot handle. */
995 if (segs_n > MLX5_MPW_DSEG_MAX)
999 /* Should we enable HW CKSUM offload */
1001 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1002 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1003 /* Retrieve packet information. */
1004 length = PKT_LEN(buf);
1006 /* Start new session if packet differs. */
1007 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1008 ((mpw.len != length) ||
1010 (mpw.wqe->eseg.cs_flags != cs_flags)))
1011 mlx5_mpw_close(txq, &mpw);
1012 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1014 * Multi-Packet WQE consumes at most two WQE.
1015 * mlx5_mpw_new() expects to be able to use such
1018 if (unlikely(max_wqe < 2))
1021 mlx5_mpw_new(txq, &mpw, length);
1022 mpw.wqe->eseg.cs_flags = cs_flags;
1024 /* Multi-segment packets must be alone in their MPW. */
1025 assert((segs_n == 1) || (mpw.pkts_n == 0));
1026 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1030 volatile struct mlx5_wqe_data_seg *dseg;
1034 (*txq->elts)[elts_head++ & elts_m] = buf;
1035 dseg = mpw.data.dseg[mpw.pkts_n];
1036 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1037 *dseg = (struct mlx5_wqe_data_seg){
1038 .byte_count = htonl(DATA_LEN(buf)),
1039 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1040 .addr = htonll(addr),
1042 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1043 length += DATA_LEN(buf);
1049 assert(length == mpw.len);
1050 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1051 mlx5_mpw_close(txq, &mpw);
1052 #ifdef MLX5_PMD_SOFT_COUNTERS
1053 /* Increment sent bytes counter. */
1054 txq->stats.obytes += length;
1058 /* Take a shortcut if nothing must be sent. */
1059 if (unlikely(i == 0))
1061 /* Check whether completion threshold has been reached. */
1062 /* "j" includes both packets and segments. */
1063 comp = txq->elts_comp + j;
1064 if (comp >= MLX5_TX_COMP_THRESH) {
1065 volatile struct mlx5_wqe *wqe = mpw.wqe;
1067 /* Request completion on last WQE. */
1068 wqe->ctrl[2] = htonl(8);
1069 /* Save elts_head in unused "immediate" field of WQE. */
1070 wqe->ctrl[3] = elts_head;
1073 txq->elts_comp = comp;
1075 #ifdef MLX5_PMD_SOFT_COUNTERS
1076 /* Increment sent packets counter. */
1077 txq->stats.opackets += i;
1079 /* Ring QP doorbell. */
1080 if (mpw.state == MLX5_MPW_STATE_OPENED)
1081 mlx5_mpw_close(txq, &mpw);
1082 mlx5_tx_dbrec(txq, mpw.wqe);
1083 txq->elts_head = elts_head;
1088 * Open a MPW inline session.
1091 * Pointer to TX queue structure.
1093 * Pointer to MPW session structure.
1098 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1100 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1101 struct mlx5_wqe_inl_small *inl;
1103 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1107 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1108 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1109 (txq->wqe_ci << 8) |
1111 mpw->wqe->ctrl[2] = 0;
1112 mpw->wqe->ctrl[3] = 0;
1113 mpw->wqe->eseg.mss = htons(length);
1114 mpw->wqe->eseg.inline_hdr_sz = 0;
1115 mpw->wqe->eseg.cs_flags = 0;
1116 mpw->wqe->eseg.rsvd0 = 0;
1117 mpw->wqe->eseg.rsvd1 = 0;
1118 mpw->wqe->eseg.rsvd2 = 0;
1119 inl = (struct mlx5_wqe_inl_small *)
1120 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1121 mpw->data.raw = (uint8_t *)&inl->raw;
1125 * Close a MPW inline session.
1128 * Pointer to TX queue structure.
1130 * Pointer to MPW session structure.
1133 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1136 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1137 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1139 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1141 * Store size in multiple of 16 bytes. Control and Ethernet segments
1144 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1145 mpw->state = MLX5_MPW_STATE_CLOSED;
1146 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1147 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1151 * DPDK callback for TX with MPW inline support.
1154 * Generic pointer to TX queue structure.
1156 * Packets to transmit.
1158 * Number of packets in array.
1161 * Number of packets successfully transmitted (<= pkts_n).
1164 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1167 struct txq *txq = (struct txq *)dpdk_txq;
1168 uint16_t elts_head = txq->elts_head;
1169 const uint16_t elts_n = 1 << txq->elts_n;
1170 const uint16_t elts_m = elts_n - 1;
1176 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1177 struct mlx5_mpw mpw = {
1178 .state = MLX5_MPW_STATE_CLOSED,
1181 * Compute the maximum number of WQE which can be consumed by inline
1184 * - 1 control segment,
1185 * - 1 Ethernet segment,
1186 * - N Dseg from the inline request.
1188 const unsigned int wqe_inl_n =
1189 ((2 * MLX5_WQE_DWORD_SIZE +
1190 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1191 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1193 if (unlikely(!pkts_n))
1195 /* Prefetch first packet cacheline. */
1196 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1197 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1198 /* Start processing. */
1200 max_elts = (elts_n - (elts_head - txq->elts_tail));
1202 struct rte_mbuf *buf = *(pkts++);
1205 unsigned int segs_n = buf->nb_segs;
1206 uint32_t cs_flags = 0;
1209 * Make sure there is enough room to store this packet and
1210 * that one ring entry remains unused.
1213 if (max_elts < segs_n)
1215 /* Do not bother with large packets MPW cannot handle. */
1216 if (segs_n > MLX5_MPW_DSEG_MAX)
1221 * Compute max_wqe in case less WQE were consumed in previous
1224 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1225 /* Should we enable HW CKSUM offload */
1227 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1228 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1229 /* Retrieve packet information. */
1230 length = PKT_LEN(buf);
1231 /* Start new session if packet differs. */
1232 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1233 if ((mpw.len != length) ||
1235 (mpw.wqe->eseg.cs_flags != cs_flags))
1236 mlx5_mpw_close(txq, &mpw);
1237 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1238 if ((mpw.len != length) ||
1240 (length > inline_room) ||
1241 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1242 mlx5_mpw_inline_close(txq, &mpw);
1244 txq->max_inline * RTE_CACHE_LINE_SIZE;
1247 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1248 if ((segs_n != 1) ||
1249 (length > inline_room)) {
1251 * Multi-Packet WQE consumes at most two WQE.
1252 * mlx5_mpw_new() expects to be able to use
1255 if (unlikely(max_wqe < 2))
1258 mlx5_mpw_new(txq, &mpw, length);
1259 mpw.wqe->eseg.cs_flags = cs_flags;
1261 if (unlikely(max_wqe < wqe_inl_n))
1263 max_wqe -= wqe_inl_n;
1264 mlx5_mpw_inline_new(txq, &mpw, length);
1265 mpw.wqe->eseg.cs_flags = cs_flags;
1268 /* Multi-segment packets must be alone in their MPW. */
1269 assert((segs_n == 1) || (mpw.pkts_n == 0));
1270 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1271 assert(inline_room ==
1272 txq->max_inline * RTE_CACHE_LINE_SIZE);
1273 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1277 volatile struct mlx5_wqe_data_seg *dseg;
1280 (*txq->elts)[elts_head++ & elts_m] = buf;
1281 dseg = mpw.data.dseg[mpw.pkts_n];
1282 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1283 *dseg = (struct mlx5_wqe_data_seg){
1284 .byte_count = htonl(DATA_LEN(buf)),
1285 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1286 .addr = htonll(addr),
1288 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1289 length += DATA_LEN(buf);
1295 assert(length == mpw.len);
1296 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1297 mlx5_mpw_close(txq, &mpw);
1301 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1302 assert(length <= inline_room);
1303 assert(length == DATA_LEN(buf));
1304 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1305 (*txq->elts)[elts_head++ & elts_m] = buf;
1306 /* Maximum number of bytes before wrapping. */
1307 max = ((((uintptr_t)(txq->wqes)) +
1310 (uintptr_t)mpw.data.raw);
1312 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1315 mpw.data.raw = (volatile void *)txq->wqes;
1316 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1317 (void *)(addr + max),
1319 mpw.data.raw += length - max;
1321 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1327 (volatile void *)txq->wqes;
1329 mpw.data.raw += length;
1332 mpw.total_len += length;
1334 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1335 mlx5_mpw_inline_close(txq, &mpw);
1337 txq->max_inline * RTE_CACHE_LINE_SIZE;
1339 inline_room -= length;
1342 #ifdef MLX5_PMD_SOFT_COUNTERS
1343 /* Increment sent bytes counter. */
1344 txq->stats.obytes += length;
1348 /* Take a shortcut if nothing must be sent. */
1349 if (unlikely(i == 0))
1351 /* Check whether completion threshold has been reached. */
1352 /* "j" includes both packets and segments. */
1353 comp = txq->elts_comp + j;
1354 if (comp >= MLX5_TX_COMP_THRESH) {
1355 volatile struct mlx5_wqe *wqe = mpw.wqe;
1357 /* Request completion on last WQE. */
1358 wqe->ctrl[2] = htonl(8);
1359 /* Save elts_head in unused "immediate" field of WQE. */
1360 wqe->ctrl[3] = elts_head;
1363 txq->elts_comp = comp;
1365 #ifdef MLX5_PMD_SOFT_COUNTERS
1366 /* Increment sent packets counter. */
1367 txq->stats.opackets += i;
1369 /* Ring QP doorbell. */
1370 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1371 mlx5_mpw_inline_close(txq, &mpw);
1372 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1373 mlx5_mpw_close(txq, &mpw);
1374 mlx5_tx_dbrec(txq, mpw.wqe);
1375 txq->elts_head = elts_head;
1380 * Open an Enhanced MPW session.
1383 * Pointer to TX queue structure.
1385 * Pointer to MPW session structure.
1390 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1392 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1394 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1396 mpw->total_len = sizeof(struct mlx5_wqe);
1397 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1398 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1399 (txq->wqe_ci << 8) |
1400 MLX5_OPCODE_ENHANCED_MPSW);
1401 mpw->wqe->ctrl[2] = 0;
1402 mpw->wqe->ctrl[3] = 0;
1403 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1404 if (unlikely(padding)) {
1405 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1407 /* Pad the first 2 DWORDs with zero-length inline header. */
1408 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1409 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1410 htonl(MLX5_INLINE_SEG);
1411 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1412 /* Start from the next WQEBB. */
1413 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1415 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1420 * Close an Enhanced MPW session.
1423 * Pointer to TX queue structure.
1425 * Pointer to MPW session structure.
1428 * Number of consumed WQEs.
1430 static inline uint16_t
1431 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1435 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1438 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1439 mpw->state = MLX5_MPW_STATE_CLOSED;
1440 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1446 * DPDK callback for TX with Enhanced MPW support.
1449 * Generic pointer to TX queue structure.
1451 * Packets to transmit.
1453 * Number of packets in array.
1456 * Number of packets successfully transmitted (<= pkts_n).
1459 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1461 struct txq *txq = (struct txq *)dpdk_txq;
1462 uint16_t elts_head = txq->elts_head;
1463 const uint16_t elts_n = 1 << txq->elts_n;
1464 const uint16_t elts_m = elts_n - 1;
1469 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1470 unsigned int mpw_room = 0;
1471 unsigned int inl_pad = 0;
1473 struct mlx5_mpw mpw = {
1474 .state = MLX5_MPW_STATE_CLOSED,
1477 if (unlikely(!pkts_n))
1479 /* Start processing. */
1481 max_elts = (elts_n - (elts_head - txq->elts_tail));
1482 /* A CQE slot must always be available. */
1483 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1484 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1485 if (unlikely(!max_wqe))
1488 struct rte_mbuf *buf = *(pkts++);
1492 unsigned int do_inline = 0; /* Whether inline is possible. */
1494 unsigned int segs_n = buf->nb_segs;
1495 uint32_t cs_flags = 0;
1498 * Make sure there is enough room to store this packet and
1499 * that one ring entry remains unused.
1502 if (max_elts - j < segs_n)
1504 /* Do not bother with large packets MPW cannot handle. */
1505 if (segs_n > MLX5_MPW_DSEG_MAX)
1507 /* Should we enable HW CKSUM offload. */
1509 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1510 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1511 /* Retrieve packet information. */
1512 length = PKT_LEN(buf);
1513 /* Start new session if:
1514 * - multi-segment packet
1515 * - no space left even for a dseg
1516 * - next packet can be inlined with a new WQE
1518 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1521 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1522 if ((segs_n != 1) ||
1523 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1525 (length <= txq->inline_max_packet_sz &&
1526 inl_pad + sizeof(inl_hdr) + length >
1528 (mpw.wqe->eseg.cs_flags != cs_flags))
1529 max_wqe -= mlx5_empw_close(txq, &mpw);
1531 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1532 if (unlikely(segs_n != 1)) {
1533 /* Fall back to legacy MPW.
1534 * A MPW session consumes 2 WQEs at most to
1535 * include MLX5_MPW_DSEG_MAX pointers.
1537 if (unlikely(max_wqe < 2))
1539 mlx5_mpw_new(txq, &mpw, length);
1541 /* In Enhanced MPW, inline as much as the budget
1542 * is allowed. The remaining space is to be
1543 * filled with dsegs. If the title WQEBB isn't
1544 * padded, it will have 2 dsegs there.
1546 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1547 (max_inline ? max_inline :
1548 pkts_n * MLX5_WQE_DWORD_SIZE) +
1550 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1553 /* Don't pad the title WQEBB to not waste WQ. */
1554 mlx5_empw_new(txq, &mpw, 0);
1555 mpw_room -= mpw.total_len;
1558 length <= txq->inline_max_packet_sz &&
1559 sizeof(inl_hdr) + length <= mpw_room &&
1562 mpw.wqe->eseg.cs_flags = cs_flags;
1564 /* Evaluate whether the next packet can be inlined.
1565 * Inlininig is possible when:
1566 * - length is less than configured value
1567 * - length fits for remaining space
1568 * - not required to fill the title WQEBB with dsegs
1571 length <= txq->inline_max_packet_sz &&
1572 inl_pad + sizeof(inl_hdr) + length <=
1574 (!txq->mpw_hdr_dseg ||
1575 mpw.total_len >= MLX5_WQE_SIZE);
1577 /* Multi-segment packets must be alone in their MPW. */
1578 assert((segs_n == 1) || (mpw.pkts_n == 0));
1579 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1580 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1584 volatile struct mlx5_wqe_data_seg *dseg;
1587 (*txq->elts)[elts_head++ & elts_m] = buf;
1588 dseg = mpw.data.dseg[mpw.pkts_n];
1589 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1590 *dseg = (struct mlx5_wqe_data_seg){
1591 .byte_count = htonl(DATA_LEN(buf)),
1592 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1593 .addr = htonll(addr),
1595 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1596 length += DATA_LEN(buf);
1602 /* A multi-segmented packet takes one MPW session.
1603 * TODO: Pack more multi-segmented packets if possible.
1605 mlx5_mpw_close(txq, &mpw);
1610 } else if (do_inline) {
1611 /* Inline packet into WQE. */
1614 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1615 assert(length == DATA_LEN(buf));
1616 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1617 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1618 mpw.data.raw = (volatile void *)
1619 ((uintptr_t)mpw.data.raw + inl_pad);
1620 max = tx_mlx5_wq_tailroom(txq,
1621 (void *)(uintptr_t)mpw.data.raw);
1622 /* Copy inline header. */
1623 mpw.data.raw = (volatile void *)
1625 (void *)(uintptr_t)mpw.data.raw,
1628 (void *)(uintptr_t)txq->wqes,
1630 max = tx_mlx5_wq_tailroom(txq,
1631 (void *)(uintptr_t)mpw.data.raw);
1632 /* Copy packet data. */
1633 mpw.data.raw = (volatile void *)
1635 (void *)(uintptr_t)mpw.data.raw,
1638 (void *)(uintptr_t)txq->wqes,
1641 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1642 /* No need to get completion as the entire packet is
1643 * copied to WQ. Free the buf right away.
1645 rte_pktmbuf_free_seg(buf);
1646 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1647 /* Add pad in the next packet if any. */
1648 inl_pad = (((uintptr_t)mpw.data.raw +
1649 (MLX5_WQE_DWORD_SIZE - 1)) &
1650 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1651 (uintptr_t)mpw.data.raw;
1653 /* No inline. Load a dseg of packet pointer. */
1654 volatile rte_v128u32_t *dseg;
1656 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1657 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1658 assert(length == DATA_LEN(buf));
1659 if (!tx_mlx5_wq_tailroom(txq,
1660 (void *)((uintptr_t)mpw.data.raw
1662 dseg = (volatile void *)txq->wqes;
1664 dseg = (volatile void *)
1665 ((uintptr_t)mpw.data.raw +
1667 (*txq->elts)[elts_head++ & elts_m] = buf;
1668 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1669 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1670 rte_prefetch2((void *)(addr +
1671 n * RTE_CACHE_LINE_SIZE));
1672 naddr = htonll(addr);
1673 *dseg = (rte_v128u32_t) {
1675 txq_mp2mr(txq, txq_mb2mp(buf)),
1679 mpw.data.raw = (volatile void *)(dseg + 1);
1680 mpw.total_len += (inl_pad + sizeof(*dseg));
1683 mpw_room -= (inl_pad + sizeof(*dseg));
1686 #ifdef MLX5_PMD_SOFT_COUNTERS
1687 /* Increment sent bytes counter. */
1688 txq->stats.obytes += length;
1691 } while (i < pkts_n);
1692 /* Take a shortcut if nothing must be sent. */
1693 if (unlikely(i == 0))
1695 /* Check whether completion threshold has been reached. */
1696 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1697 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1698 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1699 volatile struct mlx5_wqe *wqe = mpw.wqe;
1701 /* Request completion on last WQE. */
1702 wqe->ctrl[2] = htonl(8);
1703 /* Save elts_head in unused "immediate" field of WQE. */
1704 wqe->ctrl[3] = elts_head;
1706 txq->mpw_comp = txq->wqe_ci;
1709 txq->elts_comp += j;
1711 #ifdef MLX5_PMD_SOFT_COUNTERS
1712 /* Increment sent packets counter. */
1713 txq->stats.opackets += i;
1715 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1716 mlx5_empw_close(txq, &mpw);
1717 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1718 mlx5_mpw_close(txq, &mpw);
1719 /* Ring QP doorbell. */
1720 mlx5_tx_dbrec(txq, mpw.wqe);
1721 txq->elts_head = elts_head;
1726 * Translate RX completion flags to packet type.
1731 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1734 * Packet type for struct rte_mbuf.
1736 static inline uint32_t
1737 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1740 uint16_t flags = ntohs(cqe->hdr_type_etc);
1742 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1745 MLX5_CQE_RX_IPV4_PACKET,
1746 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1748 MLX5_CQE_RX_IPV6_PACKET,
1749 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1750 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1751 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1752 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1756 MLX5_CQE_L3_HDR_TYPE_IPV6,
1757 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1759 MLX5_CQE_L3_HDR_TYPE_IPV4,
1760 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1766 * Get size of the next packet for a given CQE. For compressed CQEs, the
1767 * consumer index is updated only once all packets of the current one have
1771 * Pointer to RX queue.
1774 * @param[out] rss_hash
1775 * Packet RSS Hash result.
1778 * Packet size in bytes (0 if there is none), -1 in case of completion
1782 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1783 uint16_t cqe_cnt, uint32_t *rss_hash)
1785 struct rxq_zip *zip = &rxq->zip;
1786 uint16_t cqe_n = cqe_cnt + 1;
1790 /* Process compressed data in the CQE and mini arrays. */
1792 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1793 (volatile struct mlx5_mini_cqe8 (*)[8])
1794 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1796 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1797 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1798 if ((++zip->ai & 7) == 0) {
1799 /* Invalidate consumed CQEs */
1802 while (idx != end) {
1803 (*rxq->cqes)[idx & cqe_cnt].op_own =
1804 MLX5_CQE_INVALIDATE;
1808 * Increment consumer index to skip the number of
1809 * CQEs consumed. Hardware leaves holes in the CQ
1810 * ring for software use.
1815 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1816 /* Invalidate the rest */
1820 while (idx != end) {
1821 (*rxq->cqes)[idx & cqe_cnt].op_own =
1822 MLX5_CQE_INVALIDATE;
1825 rxq->cq_ci = zip->cq_ci;
1828 /* No compressed data, get next CQE and verify if it is compressed. */
1833 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1834 if (unlikely(ret == 1))
1837 op_own = cqe->op_own;
1838 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1839 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1840 (volatile struct mlx5_mini_cqe8 (*)[8])
1841 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1844 /* Fix endianness. */
1845 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1847 * Current mini array position is the one returned by
1850 * If completion comprises several mini arrays, as a
1851 * special case the second one is located 7 CQEs after
1852 * the initial CQE instead of 8 for subsequent ones.
1854 zip->ca = rxq->cq_ci;
1855 zip->na = zip->ca + 7;
1856 /* Compute the next non compressed CQE. */
1858 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1859 /* Get packet size to return. */
1860 len = ntohl((*mc)[0].byte_cnt);
1861 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1863 /* Prefetch all the entries to be invalidated */
1866 while (idx != end) {
1867 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1871 len = ntohl(cqe->byte_cnt);
1872 *rss_hash = ntohl(cqe->rx_hash_res);
1874 /* Error while receiving packet. */
1875 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1882 * Translate RX completion flags to offload flags.
1885 * Pointer to RX queue structure.
1890 * Offload flags (ol_flags) for struct rte_mbuf.
1892 static inline uint32_t
1893 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1895 uint32_t ol_flags = 0;
1896 uint16_t flags = ntohs(cqe->hdr_type_etc);
1900 MLX5_CQE_RX_L3_HDR_VALID,
1901 PKT_RX_IP_CKSUM_GOOD) |
1903 MLX5_CQE_RX_L4_HDR_VALID,
1904 PKT_RX_L4_CKSUM_GOOD);
1905 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1908 MLX5_CQE_RX_L3_HDR_VALID,
1909 PKT_RX_IP_CKSUM_GOOD) |
1911 MLX5_CQE_RX_L4_HDR_VALID,
1912 PKT_RX_L4_CKSUM_GOOD);
1917 * DPDK callback for RX.
1920 * Generic pointer to RX queue structure.
1922 * Array to store received packets.
1924 * Maximum number of packets in array.
1927 * Number of packets successfully received (<= pkts_n).
1930 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1932 struct rxq *rxq = dpdk_rxq;
1933 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1934 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1935 const unsigned int sges_n = rxq->sges_n;
1936 struct rte_mbuf *pkt = NULL;
1937 struct rte_mbuf *seg = NULL;
1938 volatile struct mlx5_cqe *cqe =
1939 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1941 unsigned int rq_ci = rxq->rq_ci << sges_n;
1942 int len = 0; /* keep its value across iterations. */
1945 unsigned int idx = rq_ci & wqe_cnt;
1946 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1947 struct rte_mbuf *rep = (*rxq->elts)[idx];
1948 uint32_t rss_hash_res = 0;
1956 rep = rte_mbuf_raw_alloc(rxq->mp);
1957 if (unlikely(rep == NULL)) {
1958 ++rxq->stats.rx_nombuf;
1961 * no buffers before we even started,
1962 * bail out silently.
1966 while (pkt != seg) {
1967 assert(pkt != (*rxq->elts)[idx]);
1971 rte_mbuf_raw_free(pkt);
1977 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1978 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1981 rte_mbuf_raw_free(rep);
1984 if (unlikely(len == -1)) {
1985 /* RX error, packet is likely too large. */
1986 rte_mbuf_raw_free(rep);
1987 ++rxq->stats.idropped;
1991 assert(len >= (rxq->crc_present << 2));
1992 /* Update packet information. */
1993 pkt->packet_type = 0;
1995 if (rss_hash_res && rxq->rss_hash) {
1996 pkt->hash.rss = rss_hash_res;
1997 pkt->ol_flags = PKT_RX_RSS_HASH;
2000 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2001 pkt->ol_flags |= PKT_RX_FDIR;
2002 if (cqe->sop_drop_qpn !=
2003 htonl(MLX5_FLOW_MARK_DEFAULT)) {
2004 uint32_t mark = cqe->sop_drop_qpn;
2006 pkt->ol_flags |= PKT_RX_FDIR_ID;
2008 mlx5_flow_mark_get(mark);
2011 if (rxq->csum | rxq->csum_l2tun) {
2012 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2013 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2015 if (rxq->vlan_strip &&
2016 (cqe->hdr_type_etc &
2017 htons(MLX5_CQE_VLAN_STRIPPED))) {
2018 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2019 PKT_RX_VLAN_STRIPPED;
2020 pkt->vlan_tci = ntohs(cqe->vlan_info);
2022 if (rxq->crc_present)
2023 len -= ETHER_CRC_LEN;
2026 DATA_LEN(rep) = DATA_LEN(seg);
2027 PKT_LEN(rep) = PKT_LEN(seg);
2028 SET_DATA_OFF(rep, DATA_OFF(seg));
2029 PORT(rep) = PORT(seg);
2030 (*rxq->elts)[idx] = rep;
2032 * Fill NIC descriptor with the new buffer. The lkey and size
2033 * of the buffers are already known, only the buffer address
2036 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2037 if (len > DATA_LEN(seg)) {
2038 len -= DATA_LEN(seg);
2043 DATA_LEN(seg) = len;
2044 #ifdef MLX5_PMD_SOFT_COUNTERS
2045 /* Increment bytes counter. */
2046 rxq->stats.ibytes += PKT_LEN(pkt);
2048 /* Return packet. */
2054 /* Align consumer index to the next stride. */
2059 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2061 /* Update the consumer index. */
2062 rxq->rq_ci = rq_ci >> sges_n;
2064 *rxq->cq_db = htonl(rxq->cq_ci);
2066 *rxq->rq_db = htonl(rxq->rq_ci);
2067 #ifdef MLX5_PMD_SOFT_COUNTERS
2068 /* Increment packets counter. */
2069 rxq->stats.ipackets += i;
2075 * Dummy DPDK callback for TX.
2077 * This function is used to temporarily replace the real callback during
2078 * unsafe control operations on the queue, or in case of error.
2081 * Generic pointer to TX queue structure.
2083 * Packets to transmit.
2085 * Number of packets in array.
2088 * Number of packets successfully transmitted (<= pkts_n).
2091 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2100 * Dummy DPDK callback for RX.
2102 * This function is used to temporarily replace the real callback during
2103 * unsafe control operations on the queue, or in case of error.
2106 * Generic pointer to RX queue structure.
2108 * Array to store received packets.
2110 * Maximum number of packets in array.
2113 * Number of packets successfully received (<= pkts_n).
2116 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)