4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq) __attribute__((always_inline));
87 static inline uint32_t
88 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
89 __attribute__((always_inline));
92 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, uint32_t *rss_hash)
94 __attribute__((always_inline));
96 static inline uint32_t
97 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
98 __attribute__((always_inline));
103 * Verify or set magic value in CQE.
112 check_cqe_seen(volatile struct mlx5_cqe *cqe)
114 static const uint8_t magic[] = "seen";
115 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
119 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
120 if (!ret || (*buf)[i] != magic[i]) {
122 (*buf)[i] = magic[i];
130 * Check whether CQE is valid.
135 * Size of completion queue.
140 * 0 on success, 1 on failure.
143 check_cqe(volatile struct mlx5_cqe *cqe,
144 unsigned int cqes_n, const uint16_t ci)
146 uint16_t idx = ci & cqes_n;
147 uint8_t op_own = cqe->op_own;
148 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
149 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
151 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
152 return 1; /* No CQE. */
154 if ((op_code == MLX5_CQE_RESP_ERR) ||
155 (op_code == MLX5_CQE_REQ_ERR)) {
156 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
157 uint8_t syndrome = err_cqe->syndrome;
159 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
160 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
162 if (!check_cqe_seen(cqe))
163 ERROR("unexpected CQE error %u (0x%02x)"
165 op_code, op_code, syndrome);
167 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
168 (op_code != MLX5_CQE_REQ)) {
169 if (!check_cqe_seen(cqe))
170 ERROR("unexpected CQE opcode %u (0x%02x)",
179 * Return the address of the WQE.
182 * Pointer to TX queue structure.
184 * WQE consumer index.
189 static inline uintptr_t *
190 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
192 ci &= ((1 << txq->wqe_n) - 1);
193 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
197 * Manage TX completions.
199 * When sending a burst, mlx5_tx_burst() posts several WRs.
202 * Pointer to TX queue structure.
205 txq_complete(struct txq *txq)
207 const unsigned int elts_n = 1 << txq->elts_n;
208 const unsigned int cqe_n = 1 << txq->cqe_n;
209 const unsigned int cqe_cnt = cqe_n - 1;
210 uint16_t elts_free = txq->elts_tail;
212 uint16_t cq_ci = txq->cq_ci;
213 volatile struct mlx5_cqe *cqe = NULL;
214 volatile struct mlx5_wqe_ctrl *ctrl;
217 volatile struct mlx5_cqe *tmp;
219 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
220 if (check_cqe(tmp, cqe_n, cq_ci))
224 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
225 if (!check_cqe_seen(cqe))
226 ERROR("unexpected compressed CQE, TX stopped");
229 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
230 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
231 if (!check_cqe_seen(cqe))
232 ERROR("unexpected error CQE, TX stopped");
238 if (unlikely(cqe == NULL))
240 ctrl = (volatile struct mlx5_wqe_ctrl *)
241 tx_mlx5_wqe(txq, ntohs(cqe->wqe_counter));
242 elts_tail = ctrl->ctrl3;
243 assert(elts_tail < (1 << txq->wqe_n));
245 while (elts_free != elts_tail) {
246 struct rte_mbuf *elt = (*txq->elts)[elts_free];
247 unsigned int elts_free_next =
248 (elts_free + 1) & (elts_n - 1);
249 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
253 memset(&(*txq->elts)[elts_free],
255 sizeof((*txq->elts)[elts_free]));
257 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
258 /* Only one segment needs to be freed. */
259 rte_pktmbuf_free_seg(elt);
260 elts_free = elts_free_next;
263 txq->elts_tail = elts_tail;
264 /* Update the consumer index. */
266 *txq->cq_db = htonl(cq_ci);
270 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
271 * the cloned mbuf is allocated is returned instead.
277 * Memory pool where data is located for given mbuf.
279 static struct rte_mempool *
280 txq_mb2mp(struct rte_mbuf *buf)
282 if (unlikely(RTE_MBUF_INDIRECT(buf)))
283 return rte_mbuf_from_indirect(buf)->pool;
288 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
289 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
290 * remove an entry first.
293 * Pointer to TX queue structure.
295 * Memory Pool for which a Memory Region lkey must be returned.
298 * mr->lkey on success, (uint32_t)-1 on failure.
300 static inline uint32_t
301 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
304 uint32_t lkey = (uint32_t)-1;
306 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
307 if (unlikely(txq->mp2mr[i].mp == NULL)) {
308 /* Unknown MP, add a new MR for it. */
311 if (txq->mp2mr[i].mp == mp) {
312 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
313 assert(htonl(txq->mp2mr[i].mr->lkey) ==
315 lkey = txq->mp2mr[i].lkey;
319 if (unlikely(lkey == (uint32_t)-1))
320 lkey = txq_mp2mr_reg(txq, mp, i);
325 * Ring TX queue doorbell.
328 * Pointer to TX queue structure.
331 mlx5_tx_dbrec(struct txq *txq)
333 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
335 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
336 htonl(txq->qp_num_8s),
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
344 memcpy(dst, (uint8_t *)data, 16);
345 txq->bf_offset ^= (1 << txq->bf_buf_size);
352 * Pointer to TX queue structure.
354 * CQE consumer index.
357 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
359 volatile struct mlx5_cqe *cqe;
361 cqe = &(*txq->cqes)[ci & ((1 << txq->cqe_n) - 1)];
366 * DPDK callback for TX.
369 * Generic pointer to TX queue structure.
371 * Packets to transmit.
373 * Number of packets in array.
376 * Number of packets successfully transmitted (<= pkts_n).
379 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
381 struct txq *txq = (struct txq *)dpdk_txq;
382 uint16_t elts_head = txq->elts_head;
383 const unsigned int elts_n = 1 << txq->elts_n;
388 volatile struct mlx5_wqe_v *wqe = NULL;
389 unsigned int segs_n = 0;
390 struct rte_mbuf *buf = NULL;
393 if (unlikely(!pkts_n))
395 /* Prefetch first packet cacheline. */
396 tx_prefetch_cqe(txq, txq->cq_ci);
397 tx_prefetch_cqe(txq, txq->cq_ci + 1);
398 rte_prefetch0(*pkts);
399 /* Start processing. */
401 max = (elts_n - (elts_head - txq->elts_tail));
405 volatile rte_v128u32_t *dseg = NULL;
410 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
412 uint8_t cs_flags = 0;
413 #ifdef MLX5_PMD_SOFT_COUNTERS
414 uint32_t total_length = 0;
419 segs_n = buf->nb_segs;
421 * Make sure there is enough room to store this packet and
422 * that one ring entry remains unused.
425 if (max < segs_n + 1)
431 wqe = (volatile struct mlx5_wqe_v *)
432 tx_mlx5_wqe(txq, txq->wqe_ci);
433 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
435 rte_prefetch0(*pkts);
436 addr = rte_pktmbuf_mtod(buf, uintptr_t);
437 length = DATA_LEN(buf);
438 ehdr[0] = ((uint8_t *)addr)[0];
439 ehdr[1] = ((uint8_t *)addr)[1];
440 #ifdef MLX5_PMD_SOFT_COUNTERS
441 total_length = length;
443 assert(length >= MLX5_WQE_DWORD_SIZE);
444 /* Update element. */
445 (*txq->elts)[elts_head] = buf;
446 elts_head = (elts_head + 1) & (elts_n - 1);
447 /* Prefetch next buffer data. */
449 volatile void *pkt_addr;
451 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
452 rte_prefetch0(pkt_addr);
454 /* Should we enable HW CKSUM offload */
456 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
457 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
459 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
461 * Start by copying the Ethernet header minus the first two
462 * bytes which will be appended at the end of the Ethernet
465 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2, 16);
466 length -= MLX5_WQE_DWORD_SIZE;
467 addr += MLX5_WQE_DWORD_SIZE;
468 /* Replace the Ethernet type by the VLAN if necessary. */
469 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
470 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
472 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - 2 -
474 &vlan, sizeof(vlan));
475 addr -= sizeof(vlan);
476 length += sizeof(vlan);
478 /* Inline if enough room. */
479 if (txq->max_inline != 0) {
480 uintptr_t end = (uintptr_t)
481 (((uintptr_t)txq->wqes) +
482 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
483 uint16_t max_inline =
484 txq->max_inline * RTE_CACHE_LINE_SIZE;
488 * raw starts two bytes before the boundary to
489 * continue the above copy of packet data.
491 raw += MLX5_WQE_DWORD_SIZE - 2;
492 room = end - (uintptr_t)raw;
493 if (room > max_inline) {
494 uintptr_t addr_end = (addr + max_inline) &
495 ~(RTE_CACHE_LINE_SIZE - 1);
496 uint16_t copy_b = ((addr_end - addr) > length) ?
500 rte_memcpy((void *)raw, (void *)addr, copy_b);
503 pkt_inline_sz += copy_b;
505 assert(addr <= addr_end);
508 * 2 DWORDs consumed by the WQE header + 1 DSEG +
509 * the size of the inline part of the packet.
511 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
513 dseg = (volatile rte_v128u32_t *)
515 (ds * MLX5_WQE_DWORD_SIZE));
516 if ((uintptr_t)dseg >= end)
517 dseg = (volatile rte_v128u32_t *)
520 } else if (!segs_n) {
527 * No inline has been done in the packet, only the
528 * Ethernet Header as been stored.
530 dseg = (volatile rte_v128u32_t *)
531 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
534 /* Add the remaining packet as a simple ds. */
535 naddr = htonll(addr);
536 *dseg = (rte_v128u32_t){
538 txq_mp2mr(txq, txq_mb2mp(buf)),
551 * Spill on next WQE when the current one does not have
552 * enough room left. Size of WQE must a be a multiple
553 * of data segment size.
555 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
556 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
557 unsigned int n = (txq->wqe_ci + ((ds + 3) / 4)) &
558 ((1 << txq->wqe_n) - 1);
560 dseg = (volatile rte_v128u32_t *)
562 rte_prefetch0(tx_mlx5_wqe(txq, n + 1));
569 length = DATA_LEN(buf);
570 #ifdef MLX5_PMD_SOFT_COUNTERS
571 total_length += length;
573 /* Store segment information. */
574 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
575 *dseg = (rte_v128u32_t){
577 txq_mp2mr(txq, txq_mb2mp(buf)),
581 (*txq->elts)[elts_head] = buf;
582 elts_head = (elts_head + 1) & (elts_n - 1);
591 /* Initialize known and common part of the WQE structure. */
592 wqe->ctrl = (rte_v128u32_t){
593 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
594 htonl(txq->qp_num_8s | ds),
598 wqe->eseg = (rte_v128u32_t){
602 (ehdr[1] << 24) | (ehdr[0] << 16) |
603 htons(pkt_inline_sz),
605 txq->wqe_ci += (ds + 3) / 4;
606 #ifdef MLX5_PMD_SOFT_COUNTERS
607 /* Increment sent bytes counter. */
608 txq->stats.obytes += total_length;
611 /* Take a shortcut if nothing must be sent. */
612 if (unlikely(i == 0))
614 /* Check whether completion threshold has been reached. */
615 comp = txq->elts_comp + i + j;
616 if (comp >= MLX5_TX_COMP_THRESH) {
617 volatile struct mlx5_wqe_ctrl *w =
618 (volatile struct mlx5_wqe_ctrl *)wqe;
620 /* Request completion on last WQE. */
622 /* Save elts_head in unused "immediate" field of WQE. */
623 w->ctrl3 = elts_head;
626 txq->elts_comp = comp;
628 #ifdef MLX5_PMD_SOFT_COUNTERS
629 /* Increment sent packets counter. */
630 txq->stats.opackets += i;
632 /* Ring QP doorbell. */
634 txq->elts_head = elts_head;
639 * Open a MPW session.
642 * Pointer to TX queue structure.
644 * Pointer to MPW session structure.
649 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
651 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
652 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
653 (volatile struct mlx5_wqe_data_seg (*)[])
654 tx_mlx5_wqe(txq, idx + 1);
656 mpw->state = MLX5_MPW_STATE_OPENED;
660 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
661 mpw->wqe->eseg.mss = htons(length);
662 mpw->wqe->eseg.inline_hdr_sz = 0;
663 mpw->wqe->eseg.rsvd0 = 0;
664 mpw->wqe->eseg.rsvd1 = 0;
665 mpw->wqe->eseg.rsvd2 = 0;
666 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
667 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
668 mpw->wqe->ctrl[2] = 0;
669 mpw->wqe->ctrl[3] = 0;
670 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
671 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
672 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
673 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
674 mpw->data.dseg[2] = &(*dseg)[0];
675 mpw->data.dseg[3] = &(*dseg)[1];
676 mpw->data.dseg[4] = &(*dseg)[2];
680 * Close a MPW session.
683 * Pointer to TX queue structure.
685 * Pointer to MPW session structure.
688 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
690 unsigned int num = mpw->pkts_n;
693 * Store size in multiple of 16 bytes. Control and Ethernet segments
696 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
697 mpw->state = MLX5_MPW_STATE_CLOSED;
702 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
703 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
707 * DPDK callback for TX with MPW support.
710 * Generic pointer to TX queue structure.
712 * Packets to transmit.
714 * Number of packets in array.
717 * Number of packets successfully transmitted (<= pkts_n).
720 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
722 struct txq *txq = (struct txq *)dpdk_txq;
723 uint16_t elts_head = txq->elts_head;
724 const unsigned int elts_n = 1 << txq->elts_n;
729 struct mlx5_mpw mpw = {
730 .state = MLX5_MPW_STATE_CLOSED,
733 if (unlikely(!pkts_n))
735 /* Prefetch first packet cacheline. */
736 tx_prefetch_cqe(txq, txq->cq_ci);
737 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
738 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
739 /* Start processing. */
741 max = (elts_n - (elts_head - txq->elts_tail));
745 struct rte_mbuf *buf = *(pkts++);
746 unsigned int elts_head_next;
748 unsigned int segs_n = buf->nb_segs;
749 uint32_t cs_flags = 0;
752 * Make sure there is enough room to store this packet and
753 * that one ring entry remains unused.
756 if (max < segs_n + 1)
758 /* Do not bother with large packets MPW cannot handle. */
759 if (segs_n > MLX5_MPW_DSEG_MAX)
763 /* Should we enable HW CKSUM offload */
765 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
766 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
767 /* Retrieve packet information. */
768 length = PKT_LEN(buf);
770 /* Start new session if packet differs. */
771 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
772 ((mpw.len != length) ||
774 (mpw.wqe->eseg.cs_flags != cs_flags)))
775 mlx5_mpw_close(txq, &mpw);
776 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
777 mlx5_mpw_new(txq, &mpw, length);
778 mpw.wqe->eseg.cs_flags = cs_flags;
780 /* Multi-segment packets must be alone in their MPW. */
781 assert((segs_n == 1) || (mpw.pkts_n == 0));
782 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
786 volatile struct mlx5_wqe_data_seg *dseg;
789 elts_head_next = (elts_head + 1) & (elts_n - 1);
791 (*txq->elts)[elts_head] = buf;
792 dseg = mpw.data.dseg[mpw.pkts_n];
793 addr = rte_pktmbuf_mtod(buf, uintptr_t);
794 *dseg = (struct mlx5_wqe_data_seg){
795 .byte_count = htonl(DATA_LEN(buf)),
796 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
797 .addr = htonll(addr),
799 elts_head = elts_head_next;
800 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
801 length += DATA_LEN(buf);
807 assert(length == mpw.len);
808 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
809 mlx5_mpw_close(txq, &mpw);
810 elts_head = elts_head_next;
811 #ifdef MLX5_PMD_SOFT_COUNTERS
812 /* Increment sent bytes counter. */
813 txq->stats.obytes += length;
817 /* Take a shortcut if nothing must be sent. */
818 if (unlikely(i == 0))
820 /* Check whether completion threshold has been reached. */
821 /* "j" includes both packets and segments. */
822 comp = txq->elts_comp + j;
823 if (comp >= MLX5_TX_COMP_THRESH) {
824 volatile struct mlx5_wqe *wqe = mpw.wqe;
826 /* Request completion on last WQE. */
827 wqe->ctrl[2] = htonl(8);
828 /* Save elts_head in unused "immediate" field of WQE. */
829 wqe->ctrl[3] = elts_head;
832 txq->elts_comp = comp;
834 #ifdef MLX5_PMD_SOFT_COUNTERS
835 /* Increment sent packets counter. */
836 txq->stats.opackets += i;
838 /* Ring QP doorbell. */
839 if (mpw.state == MLX5_MPW_STATE_OPENED)
840 mlx5_mpw_close(txq, &mpw);
842 txq->elts_head = elts_head;
847 * Open a MPW inline session.
850 * Pointer to TX queue structure.
852 * Pointer to MPW session structure.
857 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
859 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
860 struct mlx5_wqe_inl_small *inl;
862 mpw->state = MLX5_MPW_INL_STATE_OPENED;
866 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
867 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
870 mpw->wqe->ctrl[2] = 0;
871 mpw->wqe->ctrl[3] = 0;
872 mpw->wqe->eseg.mss = htons(length);
873 mpw->wqe->eseg.inline_hdr_sz = 0;
874 mpw->wqe->eseg.cs_flags = 0;
875 mpw->wqe->eseg.rsvd0 = 0;
876 mpw->wqe->eseg.rsvd1 = 0;
877 mpw->wqe->eseg.rsvd2 = 0;
878 inl = (struct mlx5_wqe_inl_small *)
879 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
880 mpw->data.raw = (uint8_t *)&inl->raw;
884 * Close a MPW inline session.
887 * Pointer to TX queue structure.
889 * Pointer to MPW session structure.
892 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
895 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
896 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
898 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
900 * Store size in multiple of 16 bytes. Control and Ethernet segments
903 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
904 mpw->state = MLX5_MPW_STATE_CLOSED;
905 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
906 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
910 * DPDK callback for TX with MPW inline support.
913 * Generic pointer to TX queue structure.
915 * Packets to transmit.
917 * Number of packets in array.
920 * Number of packets successfully transmitted (<= pkts_n).
923 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
926 struct txq *txq = (struct txq *)dpdk_txq;
927 uint16_t elts_head = txq->elts_head;
928 const unsigned int elts_n = 1 << txq->elts_n;
933 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
934 struct mlx5_mpw mpw = {
935 .state = MLX5_MPW_STATE_CLOSED,
938 if (unlikely(!pkts_n))
940 /* Prefetch first packet cacheline. */
941 tx_prefetch_cqe(txq, txq->cq_ci);
942 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
943 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
944 /* Start processing. */
946 max = (elts_n - (elts_head - txq->elts_tail));
950 struct rte_mbuf *buf = *(pkts++);
951 unsigned int elts_head_next;
954 unsigned int segs_n = buf->nb_segs;
955 uint32_t cs_flags = 0;
958 * Make sure there is enough room to store this packet and
959 * that one ring entry remains unused.
962 if (max < segs_n + 1)
964 /* Do not bother with large packets MPW cannot handle. */
965 if (segs_n > MLX5_MPW_DSEG_MAX)
969 /* Should we enable HW CKSUM offload */
971 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
972 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
973 /* Retrieve packet information. */
974 length = PKT_LEN(buf);
975 /* Start new session if packet differs. */
976 if (mpw.state == MLX5_MPW_STATE_OPENED) {
977 if ((mpw.len != length) ||
979 (mpw.wqe->eseg.cs_flags != cs_flags))
980 mlx5_mpw_close(txq, &mpw);
981 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
982 if ((mpw.len != length) ||
984 (length > inline_room) ||
985 (mpw.wqe->eseg.cs_flags != cs_flags)) {
986 mlx5_mpw_inline_close(txq, &mpw);
988 txq->max_inline * RTE_CACHE_LINE_SIZE;
991 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
993 (length > inline_room)) {
994 mlx5_mpw_new(txq, &mpw, length);
995 mpw.wqe->eseg.cs_flags = cs_flags;
997 mlx5_mpw_inline_new(txq, &mpw, length);
998 mpw.wqe->eseg.cs_flags = cs_flags;
1001 /* Multi-segment packets must be alone in their MPW. */
1002 assert((segs_n == 1) || (mpw.pkts_n == 0));
1003 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1004 assert(inline_room ==
1005 txq->max_inline * RTE_CACHE_LINE_SIZE);
1006 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1010 volatile struct mlx5_wqe_data_seg *dseg;
1013 (elts_head + 1) & (elts_n - 1);
1015 (*txq->elts)[elts_head] = buf;
1016 dseg = mpw.data.dseg[mpw.pkts_n];
1017 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1018 *dseg = (struct mlx5_wqe_data_seg){
1019 .byte_count = htonl(DATA_LEN(buf)),
1020 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1021 .addr = htonll(addr),
1023 elts_head = elts_head_next;
1024 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1025 length += DATA_LEN(buf);
1031 assert(length == mpw.len);
1032 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1033 mlx5_mpw_close(txq, &mpw);
1037 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1038 assert(length <= inline_room);
1039 assert(length == DATA_LEN(buf));
1040 elts_head_next = (elts_head + 1) & (elts_n - 1);
1041 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1042 (*txq->elts)[elts_head] = buf;
1043 /* Maximum number of bytes before wrapping. */
1044 max = ((((uintptr_t)(txq->wqes)) +
1047 (uintptr_t)mpw.data.raw);
1049 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1052 mpw.data.raw = (volatile void *)txq->wqes;
1053 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1054 (void *)(addr + max),
1056 mpw.data.raw += length - max;
1058 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1061 mpw.data.raw += length;
1063 if ((uintptr_t)mpw.data.raw ==
1064 (uintptr_t)tx_mlx5_wqe(txq, 1 << txq->wqe_n))
1065 mpw.data.raw = (volatile void *)txq->wqes;
1068 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1069 mlx5_mpw_inline_close(txq, &mpw);
1071 txq->max_inline * RTE_CACHE_LINE_SIZE;
1073 inline_room -= length;
1076 mpw.total_len += length;
1077 elts_head = elts_head_next;
1078 #ifdef MLX5_PMD_SOFT_COUNTERS
1079 /* Increment sent bytes counter. */
1080 txq->stats.obytes += length;
1084 /* Take a shortcut if nothing must be sent. */
1085 if (unlikely(i == 0))
1087 /* Check whether completion threshold has been reached. */
1088 /* "j" includes both packets and segments. */
1089 comp = txq->elts_comp + j;
1090 if (comp >= MLX5_TX_COMP_THRESH) {
1091 volatile struct mlx5_wqe *wqe = mpw.wqe;
1093 /* Request completion on last WQE. */
1094 wqe->ctrl[2] = htonl(8);
1095 /* Save elts_head in unused "immediate" field of WQE. */
1096 wqe->ctrl[3] = elts_head;
1099 txq->elts_comp = comp;
1101 #ifdef MLX5_PMD_SOFT_COUNTERS
1102 /* Increment sent packets counter. */
1103 txq->stats.opackets += i;
1105 /* Ring QP doorbell. */
1106 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1107 mlx5_mpw_inline_close(txq, &mpw);
1108 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1109 mlx5_mpw_close(txq, &mpw);
1111 txq->elts_head = elts_head;
1116 * Translate RX completion flags to packet type.
1121 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1124 * Packet type for struct rte_mbuf.
1126 static inline uint32_t
1127 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1130 uint8_t flags = cqe->l4_hdr_type_etc;
1132 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET)
1135 MLX5_CQE_RX_OUTER_IPV4_PACKET,
1136 RTE_PTYPE_L3_IPV4) |
1138 MLX5_CQE_RX_OUTER_IPV6_PACKET,
1139 RTE_PTYPE_L3_IPV6) |
1141 MLX5_CQE_RX_IPV4_PACKET,
1142 RTE_PTYPE_INNER_L3_IPV4) |
1144 MLX5_CQE_RX_IPV6_PACKET,
1145 RTE_PTYPE_INNER_L3_IPV6);
1149 MLX5_CQE_L3_HDR_TYPE_IPV6,
1150 RTE_PTYPE_L3_IPV6) |
1152 MLX5_CQE_L3_HDR_TYPE_IPV4,
1158 * Get size of the next packet for a given CQE. For compressed CQEs, the
1159 * consumer index is updated only once all packets of the current one have
1163 * Pointer to RX queue.
1166 * @param[out] rss_hash
1167 * Packet RSS Hash result.
1170 * Packet size in bytes (0 if there is none), -1 in case of completion
1174 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1175 uint16_t cqe_cnt, uint32_t *rss_hash)
1177 struct rxq_zip *zip = &rxq->zip;
1178 uint16_t cqe_n = cqe_cnt + 1;
1181 /* Process compressed data in the CQE and mini arrays. */
1183 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1184 (volatile struct mlx5_mini_cqe8 (*)[8])
1185 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1187 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1188 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1189 if ((++zip->ai & 7) == 0) {
1191 * Increment consumer index to skip the number of
1192 * CQEs consumed. Hardware leaves holes in the CQ
1193 * ring for software use.
1198 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1199 uint16_t idx = rxq->cq_ci + 1;
1200 uint16_t end = zip->cq_ci;
1202 while (idx != end) {
1203 (*rxq->cqes)[idx & cqe_cnt].op_own =
1204 MLX5_CQE_INVALIDATE;
1207 rxq->cq_ci = zip->cq_ci;
1210 /* No compressed data, get next CQE and verify if it is compressed. */
1215 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1216 if (unlikely(ret == 1))
1219 op_own = cqe->op_own;
1220 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1221 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1222 (volatile struct mlx5_mini_cqe8 (*)[8])
1223 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1226 /* Fix endianness. */
1227 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1229 * Current mini array position is the one returned by
1232 * If completion comprises several mini arrays, as a
1233 * special case the second one is located 7 CQEs after
1234 * the initial CQE instead of 8 for subsequent ones.
1236 zip->ca = rxq->cq_ci & cqe_cnt;
1237 zip->na = zip->ca + 7;
1238 /* Compute the next non compressed CQE. */
1240 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1241 /* Get packet size to return. */
1242 len = ntohl((*mc)[0].byte_cnt);
1243 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1246 len = ntohl(cqe->byte_cnt);
1247 *rss_hash = ntohl(cqe->rx_hash_res);
1249 /* Error while receiving packet. */
1250 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1257 * Translate RX completion flags to offload flags.
1260 * Pointer to RX queue structure.
1265 * Offload flags (ol_flags) for struct rte_mbuf.
1267 static inline uint32_t
1268 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1270 uint32_t ol_flags = 0;
1271 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1272 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1274 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1275 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1276 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1278 PKT_RX_IP_CKSUM_GOOD);
1279 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1280 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1281 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1282 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1283 ol_flags |= TRANSPOSE(cqe->hds_ip_ext,
1285 PKT_RX_L4_CKSUM_GOOD);
1286 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1288 TRANSPOSE(cqe->l4_hdr_type_etc,
1289 MLX5_CQE_RX_OUTER_IP_CSUM_OK,
1290 PKT_RX_IP_CKSUM_GOOD) |
1291 TRANSPOSE(cqe->l4_hdr_type_etc,
1292 MLX5_CQE_RX_OUTER_TCP_UDP_CSUM_OK,
1293 PKT_RX_L4_CKSUM_GOOD);
1298 * DPDK callback for RX.
1301 * Generic pointer to RX queue structure.
1303 * Array to store received packets.
1305 * Maximum number of packets in array.
1308 * Number of packets successfully received (<= pkts_n).
1311 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1313 struct rxq *rxq = dpdk_rxq;
1314 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1315 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1316 const unsigned int sges_n = rxq->sges_n;
1317 struct rte_mbuf *pkt = NULL;
1318 struct rte_mbuf *seg = NULL;
1319 volatile struct mlx5_cqe *cqe =
1320 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1322 unsigned int rq_ci = rxq->rq_ci << sges_n;
1323 int len; /* keep its value across iterations. */
1326 unsigned int idx = rq_ci & wqe_cnt;
1327 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1328 struct rte_mbuf *rep = (*rxq->elts)[idx];
1329 uint32_t rss_hash_res = 0;
1337 rep = rte_mbuf_raw_alloc(rxq->mp);
1338 if (unlikely(rep == NULL)) {
1339 ++rxq->stats.rx_nombuf;
1342 * no buffers before we even started,
1343 * bail out silently.
1347 while (pkt != seg) {
1348 assert(pkt != (*rxq->elts)[idx]);
1350 rte_mbuf_refcnt_set(pkt, 0);
1351 __rte_mbuf_raw_free(pkt);
1357 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1358 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1361 rte_mbuf_refcnt_set(rep, 0);
1362 __rte_mbuf_raw_free(rep);
1365 if (unlikely(len == -1)) {
1366 /* RX error, packet is likely too large. */
1367 rte_mbuf_refcnt_set(rep, 0);
1368 __rte_mbuf_raw_free(rep);
1369 ++rxq->stats.idropped;
1373 assert(len >= (rxq->crc_present << 2));
1374 /* Update packet information. */
1375 pkt->packet_type = 0;
1377 if (rss_hash_res && rxq->rss_hash) {
1378 pkt->hash.rss = rss_hash_res;
1379 pkt->ol_flags = PKT_RX_RSS_HASH;
1382 ((cqe->sop_drop_qpn !=
1383 htonl(MLX5_FLOW_MARK_INVALID)) ||
1384 (cqe->sop_drop_qpn !=
1385 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1387 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1388 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1389 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1391 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1395 rxq_cq_to_pkt_type(cqe);
1397 rxq_cq_to_ol_flags(rxq, cqe);
1399 if (cqe->l4_hdr_type_etc &
1400 MLX5_CQE_VLAN_STRIPPED) {
1401 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1402 PKT_RX_VLAN_STRIPPED;
1403 pkt->vlan_tci = ntohs(cqe->vlan_info);
1405 if (rxq->crc_present)
1406 len -= ETHER_CRC_LEN;
1410 DATA_LEN(rep) = DATA_LEN(seg);
1411 PKT_LEN(rep) = PKT_LEN(seg);
1412 SET_DATA_OFF(rep, DATA_OFF(seg));
1413 NB_SEGS(rep) = NB_SEGS(seg);
1414 PORT(rep) = PORT(seg);
1416 (*rxq->elts)[idx] = rep;
1418 * Fill NIC descriptor with the new buffer. The lkey and size
1419 * of the buffers are already known, only the buffer address
1422 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1423 if (len > DATA_LEN(seg)) {
1424 len -= DATA_LEN(seg);
1429 DATA_LEN(seg) = len;
1430 #ifdef MLX5_PMD_SOFT_COUNTERS
1431 /* Increment bytes counter. */
1432 rxq->stats.ibytes += PKT_LEN(pkt);
1434 /* Return packet. */
1440 /* Align consumer index to the next stride. */
1445 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1447 /* Update the consumer index. */
1448 rxq->rq_ci = rq_ci >> sges_n;
1450 *rxq->cq_db = htonl(rxq->cq_ci);
1452 *rxq->rq_db = htonl(rxq->rq_ci);
1453 #ifdef MLX5_PMD_SOFT_COUNTERS
1454 /* Increment packets counter. */
1455 rxq->stats.ipackets += i;
1461 * Dummy DPDK callback for TX.
1463 * This function is used to temporarily replace the real callback during
1464 * unsafe control operations on the queue, or in case of error.
1467 * Generic pointer to TX queue structure.
1469 * Packets to transmit.
1471 * Number of packets in array.
1474 * Number of packets successfully transmitted (<= pkts_n).
1477 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1486 * Dummy DPDK callback for RX.
1488 * This function is used to temporarily replace the real callback during
1489 * unsafe control operations on the queue, or in case of error.
1492 * Generic pointer to RX queue structure.
1494 * Array to store received packets.
1496 * Maximum number of packets in array.
1499 * Number of packets successfully received (<= pkts_n).
1502 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)