1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include "mlx5_utils.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* TX burst subroutines return codes. */
38 enum mlx5_txcmp_code {
39 MLX5_TXCMP_CODE_EXIT = 0,
40 MLX5_TXCMP_CODE_ERROR,
41 MLX5_TXCMP_CODE_SINGLE,
42 MLX5_TXCMP_CODE_MULTI,
48 * These defines are used to configure Tx burst routine option set
49 * supported at compile time. The not specified options are optimized out
50 * out due to if conditions can be explicitly calculated at compile time.
51 * The offloads with bigger runtime check (require more CPU cycles to
52 * skip) overhead should have the bigger index - this is needed to
53 * select the better matching routine function if no exact match and
54 * some offloads are not actually requested.
56 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
57 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
58 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
59 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
60 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
61 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
62 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
63 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 /* The most common offloads groups. */
66 #define MLX5_TXOFF_CONFIG_NONE 0
67 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
68 MLX5_TXOFF_CONFIG_TSO | \
69 MLX5_TXOFF_CONFIG_SWP | \
70 MLX5_TXOFF_CONFIG_CSUM | \
71 MLX5_TXOFF_CONFIG_INLINE | \
72 MLX5_TXOFF_CONFIG_VLAN | \
73 MLX5_TXOFF_CONFIG_METADATA)
75 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
77 #define MLX5_TXOFF_DECL(func, olx) \
78 static uint16_t mlx5_tx_burst_##func(void *txq, \
79 struct rte_mbuf **pkts, \
82 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
83 pkts, pkts_n, (olx)); \
86 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
88 static __rte_always_inline uint32_t
89 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
91 static __rte_always_inline int
92 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
95 static __rte_always_inline uint32_t
96 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
98 static __rte_always_inline void
99 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
100 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
102 static __rte_always_inline void
103 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
104 const unsigned int strd_n);
107 mlx5_queue_state_modify(struct rte_eth_dev *dev,
108 struct mlx5_mp_arg_queue_state_modify *sm);
110 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
111 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
114 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
115 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
118 * Build a table to translate Rx completion flags to packet type.
120 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
123 mlx5_set_ptype_table(void)
126 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
128 /* Last entry must not be overwritten, reserved for errored packet. */
129 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
130 (*p)[i] = RTE_PTYPE_UNKNOWN;
132 * The index to the array should have:
133 * bit[1:0] = l3_hdr_type
134 * bit[4:2] = l4_hdr_type
137 * bit[7] = outer_l3_type
140 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
142 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
143 RTE_PTYPE_L4_NONFRAG;
144 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_L4_NONFRAG;
147 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
152 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
154 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
156 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
160 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
162 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
165 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
167 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 /* Repeat with outer_l3_type being set. Just in case. */
170 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_L4_NONFRAG;
172 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_L4_NONFRAG;
174 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
178 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
180 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
184 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
186 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
190 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
192 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
196 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_NONFRAG;
199 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_NONFRAG;
202 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
203 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_NONFRAG;
206 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 /* Tunneled - Fragmented */
210 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_FRAG;
213 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_FRAG;
216 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
223 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_TCP;
226 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_TCP;
229 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_UDP;
263 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_UDP;
266 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
275 * Build a table to translate packet to checksum type of Verbs.
278 mlx5_set_cksum_table(void)
284 * The index should have:
285 * bit[0] = PKT_TX_TCP_SEG
286 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
287 * bit[4] = PKT_TX_IP_CKSUM
288 * bit[8] = PKT_TX_OUTER_IP_CKSUM
291 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
294 /* Tunneled packet. */
295 if (i & (1 << 8)) /* Outer IP. */
296 v |= MLX5_ETH_WQE_L3_CSUM;
297 if (i & (1 << 4)) /* Inner IP. */
298 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
299 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
300 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
303 if (i & (1 << 4)) /* IP. */
304 v |= MLX5_ETH_WQE_L3_CSUM;
305 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
306 v |= MLX5_ETH_WQE_L4_CSUM;
308 mlx5_cksum_table[i] = v;
313 * Build a table to translate packet type of mbuf to SWP type of Verbs.
316 mlx5_set_swp_types_table(void)
322 * The index should have:
323 * bit[0:1] = PKT_TX_L4_MASK
324 * bit[4] = PKT_TX_IPV6
325 * bit[8] = PKT_TX_OUTER_IPV6
326 * bit[9] = PKT_TX_OUTER_UDP
328 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
331 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
333 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
335 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
336 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
337 v |= MLX5_ETH_WQE_L4_INNER_UDP;
338 mlx5_swp_types_table[i] = v;
343 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
344 * Flags must be preliminary initialized to zero.
347 * Pointer to burst routine local context.
349 * Pointer to store Software Parser flags
351 * Configured Tx offloads mask. It is fully defined at
352 * compile time and may be used for optimization.
355 * Software Parser offsets packed in dword.
356 * Software Parser flags are set by pointer.
358 static __rte_always_inline uint32_t
359 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
364 unsigned int idx, off;
367 if (!MLX5_TXOFF_CONFIG(SWP))
369 ol = loc->mbuf->ol_flags;
370 tunnel = ol & PKT_TX_TUNNEL_MASK;
372 * Check whether Software Parser is required.
373 * Only customized tunnels may ask for.
375 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
378 * The index should have:
379 * bit[0:1] = PKT_TX_L4_MASK
380 * bit[4] = PKT_TX_IPV6
381 * bit[8] = PKT_TX_OUTER_IPV6
382 * bit[9] = PKT_TX_OUTER_UDP
384 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
385 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
386 *swp_flags = mlx5_swp_types_table[idx];
388 * Set offsets for SW parser. Since ConnectX-5, SW parser just
389 * complements HW parser. SW parser starts to engage only if HW parser
390 * can't reach a header. For the older devices, HW parser will not kick
391 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
392 * should be set regardless of HW offload.
394 off = loc->mbuf->outer_l2_len;
395 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
396 off += sizeof(struct rte_vlan_hdr);
397 set = (off >> 1) << 8; /* Outer L3 offset. */
398 off += loc->mbuf->outer_l3_len;
399 if (tunnel == PKT_TX_TUNNEL_UDP)
400 set |= off >> 1; /* Outer L4 offset. */
401 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
402 const uint64_t csum = ol & PKT_TX_L4_MASK;
403 off += loc->mbuf->l2_len;
404 set |= (off >> 1) << 24; /* Inner L3 offset. */
405 if (csum == PKT_TX_TCP_CKSUM ||
406 csum == PKT_TX_UDP_CKSUM ||
407 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
408 off += loc->mbuf->l3_len;
409 set |= (off >> 1) << 16; /* Inner L4 offset. */
412 set = rte_cpu_to_le_32(set);
417 * Convert the Checksum offloads to Verbs.
420 * Pointer to the mbuf.
423 * Converted checksum flags.
425 static __rte_always_inline uint8_t
426 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
429 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
430 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
431 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
434 * The index should have:
435 * bit[0] = PKT_TX_TCP_SEG
436 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
437 * bit[4] = PKT_TX_IP_CKSUM
438 * bit[8] = PKT_TX_OUTER_IP_CKSUM
441 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
442 return mlx5_cksum_table[idx];
446 * Internal function to compute the number of used descriptors in an RX queue
452 * The number of used rx descriptor.
455 rx_queue_count(struct mlx5_rxq_data *rxq)
457 struct rxq_zip *zip = &rxq->zip;
458 volatile struct mlx5_cqe *cqe;
459 const unsigned int cqe_n = (1 << rxq->cqe_n);
460 const unsigned int cqe_cnt = cqe_n - 1;
464 /* if we are processing a compressed cqe */
466 used = zip->cqe_cnt - zip->ca;
472 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
473 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
477 op_own = cqe->op_own;
478 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
479 n = rte_be_to_cpu_32(cqe->byte_cnt);
484 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
486 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
491 * DPDK callback to check the status of a rx descriptor.
496 * The index of the descriptor in the ring.
499 * The status of the tx descriptor.
502 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
504 struct mlx5_rxq_data *rxq = rx_queue;
505 struct mlx5_rxq_ctrl *rxq_ctrl =
506 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
507 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
509 if (dev->rx_pkt_burst != mlx5_rx_burst) {
513 if (offset >= (1 << rxq->elts_n)) {
517 if (offset < rx_queue_count(rxq))
518 return RTE_ETH_RX_DESC_DONE;
519 return RTE_ETH_RX_DESC_AVAIL;
523 * DPDK callback to get the number of used descriptors in a RX queue
526 * Pointer to the device structure.
532 * The number of used rx descriptor.
533 * -EINVAL if the queue is invalid
536 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
538 struct mlx5_priv *priv = dev->data->dev_private;
539 struct mlx5_rxq_data *rxq;
541 if (dev->rx_pkt_burst != mlx5_rx_burst) {
545 rxq = (*priv->rxqs)[rx_queue_id];
550 return rx_queue_count(rxq);
553 #define MLX5_SYSTEM_LOG_DIR "/var/log"
555 * Dump debug information to log file.
560 * If not NULL this string is printed as a header to the output
561 * and the output will be in hexadecimal view.
563 * This is the buffer address to print out.
565 * The number of bytes to dump out.
568 mlx5_dump_debug_information(const char *fname, const char *hex_title,
569 const void *buf, unsigned int hex_len)
573 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
574 fd = fopen(path, "a+");
576 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
578 MKSTR(path2, "./%s", fname);
579 fd = fopen(path2, "a+");
581 DRV_LOG(ERR, "cannot open %s for debug dump\n",
585 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
587 DRV_LOG(INFO, "New debug dump in file %s\n", path);
590 rte_hexdump(fd, hex_title, buf, hex_len);
592 fprintf(fd, "%s", (const char *)buf);
593 fprintf(fd, "\n\n\n");
598 * Move QP from error state to running state and initialize indexes.
601 * Pointer to TX queue control structure.
604 * 0 on success, else -1.
607 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
609 struct mlx5_mp_arg_queue_state_modify sm = {
611 .queue_id = txq_ctrl->txq.idx,
614 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
616 txq_ctrl->txq.wqe_ci = 0;
617 txq_ctrl->txq.wqe_pi = 0;
618 txq_ctrl->txq.elts_comp = 0;
622 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
624 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
626 static const uint8_t magic[] = "seen";
630 for (i = 0; i < sizeof(magic); ++i)
631 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
633 err_cqe->rsvd1[i] = magic[i];
642 * Pointer to TX queue structure.
644 * Pointer to the error CQE.
647 * The last Tx buffer element to free.
650 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
651 volatile struct mlx5_err_cqe *err_cqe)
653 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
654 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
655 struct mlx5_txq_ctrl *txq_ctrl =
656 container_of(txq, struct mlx5_txq_ctrl, txq);
657 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
658 int seen = check_err_cqe_seen(err_cqe);
660 if (!seen && txq_ctrl->dump_file_n <
661 txq_ctrl->priv->config.max_dump_files_num) {
662 MKSTR(err_str, "Unexpected CQE error syndrome "
663 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
664 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
665 txq->cqe_s, txq->qp_num_8s >> 8,
666 rte_be_to_cpu_16(err_cqe->wqe_counter),
667 txq->wqe_ci, txq->cq_ci);
668 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
669 PORT_ID(txq_ctrl->priv), txq->idx,
670 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
671 mlx5_dump_debug_information(name, NULL, err_str, 0);
672 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
673 (const void *)((uintptr_t)
677 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
678 (const void *)((uintptr_t)
682 txq_ctrl->dump_file_n++;
686 * Count errors in WQEs units.
687 * Later it can be improved to count error packets,
688 * for example, by SQ parsing to find how much packets
689 * should be counted for each WQE.
691 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
693 if (tx_recover_qp(txq_ctrl) == 0) {
695 /* Release all the remaining buffers. */
696 return txq->elts_head;
698 /* Recovering failed - try again later on the same WQE. */
702 /* Do not release buffers. */
703 return txq->elts_tail;
707 * Translate RX completion flags to packet type.
710 * Pointer to RX queue structure.
714 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
717 * Packet type for struct rte_mbuf.
719 static inline uint32_t
720 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
723 uint8_t pinfo = cqe->pkt_info;
724 uint16_t ptype = cqe->hdr_type_etc;
727 * The index to the array should have:
728 * bit[1:0] = l3_hdr_type
729 * bit[4:2] = l4_hdr_type
732 * bit[7] = outer_l3_type
734 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
735 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
739 * Initialize Rx WQ and indexes.
742 * Pointer to RX queue structure.
745 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
747 const unsigned int wqe_n = 1 << rxq->elts_n;
750 for (i = 0; (i != wqe_n); ++i) {
751 volatile struct mlx5_wqe_data_seg *scat;
755 if (mlx5_rxq_mprq_enabled(rxq)) {
756 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
758 scat = &((volatile struct mlx5_wqe_mprq *)
760 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
761 1 << rxq->strd_num_n);
762 byte_count = (1 << rxq->strd_sz_n) *
763 (1 << rxq->strd_num_n);
765 struct rte_mbuf *buf = (*rxq->elts)[i];
767 scat = &((volatile struct mlx5_wqe_data_seg *)
769 addr = rte_pktmbuf_mtod(buf, uintptr_t);
770 byte_count = DATA_LEN(buf);
772 /* scat->addr must be able to store a pointer. */
773 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
774 *scat = (struct mlx5_wqe_data_seg){
775 .addr = rte_cpu_to_be_64(addr),
776 .byte_count = rte_cpu_to_be_32(byte_count),
777 .lkey = mlx5_rx_addr2mr(rxq, addr),
780 rxq->consumed_strd = 0;
781 rxq->decompressed = 0;
783 rxq->zip = (struct rxq_zip){
786 /* Update doorbell counter. */
787 rxq->rq_ci = wqe_n >> rxq->sges_n;
789 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
793 * Modify a Verbs/DevX queue state.
794 * This must be called from the primary process.
797 * Pointer to Ethernet device.
799 * State modify request parameters.
802 * 0 in case of success else non-zero value and rte_errno is set.
805 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
806 const struct mlx5_mp_arg_queue_state_modify *sm)
809 struct mlx5_priv *priv = dev->data->dev_private;
812 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
813 struct mlx5_rxq_ctrl *rxq_ctrl =
814 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
816 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
817 struct ibv_wq_attr mod = {
818 .attr_mask = IBV_WQ_ATTR_STATE,
819 .wq_state = sm->state,
822 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
823 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
824 struct mlx5_devx_modify_rq_attr rq_attr;
826 memset(&rq_attr, 0, sizeof(rq_attr));
827 if (sm->state == IBV_WQS_RESET) {
828 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
829 rq_attr.state = MLX5_RQC_STATE_RST;
830 } else if (sm->state == IBV_WQS_RDY) {
831 rq_attr.rq_state = MLX5_RQC_STATE_RST;
832 rq_attr.state = MLX5_RQC_STATE_RDY;
833 } else if (sm->state == IBV_WQS_ERR) {
834 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
835 rq_attr.state = MLX5_RQC_STATE_ERR;
837 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
841 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s\n",
842 sm->state, strerror(errno));
847 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
848 struct mlx5_txq_ctrl *txq_ctrl =
849 container_of(txq, struct mlx5_txq_ctrl, txq);
850 struct ibv_qp_attr mod = {
851 .qp_state = IBV_QPS_RESET,
852 .port_num = (uint8_t)priv->ibv_port,
854 struct ibv_qp *qp = txq_ctrl->ibv->qp;
856 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
858 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
859 "%s\n", strerror(errno));
863 mod.qp_state = IBV_QPS_INIT;
864 ret = mlx5_glue->modify_qp(qp, &mod,
865 (IBV_QP_STATE | IBV_QP_PORT));
867 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s\n",
872 mod.qp_state = IBV_QPS_RTR;
873 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
875 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s\n",
880 mod.qp_state = IBV_QPS_RTS;
881 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
883 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s\n",
893 * Modify a Verbs queue state.
896 * Pointer to Ethernet device.
898 * State modify request parameters.
901 * 0 in case of success else non-zero value.
904 mlx5_queue_state_modify(struct rte_eth_dev *dev,
905 struct mlx5_mp_arg_queue_state_modify *sm)
909 switch (rte_eal_process_type()) {
910 case RTE_PROC_PRIMARY:
911 ret = mlx5_queue_state_modify_primary(dev, sm);
913 case RTE_PROC_SECONDARY:
914 ret = mlx5_mp_req_queue_state_modify(dev, sm);
924 * The function inserts the RQ state to reset when the first error CQE is
925 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
926 * it moves the RQ state to ready and initializes the RQ.
927 * Next CQE identification and error counting are in the caller responsibility.
930 * Pointer to RX queue structure.
931 * @param[in] mbuf_prepare
932 * Whether to prepare mbufs for the RQ.
935 * -1 in case of recovery error, otherwise the CQE status.
938 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
940 const uint16_t cqe_n = 1 << rxq->cqe_n;
941 const uint16_t cqe_mask = cqe_n - 1;
942 const unsigned int wqe_n = 1 << rxq->elts_n;
943 struct mlx5_rxq_ctrl *rxq_ctrl =
944 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
946 volatile struct mlx5_cqe *cqe;
947 volatile struct mlx5_err_cqe *err_cqe;
949 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
951 struct mlx5_mp_arg_queue_state_modify sm;
954 switch (rxq->err_state) {
955 case MLX5_RXQ_ERR_STATE_NO_ERROR:
956 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
958 case MLX5_RXQ_ERR_STATE_NEED_RESET:
960 sm.queue_id = rxq->idx;
961 sm.state = IBV_WQS_RESET;
962 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
964 if (rxq_ctrl->dump_file_n <
965 rxq_ctrl->priv->config.max_dump_files_num) {
966 MKSTR(err_str, "Unexpected CQE error syndrome "
967 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
968 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
969 rxq->cqn, rxq_ctrl->wqn,
970 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
971 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
972 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
973 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
974 mlx5_dump_debug_information(name, NULL, err_str, 0);
975 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
976 (const void *)((uintptr_t)
978 sizeof(*u.cqe) * cqe_n);
979 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
980 (const void *)((uintptr_t)
983 rxq_ctrl->dump_file_n++;
985 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
987 case MLX5_RXQ_ERR_STATE_NEED_READY:
988 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
989 if (ret == MLX5_CQE_STATUS_HW_OWN) {
991 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
994 * The RQ consumer index must be zeroed while moving
995 * from RESET state to RDY state.
997 *rxq->rq_db = rte_cpu_to_be_32(0);
1000 sm.queue_id = rxq->idx;
1001 sm.state = IBV_WQS_RDY;
1002 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1006 const uint16_t q_mask = wqe_n - 1;
1008 struct rte_mbuf **elt;
1010 unsigned int n = wqe_n - (rxq->rq_ci -
1013 for (i = 0; i < (int)n; ++i) {
1014 elt_idx = (rxq->rq_ci + i) & q_mask;
1015 elt = &(*rxq->elts)[elt_idx];
1016 *elt = rte_mbuf_raw_alloc(rxq->mp);
1018 for (i--; i >= 0; --i) {
1019 elt_idx = (rxq->rq_ci +
1023 rte_pktmbuf_free_seg
1030 mlx5_rxq_initialize(rxq);
1031 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1040 * Get size of the next packet for a given CQE. For compressed CQEs, the
1041 * consumer index is updated only once all packets of the current one have
1045 * Pointer to RX queue.
1049 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1053 * 0 in case of empty CQE, otherwise the packet size in bytes.
1056 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1057 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1059 struct rxq_zip *zip = &rxq->zip;
1060 uint16_t cqe_n = cqe_cnt + 1;
1066 /* Process compressed data in the CQE and mini arrays. */
1068 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1069 (volatile struct mlx5_mini_cqe8 (*)[8])
1070 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1073 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1074 *mcqe = &(*mc)[zip->ai & 7];
1075 if ((++zip->ai & 7) == 0) {
1076 /* Invalidate consumed CQEs */
1079 while (idx != end) {
1080 (*rxq->cqes)[idx & cqe_cnt].op_own =
1081 MLX5_CQE_INVALIDATE;
1085 * Increment consumer index to skip the number
1086 * of CQEs consumed. Hardware leaves holes in
1087 * the CQ ring for software use.
1092 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1093 /* Invalidate the rest */
1097 while (idx != end) {
1098 (*rxq->cqes)[idx & cqe_cnt].op_own =
1099 MLX5_CQE_INVALIDATE;
1102 rxq->cq_ci = zip->cq_ci;
1106 * No compressed data, get next CQE and verify if it is
1113 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1114 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1115 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1117 ret = mlx5_rx_err_handle(rxq, 0);
1118 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1126 op_own = cqe->op_own;
1127 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1128 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1129 (volatile struct mlx5_mini_cqe8 (*)[8])
1130 (uintptr_t)(&(*rxq->cqes)
1134 /* Fix endianness. */
1135 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1137 * Current mini array position is the one
1138 * returned by check_cqe64().
1140 * If completion comprises several mini arrays,
1141 * as a special case the second one is located
1142 * 7 CQEs after the initial CQE instead of 8
1143 * for subsequent ones.
1145 zip->ca = rxq->cq_ci;
1146 zip->na = zip->ca + 7;
1147 /* Compute the next non compressed CQE. */
1149 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1150 /* Get packet size to return. */
1151 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1154 /* Prefetch all to be invalidated */
1157 while (idx != end) {
1158 rte_prefetch0(&(*rxq->cqes)[(idx) &
1163 len = rte_be_to_cpu_32(cqe->byte_cnt);
1166 if (unlikely(rxq->err_state)) {
1167 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1168 ++rxq->stats.idropped;
1176 * Translate RX completion flags to offload flags.
1182 * Offload flags (ol_flags) for struct rte_mbuf.
1184 static inline uint32_t
1185 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1187 uint32_t ol_flags = 0;
1188 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1192 MLX5_CQE_RX_L3_HDR_VALID,
1193 PKT_RX_IP_CKSUM_GOOD) |
1195 MLX5_CQE_RX_L4_HDR_VALID,
1196 PKT_RX_L4_CKSUM_GOOD);
1201 * Fill in mbuf fields from RX completion flags.
1202 * Note that pkt->ol_flags should be initialized outside of this function.
1205 * Pointer to RX queue.
1210 * @param rss_hash_res
1211 * Packet RSS Hash result.
1214 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1215 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1217 /* Update packet information. */
1218 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1219 if (rss_hash_res && rxq->rss_hash) {
1220 pkt->hash.rss = rss_hash_res;
1221 pkt->ol_flags |= PKT_RX_RSS_HASH;
1223 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1224 pkt->ol_flags |= PKT_RX_FDIR;
1225 if (cqe->sop_drop_qpn !=
1226 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1227 uint32_t mark = cqe->sop_drop_qpn;
1229 pkt->ol_flags |= PKT_RX_FDIR_ID;
1230 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1234 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1235 if (rxq->vlan_strip &&
1236 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1237 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1238 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1240 if (rxq->hw_timestamp) {
1241 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1242 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1247 * DPDK callback for RX.
1250 * Generic pointer to RX queue structure.
1252 * Array to store received packets.
1254 * Maximum number of packets in array.
1257 * Number of packets successfully received (<= pkts_n).
1260 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1262 struct mlx5_rxq_data *rxq = dpdk_rxq;
1263 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1264 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1265 const unsigned int sges_n = rxq->sges_n;
1266 struct rte_mbuf *pkt = NULL;
1267 struct rte_mbuf *seg = NULL;
1268 volatile struct mlx5_cqe *cqe =
1269 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1271 unsigned int rq_ci = rxq->rq_ci << sges_n;
1272 int len = 0; /* keep its value across iterations. */
1275 unsigned int idx = rq_ci & wqe_cnt;
1276 volatile struct mlx5_wqe_data_seg *wqe =
1277 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1278 struct rte_mbuf *rep = (*rxq->elts)[idx];
1279 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1280 uint32_t rss_hash_res;
1288 rep = rte_mbuf_raw_alloc(rxq->mp);
1289 if (unlikely(rep == NULL)) {
1290 ++rxq->stats.rx_nombuf;
1293 * no buffers before we even started,
1294 * bail out silently.
1298 while (pkt != seg) {
1299 assert(pkt != (*rxq->elts)[idx]);
1303 rte_mbuf_raw_free(pkt);
1309 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1310 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1312 rte_mbuf_raw_free(rep);
1316 assert(len >= (rxq->crc_present << 2));
1318 /* If compressed, take hash result from mini-CQE. */
1319 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1321 mcqe->rx_hash_result);
1322 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1323 if (rxq->crc_present)
1324 len -= RTE_ETHER_CRC_LEN;
1327 DATA_LEN(rep) = DATA_LEN(seg);
1328 PKT_LEN(rep) = PKT_LEN(seg);
1329 SET_DATA_OFF(rep, DATA_OFF(seg));
1330 PORT(rep) = PORT(seg);
1331 (*rxq->elts)[idx] = rep;
1333 * Fill NIC descriptor with the new buffer. The lkey and size
1334 * of the buffers are already known, only the buffer address
1337 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1338 /* If there's only one MR, no need to replace LKey in WQE. */
1339 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1340 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1341 if (len > DATA_LEN(seg)) {
1342 len -= DATA_LEN(seg);
1347 DATA_LEN(seg) = len;
1348 #ifdef MLX5_PMD_SOFT_COUNTERS
1349 /* Increment bytes counter. */
1350 rxq->stats.ibytes += PKT_LEN(pkt);
1352 /* Return packet. */
1357 /* Align consumer index to the next stride. */
1362 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1364 /* Update the consumer index. */
1365 rxq->rq_ci = rq_ci >> sges_n;
1367 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1369 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1370 #ifdef MLX5_PMD_SOFT_COUNTERS
1371 /* Increment packets counter. */
1372 rxq->stats.ipackets += i;
1378 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1380 struct mlx5_mprq_buf *buf = opaque;
1382 if (rte_atomic16_read(&buf->refcnt) == 1) {
1383 rte_mempool_put(buf->mp, buf);
1384 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1385 rte_atomic16_set(&buf->refcnt, 1);
1386 rte_mempool_put(buf->mp, buf);
1391 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1393 mlx5_mprq_buf_free_cb(NULL, buf);
1397 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1398 const unsigned int strd_n)
1400 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1401 volatile struct mlx5_wqe_data_seg *wqe =
1402 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1405 assert(rep != NULL);
1406 /* Replace MPRQ buf. */
1407 (*rxq->mprq_bufs)[rq_idx] = rep;
1409 addr = mlx5_mprq_buf_addr(rep, strd_n);
1410 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1411 /* If there's only one MR, no need to replace LKey in WQE. */
1412 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1413 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1414 /* Stash a mbuf for next replacement. */
1415 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1416 rxq->mprq_repl = rep;
1418 rxq->mprq_repl = NULL;
1422 * DPDK callback for RX with Multi-Packet RQ support.
1425 * Generic pointer to RX queue structure.
1427 * Array to store received packets.
1429 * Maximum number of packets in array.
1432 * Number of packets successfully received (<= pkts_n).
1435 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1437 struct mlx5_rxq_data *rxq = dpdk_rxq;
1438 const unsigned int strd_n = 1 << rxq->strd_num_n;
1439 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1440 const unsigned int strd_shift =
1441 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1442 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1443 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1444 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1446 uint32_t rq_ci = rxq->rq_ci;
1447 uint16_t consumed_strd = rxq->consumed_strd;
1448 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1450 while (i < pkts_n) {
1451 struct rte_mbuf *pkt;
1459 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1460 uint32_t rss_hash_res = 0;
1462 if (consumed_strd == strd_n) {
1463 /* Replace WQE only if the buffer is still in use. */
1464 if (rte_atomic16_read(&buf->refcnt) > 1) {
1465 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1466 /* Release the old buffer. */
1467 mlx5_mprq_buf_free(buf);
1468 } else if (unlikely(rxq->mprq_repl == NULL)) {
1469 struct mlx5_mprq_buf *rep;
1472 * Currently, the MPRQ mempool is out of buffer
1473 * and doing memcpy regardless of the size of Rx
1474 * packet. Retry allocation to get back to
1477 if (!rte_mempool_get(rxq->mprq_mp,
1479 rxq->mprq_repl = rep;
1481 /* Advance to the next WQE. */
1484 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1486 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1487 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1491 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1492 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1494 consumed_strd += strd_cnt;
1495 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1498 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1499 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1501 /* mini-CQE for MPRQ doesn't have hash result. */
1502 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1504 assert(strd_idx < strd_n);
1505 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1507 * Currently configured to receive a packet per a stride. But if
1508 * MTU is adjusted through kernel interface, device could
1509 * consume multiple strides without raising an error. In this
1510 * case, the packet should be dropped because it is bigger than
1511 * the max_rx_pkt_len.
1513 if (unlikely(strd_cnt > 1)) {
1514 ++rxq->stats.idropped;
1517 pkt = rte_pktmbuf_alloc(rxq->mp);
1518 if (unlikely(pkt == NULL)) {
1519 ++rxq->stats.rx_nombuf;
1522 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1523 assert((int)len >= (rxq->crc_present << 2));
1524 if (rxq->crc_present)
1525 len -= RTE_ETHER_CRC_LEN;
1526 offset = strd_idx * strd_sz + strd_shift;
1527 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1528 /* Initialize the offload flag. */
1531 * Memcpy packets to the target mbuf if:
1532 * - The size of packet is smaller than mprq_max_memcpy_len.
1533 * - Out of buffer in the Mempool for Multi-Packet RQ.
1535 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1537 * When memcpy'ing packet due to out-of-buffer, the
1538 * packet must be smaller than the target mbuf.
1540 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1541 rte_pktmbuf_free_seg(pkt);
1542 ++rxq->stats.idropped;
1545 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1547 rte_iova_t buf_iova;
1548 struct rte_mbuf_ext_shared_info *shinfo;
1549 uint16_t buf_len = strd_cnt * strd_sz;
1551 /* Increment the refcnt of the whole chunk. */
1552 rte_atomic16_add_return(&buf->refcnt, 1);
1553 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1555 addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
1557 * MLX5 device doesn't use iova but it is necessary in a
1558 * case where the Rx packet is transmitted via a
1561 buf_iova = rte_mempool_virt2iova(buf) +
1562 RTE_PTR_DIFF(addr, buf);
1563 shinfo = &buf->shinfos[strd_idx];
1564 rte_mbuf_ext_refcnt_set(shinfo, 1);
1566 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1567 * attaching the stride to mbuf and more offload flags
1568 * will be added below by calling rxq_cq_to_mbuf().
1569 * Other fields will be overwritten.
1571 rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
1573 rte_pktmbuf_reset_headroom(pkt);
1574 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1576 * Prevent potential overflow due to MTU change through
1579 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1580 rte_pktmbuf_free_seg(pkt);
1581 ++rxq->stats.idropped;
1585 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1587 DATA_LEN(pkt) = len;
1588 PORT(pkt) = rxq->port_id;
1589 #ifdef MLX5_PMD_SOFT_COUNTERS
1590 /* Increment bytes counter. */
1591 rxq->stats.ibytes += PKT_LEN(pkt);
1593 /* Return packet. */
1597 /* Update the consumer indexes. */
1598 rxq->consumed_strd = consumed_strd;
1600 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1601 if (rq_ci != rxq->rq_ci) {
1604 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1606 #ifdef MLX5_PMD_SOFT_COUNTERS
1607 /* Increment packets counter. */
1608 rxq->stats.ipackets += i;
1614 * Dummy DPDK callback for TX.
1616 * This function is used to temporarily replace the real callback during
1617 * unsafe control operations on the queue, or in case of error.
1620 * Generic pointer to TX queue structure.
1622 * Packets to transmit.
1624 * Number of packets in array.
1627 * Number of packets successfully transmitted (<= pkts_n).
1630 removed_tx_burst(void *dpdk_txq __rte_unused,
1631 struct rte_mbuf **pkts __rte_unused,
1632 uint16_t pkts_n __rte_unused)
1639 * Dummy DPDK callback for RX.
1641 * This function is used to temporarily replace the real callback during
1642 * unsafe control operations on the queue, or in case of error.
1645 * Generic pointer to RX queue structure.
1647 * Array to store received packets.
1649 * Maximum number of packets in array.
1652 * Number of packets successfully received (<= pkts_n).
1655 removed_rx_burst(void *dpdk_txq __rte_unused,
1656 struct rte_mbuf **pkts __rte_unused,
1657 uint16_t pkts_n __rte_unused)
1664 * Vectorized Rx/Tx routines are not compiled in when required vector
1665 * instructions are not supported on a target architecture. The following null
1666 * stubs are needed for linkage when those are not included outside of this file
1667 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1671 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1672 struct rte_mbuf **pkts __rte_unused,
1673 uint16_t pkts_n __rte_unused)
1679 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1685 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1691 * Free the mbufs from the linear array of pointers.
1694 * Pointer to array of packets to be free.
1696 * Number of packets to be freed.
1698 * Configured Tx offloads mask. It is fully defined at
1699 * compile time and may be used for optimization.
1701 static __rte_always_inline void
1702 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1703 unsigned int pkts_n,
1704 unsigned int olx __rte_unused)
1706 struct rte_mempool *pool = NULL;
1707 struct rte_mbuf **p_free = NULL;
1708 struct rte_mbuf *mbuf;
1709 unsigned int n_free = 0;
1712 * The implemented algorithm eliminates
1713 * copying pointers to temporary array
1714 * for rte_mempool_put_bulk() calls.
1721 * Decrement mbuf reference counter, detach
1722 * indirect and external buffers if needed.
1724 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1725 if (likely(mbuf != NULL)) {
1726 assert(mbuf == *pkts);
1727 if (likely(n_free != 0)) {
1728 if (unlikely(pool != mbuf->pool))
1729 /* From different pool. */
1732 /* Start new scan array. */
1739 if (unlikely(pkts_n == 0)) {
1745 * This happens if mbuf is still referenced.
1746 * We can't put it back to the pool, skip.
1750 if (unlikely(n_free != 0))
1751 /* There is some array to free.*/
1753 if (unlikely(pkts_n == 0))
1754 /* Last mbuf, nothing to free. */
1760 * This loop is implemented to avoid multiple
1761 * inlining of rte_mempool_put_bulk().
1767 * Free the array of pre-freed mbufs
1768 * belonging to the same memory pool.
1770 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1771 if (unlikely(mbuf != NULL)) {
1772 /* There is the request to start new scan. */
1777 if (likely(pkts_n != 0))
1780 * This is the last mbuf to be freed.
1781 * Do one more loop iteration to complete.
1782 * This is rare case of the last unique mbuf.
1787 if (likely(pkts_n == 0))
1796 * Free the mbuf from the elts ring buffer till new tail.
1799 * Pointer to Tx queue structure.
1801 * Index in elts to free up to, becomes new elts tail.
1803 * Configured Tx offloads mask. It is fully defined at
1804 * compile time and may be used for optimization.
1806 static __rte_always_inline void
1807 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1809 unsigned int olx __rte_unused)
1811 uint16_t n_elts = tail - txq->elts_tail;
1814 assert(n_elts <= txq->elts_s);
1816 * Implement a loop to support ring buffer wraparound
1817 * with single inlining of mlx5_tx_free_mbuf().
1822 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1823 part = RTE_MIN(part, n_elts);
1825 assert(part <= txq->elts_s);
1826 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1828 txq->elts_tail += part;
1834 * Store the mbuf being sent into elts ring buffer.
1835 * On Tx completion these mbufs will be freed.
1838 * Pointer to Tx queue structure.
1840 * Pointer to array of packets to be stored.
1842 * Number of packets to be stored.
1844 * Configured Tx offloads mask. It is fully defined at
1845 * compile time and may be used for optimization.
1847 static __rte_always_inline void
1848 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
1849 struct rte_mbuf **restrict pkts,
1850 unsigned int pkts_n,
1851 unsigned int olx __rte_unused)
1854 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
1858 part = txq->elts_s - (txq->elts_head & txq->elts_m);
1860 assert(part <= txq->elts_s);
1861 /* This code is a good candidate for vectorizing with SIMD. */
1862 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
1864 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
1865 txq->elts_head += pkts_n;
1866 if (unlikely(part < pkts_n))
1867 /* The copy is wrapping around the elts array. */
1868 rte_memcpy((void *)elts, (void *)(pkts + part),
1869 (pkts_n - part) * sizeof(struct rte_mbuf *));
1873 * Manage TX completions. This routine checks the CQ for
1874 * arrived CQEs, deduces the last accomplished WQE in SQ,
1875 * updates SQ producing index and frees all completed mbufs.
1878 * Pointer to TX queue structure.
1880 * Configured Tx offloads mask. It is fully defined at
1881 * compile time and may be used for optimization.
1883 * NOTE: not inlined intentionally, it makes tx_burst
1884 * routine smaller, simple and faster - from experiments.
1887 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
1888 unsigned int olx __rte_unused)
1890 bool update = false;
1894 volatile struct mlx5_wqe_cseg *cseg;
1895 volatile struct mlx5_cqe *cqe;
1898 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
1899 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
1900 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1901 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
1902 /* No new CQEs in completion queue. */
1903 assert(ret == MLX5_CQE_STATUS_HW_OWN);
1904 if (likely(update)) {
1905 /* Update the consumer index. */
1906 rte_compiler_barrier();
1908 rte_cpu_to_be_32(txq->cq_ci);
1912 /* Some error occurred, try to restart. */
1914 tail = mlx5_tx_error_cqe_handle
1915 (txq, (volatile struct mlx5_err_cqe *)cqe);
1917 /* Normal transmit completion. */
1920 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
1921 cseg = (volatile struct mlx5_wqe_cseg *)
1922 (txq->wqes + (txq->wqe_pi & txq->wqe_m));
1929 if (likely(tail != txq->elts_tail)) {
1930 /* Free data buffers from elts. */
1931 mlx5_tx_free_elts(txq, tail, olx);
1932 assert(tail == txq->elts_tail);
1939 * Check if the completion request flag should be set in the last WQE.
1940 * Both pushed mbufs and WQEs are monitored and the completion request
1941 * flag is set if any of thresholds is reached.
1944 * Pointer to TX queue structure.
1946 * Number of mbuf not stored yet in elts array.
1948 * Pointer to burst routine local context.
1950 * Configured Tx offloads mask. It is fully defined at
1951 * compile time and may be used for optimization.
1953 static __rte_always_inline void
1954 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
1955 unsigned int n_mbuf,
1956 struct mlx5_txq_local *restrict loc,
1957 unsigned int olx __rte_unused)
1959 uint16_t head = txq->elts_head + n_mbuf;
1961 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
1962 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres) {
1963 volatile struct mlx5_wqe *last = loc->wqe_last;
1965 txq->elts_comp = head;
1966 txq->wqe_comp = txq->wqe_ci;
1967 /* Request unconditional completion on last WQE. */
1968 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
1969 MLX5_COMP_MODE_OFFSET);
1970 /* Save elts_head in unused "immediate" field of WQE. */
1971 last->cseg.misc = head;
1973 * A CQE slot must always be available. Count the
1974 * issued CEQ "always" request instead of production
1975 * index due to here can be CQE with errors and
1976 * difference with ci may become inconsistent.
1978 assert(txq->cqe_s > ++txq->cq_pi);
1983 * DPDK callback to check the status of a tx descriptor.
1988 * The index of the descriptor in the ring.
1991 * The status of the tx descriptor.
1994 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
1996 struct mlx5_txq_data *restrict txq = tx_queue;
1999 mlx5_tx_handle_completion(txq, 0);
2000 used = txq->elts_head - txq->elts_tail;
2002 return RTE_ETH_TX_DESC_FULL;
2003 return RTE_ETH_TX_DESC_DONE;
2007 * Build the Control Segment with specified opcode:
2008 * - MLX5_OPCODE_SEND
2009 * - MLX5_OPCODE_ENHANCED_MPSW
2013 * Pointer to TX queue structure.
2015 * Pointer to burst routine local context.
2017 * Pointer to WQE to fill with built Control Segment.
2019 * Supposed length of WQE in segments.
2021 * SQ WQE opcode to put into Control Segment.
2023 * Configured Tx offloads mask. It is fully defined at
2024 * compile time and may be used for optimization.
2026 static __rte_always_inline void
2027 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2028 struct mlx5_txq_local *restrict loc __rte_unused,
2029 struct mlx5_wqe *restrict wqe,
2031 unsigned int opcode,
2032 unsigned int olx __rte_unused)
2034 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2036 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2037 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2038 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2039 MLX5_COMP_MODE_OFFSET);
2040 cs->misc = RTE_BE32(0);
2044 * Build the Ethernet Segment without inlined data.
2045 * Supports Software Parser, Checksums and VLAN
2046 * insertion Tx offload features.
2049 * Pointer to TX queue structure.
2051 * Pointer to burst routine local context.
2053 * Pointer to WQE to fill with built Ethernet Segment.
2055 * Configured Tx offloads mask. It is fully defined at
2056 * compile time and may be used for optimization.
2058 static __rte_always_inline void
2059 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2060 struct mlx5_txq_local *restrict loc,
2061 struct mlx5_wqe *restrict wqe,
2064 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2068 * Calculate and set check sum flags first, dword field
2069 * in segment may be shared with Software Parser flags.
2071 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2072 es->flags = rte_cpu_to_le_32(csum);
2074 * Calculate and set Software Parser offsets and flags.
2075 * These flags a set for custom UDP and IP tunnel packets.
2077 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2078 /* Fill metadata field if needed. */
2079 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2080 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2081 loc->mbuf->tx_metadata : 0 : 0;
2082 /* Engage VLAN tag insertion feature if requested. */
2083 if (MLX5_TXOFF_CONFIG(VLAN) &&
2084 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2086 * We should get here only if device support
2087 * this feature correctly.
2089 assert(txq->vlan_en);
2090 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2091 loc->mbuf->vlan_tci);
2093 es->inline_hdr = RTE_BE32(0);
2098 * Build the Ethernet Segment with minimal inlined data
2099 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2100 * used to fill the gap in single WQEBB WQEs.
2101 * Supports Software Parser, Checksums and VLAN
2102 * insertion Tx offload features.
2105 * Pointer to TX queue structure.
2107 * Pointer to burst routine local context.
2109 * Pointer to WQE to fill with built Ethernet Segment.
2111 * Length of VLAN tag insertion if any.
2113 * Configured Tx offloads mask. It is fully defined at
2114 * compile time and may be used for optimization.
2116 static __rte_always_inline void
2117 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2118 struct mlx5_txq_local *restrict loc,
2119 struct mlx5_wqe *restrict wqe,
2123 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2125 uint8_t *psrc, *pdst;
2128 * Calculate and set check sum flags first, dword field
2129 * in segment may be shared with Software Parser flags.
2131 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2132 es->flags = rte_cpu_to_le_32(csum);
2134 * Calculate and set Software Parser offsets and flags.
2135 * These flags a set for custom UDP and IP tunnel packets.
2137 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2138 /* Fill metadata field if needed. */
2139 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2140 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2141 loc->mbuf->tx_metadata : 0 : 0;
2142 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2144 sizeof(rte_v128u32_t)),
2145 "invalid Ethernet Segment data size");
2146 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2148 sizeof(struct rte_vlan_hdr) +
2149 2 * RTE_ETHER_ADDR_LEN),
2150 "invalid Ethernet Segment data size");
2151 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2152 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2153 es->inline_data = *(unaligned_uint16_t *)psrc;
2154 psrc += sizeof(uint16_t);
2155 pdst = (uint8_t *)(es + 1);
2156 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2157 /* Implement VLAN tag insertion as part inline data. */
2158 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2159 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2160 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2161 /* Insert VLAN ethertype + VLAN tag. */
2162 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2163 ((RTE_ETHER_TYPE_VLAN << 16) |
2164 loc->mbuf->vlan_tci);
2165 pdst += sizeof(struct rte_vlan_hdr);
2166 /* Copy the rest two bytes from packet data. */
2167 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2168 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2170 /* Fill the gap in the title WQEBB with inline data. */
2171 rte_mov16(pdst, psrc);
2176 * Build the Ethernet Segment with entire packet
2177 * data inlining. Checks the boundary of WQEBB and
2178 * ring buffer wrapping, supports Software Parser,
2179 * Checksums and VLAN insertion Tx offload features.
2182 * Pointer to TX queue structure.
2184 * Pointer to burst routine local context.
2186 * Pointer to WQE to fill with built Ethernet Segment.
2188 * Length of VLAN tag insertion if any.
2190 * Length of data to inline (VLAN included, if any).
2192 * TSO flag, set mss field from the packet.
2194 * Configured Tx offloads mask. It is fully defined at
2195 * compile time and may be used for optimization.
2198 * Pointer to the next Data Segment (aligned and wrapped around).
2200 static __rte_always_inline struct mlx5_wqe_dseg *
2201 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2202 struct mlx5_txq_local *restrict loc,
2203 struct mlx5_wqe *restrict wqe,
2209 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2211 uint8_t *psrc, *pdst;
2215 * Calculate and set check sum flags first, dword field
2216 * in segment may be shared with Software Parser flags.
2218 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2221 csum |= loc->mbuf->tso_segsz;
2222 es->flags = rte_cpu_to_be_32(csum);
2224 es->flags = rte_cpu_to_le_32(csum);
2227 * Calculate and set Software Parser offsets and flags.
2228 * These flags a set for custom UDP and IP tunnel packets.
2230 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2231 /* Fill metadata field if needed. */
2232 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2233 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2234 loc->mbuf->tx_metadata : 0 : 0;
2235 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2237 sizeof(rte_v128u32_t)),
2238 "invalid Ethernet Segment data size");
2239 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2241 sizeof(struct rte_vlan_hdr) +
2242 2 * RTE_ETHER_ADDR_LEN),
2243 "invalid Ethernet Segment data size");
2244 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2245 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2246 es->inline_data = *(unaligned_uint16_t *)psrc;
2247 psrc += sizeof(uint16_t);
2248 pdst = (uint8_t *)(es + 1);
2249 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2250 /* Implement VLAN tag insertion as part inline data. */
2251 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2252 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2253 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2254 /* Insert VLAN ethertype + VLAN tag. */
2255 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2256 ((RTE_ETHER_TYPE_VLAN << 16) |
2257 loc->mbuf->vlan_tci);
2258 pdst += sizeof(struct rte_vlan_hdr);
2259 /* Copy the rest two bytes from packet data. */
2260 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2261 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2262 psrc += sizeof(uint16_t);
2264 /* Fill the gap in the title WQEBB with inline data. */
2265 rte_mov16(pdst, psrc);
2266 psrc += sizeof(rte_v128u32_t);
2268 pdst = (uint8_t *)(es + 2);
2269 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2270 assert(pdst < (uint8_t *)txq->wqes_end);
2271 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2273 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2274 return (struct mlx5_wqe_dseg *)pdst;
2277 * The WQEBB space availability is checked by caller.
2278 * Here we should be aware of WQE ring buffer wraparound only.
2280 part = (uint8_t *)txq->wqes_end - pdst;
2281 part = RTE_MIN(part, inlen);
2283 rte_memcpy(pdst, psrc, part);
2285 if (likely(!inlen)) {
2287 * If return value is not used by the caller
2288 * the code below will be optimized out.
2291 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2292 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2293 pdst = (uint8_t *)txq->wqes;
2294 return (struct mlx5_wqe_dseg *)pdst;
2296 pdst = (uint8_t *)txq->wqes;
2303 * Copy data from chain of mbuf to the specified linear buffer.
2304 * Checksums and VLAN insertion Tx offload features. If data
2305 * from some mbuf copied completely this mbuf is freed. Local
2306 * structure is used to keep the byte stream state.
2309 * Pointer to the destination linear buffer.
2311 * Pointer to burst routine local context.
2313 * Length of data to be copied.
2315 * Configured Tx offloads mask. It is fully defined at
2316 * compile time and may be used for optimization.
2318 static __rte_always_inline void
2319 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2320 struct mlx5_txq_local *restrict loc,
2322 unsigned int olx __rte_unused)
2324 struct rte_mbuf *mbuf;
2325 unsigned int part, dlen;
2330 /* Allow zero length packets, must check first. */
2331 dlen = rte_pktmbuf_data_len(loc->mbuf);
2332 if (dlen <= loc->mbuf_off) {
2333 /* Exhausted packet, just free. */
2335 loc->mbuf = mbuf->next;
2336 rte_pktmbuf_free_seg(mbuf);
2338 assert(loc->mbuf_nseg > 1);
2343 dlen -= loc->mbuf_off;
2344 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2346 part = RTE_MIN(len, dlen);
2347 rte_memcpy(pdst, psrc, part);
2348 loc->mbuf_off += part;
2351 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2353 /* Exhausted packet, just free. */
2355 loc->mbuf = mbuf->next;
2356 rte_pktmbuf_free_seg(mbuf);
2358 assert(loc->mbuf_nseg >= 1);
2368 * Build the Ethernet Segment with inlined data from
2369 * multi-segment packet. Checks the boundary of WQEBB
2370 * and ring buffer wrapping, supports Software Parser,
2371 * Checksums and VLAN insertion Tx offload features.
2374 * Pointer to TX queue structure.
2376 * Pointer to burst routine local context.
2378 * Pointer to WQE to fill with built Ethernet Segment.
2380 * Length of VLAN tag insertion if any.
2382 * Length of data to inline (VLAN included, if any).
2384 * TSO flag, set mss field from the packet.
2386 * Configured Tx offloads mask. It is fully defined at
2387 * compile time and may be used for optimization.
2390 * Pointer to the next Data Segment (aligned and
2391 * possible NOT wrapped around - caller should do
2392 * wrapping check on its own).
2394 static __rte_always_inline struct mlx5_wqe_dseg *
2395 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2396 struct mlx5_txq_local *restrict loc,
2397 struct mlx5_wqe *restrict wqe,
2403 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2409 * Calculate and set check sum flags first, uint32_t field
2410 * in segment may be shared with Software Parser flags.
2412 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2415 csum |= loc->mbuf->tso_segsz;
2416 es->flags = rte_cpu_to_be_32(csum);
2418 es->flags = rte_cpu_to_le_32(csum);
2421 * Calculate and set Software Parser offsets and flags.
2422 * These flags a set for custom UDP and IP tunnel packets.
2424 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2425 /* Fill metadata field if needed. */
2426 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2427 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2428 loc->mbuf->tx_metadata : 0 : 0;
2429 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2431 sizeof(rte_v128u32_t)),
2432 "invalid Ethernet Segment data size");
2433 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2435 sizeof(struct rte_vlan_hdr) +
2436 2 * RTE_ETHER_ADDR_LEN),
2437 "invalid Ethernet Segment data size");
2438 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
2439 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2440 pdst = (uint8_t *)&es->inline_data;
2441 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2442 /* Implement VLAN tag insertion as part inline data. */
2443 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2444 pdst += 2 * RTE_ETHER_ADDR_LEN;
2445 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2446 ((RTE_ETHER_TYPE_VLAN << 16) |
2447 loc->mbuf->vlan_tci);
2448 pdst += sizeof(struct rte_vlan_hdr);
2449 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2451 assert(pdst < (uint8_t *)txq->wqes_end);
2453 * The WQEBB space availability is checked by caller.
2454 * Here we should be aware of WQE ring buffer wraparound only.
2456 part = (uint8_t *)txq->wqes_end - pdst;
2457 part = RTE_MIN(part, inlen);
2460 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2462 if (likely(!inlen)) {
2464 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2465 return (struct mlx5_wqe_dseg *)pdst;
2467 pdst = (uint8_t *)txq->wqes;
2473 * Build the Data Segment of pointer type.
2476 * Pointer to TX queue structure.
2478 * Pointer to burst routine local context.
2480 * Pointer to WQE to fill with built Data Segment.
2482 * Data buffer to point.
2484 * Data buffer length.
2486 * Configured Tx offloads mask. It is fully defined at
2487 * compile time and may be used for optimization.
2489 static __rte_always_inline void
2490 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2491 struct mlx5_txq_local *restrict loc,
2492 struct mlx5_wqe_dseg *restrict dseg,
2495 unsigned int olx __rte_unused)
2499 dseg->bcount = rte_cpu_to_be_32(len);
2500 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2501 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2505 * Build the Data Segment of pointer type or inline
2506 * if data length is less than buffer in minimal
2507 * Data Segment size.
2510 * Pointer to TX queue structure.
2512 * Pointer to burst routine local context.
2514 * Pointer to WQE to fill with built Data Segment.
2516 * Data buffer to point.
2518 * Data buffer length.
2520 * Configured Tx offloads mask. It is fully defined at
2521 * compile time and may be used for optimization.
2523 static __rte_always_inline void
2524 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2525 struct mlx5_txq_local *restrict loc,
2526 struct mlx5_wqe_dseg *restrict dseg,
2529 unsigned int olx __rte_unused)
2535 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2536 dseg->bcount = rte_cpu_to_be_32(len);
2537 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2538 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2542 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2543 /* Unrolled implementation of generic rte_memcpy. */
2544 dst = (uintptr_t)&dseg->inline_data[0];
2545 src = (uintptr_t)buf;
2546 #ifdef RTE_ARCH_STRICT_ALIGN
2547 memcpy(dst, src, len);
2550 *(uint64_t *)dst = *(uint64_t *)src;
2551 dst += sizeof(uint64_t);
2552 src += sizeof(uint64_t);
2555 *(uint32_t *)dst = *(uint32_t *)src;
2556 dst += sizeof(uint32_t);
2557 src += sizeof(uint32_t);
2560 *(uint16_t *)dst = *(uint16_t *)src;
2561 dst += sizeof(uint16_t);
2562 src += sizeof(uint16_t);
2565 *(uint8_t *)dst = *(uint8_t *)src;
2570 * Build the Data Segment of inlined data from single
2571 * segment packet, no VLAN insertion.
2574 * Pointer to TX queue structure.
2576 * Pointer to burst routine local context.
2578 * Pointer to WQE to fill with built Data Segment.
2580 * Data buffer to point.
2582 * Data buffer length.
2584 * Configured Tx offloads mask. It is fully defined at
2585 * compile time and may be used for optimization.
2588 * Pointer to the next Data Segment after inlined data.
2589 * Ring buffer wraparound check is needed. We do not
2590 * do it here because it may not be needed for the
2591 * last packet in the eMPW session.
2593 static __rte_always_inline struct mlx5_wqe_dseg *
2594 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2595 struct mlx5_txq_local *restrict loc __rte_unused,
2596 struct mlx5_wqe_dseg *restrict dseg,
2599 unsigned int olx __rte_unused)
2604 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2605 pdst = &dseg->inline_data[0];
2607 * The WQEBB space availability is checked by caller.
2608 * Here we should be aware of WQE ring buffer wraparound only.
2610 part = (uint8_t *)txq->wqes_end - pdst;
2611 part = RTE_MIN(part, len);
2613 rte_memcpy(pdst, buf, part);
2617 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2618 /* Note: no final wraparound check here. */
2619 return (struct mlx5_wqe_dseg *)pdst;
2621 pdst = (uint8_t *)txq->wqes;
2628 * Build the Data Segment of inlined data from single
2629 * segment packet with VLAN insertion.
2632 * Pointer to TX queue structure.
2634 * Pointer to burst routine local context.
2636 * Pointer to the dseg fill with built Data Segment.
2638 * Data buffer to point.
2640 * Data buffer length.
2642 * Configured Tx offloads mask. It is fully defined at
2643 * compile time and may be used for optimization.
2646 * Pointer to the next Data Segment after inlined data.
2647 * Ring buffer wraparound check is needed.
2649 static __rte_always_inline struct mlx5_wqe_dseg *
2650 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2651 struct mlx5_txq_local *restrict loc __rte_unused,
2652 struct mlx5_wqe_dseg *restrict dseg,
2655 unsigned int olx __rte_unused)
2661 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2662 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2663 (2 * RTE_ETHER_ADDR_LEN),
2664 "invalid Data Segment data size");
2665 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2666 MLX5_ETH_WQE_DATA_INLINE);
2667 pdst = &dseg->inline_data[0];
2668 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2669 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2670 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2671 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2672 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2673 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2674 loc->mbuf->vlan_tci);
2675 pdst += sizeof(struct rte_vlan_hdr);
2676 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2677 pdst = (uint8_t *)txq->wqes;
2679 * The WQEBB space availability is checked by caller.
2680 * Here we should be aware of WQE ring buffer wraparound only.
2682 part = (uint8_t *)txq->wqes_end - pdst;
2683 part = RTE_MIN(part, len);
2685 rte_memcpy(pdst, buf, part);
2689 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2690 /* Note: no final wraparound check here. */
2691 return (struct mlx5_wqe_dseg *)pdst;
2693 pdst = (uint8_t *)txq->wqes;
2700 * Build the Ethernet Segment with optionally inlined data with
2701 * VLAN insertion and following Data Segments (if any) from
2702 * multi-segment packet. Used by ordinary send and TSO.
2705 * Pointer to TX queue structure.
2707 * Pointer to burst routine local context.
2709 * Pointer to WQE to fill with built Ethernet/Data Segments.
2711 * Length of VLAN header to insert, 0 means no VLAN insertion.
2713 * Data length to inline. For TSO this parameter specifies
2714 * exact value, for ordinary send routine can be aligned by
2715 * caller to provide better WQE space saving and data buffer
2716 * start address alignment. This length includes VLAN header
2719 * Zero means ordinary send, inlined data can be extended,
2720 * otherwise this is TSO, inlined data length is fixed.
2722 * Configured Tx offloads mask. It is fully defined at
2723 * compile time and may be used for optimization.
2726 * Actual size of built WQE in segments.
2728 static __rte_always_inline unsigned int
2729 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2730 struct mlx5_txq_local *restrict loc,
2731 struct mlx5_wqe *restrict wqe,
2735 unsigned int olx __rte_unused)
2737 struct mlx5_wqe_dseg *restrict dseg;
2740 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2741 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2744 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2745 if (!loc->mbuf_nseg)
2748 * There are still some mbuf remaining, not inlined.
2749 * The first mbuf may be partially inlined and we
2750 * must process the possible non-zero data offset.
2752 if (loc->mbuf_off) {
2757 * Exhausted packets must be dropped before.
2758 * Non-zero offset means there are some data
2759 * remained in the packet.
2761 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2762 assert(rte_pktmbuf_data_len(loc->mbuf));
2763 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2765 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2767 * Build the pointer/minimal data Data Segment.
2768 * Do ring buffer wrapping check in advance.
2770 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2771 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2772 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2773 /* Store the mbuf to be freed on completion. */
2774 assert(loc->elts_free);
2775 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2778 if (--loc->mbuf_nseg == 0)
2780 loc->mbuf = loc->mbuf->next;
2784 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2785 struct rte_mbuf *mbuf;
2787 /* Zero length segment found, just skip. */
2789 loc->mbuf = loc->mbuf->next;
2790 rte_pktmbuf_free_seg(mbuf);
2791 if (--loc->mbuf_nseg == 0)
2794 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2795 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2798 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2799 rte_pktmbuf_data_len(loc->mbuf), olx);
2800 assert(loc->elts_free);
2801 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2804 if (--loc->mbuf_nseg == 0)
2806 loc->mbuf = loc->mbuf->next;
2811 /* Calculate actual segments used from the dseg pointer. */
2812 if ((uintptr_t)wqe < (uintptr_t)dseg)
2813 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
2815 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
2816 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
2821 * Tx one packet function for multi-segment TSO. Supports all
2822 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
2823 * sends one packet per WQE.
2825 * This routine is responsible for storing processed mbuf
2826 * into elts ring buffer and update elts_head.
2829 * Pointer to TX queue structure.
2831 * Pointer to burst routine local context.
2833 * Configured Tx offloads mask. It is fully defined at
2834 * compile time and may be used for optimization.
2837 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2838 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2839 * Local context variables partially updated.
2841 static __rte_always_inline enum mlx5_txcmp_code
2842 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
2843 struct mlx5_txq_local *restrict loc,
2846 struct mlx5_wqe *restrict wqe;
2847 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
2850 * Calculate data length to be inlined to estimate
2851 * the required space in WQE ring buffer.
2853 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
2854 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
2855 vlan = sizeof(struct rte_vlan_hdr);
2856 inlen = loc->mbuf->l2_len + vlan +
2857 loc->mbuf->l3_len + loc->mbuf->l4_len;
2858 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
2859 return MLX5_TXCMP_CODE_ERROR;
2860 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
2861 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
2862 /* Packet must contain all TSO headers. */
2863 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
2864 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
2865 inlen > (dlen + vlan)))
2866 return MLX5_TXCMP_CODE_ERROR;
2867 assert(inlen >= txq->inlen_mode);
2869 * Check whether there are enough free WQEBBs:
2871 * - Ethernet Segment
2872 * - First Segment of inlined Ethernet data
2873 * - ... data continued ...
2874 * - Data Segments of pointer/min inline type
2876 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
2877 MLX5_ESEG_MIN_INLINE_SIZE +
2879 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
2880 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
2881 return MLX5_TXCMP_CODE_EXIT;
2882 /* Check for maximal WQE size. */
2883 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
2884 return MLX5_TXCMP_CODE_ERROR;
2885 #ifdef MLX5_PMD_SOFT_COUNTERS
2886 /* Update sent data bytes/packets counters. */
2887 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
2888 loc->mbuf->tso_segsz;
2890 * One will be added for mbuf itself
2891 * at the end of the mlx5_tx_burst from
2892 * loc->pkts_sent field.
2895 txq->stats.opackets += ntcp;
2896 txq->stats.obytes += dlen + vlan + ntcp * inlen;
2898 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2899 loc->wqe_last = wqe;
2900 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
2901 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
2902 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2903 txq->wqe_ci += (ds + 3) / 4;
2904 loc->wqe_free -= (ds + 3) / 4;
2905 return MLX5_TXCMP_CODE_MULTI;
2909 * Tx one packet function for multi-segment SEND. Supports all
2910 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
2911 * sends one packet per WQE, without any data inlining in
2914 * This routine is responsible for storing processed mbuf
2915 * into elts ring buffer and update elts_head.
2918 * Pointer to TX queue structure.
2920 * Pointer to burst routine local context.
2922 * Configured Tx offloads mask. It is fully defined at
2923 * compile time and may be used for optimization.
2926 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2927 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2928 * Local context variables partially updated.
2930 static __rte_always_inline enum mlx5_txcmp_code
2931 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
2932 struct mlx5_txq_local *restrict loc,
2935 struct mlx5_wqe_dseg *restrict dseg;
2936 struct mlx5_wqe *restrict wqe;
2937 unsigned int ds, nseg;
2939 assert(NB_SEGS(loc->mbuf) > 1);
2941 * No inline at all, it means the CPU cycles saving
2942 * is prioritized at configuration, we should not
2943 * copy any packet data to WQE.
2945 nseg = NB_SEGS(loc->mbuf);
2947 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
2948 return MLX5_TXCMP_CODE_EXIT;
2949 /* Check for maximal WQE size. */
2950 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
2951 return MLX5_TXCMP_CODE_ERROR;
2953 * Some Tx offloads may cause an error if
2954 * packet is not long enough, check against
2955 * assumed minimal length.
2957 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
2958 return MLX5_TXCMP_CODE_ERROR;
2959 #ifdef MLX5_PMD_SOFT_COUNTERS
2960 /* Update sent data bytes counter. */
2961 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
2962 if (MLX5_TXOFF_CONFIG(VLAN) &&
2963 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
2964 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
2967 * SEND WQE, one WQEBB:
2968 * - Control Segment, SEND opcode
2969 * - Ethernet Segment, optional VLAN, no inline
2970 * - Data Segments, pointer only type
2972 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
2973 loc->wqe_last = wqe;
2974 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
2975 mlx5_tx_eseg_none(txq, loc, wqe, olx);
2976 dseg = &wqe->dseg[0];
2978 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2979 struct rte_mbuf *mbuf;
2982 * Zero length segment found, have to
2983 * correct total size of WQE in segments.
2984 * It is supposed to be rare occasion, so
2985 * in normal case (no zero length segments)
2986 * we avoid extra writing to the Control
2990 wqe->cseg.sq_ds -= RTE_BE32(1);
2992 loc->mbuf = mbuf->next;
2993 rte_pktmbuf_free_seg(mbuf);
2999 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3000 rte_pktmbuf_data_len(loc->mbuf), olx);
3001 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3006 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3007 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3008 loc->mbuf = loc->mbuf->next;
3011 txq->wqe_ci += (ds + 3) / 4;
3012 loc->wqe_free -= (ds + 3) / 4;
3013 return MLX5_TXCMP_CODE_MULTI;
3017 * Tx one packet function for multi-segment SEND. Supports all
3018 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3019 * sends one packet per WQE, with data inlining in
3020 * Ethernet Segment and minimal Data Segments.
3022 * This routine is responsible for storing processed mbuf
3023 * into elts ring buffer and update elts_head.
3026 * Pointer to TX queue structure.
3028 * Pointer to burst routine local context.
3030 * Configured Tx offloads mask. It is fully defined at
3031 * compile time and may be used for optimization.
3034 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3035 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3036 * Local context variables partially updated.
3038 static __rte_always_inline enum mlx5_txcmp_code
3039 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3040 struct mlx5_txq_local *restrict loc,
3043 struct mlx5_wqe *restrict wqe;
3044 unsigned int ds, inlen, dlen, vlan = 0;
3046 assert(MLX5_TXOFF_CONFIG(INLINE));
3047 assert(NB_SEGS(loc->mbuf) > 1);
3049 * First calculate data length to be inlined
3050 * to estimate the required space for WQE.
3052 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3053 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3054 vlan = sizeof(struct rte_vlan_hdr);
3055 inlen = dlen + vlan;
3056 /* Check against minimal length. */
3057 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3058 return MLX5_TXCMP_CODE_ERROR;
3059 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3060 if (inlen > txq->inlen_send) {
3061 struct rte_mbuf *mbuf;
3066 * Packet length exceeds the allowed inline
3067 * data length, check whether the minimal
3068 * inlining is required.
3070 if (txq->inlen_mode) {
3071 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3072 assert(txq->inlen_mode <= txq->inlen_send);
3073 inlen = txq->inlen_mode;
3075 if (!vlan || txq->vlan_en) {
3077 * VLAN insertion will be done inside by HW.
3078 * It is not utmost effective - VLAN flag is
3079 * checked twice, but we should proceed the
3080 * inlining length correctly and take into
3081 * account the VLAN header being inserted.
3083 return mlx5_tx_packet_multi_send
3086 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3089 * Now we know the minimal amount of data is requested
3090 * to inline. Check whether we should inline the buffers
3091 * from the chain beginning to eliminate some mbufs.
3094 nxlen = rte_pktmbuf_data_len(mbuf);
3095 if (unlikely(nxlen <= txq->inlen_send)) {
3096 /* We can inline first mbuf at least. */
3097 if (nxlen < inlen) {
3100 /* Scan mbufs till inlen filled. */
3105 nxlen = rte_pktmbuf_data_len(mbuf);
3107 } while (unlikely(nxlen < inlen));
3108 if (unlikely(nxlen > txq->inlen_send)) {
3109 /* We cannot inline entire mbuf. */
3110 smlen = inlen - smlen;
3111 start = rte_pktmbuf_mtod_offset
3112 (mbuf, uintptr_t, smlen);
3119 /* There should be not end of packet. */
3121 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3122 } while (unlikely(nxlen < txq->inlen_send));
3124 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3126 * Check whether we can do inline to align start
3127 * address of data buffer to cacheline.
3130 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3131 if (unlikely(start)) {
3133 if (start <= txq->inlen_send)
3138 * Check whether there are enough free WQEBBs:
3140 * - Ethernet Segment
3141 * - First Segment of inlined Ethernet data
3142 * - ... data continued ...
3143 * - Data Segments of pointer/min inline type
3145 * Estimate the number of Data Segments conservatively,
3146 * supposing no any mbufs is being freed during inlining.
3148 assert(inlen <= txq->inlen_send);
3149 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3150 MLX5_ESEG_MIN_INLINE_SIZE +
3152 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3153 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3154 return MLX5_TXCMP_CODE_EXIT;
3155 /* Check for maximal WQE size. */
3156 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3157 return MLX5_TXCMP_CODE_ERROR;
3158 #ifdef MLX5_PMD_SOFT_COUNTERS
3159 /* Update sent data bytes/packets counters. */
3160 txq->stats.obytes += dlen + vlan;
3162 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3163 loc->wqe_last = wqe;
3164 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3165 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3166 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3167 txq->wqe_ci += (ds + 3) / 4;
3168 loc->wqe_free -= (ds + 3) / 4;
3169 return MLX5_TXCMP_CODE_MULTI;
3173 * Tx burst function for multi-segment packets. Supports all
3174 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3175 * sends one packet per WQE. Function stops sending if it
3176 * encounters the single-segment packet.
3178 * This routine is responsible for storing processed mbuf
3179 * into elts ring buffer and update elts_head.
3182 * Pointer to TX queue structure.
3184 * Packets to transmit.
3186 * Number of packets in array.
3188 * Pointer to burst routine local context.
3190 * Configured Tx offloads mask. It is fully defined at
3191 * compile time and may be used for optimization.
3194 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3195 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3196 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3197 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3198 * Local context variables updated.
3200 static __rte_always_inline enum mlx5_txcmp_code
3201 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3202 struct rte_mbuf **restrict pkts,
3203 unsigned int pkts_n,
3204 struct mlx5_txq_local *restrict loc,
3207 assert(loc->elts_free && loc->wqe_free);
3208 assert(pkts_n > loc->pkts_sent);
3209 pkts += loc->pkts_sent + 1;
3210 pkts_n -= loc->pkts_sent;
3212 enum mlx5_txcmp_code ret;
3214 assert(NB_SEGS(loc->mbuf) > 1);
3216 * Estimate the number of free elts quickly but
3217 * conservatively. Some segment may be fully inlined
3218 * and freed, ignore this here - precise estimation
3221 if (loc->elts_free < NB_SEGS(loc->mbuf))
3222 return MLX5_TXCMP_CODE_EXIT;
3223 if (MLX5_TXOFF_CONFIG(TSO) &&
3224 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3225 /* Proceed with multi-segment TSO. */
3226 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3227 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3228 /* Proceed with multi-segment SEND with inlining. */
3229 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3231 /* Proceed with multi-segment SEND w/o inlining. */
3232 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3234 if (ret == MLX5_TXCMP_CODE_EXIT)
3235 return MLX5_TXCMP_CODE_EXIT;
3236 if (ret == MLX5_TXCMP_CODE_ERROR)
3237 return MLX5_TXCMP_CODE_ERROR;
3238 /* WQE is built, go to the next packet. */
3241 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3242 return MLX5_TXCMP_CODE_EXIT;
3243 loc->mbuf = *pkts++;
3245 rte_prefetch0(*pkts);
3246 if (likely(NB_SEGS(loc->mbuf) > 1))
3248 /* Here ends the series of multi-segment packets. */
3249 if (MLX5_TXOFF_CONFIG(TSO) &&
3250 unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3251 return MLX5_TXCMP_CODE_TSO;
3252 return MLX5_TXCMP_CODE_SINGLE;
3258 * Tx burst function for single-segment packets with TSO.
3259 * Supports all types of Tx offloads, except multi-packets.
3260 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3261 * Function stops sending if it encounters the multi-segment
3262 * packet or packet without TSO requested.
3264 * The routine is responsible for storing processed mbuf
3265 * into elts ring buffer and update elts_head if inline
3266 * offloads is requested due to possible early freeing
3267 * of the inlined mbufs (can not store pkts array in elts
3271 * Pointer to TX queue structure.
3273 * Packets to transmit.
3275 * Number of packets in array.
3277 * Pointer to burst routine local context.
3279 * Configured Tx offloads mask. It is fully defined at
3280 * compile time and may be used for optimization.
3283 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3284 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3285 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3286 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3287 * Local context variables updated.
3289 static __rte_always_inline enum mlx5_txcmp_code
3290 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3291 struct rte_mbuf **restrict pkts,
3292 unsigned int pkts_n,
3293 struct mlx5_txq_local *restrict loc,
3296 assert(loc->elts_free && loc->wqe_free);
3297 assert(pkts_n > loc->pkts_sent);
3298 pkts += loc->pkts_sent + 1;
3299 pkts_n -= loc->pkts_sent;
3301 struct mlx5_wqe_dseg *restrict dseg;
3302 struct mlx5_wqe *restrict wqe;
3303 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3306 assert(NB_SEGS(loc->mbuf) == 1);
3307 dlen = rte_pktmbuf_data_len(loc->mbuf);
3308 if (MLX5_TXOFF_CONFIG(VLAN) &&
3309 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3310 vlan = sizeof(struct rte_vlan_hdr);
3313 * First calculate the WQE size to check
3314 * whether we have enough space in ring buffer.
3316 hlen = loc->mbuf->l2_len + vlan +
3317 loc->mbuf->l3_len + loc->mbuf->l4_len;
3318 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3319 return MLX5_TXCMP_CODE_ERROR;
3320 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3321 hlen += loc->mbuf->outer_l2_len +
3322 loc->mbuf->outer_l3_len;
3323 /* Segment must contain all TSO headers. */
3324 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3325 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3326 hlen > (dlen + vlan)))
3327 return MLX5_TXCMP_CODE_ERROR;
3329 * Check whether there are enough free WQEBBs:
3331 * - Ethernet Segment
3332 * - First Segment of inlined Ethernet data
3333 * - ... data continued ...
3334 * - Finishing Data Segment of pointer type
3336 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3337 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3338 if (loc->wqe_free < ((ds + 3) / 4))
3339 return MLX5_TXCMP_CODE_EXIT;
3340 #ifdef MLX5_PMD_SOFT_COUNTERS
3341 /* Update sent data bytes/packets counters. */
3342 ntcp = (dlen + vlan - hlen +
3343 loc->mbuf->tso_segsz - 1) /
3344 loc->mbuf->tso_segsz;
3346 * One will be added for mbuf itself at the end
3347 * of the mlx5_tx_burst from loc->pkts_sent field.
3350 txq->stats.opackets += ntcp;
3351 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3354 * Build the TSO WQE:
3356 * - Ethernet Segment with hlen bytes inlined
3357 * - Data Segment of pointer type
3359 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3360 loc->wqe_last = wqe;
3361 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3362 MLX5_OPCODE_TSO, olx);
3363 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3364 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3365 dlen -= hlen - vlan;
3366 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3368 * WQE is built, update the loop parameters
3369 * and go to the next packet.
3371 txq->wqe_ci += (ds + 3) / 4;
3372 loc->wqe_free -= (ds + 3) / 4;
3373 if (MLX5_TXOFF_CONFIG(INLINE))
3374 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3378 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3379 return MLX5_TXCMP_CODE_EXIT;
3380 loc->mbuf = *pkts++;
3382 rte_prefetch0(*pkts);
3383 if (MLX5_TXOFF_CONFIG(MULTI) &&
3384 unlikely(NB_SEGS(loc->mbuf) > 1))
3385 return MLX5_TXCMP_CODE_MULTI;
3386 if (unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3387 return MLX5_TXCMP_CODE_SINGLE;
3388 /* Continue with the next TSO packet. */
3394 * Analyze the packet and select the best method to send.
3397 * Pointer to TX queue structure.
3399 * Pointer to burst routine local context.
3401 * Configured Tx offloads mask. It is fully defined at
3402 * compile time and may be used for optimization.
3404 * The predefined flag whether do complete check for
3405 * multi-segment packets and TSO.
3408 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3409 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3410 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3411 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3413 static __rte_always_inline enum mlx5_txcmp_code
3414 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3415 struct mlx5_txq_local *restrict loc,
3419 /* Check for multi-segment packet. */
3421 MLX5_TXOFF_CONFIG(MULTI) &&
3422 unlikely(NB_SEGS(loc->mbuf) > 1))
3423 return MLX5_TXCMP_CODE_MULTI;
3424 /* Check for TSO packet. */
3426 MLX5_TXOFF_CONFIG(TSO) &&
3427 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3428 return MLX5_TXCMP_CODE_TSO;
3429 /* Check if eMPW is enabled at all. */
3430 if (!MLX5_TXOFF_CONFIG(EMPW))
3431 return MLX5_TXCMP_CODE_SINGLE;
3432 /* Check if eMPW can be engaged. */
3433 if (MLX5_TXOFF_CONFIG(VLAN) &&
3434 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3435 (!MLX5_TXOFF_CONFIG(INLINE) ||
3436 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3437 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3439 * eMPW does not support VLAN insertion offload,
3440 * we have to inline the entire packet but
3441 * packet is too long for inlining.
3443 return MLX5_TXCMP_CODE_SINGLE;
3445 return MLX5_TXCMP_CODE_EMPW;
3449 * Check the next packet attributes to match with the eMPW batch ones.
3452 * Pointer to TX queue structure.
3454 * Pointer to Ethernet Segment of eMPW batch.
3456 * Pointer to burst routine local context.
3458 * Configured Tx offloads mask. It is fully defined at
3459 * compile time and may be used for optimization.
3462 * true - packet match with eMPW batch attributes.
3463 * false - no match, eMPW should be restarted.
3465 static __rte_always_inline bool
3466 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3467 struct mlx5_wqe_eseg *restrict es,
3468 struct mlx5_txq_local *restrict loc,
3471 uint8_t swp_flags = 0;
3473 /* Compare the checksum flags, if any. */
3474 if (MLX5_TXOFF_CONFIG(CSUM) &&
3475 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3477 /* Compare the Software Parser offsets and flags. */
3478 if (MLX5_TXOFF_CONFIG(SWP) &&
3479 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3480 es->swp_flags != swp_flags))
3482 /* Fill metadata field if needed. */
3483 if (MLX5_TXOFF_CONFIG(METADATA) &&
3484 es->metadata != (loc->mbuf->ol_flags & PKT_TX_METADATA ?
3485 loc->mbuf->tx_metadata : 0))
3487 /* There must be no VLAN packets in eMPW loop. */
3488 if (MLX5_TXOFF_CONFIG(VLAN))
3489 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3494 * Update send loop variables and WQE for eMPW loop
3495 * without data inlining. Number of Data Segments is
3496 * equal to the number of sent packets.
3499 * Pointer to TX queue structure.
3501 * Pointer to burst routine local context.
3503 * Number of packets/Data Segments/Packets.
3505 * Accumulated statistics, bytes sent
3507 * Configured Tx offloads mask. It is fully defined at
3508 * compile time and may be used for optimization.
3511 * true - packet match with eMPW batch attributes.
3512 * false - no match, eMPW should be restarted.
3514 static __rte_always_inline void
3515 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3516 struct mlx5_txq_local *restrict loc,
3519 unsigned int olx __rte_unused)
3521 assert(!MLX5_TXOFF_CONFIG(INLINE));
3522 #ifdef MLX5_PMD_SOFT_COUNTERS
3523 /* Update sent data bytes counter. */
3524 txq->stats.obytes += slen;
3528 loc->elts_free -= ds;
3529 loc->pkts_sent += ds;
3531 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3532 txq->wqe_ci += (ds + 3) / 4;
3533 loc->wqe_free -= (ds + 3) / 4;
3537 * Update send loop variables and WQE for eMPW loop
3538 * with data inlining. Gets the size of pushed descriptors
3539 * and data to the WQE.
3542 * Pointer to TX queue structure.
3544 * Pointer to burst routine local context.
3546 * Total size of descriptor/data in bytes.
3548 * Accumulated statistics, data bytes sent.
3550 * Configured Tx offloads mask. It is fully defined at
3551 * compile time and may be used for optimization.
3554 * true - packet match with eMPW batch attributes.
3555 * false - no match, eMPW should be restarted.
3557 static __rte_always_inline void
3558 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3559 struct mlx5_txq_local *restrict loc,
3562 unsigned int olx __rte_unused)
3564 assert(MLX5_TXOFF_CONFIG(INLINE));
3565 assert((len % MLX5_WSEG_SIZE) == 0);
3566 #ifdef MLX5_PMD_SOFT_COUNTERS
3567 /* Update sent data bytes counter. */
3568 txq->stats.obytes += slen;
3572 len = len / MLX5_WSEG_SIZE + 2;
3573 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3574 txq->wqe_ci += (len + 3) / 4;
3575 loc->wqe_free -= (len + 3) / 4;
3579 * The set of Tx burst functions for single-segment packets
3580 * without TSO and with Multi-Packet Writing feature support.
3581 * Supports all types of Tx offloads, except multi-packets
3584 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3585 * as many packet per WQE as it can. If eMPW is not configured
3586 * or packet can not be sent with eMPW (VLAN insertion) the
3587 * ordinary SEND opcode is used and only one packet placed
3590 * Functions stop sending if it encounters the multi-segment
3591 * packet or packet with TSO requested.
3593 * The routines are responsible for storing processed mbuf
3594 * into elts ring buffer and update elts_head if inlining
3595 * offload is requested. Otherwise the copying mbufs to elts
3596 * can be postponed and completed at the end of burst routine.
3599 * Pointer to TX queue structure.
3601 * Packets to transmit.
3603 * Number of packets in array.
3605 * Pointer to burst routine local context.
3607 * Configured Tx offloads mask. It is fully defined at
3608 * compile time and may be used for optimization.
3611 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3612 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3613 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3614 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3615 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3616 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3618 * Local context variables updated.
3621 * The routine sends packets with MLX5_OPCODE_EMPW
3622 * without inlining, this is dedicated optimized branch.
3623 * No VLAN insertion is supported.
3625 static __rte_always_inline enum mlx5_txcmp_code
3626 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3627 struct rte_mbuf **restrict pkts,
3628 unsigned int pkts_n,
3629 struct mlx5_txq_local *restrict loc,
3633 * Subroutine is the part of mlx5_tx_burst_single()
3634 * and sends single-segment packet with eMPW opcode
3635 * without data inlining.
3637 assert(!MLX5_TXOFF_CONFIG(INLINE));
3638 assert(MLX5_TXOFF_CONFIG(EMPW));
3639 assert(loc->elts_free && loc->wqe_free);
3640 assert(pkts_n > loc->pkts_sent);
3641 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3642 pkts += loc->pkts_sent + 1;
3643 pkts_n -= loc->pkts_sent;
3645 struct mlx5_wqe_dseg *restrict dseg;
3646 struct mlx5_wqe_eseg *restrict eseg;
3647 enum mlx5_txcmp_code ret;
3648 unsigned int part, loop;
3649 unsigned int slen = 0;
3652 part = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3653 if (unlikely(loc->elts_free < part)) {
3654 /* We have no enough elts to save all mbufs. */
3655 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3656 return MLX5_TXCMP_CODE_EXIT;
3657 /* But we still able to send at least minimal eMPW. */
3658 part = loc->elts_free;
3660 /* Check whether we have enough WQEs */
3661 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3662 if (unlikely(loc->wqe_free <
3663 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3664 return MLX5_TXCMP_CODE_EXIT;
3665 part = (loc->wqe_free * 4) - 2;
3667 if (likely(part > 1))
3668 rte_prefetch0(*pkts);
3669 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3671 * Build eMPW title WQEBB:
3672 * - Control Segment, eMPW opcode
3673 * - Ethernet Segment, no inline
3675 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3676 MLX5_OPCODE_ENHANCED_MPSW, olx);
3677 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3678 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3679 eseg = &loc->wqe_last->eseg;
3680 dseg = &loc->wqe_last->dseg[0];
3683 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3684 #ifdef MLX5_PMD_SOFT_COUNTERS
3685 /* Update sent data bytes counter. */
3690 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3692 if (unlikely(--loop == 0))
3694 loc->mbuf = *pkts++;
3695 if (likely(loop > 1))
3696 rte_prefetch0(*pkts);
3697 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3699 * Unroll the completion code to avoid
3700 * returning variable value - it results in
3701 * unoptimized sequent checking in caller.
3703 if (ret == MLX5_TXCMP_CODE_MULTI) {
3705 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3706 if (unlikely(!loc->elts_free ||
3708 return MLX5_TXCMP_CODE_EXIT;
3709 return MLX5_TXCMP_CODE_MULTI;
3711 if (ret == MLX5_TXCMP_CODE_TSO) {
3713 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3714 if (unlikely(!loc->elts_free ||
3716 return MLX5_TXCMP_CODE_EXIT;
3717 return MLX5_TXCMP_CODE_TSO;
3719 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3721 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3722 if (unlikely(!loc->elts_free ||
3724 return MLX5_TXCMP_CODE_EXIT;
3725 return MLX5_TXCMP_CODE_SINGLE;
3727 if (ret != MLX5_TXCMP_CODE_EMPW) {
3730 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3731 return MLX5_TXCMP_CODE_ERROR;
3734 * Check whether packet parameters coincide
3735 * within assumed eMPW batch:
3736 * - check sum settings
3738 * - software parser settings
3740 if (!mlx5_tx_match_empw(txq, eseg, loc, olx)) {
3743 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3744 if (unlikely(!loc->elts_free ||
3746 return MLX5_TXCMP_CODE_EXIT;
3749 /* Packet attributes match, continue the same eMPW. */
3751 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3752 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3754 /* eMPW is built successfully, update loop parameters. */
3756 assert(pkts_n >= part);
3757 #ifdef MLX5_PMD_SOFT_COUNTERS
3758 /* Update sent data bytes counter. */
3759 txq->stats.obytes += slen;
3761 loc->elts_free -= part;
3762 loc->pkts_sent += part;
3763 txq->wqe_ci += (2 + part + 3) / 4;
3764 loc->wqe_free -= (2 + part + 3) / 4;
3766 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3767 return MLX5_TXCMP_CODE_EXIT;
3768 loc->mbuf = *pkts++;
3769 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3770 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
3772 /* Continue sending eMPW batches. */
3778 * The routine sends packets with MLX5_OPCODE_EMPW
3779 * with inlining, optionally supports VLAN insertion.
3781 static __rte_always_inline enum mlx5_txcmp_code
3782 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
3783 struct rte_mbuf **restrict pkts,
3784 unsigned int pkts_n,
3785 struct mlx5_txq_local *restrict loc,
3789 * Subroutine is the part of mlx5_tx_burst_single()
3790 * and sends single-segment packet with eMPW opcode
3791 * with data inlining.
3793 assert(MLX5_TXOFF_CONFIG(INLINE));
3794 assert(MLX5_TXOFF_CONFIG(EMPW));
3795 assert(loc->elts_free && loc->wqe_free);
3796 assert(pkts_n > loc->pkts_sent);
3797 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3798 pkts += loc->pkts_sent + 1;
3799 pkts_n -= loc->pkts_sent;
3801 struct mlx5_wqe_dseg *restrict dseg;
3802 struct mlx5_wqe_eseg *restrict eseg;
3803 enum mlx5_txcmp_code ret;
3804 unsigned int room, part;
3805 unsigned int slen = 0;
3808 /* Check whether we have minimal amount WQEs */
3809 if (unlikely(loc->wqe_free <
3810 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3811 return MLX5_TXCMP_CODE_EXIT;
3812 if (likely(pkts_n > 1))
3813 rte_prefetch0(*pkts);
3814 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3816 * Build eMPW title WQEBB:
3817 * - Control Segment, eMPW opcode, zero DS
3818 * - Ethernet Segment, no inline
3820 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
3821 MLX5_OPCODE_ENHANCED_MPSW, olx);
3822 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3823 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3824 eseg = &loc->wqe_last->eseg;
3825 dseg = &loc->wqe_last->dseg[0];
3826 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
3827 loc->wqe_free) * MLX5_WQE_SIZE -
3828 MLX5_WQE_CSEG_SIZE -
3830 /* Build WQE till we have space, packets and resources. */
3833 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3834 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
3837 assert(room >= MLX5_WQE_DSEG_SIZE);
3838 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
3839 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
3841 * Some Tx offloads may cause an error if
3842 * packet is not long enough, check against
3843 * assumed minimal length.
3845 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
3847 if (unlikely(!part))
3848 return MLX5_TXCMP_CODE_ERROR;
3850 * We have some successfully built
3851 * packet Data Segments to send.
3853 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3854 return MLX5_TXCMP_CODE_ERROR;
3856 /* Inline or not inline - that's the Question. */
3857 if (dlen > txq->inlen_empw)
3859 /* Inline entire packet, optional VLAN insertion. */
3860 tlen = sizeof(dseg->bcount) + dlen;
3861 if (MLX5_TXOFF_CONFIG(VLAN) &&
3862 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3864 * The packet length must be checked in
3865 * mlx5_tx_able_to_empw() and packet
3866 * fits into inline length guaranteed.
3868 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
3870 tlen += sizeof(struct rte_vlan_hdr);
3873 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
3875 #ifdef MLX5_PMD_SOFT_COUNTERS
3876 /* Update sent data bytes counter. */
3877 slen += sizeof(struct rte_vlan_hdr);
3882 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
3885 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
3886 assert(room >= tlen);
3889 * Packet data are completely inlined,
3890 * free the packet immediately.
3892 rte_pktmbuf_free_seg(loc->mbuf);
3896 * Not inlinable VLAN packets are
3897 * proceeded outside of this routine.
3899 assert(room >= MLX5_WQE_DSEG_SIZE);
3900 if (MLX5_TXOFF_CONFIG(VLAN))
3901 assert(!(loc->mbuf->ol_flags &
3903 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3904 /* We have to store mbuf in elts.*/
3905 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3906 room -= MLX5_WQE_DSEG_SIZE;
3907 /* Ring buffer wraparound is checked at the loop end.*/
3910 #ifdef MLX5_PMD_SOFT_COUNTERS
3911 /* Update sent data bytes counter. */
3917 if (unlikely(!pkts_n || !loc->elts_free)) {
3919 * We have no resources/packets to
3920 * continue build descriptors.
3923 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3924 return MLX5_TXCMP_CODE_EXIT;
3926 /* Check if we have minimal room left. */
3927 if (room < MLX5_WQE_DSEG_SIZE) {
3929 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3932 loc->mbuf = *pkts++;
3933 if (likely(pkts_n > 1))
3934 rte_prefetch0(*pkts);
3935 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3937 * Unroll the completion code to avoid
3938 * returning variable value - it results in
3939 * unoptimized sequent checking in caller.
3941 if (ret == MLX5_TXCMP_CODE_MULTI) {
3943 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3944 if (unlikely(!loc->elts_free ||
3946 return MLX5_TXCMP_CODE_EXIT;
3947 return MLX5_TXCMP_CODE_MULTI;
3949 if (ret == MLX5_TXCMP_CODE_TSO) {
3951 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3952 if (unlikely(!loc->elts_free ||
3954 return MLX5_TXCMP_CODE_EXIT;
3955 return MLX5_TXCMP_CODE_TSO;
3957 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3959 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3960 if (unlikely(!loc->elts_free ||
3962 return MLX5_TXCMP_CODE_EXIT;
3963 return MLX5_TXCMP_CODE_SINGLE;
3965 if (ret != MLX5_TXCMP_CODE_EMPW) {
3968 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3969 return MLX5_TXCMP_CODE_ERROR;
3972 * Check whether packet parameters coincide
3973 * within assumed eMPW batch:
3974 * - check sum settings
3976 * - software parser settings
3978 if (!mlx5_tx_match_empw(txq, eseg, loc, olx))
3980 /* Packet attributes match, continue the same eMPW. */
3981 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3982 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3985 * We get here to close an existing eMPW
3986 * session and start the new one.
3990 if (unlikely(!part))
3991 return MLX5_TXCMP_CODE_EXIT;
3992 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3993 if (unlikely(!loc->elts_free ||
3995 return MLX5_TXCMP_CODE_EXIT;
4002 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4003 * Data inlining and VLAN insertion are supported.
4005 static __rte_always_inline enum mlx5_txcmp_code
4006 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4007 struct rte_mbuf **restrict pkts,
4008 unsigned int pkts_n,
4009 struct mlx5_txq_local *restrict loc,
4013 * Subroutine is the part of mlx5_tx_burst_single()
4014 * and sends single-segment packet with SEND opcode.
4016 assert(loc->elts_free && loc->wqe_free);
4017 assert(pkts_n > loc->pkts_sent);
4018 pkts += loc->pkts_sent + 1;
4019 pkts_n -= loc->pkts_sent;
4021 struct mlx5_wqe *restrict wqe;
4022 enum mlx5_txcmp_code ret;
4024 assert(NB_SEGS(loc->mbuf) == 1);
4025 if (MLX5_TXOFF_CONFIG(INLINE)) {
4026 unsigned int inlen, vlan = 0;
4028 inlen = rte_pktmbuf_data_len(loc->mbuf);
4029 if (MLX5_TXOFF_CONFIG(VLAN) &&
4030 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4031 vlan = sizeof(struct rte_vlan_hdr);
4033 static_assert((sizeof(struct rte_vlan_hdr) +
4034 sizeof(struct rte_ether_hdr)) ==
4035 MLX5_ESEG_MIN_INLINE_SIZE,
4036 "invalid min inline data size");
4039 * If inlining is enabled at configuration time
4040 * the limit must be not less than minimal size.
4041 * Otherwise we would do extra check for data
4042 * size to avoid crashes due to length overflow.
4044 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4045 if (inlen <= txq->inlen_send) {
4046 unsigned int seg_n, wqe_n;
4048 rte_prefetch0(rte_pktmbuf_mtod
4049 (loc->mbuf, uint8_t *));
4050 /* Check against minimal length. */
4051 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4052 return MLX5_TXCMP_CODE_ERROR;
4054 * Completely inlined packet data WQE:
4055 * - Control Segment, SEND opcode
4056 * - Ethernet Segment, no VLAN insertion
4057 * - Data inlined, VLAN optionally inserted
4058 * - Alignment to MLX5_WSEG_SIZE
4059 * Have to estimate amount of WQEBBs
4061 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4062 MLX5_ESEG_MIN_INLINE_SIZE +
4063 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4064 /* Check if there are enough WQEBBs. */
4065 wqe_n = (seg_n + 3) / 4;
4066 if (wqe_n > loc->wqe_free)
4067 return MLX5_TXCMP_CODE_EXIT;
4068 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4069 loc->wqe_last = wqe;
4070 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4071 MLX5_OPCODE_SEND, olx);
4072 mlx5_tx_eseg_data(txq, loc, wqe,
4073 vlan, inlen, 0, olx);
4074 txq->wqe_ci += wqe_n;
4075 loc->wqe_free -= wqe_n;
4077 * Packet data are completely inlined,
4078 * free the packet immediately.
4080 rte_pktmbuf_free_seg(loc->mbuf);
4081 } else if (!MLX5_TXOFF_CONFIG(EMPW) &&
4084 * If minimal inlining is requested the eMPW
4085 * feature should be disabled due to data is
4086 * inlined into Ethernet Segment, which can
4087 * not contain inlined data for eMPW due to
4088 * segment shared for all packets.
4090 struct mlx5_wqe_dseg *restrict dseg;
4095 * The inline-mode settings require
4096 * to inline the specified amount of
4097 * data bytes to the Ethernet Segment.
4098 * We should check the free space in
4099 * WQE ring buffer to inline partially.
4101 assert(txq->inlen_send >= txq->inlen_mode);
4102 assert(inlen > txq->inlen_mode);
4103 assert(txq->inlen_mode >=
4104 MLX5_ESEG_MIN_INLINE_SIZE);
4106 * Check whether there are enough free WQEBBs:
4108 * - Ethernet Segment
4109 * - First Segment of inlined Ethernet data
4110 * - ... data continued ...
4111 * - Finishing Data Segment of pointer type
4113 ds = (MLX5_WQE_CSEG_SIZE +
4114 MLX5_WQE_ESEG_SIZE +
4115 MLX5_WQE_DSEG_SIZE +
4117 MLX5_ESEG_MIN_INLINE_SIZE +
4118 MLX5_WQE_DSEG_SIZE +
4119 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4120 if (loc->wqe_free < ((ds + 3) / 4))
4121 return MLX5_TXCMP_CODE_EXIT;
4123 * Build the ordinary SEND WQE:
4125 * - Ethernet Segment, inline inlen_mode bytes
4126 * - Data Segment of pointer type
4128 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4129 loc->wqe_last = wqe;
4130 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4131 MLX5_OPCODE_SEND, olx);
4132 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4135 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4136 txq->inlen_mode - vlan;
4137 inlen -= txq->inlen_mode;
4138 mlx5_tx_dseg_ptr(txq, loc, dseg,
4141 * WQE is built, update the loop parameters
4142 * and got to the next packet.
4144 txq->wqe_ci += (ds + 3) / 4;
4145 loc->wqe_free -= (ds + 3) / 4;
4146 /* We have to store mbuf in elts.*/
4147 assert(MLX5_TXOFF_CONFIG(INLINE));
4148 txq->elts[txq->elts_head++ & txq->elts_m] =
4156 * Partially inlined packet data WQE, we have
4157 * some space in title WQEBB, we can fill it
4158 * with some packet data. It takes one WQEBB,
4159 * it is available, no extra space check:
4160 * - Control Segment, SEND opcode
4161 * - Ethernet Segment, no VLAN insertion
4162 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4163 * - Data Segment, pointer type
4165 * We also get here if VLAN insertion is not
4166 * supported by HW, the inline is enabled.
4168 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4169 loc->wqe_last = wqe;
4170 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4171 MLX5_OPCODE_SEND, olx);
4172 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4173 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4174 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4176 * The length check is performed above, by
4177 * comparing with txq->inlen_send. We should
4178 * not get overflow here.
4180 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4181 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4182 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4186 /* We have to store mbuf in elts.*/
4187 assert(MLX5_TXOFF_CONFIG(INLINE));
4188 txq->elts[txq->elts_head++ & txq->elts_m] =
4192 #ifdef MLX5_PMD_SOFT_COUNTERS
4193 /* Update sent data bytes counter. */
4194 txq->stats.obytes += vlan +
4195 rte_pktmbuf_data_len(loc->mbuf);
4199 * No inline at all, it means the CPU cycles saving
4200 * is prioritized at configuration, we should not
4201 * copy any packet data to WQE.
4203 * SEND WQE, one WQEBB:
4204 * - Control Segment, SEND opcode
4205 * - Ethernet Segment, optional VLAN, no inline
4206 * - Data Segment, pointer type
4208 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4209 loc->wqe_last = wqe;
4210 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4211 MLX5_OPCODE_SEND, olx);
4212 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4214 (txq, loc, &wqe->dseg[0],
4215 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4216 rte_pktmbuf_data_len(loc->mbuf), olx);
4220 * We should not store mbuf pointer in elts
4221 * if no inlining is configured, this is done
4222 * by calling routine in a batch copy.
4224 assert(!MLX5_TXOFF_CONFIG(INLINE));
4226 #ifdef MLX5_PMD_SOFT_COUNTERS
4227 /* Update sent data bytes counter. */
4228 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4229 if (MLX5_TXOFF_CONFIG(VLAN) &&
4230 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4231 txq->stats.obytes +=
4232 sizeof(struct rte_vlan_hdr);
4237 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4238 return MLX5_TXCMP_CODE_EXIT;
4239 loc->mbuf = *pkts++;
4241 rte_prefetch0(*pkts);
4242 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4243 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4249 static __rte_always_inline enum mlx5_txcmp_code
4250 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4251 struct rte_mbuf **restrict pkts,
4252 unsigned int pkts_n,
4253 struct mlx5_txq_local *restrict loc,
4256 enum mlx5_txcmp_code ret;
4258 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4259 if (ret == MLX5_TXCMP_CODE_SINGLE)
4261 assert(ret == MLX5_TXCMP_CODE_EMPW);
4263 /* Optimize for inline/no inline eMPW send. */
4264 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4265 mlx5_tx_burst_empw_inline
4266 (txq, pkts, pkts_n, loc, olx) :
4267 mlx5_tx_burst_empw_simple
4268 (txq, pkts, pkts_n, loc, olx);
4269 if (ret != MLX5_TXCMP_CODE_SINGLE)
4271 /* The resources to send one packet should remain. */
4272 assert(loc->elts_free && loc->wqe_free);
4274 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4275 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4276 if (ret != MLX5_TXCMP_CODE_EMPW)
4278 /* The resources to send one packet should remain. */
4279 assert(loc->elts_free && loc->wqe_free);
4284 * DPDK Tx callback template. This is configured template
4285 * used to generate routines optimized for specified offload setup.
4286 * One of this generated functions is chosen at SQ configuration
4290 * Generic pointer to TX queue structure.
4292 * Packets to transmit.
4294 * Number of packets in array.
4296 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4297 * values. Should be static to take compile time static configuration
4301 * Number of packets successfully transmitted (<= pkts_n).
4303 static __rte_always_inline uint16_t
4304 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4305 struct rte_mbuf **restrict pkts,
4309 struct mlx5_txq_local loc;
4310 enum mlx5_txcmp_code ret;
4313 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4314 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4316 * Check if there are some CQEs, if any:
4317 * - process an encountered errors
4318 * - process the completed WQEs
4319 * - free related mbufs
4320 * - doorbell the NIC about processed CQEs
4322 if (unlikely(!pkts_n))
4324 rte_prefetch0(*pkts);
4325 mlx5_tx_handle_completion(txq, olx);
4327 * Calculate the number of available resources - elts and WQEs.
4328 * There are two possible different scenarios:
4329 * - no data inlining into WQEs, one WQEBB may contains upto
4330 * four packets, in this case elts become scarce resource
4331 * - data inlining into WQEs, one packet may require multiple
4332 * WQEBBs, the WQEs become the limiting factor.
4334 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4335 loc.elts_free = txq->elts_s -
4336 (uint16_t)(txq->elts_head - txq->elts_tail);
4337 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4338 loc.wqe_free = txq->wqe_s -
4339 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4340 if (unlikely(!loc.elts_free || !loc.wqe_free))
4344 loc.wqe_last = NULL;
4347 * Fetch the packet from array. Usually this is
4348 * the first packet in series of multi/single
4351 loc.mbuf = *(pkts + loc.pkts_sent);
4352 /* Dedicated branch for multi-segment packets. */
4353 if (MLX5_TXOFF_CONFIG(MULTI) &&
4354 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4356 * Multi-segment packet encountered.
4357 * Hardware is able to process it only
4358 * with SEND/TSO opcodes, one packet
4359 * per WQE, do it in dedicated routine.
4362 assert(loc.pkts_sent >= loc.pkts_copy);
4363 part = loc.pkts_sent - loc.pkts_copy;
4364 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4366 * There are some single-segment mbufs not
4367 * stored in elts. The mbufs must be in the
4368 * same order as WQEs, so we must copy the
4369 * mbufs to elts here, before the coming
4370 * multi-segment packet mbufs is appended.
4372 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4374 loc.pkts_copy = loc.pkts_sent;
4376 assert(pkts_n > loc.pkts_sent);
4377 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4378 if (!MLX5_TXOFF_CONFIG(INLINE))
4379 loc.pkts_copy = loc.pkts_sent;
4381 * These returned code checks are supposed
4382 * to be optimized out due to routine inlining.
4384 if (ret == MLX5_TXCMP_CODE_EXIT) {
4386 * The routine returns this code when
4387 * all packets are sent or there is no
4388 * enough resources to complete request.
4392 if (ret == MLX5_TXCMP_CODE_ERROR) {
4394 * The routine returns this code when
4395 * some error in the incoming packets
4398 txq->stats.oerrors++;
4401 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4403 * The single-segment packet was encountered
4404 * in the array, try to send it with the
4405 * best optimized way, possible engaging eMPW.
4407 goto enter_send_single;
4409 if (MLX5_TXOFF_CONFIG(TSO) &&
4410 ret == MLX5_TXCMP_CODE_TSO) {
4412 * The single-segment TSO packet was
4413 * encountered in the array.
4415 goto enter_send_tso;
4417 /* We must not get here. Something is going wrong. */
4419 txq->stats.oerrors++;
4422 /* Dedicated branch for single-segment TSO packets. */
4423 if (MLX5_TXOFF_CONFIG(TSO) &&
4424 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4426 * TSO might require special way for inlining
4427 * (dedicated parameters) and is sent with
4428 * MLX5_OPCODE_TSO opcode only, provide this
4429 * in dedicated branch.
4432 assert(NB_SEGS(loc.mbuf) == 1);
4433 assert(pkts_n > loc.pkts_sent);
4434 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4436 * These returned code checks are supposed
4437 * to be optimized out due to routine inlining.
4439 if (ret == MLX5_TXCMP_CODE_EXIT)
4441 if (ret == MLX5_TXCMP_CODE_ERROR) {
4442 txq->stats.oerrors++;
4445 if (ret == MLX5_TXCMP_CODE_SINGLE)
4446 goto enter_send_single;
4447 if (MLX5_TXOFF_CONFIG(MULTI) &&
4448 ret == MLX5_TXCMP_CODE_MULTI) {
4450 * The multi-segment packet was
4451 * encountered in the array.
4453 goto enter_send_multi;
4455 /* We must not get here. Something is going wrong. */
4457 txq->stats.oerrors++;
4461 * The dedicated branch for the single-segment packets
4462 * without TSO. Often these ones can be sent using
4463 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4464 * The routine builds the WQEs till it encounters
4465 * the TSO or multi-segment packet (in case if these
4466 * offloads are requested at SQ configuration time).
4469 assert(pkts_n > loc.pkts_sent);
4470 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4472 * These returned code checks are supposed
4473 * to be optimized out due to routine inlining.
4475 if (ret == MLX5_TXCMP_CODE_EXIT)
4477 if (ret == MLX5_TXCMP_CODE_ERROR) {
4478 txq->stats.oerrors++;
4481 if (MLX5_TXOFF_CONFIG(MULTI) &&
4482 ret == MLX5_TXCMP_CODE_MULTI) {
4484 * The multi-segment packet was
4485 * encountered in the array.
4487 goto enter_send_multi;
4489 if (MLX5_TXOFF_CONFIG(TSO) &&
4490 ret == MLX5_TXCMP_CODE_TSO) {
4492 * The single-segment TSO packet was
4493 * encountered in the array.
4495 goto enter_send_tso;
4497 /* We must not get here. Something is going wrong. */
4499 txq->stats.oerrors++;
4503 * Main Tx loop is completed, do the rest:
4504 * - set completion request if thresholds are reached
4505 * - doorbell the hardware
4506 * - copy the rest of mbufs to elts (if any)
4508 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4509 /* Take a shortcut if nothing is sent. */
4510 if (unlikely(loc.pkts_sent == 0))
4512 /* Not all of the mbufs may be stored into elts yet. */
4513 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4514 mlx5_tx_request_completion(txq, part, &loc, olx);
4516 * Ring QP doorbell immediately after WQE building completion
4517 * to improve latencies. The pure software related data treatment
4518 * can be completed after doorbell. Tx CQEs for this SQ are
4519 * processed in this thread only by the polling.
4521 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);
4522 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4524 * There are some single-segment mbufs not stored in elts.
4525 * It can be only if last packet was single-segment.
4526 * The copying is gathered into one place due to it is
4527 * a good opportunity to optimize that with SIMD.
4528 * Unfortunately if inlining is enabled the gaps in
4529 * pointer array may happen due to early freeing of the
4532 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4534 #ifdef MLX5_PMD_SOFT_COUNTERS
4535 /* Increment sent packets counter. */
4536 txq->stats.opackets += loc.pkts_sent;
4538 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4539 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4540 return loc.pkts_sent;
4543 /* Generate routines with Enhanced Multi-Packet Write support. */
4544 MLX5_TXOFF_DECL(full_empw,
4545 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4547 MLX5_TXOFF_DECL(none_empw,
4548 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4550 MLX5_TXOFF_DECL(md_empw,
4551 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4553 MLX5_TXOFF_DECL(mt_empw,
4554 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4555 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4557 MLX5_TXOFF_DECL(mtsc_empw,
4558 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4559 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4560 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4562 MLX5_TXOFF_DECL(mti_empw,
4563 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4564 MLX5_TXOFF_CONFIG_INLINE |
4565 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4567 MLX5_TXOFF_DECL(mtv_empw,
4568 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4569 MLX5_TXOFF_CONFIG_VLAN |
4570 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4572 MLX5_TXOFF_DECL(mtiv_empw,
4573 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4574 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4575 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4577 MLX5_TXOFF_DECL(sc_empw,
4578 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4579 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4581 MLX5_TXOFF_DECL(sci_empw,
4582 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4583 MLX5_TXOFF_CONFIG_INLINE |
4584 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4586 MLX5_TXOFF_DECL(scv_empw,
4587 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4588 MLX5_TXOFF_CONFIG_VLAN |
4589 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4591 MLX5_TXOFF_DECL(sciv_empw,
4592 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4593 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4594 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4596 MLX5_TXOFF_DECL(i_empw,
4597 MLX5_TXOFF_CONFIG_INLINE |
4598 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4600 MLX5_TXOFF_DECL(v_empw,
4601 MLX5_TXOFF_CONFIG_VLAN |
4602 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4604 MLX5_TXOFF_DECL(iv_empw,
4605 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4606 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4608 /* Generate routines without Enhanced Multi-Packet Write support. */
4609 MLX5_TXOFF_DECL(full,
4610 MLX5_TXOFF_CONFIG_FULL)
4612 MLX5_TXOFF_DECL(none,
4613 MLX5_TXOFF_CONFIG_NONE)
4616 MLX5_TXOFF_CONFIG_METADATA)
4619 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4620 MLX5_TXOFF_CONFIG_METADATA)
4622 MLX5_TXOFF_DECL(mtsc,
4623 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4624 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4625 MLX5_TXOFF_CONFIG_METADATA)
4627 MLX5_TXOFF_DECL(mti,
4628 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4629 MLX5_TXOFF_CONFIG_INLINE |
4630 MLX5_TXOFF_CONFIG_METADATA)
4633 MLX5_TXOFF_DECL(mtv,
4634 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4635 MLX5_TXOFF_CONFIG_VLAN |
4636 MLX5_TXOFF_CONFIG_METADATA)
4639 MLX5_TXOFF_DECL(mtiv,
4640 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4641 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4642 MLX5_TXOFF_CONFIG_METADATA)
4645 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4646 MLX5_TXOFF_CONFIG_METADATA)
4648 MLX5_TXOFF_DECL(sci,
4649 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4650 MLX5_TXOFF_CONFIG_INLINE |
4651 MLX5_TXOFF_CONFIG_METADATA)
4654 MLX5_TXOFF_DECL(scv,
4655 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4656 MLX5_TXOFF_CONFIG_VLAN |
4657 MLX5_TXOFF_CONFIG_METADATA)
4660 MLX5_TXOFF_DECL(sciv,
4661 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4662 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4663 MLX5_TXOFF_CONFIG_METADATA)
4666 MLX5_TXOFF_CONFIG_INLINE |
4667 MLX5_TXOFF_CONFIG_METADATA)
4670 MLX5_TXOFF_CONFIG_VLAN |
4671 MLX5_TXOFF_CONFIG_METADATA)
4674 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4675 MLX5_TXOFF_CONFIG_METADATA)
4678 * Array of declared and compiled Tx burst function and corresponding
4679 * supported offloads set. The array is used to select the Tx burst
4680 * function for specified offloads set at Tx queue configuration time.
4683 eth_tx_burst_t func;
4686 MLX5_TXOFF_INFO(full_empw,
4687 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4688 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4689 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4690 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4692 MLX5_TXOFF_INFO(none_empw,
4693 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4695 MLX5_TXOFF_INFO(md_empw,
4696 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4698 MLX5_TXOFF_INFO(mt_empw,
4699 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4700 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4702 MLX5_TXOFF_INFO(mtsc_empw,
4703 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4704 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4705 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4707 MLX5_TXOFF_INFO(mti_empw,
4708 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4709 MLX5_TXOFF_CONFIG_INLINE |
4710 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4712 MLX5_TXOFF_INFO(mtv_empw,
4713 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4714 MLX5_TXOFF_CONFIG_VLAN |
4715 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4717 MLX5_TXOFF_INFO(mtiv_empw,
4718 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4719 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4720 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4722 MLX5_TXOFF_INFO(sc_empw,
4723 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4724 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4726 MLX5_TXOFF_INFO(sci_empw,
4727 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4728 MLX5_TXOFF_CONFIG_INLINE |
4729 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4731 MLX5_TXOFF_INFO(scv_empw,
4732 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4733 MLX5_TXOFF_CONFIG_VLAN |
4734 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4736 MLX5_TXOFF_INFO(sciv_empw,
4737 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4738 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4739 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4741 MLX5_TXOFF_INFO(i_empw,
4742 MLX5_TXOFF_CONFIG_INLINE |
4743 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4745 MLX5_TXOFF_INFO(v_empw,
4746 MLX5_TXOFF_CONFIG_VLAN |
4747 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4749 MLX5_TXOFF_INFO(iv_empw,
4750 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4751 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4753 MLX5_TXOFF_INFO(full,
4754 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4755 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4756 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4757 MLX5_TXOFF_CONFIG_METADATA)
4759 MLX5_TXOFF_INFO(none,
4760 MLX5_TXOFF_CONFIG_NONE)
4763 MLX5_TXOFF_CONFIG_METADATA)
4766 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4767 MLX5_TXOFF_CONFIG_METADATA)
4769 MLX5_TXOFF_INFO(mtsc,
4770 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4771 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4772 MLX5_TXOFF_CONFIG_METADATA)
4774 MLX5_TXOFF_INFO(mti,
4775 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4776 MLX5_TXOFF_CONFIG_INLINE |
4777 MLX5_TXOFF_CONFIG_METADATA)
4780 MLX5_TXOFF_INFO(mtv,
4781 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4782 MLX5_TXOFF_CONFIG_VLAN |
4783 MLX5_TXOFF_CONFIG_METADATA)
4785 MLX5_TXOFF_INFO(mtiv,
4786 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4787 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4788 MLX5_TXOFF_CONFIG_METADATA)
4791 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4792 MLX5_TXOFF_CONFIG_METADATA)
4794 MLX5_TXOFF_INFO(sci,
4795 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4796 MLX5_TXOFF_CONFIG_INLINE |
4797 MLX5_TXOFF_CONFIG_METADATA)
4799 MLX5_TXOFF_INFO(scv,
4800 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4801 MLX5_TXOFF_CONFIG_VLAN |
4802 MLX5_TXOFF_CONFIG_METADATA)
4804 MLX5_TXOFF_INFO(sciv,
4805 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4806 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4807 MLX5_TXOFF_CONFIG_METADATA)
4810 MLX5_TXOFF_CONFIG_INLINE |
4811 MLX5_TXOFF_CONFIG_METADATA)
4814 MLX5_TXOFF_CONFIG_VLAN |
4815 MLX5_TXOFF_CONFIG_METADATA)
4818 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4819 MLX5_TXOFF_CONFIG_METADATA)
4823 * Configure the Tx function to use. The routine checks configured
4824 * Tx offloads for the device and selects appropriate Tx burst
4825 * routine. There are multiple Tx burst routines compiled from
4826 * the same template in the most optimal way for the dedicated
4830 * Pointer to private data structure.
4833 * Pointer to selected Tx burst function.
4836 mlx5_select_tx_function(struct rte_eth_dev *dev)
4838 struct mlx5_priv *priv = dev->data->dev_private;
4839 struct mlx5_dev_config *config = &priv->config;
4840 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
4841 unsigned int diff = 0, olx = 0, i, m;
4843 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
4844 MLX5_DSEG_MAX, "invalid WQE max size");
4845 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
4846 "invalid WQE Control Segment size");
4847 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
4848 "invalid WQE Ethernet Segment size");
4849 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
4850 "invalid WQE Data Segment size");
4851 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
4852 "invalid WQE size");
4854 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
4855 /* We should support Multi-Segment Packets. */
4856 olx |= MLX5_TXOFF_CONFIG_MULTI;
4858 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
4859 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
4860 DEV_TX_OFFLOAD_GRE_TNL_TSO |
4861 DEV_TX_OFFLOAD_IP_TNL_TSO |
4862 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
4863 /* We should support TCP Send Offload. */
4864 olx |= MLX5_TXOFF_CONFIG_TSO;
4866 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
4867 DEV_TX_OFFLOAD_UDP_TNL_TSO |
4868 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
4869 /* We should support Software Parser for Tunnels. */
4870 olx |= MLX5_TXOFF_CONFIG_SWP;
4872 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
4873 DEV_TX_OFFLOAD_UDP_CKSUM |
4874 DEV_TX_OFFLOAD_TCP_CKSUM |
4875 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
4876 /* We should support IP/TCP/UDP Checksums. */
4877 olx |= MLX5_TXOFF_CONFIG_CSUM;
4879 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
4880 /* We should support VLAN insertion. */
4881 olx |= MLX5_TXOFF_CONFIG_VLAN;
4883 if (priv->txqs_n && (*priv->txqs)[0]) {
4884 struct mlx5_txq_data *txd = (*priv->txqs)[0];
4886 if (txd->inlen_send) {
4888 * Check the data inline requirements. Data inline
4889 * is enabled on per device basis, we can check
4890 * the first Tx queue only.
4892 * If device does not support VLAN insertion in WQE
4893 * and some queues are requested to perform VLAN
4894 * insertion offload than inline must be enabled.
4896 olx |= MLX5_TXOFF_CONFIG_INLINE;
4899 if (config->mps == MLX5_MPW_ENHANCED &&
4900 config->txq_inline_min <= 0) {
4902 * The NIC supports Enhanced Multi-Packet Write.
4903 * We do not support legacy MPW due to its
4904 * hardware related problems, so we just ignore
4905 * legacy MLX5_MPW settings. There should be no
4906 * minimal required inline data.
4908 olx |= MLX5_TXOFF_CONFIG_EMPW;
4910 if (tx_offloads & DEV_TX_OFFLOAD_MATCH_METADATA) {
4911 /* We should support Flow metadata. */
4912 olx |= MLX5_TXOFF_CONFIG_METADATA;
4915 * Scan the routines table to find the minimal
4916 * satisfying routine with requested offloads.
4918 m = RTE_DIM(txoff_func);
4919 for (i = 0; i < RTE_DIM(txoff_func); i++) {
4922 tmp = txoff_func[i].olx;
4924 /* Meets requested offloads exactly.*/
4928 if ((tmp & olx) != olx) {
4929 /* Does not meet requested offloads at all. */
4932 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
4933 /* Do not enable eMPW if not configured. */
4935 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
4936 /* Do not enable inlining if not configured. */
4939 * Some routine meets the requirements.
4940 * Check whether it has minimal amount
4941 * of not requested offloads.
4943 tmp = __builtin_popcountl(tmp & ~olx);
4944 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
4945 /* First or better match, save and continue. */
4951 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
4952 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
4953 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
4954 /* Lighter not requested offload. */
4959 if (m >= RTE_DIM(txoff_func)) {
4960 DRV_LOG(DEBUG, "port %u has no selected Tx function"
4961 " for requested offloads %04X",
4962 dev->data->port_id, olx);
4965 DRV_LOG(DEBUG, "port %u has selected Tx function"
4966 " supporting offloads %04X/%04X",
4967 dev->data->port_id, olx, txoff_func[m].olx);
4968 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
4969 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
4970 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
4971 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
4972 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
4973 DRV_LOG(DEBUG, "\tSWP (software parser)");
4974 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
4975 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
4976 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
4977 DRV_LOG(DEBUG, "\tINLIN (inline data)");
4978 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
4979 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
4980 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
4981 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
4982 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW)
4983 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
4984 return txoff_func[m].func;