1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include "mlx5_utils.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* TX burst subroutines return codes. */
38 enum mlx5_txcmp_code {
39 MLX5_TXCMP_CODE_EXIT = 0,
40 MLX5_TXCMP_CODE_ERROR,
41 MLX5_TXCMP_CODE_SINGLE,
42 MLX5_TXCMP_CODE_MULTI,
48 * These defines are used to configure Tx burst routine option set
49 * supported at compile time. The not specified options are optimized out
50 * out due to if conditions can be explicitly calculated at compile time.
51 * The offloads with bigger runtime check (require more CPU cycles to
52 * skip) overhead should have the bigger index - this is needed to
53 * select the better matching routine function if no exact match and
54 * some offloads are not actually requested.
56 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
57 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
58 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
59 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
60 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
61 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
62 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
63 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 /* The most common offloads groups. */
66 #define MLX5_TXOFF_CONFIG_NONE 0
67 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
68 MLX5_TXOFF_CONFIG_TSO | \
69 MLX5_TXOFF_CONFIG_SWP | \
70 MLX5_TXOFF_CONFIG_CSUM | \
71 MLX5_TXOFF_CONFIG_INLINE | \
72 MLX5_TXOFF_CONFIG_VLAN | \
73 MLX5_TXOFF_CONFIG_METADATA)
75 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
77 #define MLX5_TXOFF_DECL(func, olx) \
78 static uint16_t mlx5_tx_burst_##func(void *txq, \
79 struct rte_mbuf **pkts, \
82 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
83 pkts, pkts_n, (olx)); \
86 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
88 static __rte_always_inline uint32_t
89 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
91 static __rte_always_inline int
92 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
95 static __rte_always_inline uint32_t
96 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
98 static __rte_always_inline void
99 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
100 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
102 static __rte_always_inline void
103 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
104 const unsigned int strd_n);
107 mlx5_queue_state_modify(struct rte_eth_dev *dev,
108 struct mlx5_mp_arg_queue_state_modify *sm);
111 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
112 volatile struct mlx5_cqe *restrict cqe,
116 mlx5_lro_update_hdr(uint8_t *restrict padd,
117 volatile struct mlx5_cqe *restrict cqe,
120 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
121 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
124 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
125 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
128 * Build a table to translate Rx completion flags to packet type.
130 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
133 mlx5_set_ptype_table(void)
136 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
138 /* Last entry must not be overwritten, reserved for errored packet. */
139 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
140 (*p)[i] = RTE_PTYPE_UNKNOWN;
142 * The index to the array should have:
143 * bit[1:0] = l3_hdr_type
144 * bit[4:2] = l4_hdr_type
147 * bit[7] = outer_l3_type
150 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
152 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
153 RTE_PTYPE_L4_NONFRAG;
154 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_L4_NONFRAG;
157 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
159 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
172 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 /* Repeat with outer_l3_type being set. Just in case. */
180 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_L4_NONFRAG;
182 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_L4_NONFRAG;
184 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
202 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
206 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
213 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_NONFRAG;
216 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_NONFRAG;
219 /* Tunneled - Fragmented */
220 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_FRAG;
223 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_FRAG;
226 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_FRAG;
229 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_FRAG;
233 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_TCP;
236 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L4_TCP;
239 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L4_TCP;
242 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L4_TCP;
245 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
247 RTE_PTYPE_INNER_L4_TCP;
248 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L4_TCP;
251 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L4_TCP;
254 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L4_TCP;
257 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
259 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_TCP;
263 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_TCP;
270 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_UDP;
273 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L4_UDP;
276 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
278 RTE_PTYPE_INNER_L4_UDP;
279 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_UDP;
285 * Build a table to translate packet to checksum type of Verbs.
288 mlx5_set_cksum_table(void)
294 * The index should have:
295 * bit[0] = PKT_TX_TCP_SEG
296 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
297 * bit[4] = PKT_TX_IP_CKSUM
298 * bit[8] = PKT_TX_OUTER_IP_CKSUM
301 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
304 /* Tunneled packet. */
305 if (i & (1 << 8)) /* Outer IP. */
306 v |= MLX5_ETH_WQE_L3_CSUM;
307 if (i & (1 << 4)) /* Inner IP. */
308 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
309 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
310 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
313 if (i & (1 << 4)) /* IP. */
314 v |= MLX5_ETH_WQE_L3_CSUM;
315 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
316 v |= MLX5_ETH_WQE_L4_CSUM;
318 mlx5_cksum_table[i] = v;
323 * Build a table to translate packet type of mbuf to SWP type of Verbs.
326 mlx5_set_swp_types_table(void)
332 * The index should have:
333 * bit[0:1] = PKT_TX_L4_MASK
334 * bit[4] = PKT_TX_IPV6
335 * bit[8] = PKT_TX_OUTER_IPV6
336 * bit[9] = PKT_TX_OUTER_UDP
338 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
341 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
343 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
345 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
346 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
347 v |= MLX5_ETH_WQE_L4_INNER_UDP;
348 mlx5_swp_types_table[i] = v;
353 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
354 * Flags must be preliminary initialized to zero.
357 * Pointer to burst routine local context.
359 * Pointer to store Software Parser flags
361 * Configured Tx offloads mask. It is fully defined at
362 * compile time and may be used for optimization.
365 * Software Parser offsets packed in dword.
366 * Software Parser flags are set by pointer.
368 static __rte_always_inline uint32_t
369 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
374 unsigned int idx, off;
377 if (!MLX5_TXOFF_CONFIG(SWP))
379 ol = loc->mbuf->ol_flags;
380 tunnel = ol & PKT_TX_TUNNEL_MASK;
382 * Check whether Software Parser is required.
383 * Only customized tunnels may ask for.
385 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
388 * The index should have:
389 * bit[0:1] = PKT_TX_L4_MASK
390 * bit[4] = PKT_TX_IPV6
391 * bit[8] = PKT_TX_OUTER_IPV6
392 * bit[9] = PKT_TX_OUTER_UDP
394 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
395 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
396 *swp_flags = mlx5_swp_types_table[idx];
398 * Set offsets for SW parser. Since ConnectX-5, SW parser just
399 * complements HW parser. SW parser starts to engage only if HW parser
400 * can't reach a header. For the older devices, HW parser will not kick
401 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
402 * should be set regardless of HW offload.
404 off = loc->mbuf->outer_l2_len;
405 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
406 off += sizeof(struct rte_vlan_hdr);
407 set = (off >> 1) << 8; /* Outer L3 offset. */
408 off += loc->mbuf->outer_l3_len;
409 if (tunnel == PKT_TX_TUNNEL_UDP)
410 set |= off >> 1; /* Outer L4 offset. */
411 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
412 const uint64_t csum = ol & PKT_TX_L4_MASK;
413 off += loc->mbuf->l2_len;
414 set |= (off >> 1) << 24; /* Inner L3 offset. */
415 if (csum == PKT_TX_TCP_CKSUM ||
416 csum == PKT_TX_UDP_CKSUM ||
417 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
418 off += loc->mbuf->l3_len;
419 set |= (off >> 1) << 16; /* Inner L4 offset. */
422 set = rte_cpu_to_le_32(set);
427 * Convert the Checksum offloads to Verbs.
430 * Pointer to the mbuf.
433 * Converted checksum flags.
435 static __rte_always_inline uint8_t
436 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
439 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
440 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
441 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
444 * The index should have:
445 * bit[0] = PKT_TX_TCP_SEG
446 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
447 * bit[4] = PKT_TX_IP_CKSUM
448 * bit[8] = PKT_TX_OUTER_IP_CKSUM
451 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
452 return mlx5_cksum_table[idx];
456 * Internal function to compute the number of used descriptors in an RX queue
462 * The number of used rx descriptor.
465 rx_queue_count(struct mlx5_rxq_data *rxq)
467 struct rxq_zip *zip = &rxq->zip;
468 volatile struct mlx5_cqe *cqe;
469 const unsigned int cqe_n = (1 << rxq->cqe_n);
470 const unsigned int cqe_cnt = cqe_n - 1;
474 /* if we are processing a compressed cqe */
476 used = zip->cqe_cnt - zip->ca;
482 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
483 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
487 op_own = cqe->op_own;
488 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
489 n = rte_be_to_cpu_32(cqe->byte_cnt);
494 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
496 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
501 * DPDK callback to check the status of a rx descriptor.
506 * The index of the descriptor in the ring.
509 * The status of the tx descriptor.
512 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
514 struct mlx5_rxq_data *rxq = rx_queue;
515 struct mlx5_rxq_ctrl *rxq_ctrl =
516 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
517 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
519 if (dev->rx_pkt_burst != mlx5_rx_burst) {
523 if (offset >= (1 << rxq->elts_n)) {
527 if (offset < rx_queue_count(rxq))
528 return RTE_ETH_RX_DESC_DONE;
529 return RTE_ETH_RX_DESC_AVAIL;
533 * DPDK callback to get the number of used descriptors in a RX queue
536 * Pointer to the device structure.
542 * The number of used rx descriptor.
543 * -EINVAL if the queue is invalid
546 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
548 struct mlx5_priv *priv = dev->data->dev_private;
549 struct mlx5_rxq_data *rxq;
551 if (dev->rx_pkt_burst != mlx5_rx_burst) {
555 rxq = (*priv->rxqs)[rx_queue_id];
560 return rx_queue_count(rxq);
563 #define MLX5_SYSTEM_LOG_DIR "/var/log"
565 * Dump debug information to log file.
570 * If not NULL this string is printed as a header to the output
571 * and the output will be in hexadecimal view.
573 * This is the buffer address to print out.
575 * The number of bytes to dump out.
578 mlx5_dump_debug_information(const char *fname, const char *hex_title,
579 const void *buf, unsigned int hex_len)
583 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
584 fd = fopen(path, "a+");
586 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
588 MKSTR(path2, "./%s", fname);
589 fd = fopen(path2, "a+");
591 DRV_LOG(ERR, "cannot open %s for debug dump\n",
595 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
597 DRV_LOG(INFO, "New debug dump in file %s\n", path);
600 rte_hexdump(fd, hex_title, buf, hex_len);
602 fprintf(fd, "%s", (const char *)buf);
603 fprintf(fd, "\n\n\n");
608 * Move QP from error state to running state and initialize indexes.
611 * Pointer to TX queue control structure.
614 * 0 on success, else -1.
617 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
619 struct mlx5_mp_arg_queue_state_modify sm = {
621 .queue_id = txq_ctrl->txq.idx,
624 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
626 txq_ctrl->txq.wqe_ci = 0;
627 txq_ctrl->txq.wqe_pi = 0;
628 txq_ctrl->txq.elts_comp = 0;
632 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
634 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
636 static const uint8_t magic[] = "seen";
640 for (i = 0; i < sizeof(magic); ++i)
641 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
643 err_cqe->rsvd1[i] = magic[i];
652 * Pointer to TX queue structure.
654 * Pointer to the error CQE.
657 * The last Tx buffer element to free.
660 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
661 volatile struct mlx5_err_cqe *err_cqe)
663 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
664 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
665 struct mlx5_txq_ctrl *txq_ctrl =
666 container_of(txq, struct mlx5_txq_ctrl, txq);
667 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
668 int seen = check_err_cqe_seen(err_cqe);
670 if (!seen && txq_ctrl->dump_file_n <
671 txq_ctrl->priv->config.max_dump_files_num) {
672 MKSTR(err_str, "Unexpected CQE error syndrome "
673 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
674 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
675 txq->cqe_s, txq->qp_num_8s >> 8,
676 rte_be_to_cpu_16(err_cqe->wqe_counter),
677 txq->wqe_ci, txq->cq_ci);
678 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
679 PORT_ID(txq_ctrl->priv), txq->idx,
680 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
681 mlx5_dump_debug_information(name, NULL, err_str, 0);
682 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
683 (const void *)((uintptr_t)
687 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
688 (const void *)((uintptr_t)
692 txq_ctrl->dump_file_n++;
696 * Count errors in WQEs units.
697 * Later it can be improved to count error packets,
698 * for example, by SQ parsing to find how much packets
699 * should be counted for each WQE.
701 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
703 if (tx_recover_qp(txq_ctrl) == 0) {
705 /* Release all the remaining buffers. */
706 return txq->elts_head;
708 /* Recovering failed - try again later on the same WQE. */
712 /* Do not release buffers. */
713 return txq->elts_tail;
717 * Translate RX completion flags to packet type.
720 * Pointer to RX queue structure.
724 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
727 * Packet type for struct rte_mbuf.
729 static inline uint32_t
730 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
733 uint8_t pinfo = cqe->pkt_info;
734 uint16_t ptype = cqe->hdr_type_etc;
737 * The index to the array should have:
738 * bit[1:0] = l3_hdr_type
739 * bit[4:2] = l4_hdr_type
742 * bit[7] = outer_l3_type
744 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
745 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
749 * Initialize Rx WQ and indexes.
752 * Pointer to RX queue structure.
755 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
757 const unsigned int wqe_n = 1 << rxq->elts_n;
760 for (i = 0; (i != wqe_n); ++i) {
761 volatile struct mlx5_wqe_data_seg *scat;
765 if (mlx5_rxq_mprq_enabled(rxq)) {
766 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
768 scat = &((volatile struct mlx5_wqe_mprq *)
770 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
771 1 << rxq->strd_num_n);
772 byte_count = (1 << rxq->strd_sz_n) *
773 (1 << rxq->strd_num_n);
775 struct rte_mbuf *buf = (*rxq->elts)[i];
777 scat = &((volatile struct mlx5_wqe_data_seg *)
779 addr = rte_pktmbuf_mtod(buf, uintptr_t);
780 byte_count = DATA_LEN(buf);
782 /* scat->addr must be able to store a pointer. */
783 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
784 *scat = (struct mlx5_wqe_data_seg){
785 .addr = rte_cpu_to_be_64(addr),
786 .byte_count = rte_cpu_to_be_32(byte_count),
787 .lkey = mlx5_rx_addr2mr(rxq, addr),
790 rxq->consumed_strd = 0;
791 rxq->decompressed = 0;
793 rxq->zip = (struct rxq_zip){
796 /* Update doorbell counter. */
797 rxq->rq_ci = wqe_n >> rxq->sges_n;
799 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
803 * Modify a Verbs/DevX queue state.
804 * This must be called from the primary process.
807 * Pointer to Ethernet device.
809 * State modify request parameters.
812 * 0 in case of success else non-zero value and rte_errno is set.
815 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
816 const struct mlx5_mp_arg_queue_state_modify *sm)
819 struct mlx5_priv *priv = dev->data->dev_private;
822 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
823 struct mlx5_rxq_ctrl *rxq_ctrl =
824 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
826 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
827 struct ibv_wq_attr mod = {
828 .attr_mask = IBV_WQ_ATTR_STATE,
829 .wq_state = sm->state,
832 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
833 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
834 struct mlx5_devx_modify_rq_attr rq_attr;
836 memset(&rq_attr, 0, sizeof(rq_attr));
837 if (sm->state == IBV_WQS_RESET) {
838 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
839 rq_attr.state = MLX5_RQC_STATE_RST;
840 } else if (sm->state == IBV_WQS_RDY) {
841 rq_attr.rq_state = MLX5_RQC_STATE_RST;
842 rq_attr.state = MLX5_RQC_STATE_RDY;
843 } else if (sm->state == IBV_WQS_ERR) {
844 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
845 rq_attr.state = MLX5_RQC_STATE_ERR;
847 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
851 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s\n",
852 sm->state, strerror(errno));
857 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
858 struct mlx5_txq_ctrl *txq_ctrl =
859 container_of(txq, struct mlx5_txq_ctrl, txq);
860 struct ibv_qp_attr mod = {
861 .qp_state = IBV_QPS_RESET,
862 .port_num = (uint8_t)priv->ibv_port,
864 struct ibv_qp *qp = txq_ctrl->ibv->qp;
866 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
868 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
869 "%s\n", strerror(errno));
873 mod.qp_state = IBV_QPS_INIT;
874 ret = mlx5_glue->modify_qp(qp, &mod,
875 (IBV_QP_STATE | IBV_QP_PORT));
877 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s\n",
882 mod.qp_state = IBV_QPS_RTR;
883 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
885 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s\n",
890 mod.qp_state = IBV_QPS_RTS;
891 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
893 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s\n",
903 * Modify a Verbs queue state.
906 * Pointer to Ethernet device.
908 * State modify request parameters.
911 * 0 in case of success else non-zero value.
914 mlx5_queue_state_modify(struct rte_eth_dev *dev,
915 struct mlx5_mp_arg_queue_state_modify *sm)
919 switch (rte_eal_process_type()) {
920 case RTE_PROC_PRIMARY:
921 ret = mlx5_queue_state_modify_primary(dev, sm);
923 case RTE_PROC_SECONDARY:
924 ret = mlx5_mp_req_queue_state_modify(dev, sm);
934 * The function inserts the RQ state to reset when the first error CQE is
935 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
936 * it moves the RQ state to ready and initializes the RQ.
937 * Next CQE identification and error counting are in the caller responsibility.
940 * Pointer to RX queue structure.
941 * @param[in] mbuf_prepare
942 * Whether to prepare mbufs for the RQ.
945 * -1 in case of recovery error, otherwise the CQE status.
948 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
950 const uint16_t cqe_n = 1 << rxq->cqe_n;
951 const uint16_t cqe_mask = cqe_n - 1;
952 const unsigned int wqe_n = 1 << rxq->elts_n;
953 struct mlx5_rxq_ctrl *rxq_ctrl =
954 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
956 volatile struct mlx5_cqe *cqe;
957 volatile struct mlx5_err_cqe *err_cqe;
959 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
961 struct mlx5_mp_arg_queue_state_modify sm;
964 switch (rxq->err_state) {
965 case MLX5_RXQ_ERR_STATE_NO_ERROR:
966 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
968 case MLX5_RXQ_ERR_STATE_NEED_RESET:
970 sm.queue_id = rxq->idx;
971 sm.state = IBV_WQS_RESET;
972 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
974 if (rxq_ctrl->dump_file_n <
975 rxq_ctrl->priv->config.max_dump_files_num) {
976 MKSTR(err_str, "Unexpected CQE error syndrome "
977 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
978 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
979 rxq->cqn, rxq_ctrl->wqn,
980 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
981 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
982 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
983 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
984 mlx5_dump_debug_information(name, NULL, err_str, 0);
985 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
986 (const void *)((uintptr_t)
988 sizeof(*u.cqe) * cqe_n);
989 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
990 (const void *)((uintptr_t)
993 rxq_ctrl->dump_file_n++;
995 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
997 case MLX5_RXQ_ERR_STATE_NEED_READY:
998 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
999 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1001 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1004 * The RQ consumer index must be zeroed while moving
1005 * from RESET state to RDY state.
1007 *rxq->rq_db = rte_cpu_to_be_32(0);
1010 sm.queue_id = rxq->idx;
1011 sm.state = IBV_WQS_RDY;
1012 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1016 const uint16_t q_mask = wqe_n - 1;
1018 struct rte_mbuf **elt;
1020 unsigned int n = wqe_n - (rxq->rq_ci -
1023 for (i = 0; i < (int)n; ++i) {
1024 elt_idx = (rxq->rq_ci + i) & q_mask;
1025 elt = &(*rxq->elts)[elt_idx];
1026 *elt = rte_mbuf_raw_alloc(rxq->mp);
1028 for (i--; i >= 0; --i) {
1029 elt_idx = (rxq->rq_ci +
1033 rte_pktmbuf_free_seg
1040 mlx5_rxq_initialize(rxq);
1041 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1050 * Get size of the next packet for a given CQE. For compressed CQEs, the
1051 * consumer index is updated only once all packets of the current one have
1055 * Pointer to RX queue.
1059 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1063 * 0 in case of empty CQE, otherwise the packet size in bytes.
1066 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1067 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1069 struct rxq_zip *zip = &rxq->zip;
1070 uint16_t cqe_n = cqe_cnt + 1;
1076 /* Process compressed data in the CQE and mini arrays. */
1078 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1079 (volatile struct mlx5_mini_cqe8 (*)[8])
1080 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1083 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1084 *mcqe = &(*mc)[zip->ai & 7];
1085 if ((++zip->ai & 7) == 0) {
1086 /* Invalidate consumed CQEs */
1089 while (idx != end) {
1090 (*rxq->cqes)[idx & cqe_cnt].op_own =
1091 MLX5_CQE_INVALIDATE;
1095 * Increment consumer index to skip the number
1096 * of CQEs consumed. Hardware leaves holes in
1097 * the CQ ring for software use.
1102 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1103 /* Invalidate the rest */
1107 while (idx != end) {
1108 (*rxq->cqes)[idx & cqe_cnt].op_own =
1109 MLX5_CQE_INVALIDATE;
1112 rxq->cq_ci = zip->cq_ci;
1116 * No compressed data, get next CQE and verify if it is
1123 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1124 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1125 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1127 ret = mlx5_rx_err_handle(rxq, 0);
1128 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1136 op_own = cqe->op_own;
1137 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1138 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1139 (volatile struct mlx5_mini_cqe8 (*)[8])
1140 (uintptr_t)(&(*rxq->cqes)
1144 /* Fix endianness. */
1145 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1147 * Current mini array position is the one
1148 * returned by check_cqe64().
1150 * If completion comprises several mini arrays,
1151 * as a special case the second one is located
1152 * 7 CQEs after the initial CQE instead of 8
1153 * for subsequent ones.
1155 zip->ca = rxq->cq_ci;
1156 zip->na = zip->ca + 7;
1157 /* Compute the next non compressed CQE. */
1159 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1160 /* Get packet size to return. */
1161 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1164 /* Prefetch all to be invalidated */
1167 while (idx != end) {
1168 rte_prefetch0(&(*rxq->cqes)[(idx) &
1173 len = rte_be_to_cpu_32(cqe->byte_cnt);
1176 if (unlikely(rxq->err_state)) {
1177 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1178 ++rxq->stats.idropped;
1186 * Translate RX completion flags to offload flags.
1192 * Offload flags (ol_flags) for struct rte_mbuf.
1194 static inline uint32_t
1195 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1197 uint32_t ol_flags = 0;
1198 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1202 MLX5_CQE_RX_L3_HDR_VALID,
1203 PKT_RX_IP_CKSUM_GOOD) |
1205 MLX5_CQE_RX_L4_HDR_VALID,
1206 PKT_RX_L4_CKSUM_GOOD);
1211 * Fill in mbuf fields from RX completion flags.
1212 * Note that pkt->ol_flags should be initialized outside of this function.
1215 * Pointer to RX queue.
1220 * @param rss_hash_res
1221 * Packet RSS Hash result.
1224 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1225 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1227 /* Update packet information. */
1228 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1229 if (rss_hash_res && rxq->rss_hash) {
1230 pkt->hash.rss = rss_hash_res;
1231 pkt->ol_flags |= PKT_RX_RSS_HASH;
1233 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1234 pkt->ol_flags |= PKT_RX_FDIR;
1235 if (cqe->sop_drop_qpn !=
1236 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1237 uint32_t mark = cqe->sop_drop_qpn;
1239 pkt->ol_flags |= PKT_RX_FDIR_ID;
1240 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1244 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1245 if (rxq->vlan_strip &&
1246 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1247 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1248 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1250 if (rxq->hw_timestamp) {
1251 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1252 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1257 * DPDK callback for RX.
1260 * Generic pointer to RX queue structure.
1262 * Array to store received packets.
1264 * Maximum number of packets in array.
1267 * Number of packets successfully received (<= pkts_n).
1270 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1272 struct mlx5_rxq_data *rxq = dpdk_rxq;
1273 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1274 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1275 const unsigned int sges_n = rxq->sges_n;
1276 struct rte_mbuf *pkt = NULL;
1277 struct rte_mbuf *seg = NULL;
1278 volatile struct mlx5_cqe *cqe =
1279 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1281 unsigned int rq_ci = rxq->rq_ci << sges_n;
1282 int len = 0; /* keep its value across iterations. */
1285 unsigned int idx = rq_ci & wqe_cnt;
1286 volatile struct mlx5_wqe_data_seg *wqe =
1287 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1288 struct rte_mbuf *rep = (*rxq->elts)[idx];
1289 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1290 uint32_t rss_hash_res;
1298 rep = rte_mbuf_raw_alloc(rxq->mp);
1299 if (unlikely(rep == NULL)) {
1300 ++rxq->stats.rx_nombuf;
1303 * no buffers before we even started,
1304 * bail out silently.
1308 while (pkt != seg) {
1309 assert(pkt != (*rxq->elts)[idx]);
1313 rte_mbuf_raw_free(pkt);
1319 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1320 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1322 rte_mbuf_raw_free(rep);
1326 assert(len >= (rxq->crc_present << 2));
1328 /* If compressed, take hash result from mini-CQE. */
1329 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1331 mcqe->rx_hash_result);
1332 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1333 if (rxq->crc_present)
1334 len -= RTE_ETHER_CRC_LEN;
1336 if (cqe->lro_num_seg > 1) {
1338 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1340 pkt->ol_flags |= PKT_RX_LRO;
1341 pkt->tso_segsz = len / cqe->lro_num_seg;
1344 DATA_LEN(rep) = DATA_LEN(seg);
1345 PKT_LEN(rep) = PKT_LEN(seg);
1346 SET_DATA_OFF(rep, DATA_OFF(seg));
1347 PORT(rep) = PORT(seg);
1348 (*rxq->elts)[idx] = rep;
1350 * Fill NIC descriptor with the new buffer. The lkey and size
1351 * of the buffers are already known, only the buffer address
1354 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1355 /* If there's only one MR, no need to replace LKey in WQE. */
1356 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1357 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1358 if (len > DATA_LEN(seg)) {
1359 len -= DATA_LEN(seg);
1364 DATA_LEN(seg) = len;
1365 #ifdef MLX5_PMD_SOFT_COUNTERS
1366 /* Increment bytes counter. */
1367 rxq->stats.ibytes += PKT_LEN(pkt);
1369 /* Return packet. */
1374 /* Align consumer index to the next stride. */
1379 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1381 /* Update the consumer index. */
1382 rxq->rq_ci = rq_ci >> sges_n;
1384 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1386 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1387 #ifdef MLX5_PMD_SOFT_COUNTERS
1388 /* Increment packets counter. */
1389 rxq->stats.ipackets += i;
1395 * Update LRO packet TCP header.
1396 * The HW LRO feature doesn't update the TCP header after coalescing the
1397 * TCP segments but supplies information in CQE to fill it by SW.
1400 * Pointer to the TCP header.
1402 * Pointer to the completion entry..
1404 * The L3 pseudo-header checksum.
1407 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1408 volatile struct mlx5_cqe *restrict cqe,
1411 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1412 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1414 * The HW calculates only the TCP payload checksum, need to complete
1415 * the TCP header checksum and the L3 pseudo-header checksum.
1417 uint32_t csum = phcsum + cqe->csum;
1419 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1420 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1421 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1422 tcp->recv_ack = cqe->lro_ack_seq_num;
1423 tcp->rx_win = cqe->lro_tcp_win;
1425 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1426 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1428 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1429 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1430 csum = (~csum) & 0xffff;
1437 * Update LRO packet headers.
1438 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1439 * TCP segments but supply information in CQE to fill it by SW.
1442 * The packet address.
1444 * Pointer to the completion entry..
1446 * The packet length.
1449 mlx5_lro_update_hdr(uint8_t *restrict padd,
1450 volatile struct mlx5_cqe *restrict cqe,
1454 struct rte_ether_hdr *eth;
1455 struct rte_vlan_hdr *vlan;
1456 struct rte_ipv4_hdr *ipv4;
1457 struct rte_ipv6_hdr *ipv6;
1458 struct rte_tcp_hdr *tcp;
1463 uint16_t proto = h.eth->ether_type;
1467 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1468 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1469 proto = h.vlan->eth_proto;
1472 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1473 h.ipv4->time_to_live = cqe->lro_min_ttl;
1474 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1475 h.ipv4->hdr_checksum = 0;
1476 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1477 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1480 h.ipv6->hop_limits = cqe->lro_min_ttl;
1481 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1483 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1486 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1490 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1492 struct mlx5_mprq_buf *buf = opaque;
1494 if (rte_atomic16_read(&buf->refcnt) == 1) {
1495 rte_mempool_put(buf->mp, buf);
1496 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1497 rte_atomic16_set(&buf->refcnt, 1);
1498 rte_mempool_put(buf->mp, buf);
1503 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1505 mlx5_mprq_buf_free_cb(NULL, buf);
1509 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1510 const unsigned int strd_n)
1512 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1513 volatile struct mlx5_wqe_data_seg *wqe =
1514 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1517 assert(rep != NULL);
1518 /* Replace MPRQ buf. */
1519 (*rxq->mprq_bufs)[rq_idx] = rep;
1521 addr = mlx5_mprq_buf_addr(rep, strd_n);
1522 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1523 /* If there's only one MR, no need to replace LKey in WQE. */
1524 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1525 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1526 /* Stash a mbuf for next replacement. */
1527 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1528 rxq->mprq_repl = rep;
1530 rxq->mprq_repl = NULL;
1534 * DPDK callback for RX with Multi-Packet RQ support.
1537 * Generic pointer to RX queue structure.
1539 * Array to store received packets.
1541 * Maximum number of packets in array.
1544 * Number of packets successfully received (<= pkts_n).
1547 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1549 struct mlx5_rxq_data *rxq = dpdk_rxq;
1550 const unsigned int strd_n = 1 << rxq->strd_num_n;
1551 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1552 const unsigned int strd_shift =
1553 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1554 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1555 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1556 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1558 uint32_t rq_ci = rxq->rq_ci;
1559 uint16_t consumed_strd = rxq->consumed_strd;
1560 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1561 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1563 while (i < pkts_n) {
1564 struct rte_mbuf *pkt;
1572 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1573 uint32_t rss_hash_res = 0;
1574 uint8_t lro_num_seg;
1576 if (consumed_strd == strd_n) {
1577 /* Replace WQE only if the buffer is still in use. */
1578 if (rte_atomic16_read(&buf->refcnt) > 1) {
1579 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1580 /* Release the old buffer. */
1581 mlx5_mprq_buf_free(buf);
1582 } else if (unlikely(rxq->mprq_repl == NULL)) {
1583 struct mlx5_mprq_buf *rep;
1586 * Currently, the MPRQ mempool is out of buffer
1587 * and doing memcpy regardless of the size of Rx
1588 * packet. Retry allocation to get back to
1591 if (!rte_mempool_get(rxq->mprq_mp,
1593 rxq->mprq_repl = rep;
1595 /* Advance to the next WQE. */
1598 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1600 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1601 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1605 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1606 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1608 consumed_strd += strd_cnt;
1609 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1612 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1613 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1615 /* mini-CQE for MPRQ doesn't have hash result. */
1616 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1618 assert(strd_idx < strd_n);
1619 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1620 lro_num_seg = cqe->lro_num_seg;
1622 * Currently configured to receive a packet per a stride. But if
1623 * MTU is adjusted through kernel interface, device could
1624 * consume multiple strides without raising an error. In this
1625 * case, the packet should be dropped because it is bigger than
1626 * the max_rx_pkt_len.
1628 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1629 ++rxq->stats.idropped;
1632 pkt = rte_pktmbuf_alloc(rxq->mp);
1633 if (unlikely(pkt == NULL)) {
1634 ++rxq->stats.rx_nombuf;
1637 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1638 assert((int)len >= (rxq->crc_present << 2));
1639 if (rxq->crc_present)
1640 len -= RTE_ETHER_CRC_LEN;
1641 offset = strd_idx * strd_sz + strd_shift;
1642 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1644 * Memcpy packets to the target mbuf if:
1645 * - The size of packet is smaller than mprq_max_memcpy_len.
1646 * - Out of buffer in the Mempool for Multi-Packet RQ.
1648 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1650 * When memcpy'ing packet due to out-of-buffer, the
1651 * packet must be smaller than the target mbuf.
1653 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1654 rte_pktmbuf_free_seg(pkt);
1655 ++rxq->stats.idropped;
1658 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1659 DATA_LEN(pkt) = len;
1661 rte_iova_t buf_iova;
1662 struct rte_mbuf_ext_shared_info *shinfo;
1663 uint16_t buf_len = strd_cnt * strd_sz;
1666 /* Increment the refcnt of the whole chunk. */
1667 rte_atomic16_add_return(&buf->refcnt, 1);
1668 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1670 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1672 * MLX5 device doesn't use iova but it is necessary in a
1673 * case where the Rx packet is transmitted via a
1676 buf_iova = rte_mempool_virt2iova(buf) +
1677 RTE_PTR_DIFF(buf_addr, buf);
1678 shinfo = &buf->shinfos[strd_idx];
1679 rte_mbuf_ext_refcnt_set(shinfo, 1);
1681 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1682 * attaching the stride to mbuf and more offload flags
1683 * will be added below by calling rxq_cq_to_mbuf().
1684 * Other fields will be overwritten.
1686 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1688 /* Set mbuf head-room. */
1689 pkt->data_off = headroom_sz;
1690 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1692 * Prevent potential overflow due to MTU change through
1695 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1696 rte_pktmbuf_free_seg(pkt);
1697 ++rxq->stats.idropped;
1700 DATA_LEN(pkt) = len;
1702 * LRO packet may consume all the stride memory, in this
1703 * case packet head-room space is not guaranteed so must
1704 * to add an empty mbuf for the head-room.
1706 if (!rxq->strd_headroom_en) {
1707 struct rte_mbuf *headroom_mbuf =
1708 rte_pktmbuf_alloc(rxq->mp);
1710 if (unlikely(headroom_mbuf == NULL)) {
1711 rte_pktmbuf_free_seg(pkt);
1712 ++rxq->stats.rx_nombuf;
1715 PORT(pkt) = rxq->port_id;
1716 NEXT(headroom_mbuf) = pkt;
1717 pkt = headroom_mbuf;
1721 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1722 if (lro_num_seg > 1) {
1723 mlx5_lro_update_hdr(addr, cqe, len);
1724 pkt->ol_flags |= PKT_RX_LRO;
1725 pkt->tso_segsz = strd_sz;
1728 PORT(pkt) = rxq->port_id;
1729 #ifdef MLX5_PMD_SOFT_COUNTERS
1730 /* Increment bytes counter. */
1731 rxq->stats.ibytes += PKT_LEN(pkt);
1733 /* Return packet. */
1737 /* Update the consumer indexes. */
1738 rxq->consumed_strd = consumed_strd;
1740 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1741 if (rq_ci != rxq->rq_ci) {
1744 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1746 #ifdef MLX5_PMD_SOFT_COUNTERS
1747 /* Increment packets counter. */
1748 rxq->stats.ipackets += i;
1754 * Dummy DPDK callback for TX.
1756 * This function is used to temporarily replace the real callback during
1757 * unsafe control operations on the queue, or in case of error.
1760 * Generic pointer to TX queue structure.
1762 * Packets to transmit.
1764 * Number of packets in array.
1767 * Number of packets successfully transmitted (<= pkts_n).
1770 removed_tx_burst(void *dpdk_txq __rte_unused,
1771 struct rte_mbuf **pkts __rte_unused,
1772 uint16_t pkts_n __rte_unused)
1779 * Dummy DPDK callback for RX.
1781 * This function is used to temporarily replace the real callback during
1782 * unsafe control operations on the queue, or in case of error.
1785 * Generic pointer to RX queue structure.
1787 * Array to store received packets.
1789 * Maximum number of packets in array.
1792 * Number of packets successfully received (<= pkts_n).
1795 removed_rx_burst(void *dpdk_txq __rte_unused,
1796 struct rte_mbuf **pkts __rte_unused,
1797 uint16_t pkts_n __rte_unused)
1804 * Vectorized Rx/Tx routines are not compiled in when required vector
1805 * instructions are not supported on a target architecture. The following null
1806 * stubs are needed for linkage when those are not included outside of this file
1807 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1811 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1812 struct rte_mbuf **pkts __rte_unused,
1813 uint16_t pkts_n __rte_unused)
1819 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1825 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1831 * Free the mbufs from the linear array of pointers.
1834 * Pointer to array of packets to be free.
1836 * Number of packets to be freed.
1838 * Configured Tx offloads mask. It is fully defined at
1839 * compile time and may be used for optimization.
1841 static __rte_always_inline void
1842 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1843 unsigned int pkts_n,
1844 unsigned int olx __rte_unused)
1846 struct rte_mempool *pool = NULL;
1847 struct rte_mbuf **p_free = NULL;
1848 struct rte_mbuf *mbuf;
1849 unsigned int n_free = 0;
1852 * The implemented algorithm eliminates
1853 * copying pointers to temporary array
1854 * for rte_mempool_put_bulk() calls.
1861 * Decrement mbuf reference counter, detach
1862 * indirect and external buffers if needed.
1864 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1865 if (likely(mbuf != NULL)) {
1866 assert(mbuf == *pkts);
1867 if (likely(n_free != 0)) {
1868 if (unlikely(pool != mbuf->pool))
1869 /* From different pool. */
1872 /* Start new scan array. */
1879 if (unlikely(pkts_n == 0)) {
1885 * This happens if mbuf is still referenced.
1886 * We can't put it back to the pool, skip.
1890 if (unlikely(n_free != 0))
1891 /* There is some array to free.*/
1893 if (unlikely(pkts_n == 0))
1894 /* Last mbuf, nothing to free. */
1900 * This loop is implemented to avoid multiple
1901 * inlining of rte_mempool_put_bulk().
1907 * Free the array of pre-freed mbufs
1908 * belonging to the same memory pool.
1910 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1911 if (unlikely(mbuf != NULL)) {
1912 /* There is the request to start new scan. */
1917 if (likely(pkts_n != 0))
1920 * This is the last mbuf to be freed.
1921 * Do one more loop iteration to complete.
1922 * This is rare case of the last unique mbuf.
1927 if (likely(pkts_n == 0))
1936 * Free the mbuf from the elts ring buffer till new tail.
1939 * Pointer to Tx queue structure.
1941 * Index in elts to free up to, becomes new elts tail.
1943 * Configured Tx offloads mask. It is fully defined at
1944 * compile time and may be used for optimization.
1946 static __rte_always_inline void
1947 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1949 unsigned int olx __rte_unused)
1951 uint16_t n_elts = tail - txq->elts_tail;
1954 assert(n_elts <= txq->elts_s);
1956 * Implement a loop to support ring buffer wraparound
1957 * with single inlining of mlx5_tx_free_mbuf().
1962 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1963 part = RTE_MIN(part, n_elts);
1965 assert(part <= txq->elts_s);
1966 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1968 txq->elts_tail += part;
1974 * Store the mbuf being sent into elts ring buffer.
1975 * On Tx completion these mbufs will be freed.
1978 * Pointer to Tx queue structure.
1980 * Pointer to array of packets to be stored.
1982 * Number of packets to be stored.
1984 * Configured Tx offloads mask. It is fully defined at
1985 * compile time and may be used for optimization.
1987 static __rte_always_inline void
1988 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
1989 struct rte_mbuf **restrict pkts,
1990 unsigned int pkts_n,
1991 unsigned int olx __rte_unused)
1994 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
1998 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2000 assert(part <= txq->elts_s);
2001 /* This code is a good candidate for vectorizing with SIMD. */
2002 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2004 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2005 txq->elts_head += pkts_n;
2006 if (unlikely(part < pkts_n))
2007 /* The copy is wrapping around the elts array. */
2008 rte_memcpy((void *)elts, (void *)(pkts + part),
2009 (pkts_n - part) * sizeof(struct rte_mbuf *));
2013 * Manage TX completions. This routine checks the CQ for
2014 * arrived CQEs, deduces the last accomplished WQE in SQ,
2015 * updates SQ producing index and frees all completed mbufs.
2018 * Pointer to TX queue structure.
2020 * Configured Tx offloads mask. It is fully defined at
2021 * compile time and may be used for optimization.
2023 * NOTE: not inlined intentionally, it makes tx_burst
2024 * routine smaller, simple and faster - from experiments.
2027 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2028 unsigned int olx __rte_unused)
2030 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2031 bool update = false;
2032 uint16_t tail = txq->elts_tail;
2036 volatile struct mlx5_cqe *cqe;
2038 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2039 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2040 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2041 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2042 /* No new CQEs in completion queue. */
2043 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2046 /* Some error occurred, try to restart. */
2048 tail = mlx5_tx_error_cqe_handle
2049 (txq, (volatile struct mlx5_err_cqe *)cqe);
2050 if (likely(tail != txq->elts_tail)) {
2051 mlx5_tx_free_elts(txq, tail, olx);
2052 assert(tail == txq->elts_tail);
2054 /* Allow flushing all CQEs from the queue. */
2057 volatile struct mlx5_wqe_cseg *cseg;
2059 /* Normal transmit completion. */
2062 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
2063 cseg = (volatile struct mlx5_wqe_cseg *)
2064 (txq->wqes + (txq->wqe_pi & txq->wqe_m));
2073 * We have to restrict the amount of processed CQEs
2074 * in one tx_burst routine call. The CQ may be large
2075 * and many CQEs may be updated by the NIC in one
2076 * transaction. Buffers freeing is time consuming,
2077 * multiple iterations may introduce significant
2081 if (likely(tail != txq->elts_tail)) {
2082 /* Free data buffers from elts. */
2083 mlx5_tx_free_elts(txq, tail, olx);
2084 assert(tail == txq->elts_tail);
2086 if (likely(update)) {
2087 /* Update the consumer index. */
2088 rte_compiler_barrier();
2090 rte_cpu_to_be_32(txq->cq_ci);
2095 * Check if the completion request flag should be set in the last WQE.
2096 * Both pushed mbufs and WQEs are monitored and the completion request
2097 * flag is set if any of thresholds is reached.
2100 * Pointer to TX queue structure.
2102 * Pointer to burst routine local context.
2104 * Configured Tx offloads mask. It is fully defined at
2105 * compile time and may be used for optimization.
2107 static __rte_always_inline void
2108 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2109 struct mlx5_txq_local *restrict loc,
2112 uint16_t head = txq->elts_head;
2115 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc->pkts_sent -
2116 (MLX5_TXOFF_CONFIG(MULTI) ? loc->pkts_copy : 0);
2118 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2119 (MLX5_TXOFF_CONFIG(INLINE) &&
2120 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2121 volatile struct mlx5_wqe *last = loc->wqe_last;
2123 txq->elts_comp = head;
2124 if (MLX5_TXOFF_CONFIG(INLINE))
2125 txq->wqe_comp = txq->wqe_ci;
2126 /* Request unconditional completion on last WQE. */
2127 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2128 MLX5_COMP_MODE_OFFSET);
2129 /* Save elts_head in unused "immediate" field of WQE. */
2130 last->cseg.misc = head;
2132 * A CQE slot must always be available. Count the
2133 * issued CEQ "always" request instead of production
2134 * index due to here can be CQE with errors and
2135 * difference with ci may become inconsistent.
2137 assert(txq->cqe_s > ++txq->cq_pi);
2142 * DPDK callback to check the status of a tx descriptor.
2147 * The index of the descriptor in the ring.
2150 * The status of the tx descriptor.
2153 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2155 struct mlx5_txq_data *restrict txq = tx_queue;
2158 mlx5_tx_handle_completion(txq, 0);
2159 used = txq->elts_head - txq->elts_tail;
2161 return RTE_ETH_TX_DESC_FULL;
2162 return RTE_ETH_TX_DESC_DONE;
2166 * Build the Control Segment with specified opcode:
2167 * - MLX5_OPCODE_SEND
2168 * - MLX5_OPCODE_ENHANCED_MPSW
2172 * Pointer to TX queue structure.
2174 * Pointer to burst routine local context.
2176 * Pointer to WQE to fill with built Control Segment.
2178 * Supposed length of WQE in segments.
2180 * SQ WQE opcode to put into Control Segment.
2182 * Configured Tx offloads mask. It is fully defined at
2183 * compile time and may be used for optimization.
2185 static __rte_always_inline void
2186 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2187 struct mlx5_txq_local *restrict loc __rte_unused,
2188 struct mlx5_wqe *restrict wqe,
2190 unsigned int opcode,
2191 unsigned int olx __rte_unused)
2193 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2195 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2196 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2197 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2198 MLX5_COMP_MODE_OFFSET);
2199 cs->misc = RTE_BE32(0);
2203 * Build the Ethernet Segment without inlined data.
2204 * Supports Software Parser, Checksums and VLAN
2205 * insertion Tx offload features.
2208 * Pointer to TX queue structure.
2210 * Pointer to burst routine local context.
2212 * Pointer to WQE to fill with built Ethernet Segment.
2214 * Configured Tx offloads mask. It is fully defined at
2215 * compile time and may be used for optimization.
2217 static __rte_always_inline void
2218 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2219 struct mlx5_txq_local *restrict loc,
2220 struct mlx5_wqe *restrict wqe,
2223 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2227 * Calculate and set check sum flags first, dword field
2228 * in segment may be shared with Software Parser flags.
2230 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2231 es->flags = rte_cpu_to_le_32(csum);
2233 * Calculate and set Software Parser offsets and flags.
2234 * These flags a set for custom UDP and IP tunnel packets.
2236 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2237 /* Fill metadata field if needed. */
2238 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2239 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2240 loc->mbuf->tx_metadata : 0 : 0;
2241 /* Engage VLAN tag insertion feature if requested. */
2242 if (MLX5_TXOFF_CONFIG(VLAN) &&
2243 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2245 * We should get here only if device support
2246 * this feature correctly.
2248 assert(txq->vlan_en);
2249 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2250 loc->mbuf->vlan_tci);
2252 es->inline_hdr = RTE_BE32(0);
2257 * Build the Ethernet Segment with minimal inlined data
2258 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2259 * used to fill the gap in single WQEBB WQEs.
2260 * Supports Software Parser, Checksums and VLAN
2261 * insertion Tx offload features.
2264 * Pointer to TX queue structure.
2266 * Pointer to burst routine local context.
2268 * Pointer to WQE to fill with built Ethernet Segment.
2270 * Length of VLAN tag insertion if any.
2272 * Configured Tx offloads mask. It is fully defined at
2273 * compile time and may be used for optimization.
2275 static __rte_always_inline void
2276 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2277 struct mlx5_txq_local *restrict loc,
2278 struct mlx5_wqe *restrict wqe,
2282 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2284 uint8_t *psrc, *pdst;
2287 * Calculate and set check sum flags first, dword field
2288 * in segment may be shared with Software Parser flags.
2290 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2291 es->flags = rte_cpu_to_le_32(csum);
2293 * Calculate and set Software Parser offsets and flags.
2294 * These flags a set for custom UDP and IP tunnel packets.
2296 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2297 /* Fill metadata field if needed. */
2298 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2299 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2300 loc->mbuf->tx_metadata : 0 : 0;
2301 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2303 sizeof(rte_v128u32_t)),
2304 "invalid Ethernet Segment data size");
2305 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2307 sizeof(struct rte_vlan_hdr) +
2308 2 * RTE_ETHER_ADDR_LEN),
2309 "invalid Ethernet Segment data size");
2310 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2311 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2312 es->inline_data = *(unaligned_uint16_t *)psrc;
2313 psrc += sizeof(uint16_t);
2314 pdst = (uint8_t *)(es + 1);
2315 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2316 /* Implement VLAN tag insertion as part inline data. */
2317 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2318 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2319 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2320 /* Insert VLAN ethertype + VLAN tag. */
2321 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2322 ((RTE_ETHER_TYPE_VLAN << 16) |
2323 loc->mbuf->vlan_tci);
2324 pdst += sizeof(struct rte_vlan_hdr);
2325 /* Copy the rest two bytes from packet data. */
2326 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2327 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2329 /* Fill the gap in the title WQEBB with inline data. */
2330 rte_mov16(pdst, psrc);
2335 * Build the Ethernet Segment with entire packet
2336 * data inlining. Checks the boundary of WQEBB and
2337 * ring buffer wrapping, supports Software Parser,
2338 * Checksums and VLAN insertion Tx offload features.
2341 * Pointer to TX queue structure.
2343 * Pointer to burst routine local context.
2345 * Pointer to WQE to fill with built Ethernet Segment.
2347 * Length of VLAN tag insertion if any.
2349 * Length of data to inline (VLAN included, if any).
2351 * TSO flag, set mss field from the packet.
2353 * Configured Tx offloads mask. It is fully defined at
2354 * compile time and may be used for optimization.
2357 * Pointer to the next Data Segment (aligned and wrapped around).
2359 static __rte_always_inline struct mlx5_wqe_dseg *
2360 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2361 struct mlx5_txq_local *restrict loc,
2362 struct mlx5_wqe *restrict wqe,
2368 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2370 uint8_t *psrc, *pdst;
2374 * Calculate and set check sum flags first, dword field
2375 * in segment may be shared with Software Parser flags.
2377 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2380 csum |= loc->mbuf->tso_segsz;
2381 es->flags = rte_cpu_to_be_32(csum);
2383 es->flags = rte_cpu_to_le_32(csum);
2386 * Calculate and set Software Parser offsets and flags.
2387 * These flags a set for custom UDP and IP tunnel packets.
2389 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2390 /* Fill metadata field if needed. */
2391 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2392 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2393 loc->mbuf->tx_metadata : 0 : 0;
2394 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2396 sizeof(rte_v128u32_t)),
2397 "invalid Ethernet Segment data size");
2398 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2400 sizeof(struct rte_vlan_hdr) +
2401 2 * RTE_ETHER_ADDR_LEN),
2402 "invalid Ethernet Segment data size");
2403 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2404 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2405 es->inline_data = *(unaligned_uint16_t *)psrc;
2406 psrc += sizeof(uint16_t);
2407 pdst = (uint8_t *)(es + 1);
2408 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2409 /* Implement VLAN tag insertion as part inline data. */
2410 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2411 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2412 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2413 /* Insert VLAN ethertype + VLAN tag. */
2414 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2415 ((RTE_ETHER_TYPE_VLAN << 16) |
2416 loc->mbuf->vlan_tci);
2417 pdst += sizeof(struct rte_vlan_hdr);
2418 /* Copy the rest two bytes from packet data. */
2419 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2420 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2421 psrc += sizeof(uint16_t);
2423 /* Fill the gap in the title WQEBB with inline data. */
2424 rte_mov16(pdst, psrc);
2425 psrc += sizeof(rte_v128u32_t);
2427 pdst = (uint8_t *)(es + 2);
2428 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2429 assert(pdst < (uint8_t *)txq->wqes_end);
2430 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2432 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2433 return (struct mlx5_wqe_dseg *)pdst;
2436 * The WQEBB space availability is checked by caller.
2437 * Here we should be aware of WQE ring buffer wraparound only.
2439 part = (uint8_t *)txq->wqes_end - pdst;
2440 part = RTE_MIN(part, inlen);
2442 rte_memcpy(pdst, psrc, part);
2444 if (likely(!inlen)) {
2446 * If return value is not used by the caller
2447 * the code below will be optimized out.
2450 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2451 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2452 pdst = (uint8_t *)txq->wqes;
2453 return (struct mlx5_wqe_dseg *)pdst;
2455 pdst = (uint8_t *)txq->wqes;
2462 * Copy data from chain of mbuf to the specified linear buffer.
2463 * Checksums and VLAN insertion Tx offload features. If data
2464 * from some mbuf copied completely this mbuf is freed. Local
2465 * structure is used to keep the byte stream state.
2468 * Pointer to the destination linear buffer.
2470 * Pointer to burst routine local context.
2472 * Length of data to be copied.
2474 * Configured Tx offloads mask. It is fully defined at
2475 * compile time and may be used for optimization.
2477 static __rte_always_inline void
2478 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2479 struct mlx5_txq_local *restrict loc,
2481 unsigned int olx __rte_unused)
2483 struct rte_mbuf *mbuf;
2484 unsigned int part, dlen;
2489 /* Allow zero length packets, must check first. */
2490 dlen = rte_pktmbuf_data_len(loc->mbuf);
2491 if (dlen <= loc->mbuf_off) {
2492 /* Exhausted packet, just free. */
2494 loc->mbuf = mbuf->next;
2495 rte_pktmbuf_free_seg(mbuf);
2497 assert(loc->mbuf_nseg > 1);
2502 dlen -= loc->mbuf_off;
2503 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2505 part = RTE_MIN(len, dlen);
2506 rte_memcpy(pdst, psrc, part);
2507 loc->mbuf_off += part;
2510 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2512 /* Exhausted packet, just free. */
2514 loc->mbuf = mbuf->next;
2515 rte_pktmbuf_free_seg(mbuf);
2517 assert(loc->mbuf_nseg >= 1);
2527 * Build the Ethernet Segment with inlined data from
2528 * multi-segment packet. Checks the boundary of WQEBB
2529 * and ring buffer wrapping, supports Software Parser,
2530 * Checksums and VLAN insertion Tx offload features.
2533 * Pointer to TX queue structure.
2535 * Pointer to burst routine local context.
2537 * Pointer to WQE to fill with built Ethernet Segment.
2539 * Length of VLAN tag insertion if any.
2541 * Length of data to inline (VLAN included, if any).
2543 * TSO flag, set mss field from the packet.
2545 * Configured Tx offloads mask. It is fully defined at
2546 * compile time and may be used for optimization.
2549 * Pointer to the next Data Segment (aligned and
2550 * possible NOT wrapped around - caller should do
2551 * wrapping check on its own).
2553 static __rte_always_inline struct mlx5_wqe_dseg *
2554 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2555 struct mlx5_txq_local *restrict loc,
2556 struct mlx5_wqe *restrict wqe,
2562 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2568 * Calculate and set check sum flags first, uint32_t field
2569 * in segment may be shared with Software Parser flags.
2571 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2574 csum |= loc->mbuf->tso_segsz;
2575 es->flags = rte_cpu_to_be_32(csum);
2577 es->flags = rte_cpu_to_le_32(csum);
2580 * Calculate and set Software Parser offsets and flags.
2581 * These flags a set for custom UDP and IP tunnel packets.
2583 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2584 /* Fill metadata field if needed. */
2585 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2586 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2587 loc->mbuf->tx_metadata : 0 : 0;
2588 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2590 sizeof(rte_v128u32_t)),
2591 "invalid Ethernet Segment data size");
2592 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2594 sizeof(struct rte_vlan_hdr) +
2595 2 * RTE_ETHER_ADDR_LEN),
2596 "invalid Ethernet Segment data size");
2597 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2598 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2599 pdst = (uint8_t *)&es->inline_data;
2600 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2601 /* Implement VLAN tag insertion as part inline data. */
2602 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2603 pdst += 2 * RTE_ETHER_ADDR_LEN;
2604 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2605 ((RTE_ETHER_TYPE_VLAN << 16) |
2606 loc->mbuf->vlan_tci);
2607 pdst += sizeof(struct rte_vlan_hdr);
2608 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2610 assert(pdst < (uint8_t *)txq->wqes_end);
2612 * The WQEBB space availability is checked by caller.
2613 * Here we should be aware of WQE ring buffer wraparound only.
2615 part = (uint8_t *)txq->wqes_end - pdst;
2616 part = RTE_MIN(part, inlen);
2619 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2621 if (likely(!inlen)) {
2623 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2624 return (struct mlx5_wqe_dseg *)pdst;
2626 pdst = (uint8_t *)txq->wqes;
2632 * Build the Data Segment of pointer type.
2635 * Pointer to TX queue structure.
2637 * Pointer to burst routine local context.
2639 * Pointer to WQE to fill with built Data Segment.
2641 * Data buffer to point.
2643 * Data buffer length.
2645 * Configured Tx offloads mask. It is fully defined at
2646 * compile time and may be used for optimization.
2648 static __rte_always_inline void
2649 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2650 struct mlx5_txq_local *restrict loc,
2651 struct mlx5_wqe_dseg *restrict dseg,
2654 unsigned int olx __rte_unused)
2658 dseg->bcount = rte_cpu_to_be_32(len);
2659 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2660 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2664 * Build the Data Segment of pointer type or inline
2665 * if data length is less than buffer in minimal
2666 * Data Segment size.
2669 * Pointer to TX queue structure.
2671 * Pointer to burst routine local context.
2673 * Pointer to WQE to fill with built Data Segment.
2675 * Data buffer to point.
2677 * Data buffer length.
2679 * Configured Tx offloads mask. It is fully defined at
2680 * compile time and may be used for optimization.
2682 static __rte_always_inline void
2683 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2684 struct mlx5_txq_local *restrict loc,
2685 struct mlx5_wqe_dseg *restrict dseg,
2688 unsigned int olx __rte_unused)
2694 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2695 dseg->bcount = rte_cpu_to_be_32(len);
2696 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2697 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2701 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2702 /* Unrolled implementation of generic rte_memcpy. */
2703 dst = (uintptr_t)&dseg->inline_data[0];
2704 src = (uintptr_t)buf;
2705 #ifdef RTE_ARCH_STRICT_ALIGN
2706 memcpy(dst, src, len);
2709 *(uint64_t *)dst = *(uint64_t *)src;
2710 dst += sizeof(uint64_t);
2711 src += sizeof(uint64_t);
2714 *(uint32_t *)dst = *(uint32_t *)src;
2715 dst += sizeof(uint32_t);
2716 src += sizeof(uint32_t);
2719 *(uint16_t *)dst = *(uint16_t *)src;
2720 dst += sizeof(uint16_t);
2721 src += sizeof(uint16_t);
2724 *(uint8_t *)dst = *(uint8_t *)src;
2729 * Build the Data Segment of inlined data from single
2730 * segment packet, no VLAN insertion.
2733 * Pointer to TX queue structure.
2735 * Pointer to burst routine local context.
2737 * Pointer to WQE to fill with built Data Segment.
2739 * Data buffer to point.
2741 * Data buffer length.
2743 * Configured Tx offloads mask. It is fully defined at
2744 * compile time and may be used for optimization.
2747 * Pointer to the next Data Segment after inlined data.
2748 * Ring buffer wraparound check is needed. We do not
2749 * do it here because it may not be needed for the
2750 * last packet in the eMPW session.
2752 static __rte_always_inline struct mlx5_wqe_dseg *
2753 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2754 struct mlx5_txq_local *restrict loc __rte_unused,
2755 struct mlx5_wqe_dseg *restrict dseg,
2758 unsigned int olx __rte_unused)
2763 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2764 pdst = &dseg->inline_data[0];
2766 * The WQEBB space availability is checked by caller.
2767 * Here we should be aware of WQE ring buffer wraparound only.
2769 part = (uint8_t *)txq->wqes_end - pdst;
2770 part = RTE_MIN(part, len);
2772 rte_memcpy(pdst, buf, part);
2776 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2777 /* Note: no final wraparound check here. */
2778 return (struct mlx5_wqe_dseg *)pdst;
2780 pdst = (uint8_t *)txq->wqes;
2787 * Build the Data Segment of inlined data from single
2788 * segment packet with VLAN insertion.
2791 * Pointer to TX queue structure.
2793 * Pointer to burst routine local context.
2795 * Pointer to the dseg fill with built Data Segment.
2797 * Data buffer to point.
2799 * Data buffer length.
2801 * Configured Tx offloads mask. It is fully defined at
2802 * compile time and may be used for optimization.
2805 * Pointer to the next Data Segment after inlined data.
2806 * Ring buffer wraparound check is needed.
2808 static __rte_always_inline struct mlx5_wqe_dseg *
2809 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2810 struct mlx5_txq_local *restrict loc __rte_unused,
2811 struct mlx5_wqe_dseg *restrict dseg,
2814 unsigned int olx __rte_unused)
2820 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2821 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2822 (2 * RTE_ETHER_ADDR_LEN),
2823 "invalid Data Segment data size");
2824 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2825 MLX5_ETH_WQE_DATA_INLINE);
2826 pdst = &dseg->inline_data[0];
2827 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2828 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2829 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2830 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2831 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2832 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2833 loc->mbuf->vlan_tci);
2834 pdst += sizeof(struct rte_vlan_hdr);
2835 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2836 pdst = (uint8_t *)txq->wqes;
2838 * The WQEBB space availability is checked by caller.
2839 * Here we should be aware of WQE ring buffer wraparound only.
2841 part = (uint8_t *)txq->wqes_end - pdst;
2842 part = RTE_MIN(part, len);
2844 rte_memcpy(pdst, buf, part);
2848 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2849 /* Note: no final wraparound check here. */
2850 return (struct mlx5_wqe_dseg *)pdst;
2852 pdst = (uint8_t *)txq->wqes;
2859 * Build the Ethernet Segment with optionally inlined data with
2860 * VLAN insertion and following Data Segments (if any) from
2861 * multi-segment packet. Used by ordinary send and TSO.
2864 * Pointer to TX queue structure.
2866 * Pointer to burst routine local context.
2868 * Pointer to WQE to fill with built Ethernet/Data Segments.
2870 * Length of VLAN header to insert, 0 means no VLAN insertion.
2872 * Data length to inline. For TSO this parameter specifies
2873 * exact value, for ordinary send routine can be aligned by
2874 * caller to provide better WQE space saving and data buffer
2875 * start address alignment. This length includes VLAN header
2878 * Zero means ordinary send, inlined data can be extended,
2879 * otherwise this is TSO, inlined data length is fixed.
2881 * Configured Tx offloads mask. It is fully defined at
2882 * compile time and may be used for optimization.
2885 * Actual size of built WQE in segments.
2887 static __rte_always_inline unsigned int
2888 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2889 struct mlx5_txq_local *restrict loc,
2890 struct mlx5_wqe *restrict wqe,
2894 unsigned int olx __rte_unused)
2896 struct mlx5_wqe_dseg *restrict dseg;
2899 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2900 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2903 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2904 if (!loc->mbuf_nseg)
2907 * There are still some mbuf remaining, not inlined.
2908 * The first mbuf may be partially inlined and we
2909 * must process the possible non-zero data offset.
2911 if (loc->mbuf_off) {
2916 * Exhausted packets must be dropped before.
2917 * Non-zero offset means there are some data
2918 * remained in the packet.
2920 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2921 assert(rte_pktmbuf_data_len(loc->mbuf));
2922 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2924 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2926 * Build the pointer/minimal data Data Segment.
2927 * Do ring buffer wrapping check in advance.
2929 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2930 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2931 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2932 /* Store the mbuf to be freed on completion. */
2933 assert(loc->elts_free);
2934 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2937 if (--loc->mbuf_nseg == 0)
2939 loc->mbuf = loc->mbuf->next;
2943 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2944 struct rte_mbuf *mbuf;
2946 /* Zero length segment found, just skip. */
2948 loc->mbuf = loc->mbuf->next;
2949 rte_pktmbuf_free_seg(mbuf);
2950 if (--loc->mbuf_nseg == 0)
2953 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2954 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2957 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2958 rte_pktmbuf_data_len(loc->mbuf), olx);
2959 assert(loc->elts_free);
2960 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2963 if (--loc->mbuf_nseg == 0)
2965 loc->mbuf = loc->mbuf->next;
2970 /* Calculate actual segments used from the dseg pointer. */
2971 if ((uintptr_t)wqe < (uintptr_t)dseg)
2972 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
2974 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
2975 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
2980 * Tx one packet function for multi-segment TSO. Supports all
2981 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
2982 * sends one packet per WQE.
2984 * This routine is responsible for storing processed mbuf
2985 * into elts ring buffer and update elts_head.
2988 * Pointer to TX queue structure.
2990 * Pointer to burst routine local context.
2992 * Configured Tx offloads mask. It is fully defined at
2993 * compile time and may be used for optimization.
2996 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2997 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2998 * Local context variables partially updated.
3000 static __rte_always_inline enum mlx5_txcmp_code
3001 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3002 struct mlx5_txq_local *restrict loc,
3005 struct mlx5_wqe *restrict wqe;
3006 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3009 * Calculate data length to be inlined to estimate
3010 * the required space in WQE ring buffer.
3012 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3013 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3014 vlan = sizeof(struct rte_vlan_hdr);
3015 inlen = loc->mbuf->l2_len + vlan +
3016 loc->mbuf->l3_len + loc->mbuf->l4_len;
3017 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3018 return MLX5_TXCMP_CODE_ERROR;
3019 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3020 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3021 /* Packet must contain all TSO headers. */
3022 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3023 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3024 inlen > (dlen + vlan)))
3025 return MLX5_TXCMP_CODE_ERROR;
3026 assert(inlen >= txq->inlen_mode);
3028 * Check whether there are enough free WQEBBs:
3030 * - Ethernet Segment
3031 * - First Segment of inlined Ethernet data
3032 * - ... data continued ...
3033 * - Data Segments of pointer/min inline type
3035 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3036 MLX5_ESEG_MIN_INLINE_SIZE +
3038 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3039 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3040 return MLX5_TXCMP_CODE_EXIT;
3041 /* Check for maximal WQE size. */
3042 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3043 return MLX5_TXCMP_CODE_ERROR;
3044 #ifdef MLX5_PMD_SOFT_COUNTERS
3045 /* Update sent data bytes/packets counters. */
3046 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3047 loc->mbuf->tso_segsz;
3049 * One will be added for mbuf itself
3050 * at the end of the mlx5_tx_burst from
3051 * loc->pkts_sent field.
3054 txq->stats.opackets += ntcp;
3055 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3057 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3058 loc->wqe_last = wqe;
3059 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3060 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3061 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3062 txq->wqe_ci += (ds + 3) / 4;
3063 loc->wqe_free -= (ds + 3) / 4;
3064 /* Request CQE generation if limits are reached. */
3065 mlx5_tx_request_completion(txq, loc, olx);
3066 return MLX5_TXCMP_CODE_MULTI;
3070 * Tx one packet function for multi-segment SEND. Supports all
3071 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3072 * sends one packet per WQE, without any data inlining in
3075 * This routine is responsible for storing processed mbuf
3076 * into elts ring buffer and update elts_head.
3079 * Pointer to TX queue structure.
3081 * Pointer to burst routine local context.
3083 * Configured Tx offloads mask. It is fully defined at
3084 * compile time and may be used for optimization.
3087 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3088 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3089 * Local context variables partially updated.
3091 static __rte_always_inline enum mlx5_txcmp_code
3092 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3093 struct mlx5_txq_local *restrict loc,
3096 struct mlx5_wqe_dseg *restrict dseg;
3097 struct mlx5_wqe *restrict wqe;
3098 unsigned int ds, nseg;
3100 assert(NB_SEGS(loc->mbuf) > 1);
3102 * No inline at all, it means the CPU cycles saving
3103 * is prioritized at configuration, we should not
3104 * copy any packet data to WQE.
3106 nseg = NB_SEGS(loc->mbuf);
3108 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3109 return MLX5_TXCMP_CODE_EXIT;
3110 /* Check for maximal WQE size. */
3111 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3112 return MLX5_TXCMP_CODE_ERROR;
3114 * Some Tx offloads may cause an error if
3115 * packet is not long enough, check against
3116 * assumed minimal length.
3118 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3119 return MLX5_TXCMP_CODE_ERROR;
3120 #ifdef MLX5_PMD_SOFT_COUNTERS
3121 /* Update sent data bytes counter. */
3122 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3123 if (MLX5_TXOFF_CONFIG(VLAN) &&
3124 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3125 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3128 * SEND WQE, one WQEBB:
3129 * - Control Segment, SEND opcode
3130 * - Ethernet Segment, optional VLAN, no inline
3131 * - Data Segments, pointer only type
3133 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3134 loc->wqe_last = wqe;
3135 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3136 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3137 dseg = &wqe->dseg[0];
3139 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3140 struct rte_mbuf *mbuf;
3143 * Zero length segment found, have to
3144 * correct total size of WQE in segments.
3145 * It is supposed to be rare occasion, so
3146 * in normal case (no zero length segments)
3147 * we avoid extra writing to the Control
3151 wqe->cseg.sq_ds -= RTE_BE32(1);
3153 loc->mbuf = mbuf->next;
3154 rte_pktmbuf_free_seg(mbuf);
3160 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3161 rte_pktmbuf_data_len(loc->mbuf), olx);
3162 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3167 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3168 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3169 loc->mbuf = loc->mbuf->next;
3172 txq->wqe_ci += (ds + 3) / 4;
3173 loc->wqe_free -= (ds + 3) / 4;
3174 /* Request CQE generation if limits are reached. */
3175 mlx5_tx_request_completion(txq, loc, olx);
3176 return MLX5_TXCMP_CODE_MULTI;
3180 * Tx one packet function for multi-segment SEND. Supports all
3181 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3182 * sends one packet per WQE, with data inlining in
3183 * Ethernet Segment and minimal Data Segments.
3185 * This routine is responsible for storing processed mbuf
3186 * into elts ring buffer and update elts_head.
3189 * Pointer to TX queue structure.
3191 * Pointer to burst routine local context.
3193 * Configured Tx offloads mask. It is fully defined at
3194 * compile time and may be used for optimization.
3197 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3198 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3199 * Local context variables partially updated.
3201 static __rte_always_inline enum mlx5_txcmp_code
3202 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3203 struct mlx5_txq_local *restrict loc,
3206 struct mlx5_wqe *restrict wqe;
3207 unsigned int ds, inlen, dlen, vlan = 0;
3209 assert(MLX5_TXOFF_CONFIG(INLINE));
3210 assert(NB_SEGS(loc->mbuf) > 1);
3212 * First calculate data length to be inlined
3213 * to estimate the required space for WQE.
3215 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3216 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3217 vlan = sizeof(struct rte_vlan_hdr);
3218 inlen = dlen + vlan;
3219 /* Check against minimal length. */
3220 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3221 return MLX5_TXCMP_CODE_ERROR;
3222 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3223 if (inlen > txq->inlen_send) {
3224 struct rte_mbuf *mbuf;
3229 * Packet length exceeds the allowed inline
3230 * data length, check whether the minimal
3231 * inlining is required.
3233 if (txq->inlen_mode) {
3234 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3235 assert(txq->inlen_mode <= txq->inlen_send);
3236 inlen = txq->inlen_mode;
3238 if (!vlan || txq->vlan_en) {
3240 * VLAN insertion will be done inside by HW.
3241 * It is not utmost effective - VLAN flag is
3242 * checked twice, but we should proceed the
3243 * inlining length correctly and take into
3244 * account the VLAN header being inserted.
3246 return mlx5_tx_packet_multi_send
3249 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3252 * Now we know the minimal amount of data is requested
3253 * to inline. Check whether we should inline the buffers
3254 * from the chain beginning to eliminate some mbufs.
3257 nxlen = rte_pktmbuf_data_len(mbuf);
3258 if (unlikely(nxlen <= txq->inlen_send)) {
3259 /* We can inline first mbuf at least. */
3260 if (nxlen < inlen) {
3263 /* Scan mbufs till inlen filled. */
3268 nxlen = rte_pktmbuf_data_len(mbuf);
3270 } while (unlikely(nxlen < inlen));
3271 if (unlikely(nxlen > txq->inlen_send)) {
3272 /* We cannot inline entire mbuf. */
3273 smlen = inlen - smlen;
3274 start = rte_pktmbuf_mtod_offset
3275 (mbuf, uintptr_t, smlen);
3282 /* There should be not end of packet. */
3284 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3285 } while (unlikely(nxlen < txq->inlen_send));
3287 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3289 * Check whether we can do inline to align start
3290 * address of data buffer to cacheline.
3293 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3294 if (unlikely(start)) {
3296 if (start <= txq->inlen_send)
3301 * Check whether there are enough free WQEBBs:
3303 * - Ethernet Segment
3304 * - First Segment of inlined Ethernet data
3305 * - ... data continued ...
3306 * - Data Segments of pointer/min inline type
3308 * Estimate the number of Data Segments conservatively,
3309 * supposing no any mbufs is being freed during inlining.
3311 assert(inlen <= txq->inlen_send);
3312 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3313 MLX5_ESEG_MIN_INLINE_SIZE +
3315 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3316 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3317 return MLX5_TXCMP_CODE_EXIT;
3318 /* Check for maximal WQE size. */
3319 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3320 return MLX5_TXCMP_CODE_ERROR;
3321 #ifdef MLX5_PMD_SOFT_COUNTERS
3322 /* Update sent data bytes/packets counters. */
3323 txq->stats.obytes += dlen + vlan;
3325 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3326 loc->wqe_last = wqe;
3327 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3328 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3329 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3330 txq->wqe_ci += (ds + 3) / 4;
3331 loc->wqe_free -= (ds + 3) / 4;
3332 /* Request CQE generation if limits are reached. */
3333 mlx5_tx_request_completion(txq, loc, olx);
3334 return MLX5_TXCMP_CODE_MULTI;
3338 * Tx burst function for multi-segment packets. Supports all
3339 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3340 * sends one packet per WQE. Function stops sending if it
3341 * encounters the single-segment packet.
3343 * This routine is responsible for storing processed mbuf
3344 * into elts ring buffer and update elts_head.
3347 * Pointer to TX queue structure.
3349 * Packets to transmit.
3351 * Number of packets in array.
3353 * Pointer to burst routine local context.
3355 * Configured Tx offloads mask. It is fully defined at
3356 * compile time and may be used for optimization.
3359 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3360 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3361 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3362 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3363 * Local context variables updated.
3365 static __rte_always_inline enum mlx5_txcmp_code
3366 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3367 struct rte_mbuf **restrict pkts,
3368 unsigned int pkts_n,
3369 struct mlx5_txq_local *restrict loc,
3372 assert(loc->elts_free && loc->wqe_free);
3373 assert(pkts_n > loc->pkts_sent);
3374 pkts += loc->pkts_sent + 1;
3375 pkts_n -= loc->pkts_sent;
3377 enum mlx5_txcmp_code ret;
3379 assert(NB_SEGS(loc->mbuf) > 1);
3381 * Estimate the number of free elts quickly but
3382 * conservatively. Some segment may be fully inlined
3383 * and freed, ignore this here - precise estimation
3386 if (loc->elts_free < NB_SEGS(loc->mbuf))
3387 return MLX5_TXCMP_CODE_EXIT;
3388 if (MLX5_TXOFF_CONFIG(TSO) &&
3389 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3390 /* Proceed with multi-segment TSO. */
3391 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3392 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3393 /* Proceed with multi-segment SEND with inlining. */
3394 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3396 /* Proceed with multi-segment SEND w/o inlining. */
3397 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3399 if (ret == MLX5_TXCMP_CODE_EXIT)
3400 return MLX5_TXCMP_CODE_EXIT;
3401 if (ret == MLX5_TXCMP_CODE_ERROR)
3402 return MLX5_TXCMP_CODE_ERROR;
3403 /* WQE is built, go to the next packet. */
3406 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3407 return MLX5_TXCMP_CODE_EXIT;
3408 loc->mbuf = *pkts++;
3410 rte_prefetch0(*pkts);
3411 if (likely(NB_SEGS(loc->mbuf) > 1))
3413 /* Here ends the series of multi-segment packets. */
3414 if (MLX5_TXOFF_CONFIG(TSO) &&
3415 unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3416 return MLX5_TXCMP_CODE_TSO;
3417 return MLX5_TXCMP_CODE_SINGLE;
3423 * Tx burst function for single-segment packets with TSO.
3424 * Supports all types of Tx offloads, except multi-packets.
3425 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3426 * Function stops sending if it encounters the multi-segment
3427 * packet or packet without TSO requested.
3429 * The routine is responsible for storing processed mbuf
3430 * into elts ring buffer and update elts_head if inline
3431 * offloads is requested due to possible early freeing
3432 * of the inlined mbufs (can not store pkts array in elts
3436 * Pointer to TX queue structure.
3438 * Packets to transmit.
3440 * Number of packets in array.
3442 * Pointer to burst routine local context.
3444 * Configured Tx offloads mask. It is fully defined at
3445 * compile time and may be used for optimization.
3448 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3449 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3450 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3451 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3452 * Local context variables updated.
3454 static __rte_always_inline enum mlx5_txcmp_code
3455 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3456 struct rte_mbuf **restrict pkts,
3457 unsigned int pkts_n,
3458 struct mlx5_txq_local *restrict loc,
3461 assert(loc->elts_free && loc->wqe_free);
3462 assert(pkts_n > loc->pkts_sent);
3463 pkts += loc->pkts_sent + 1;
3464 pkts_n -= loc->pkts_sent;
3466 struct mlx5_wqe_dseg *restrict dseg;
3467 struct mlx5_wqe *restrict wqe;
3468 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3471 assert(NB_SEGS(loc->mbuf) == 1);
3472 dlen = rte_pktmbuf_data_len(loc->mbuf);
3473 if (MLX5_TXOFF_CONFIG(VLAN) &&
3474 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3475 vlan = sizeof(struct rte_vlan_hdr);
3478 * First calculate the WQE size to check
3479 * whether we have enough space in ring buffer.
3481 hlen = loc->mbuf->l2_len + vlan +
3482 loc->mbuf->l3_len + loc->mbuf->l4_len;
3483 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3484 return MLX5_TXCMP_CODE_ERROR;
3485 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3486 hlen += loc->mbuf->outer_l2_len +
3487 loc->mbuf->outer_l3_len;
3488 /* Segment must contain all TSO headers. */
3489 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3490 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3491 hlen > (dlen + vlan)))
3492 return MLX5_TXCMP_CODE_ERROR;
3494 * Check whether there are enough free WQEBBs:
3496 * - Ethernet Segment
3497 * - First Segment of inlined Ethernet data
3498 * - ... data continued ...
3499 * - Finishing Data Segment of pointer type
3501 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3502 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3503 if (loc->wqe_free < ((ds + 3) / 4))
3504 return MLX5_TXCMP_CODE_EXIT;
3505 #ifdef MLX5_PMD_SOFT_COUNTERS
3506 /* Update sent data bytes/packets counters. */
3507 ntcp = (dlen + vlan - hlen +
3508 loc->mbuf->tso_segsz - 1) /
3509 loc->mbuf->tso_segsz;
3511 * One will be added for mbuf itself at the end
3512 * of the mlx5_tx_burst from loc->pkts_sent field.
3515 txq->stats.opackets += ntcp;
3516 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3519 * Build the TSO WQE:
3521 * - Ethernet Segment with hlen bytes inlined
3522 * - Data Segment of pointer type
3524 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3525 loc->wqe_last = wqe;
3526 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3527 MLX5_OPCODE_TSO, olx);
3528 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3529 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3530 dlen -= hlen - vlan;
3531 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3533 * WQE is built, update the loop parameters
3534 * and go to the next packet.
3536 txq->wqe_ci += (ds + 3) / 4;
3537 loc->wqe_free -= (ds + 3) / 4;
3538 if (MLX5_TXOFF_CONFIG(INLINE))
3539 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3543 /* Request CQE generation if limits are reached. */
3544 mlx5_tx_request_completion(txq, loc, olx);
3545 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3546 return MLX5_TXCMP_CODE_EXIT;
3547 loc->mbuf = *pkts++;
3549 rte_prefetch0(*pkts);
3550 if (MLX5_TXOFF_CONFIG(MULTI) &&
3551 unlikely(NB_SEGS(loc->mbuf) > 1))
3552 return MLX5_TXCMP_CODE_MULTI;
3553 if (unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3554 return MLX5_TXCMP_CODE_SINGLE;
3555 /* Continue with the next TSO packet. */
3561 * Analyze the packet and select the best method to send.
3564 * Pointer to TX queue structure.
3566 * Pointer to burst routine local context.
3568 * Configured Tx offloads mask. It is fully defined at
3569 * compile time and may be used for optimization.
3571 * The predefined flag whether do complete check for
3572 * multi-segment packets and TSO.
3575 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3576 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3577 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3578 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3580 static __rte_always_inline enum mlx5_txcmp_code
3581 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3582 struct mlx5_txq_local *restrict loc,
3586 /* Check for multi-segment packet. */
3588 MLX5_TXOFF_CONFIG(MULTI) &&
3589 unlikely(NB_SEGS(loc->mbuf) > 1))
3590 return MLX5_TXCMP_CODE_MULTI;
3591 /* Check for TSO packet. */
3593 MLX5_TXOFF_CONFIG(TSO) &&
3594 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3595 return MLX5_TXCMP_CODE_TSO;
3596 /* Check if eMPW is enabled at all. */
3597 if (!MLX5_TXOFF_CONFIG(EMPW))
3598 return MLX5_TXCMP_CODE_SINGLE;
3599 /* Check if eMPW can be engaged. */
3600 if (MLX5_TXOFF_CONFIG(VLAN) &&
3601 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3602 (!MLX5_TXOFF_CONFIG(INLINE) ||
3603 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3604 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3606 * eMPW does not support VLAN insertion offload,
3607 * we have to inline the entire packet but
3608 * packet is too long for inlining.
3610 return MLX5_TXCMP_CODE_SINGLE;
3612 return MLX5_TXCMP_CODE_EMPW;
3616 * Check the next packet attributes to match with the eMPW batch ones.
3619 * Pointer to TX queue structure.
3621 * Pointer to Ethernet Segment of eMPW batch.
3623 * Pointer to burst routine local context.
3625 * Configured Tx offloads mask. It is fully defined at
3626 * compile time and may be used for optimization.
3629 * true - packet match with eMPW batch attributes.
3630 * false - no match, eMPW should be restarted.
3632 static __rte_always_inline bool
3633 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3634 struct mlx5_wqe_eseg *restrict es,
3635 struct mlx5_txq_local *restrict loc,
3638 uint8_t swp_flags = 0;
3640 /* Compare the checksum flags, if any. */
3641 if (MLX5_TXOFF_CONFIG(CSUM) &&
3642 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3644 /* Compare the Software Parser offsets and flags. */
3645 if (MLX5_TXOFF_CONFIG(SWP) &&
3646 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3647 es->swp_flags != swp_flags))
3649 /* Fill metadata field if needed. */
3650 if (MLX5_TXOFF_CONFIG(METADATA) &&
3651 es->metadata != (loc->mbuf->ol_flags & PKT_TX_METADATA ?
3652 loc->mbuf->tx_metadata : 0))
3654 /* There must be no VLAN packets in eMPW loop. */
3655 if (MLX5_TXOFF_CONFIG(VLAN))
3656 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3661 * Update send loop variables and WQE for eMPW loop
3662 * without data inlining. Number of Data Segments is
3663 * equal to the number of sent packets.
3666 * Pointer to TX queue structure.
3668 * Pointer to burst routine local context.
3670 * Number of packets/Data Segments/Packets.
3672 * Accumulated statistics, bytes sent
3674 * Configured Tx offloads mask. It is fully defined at
3675 * compile time and may be used for optimization.
3678 * true - packet match with eMPW batch attributes.
3679 * false - no match, eMPW should be restarted.
3681 static __rte_always_inline void
3682 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3683 struct mlx5_txq_local *restrict loc,
3688 assert(!MLX5_TXOFF_CONFIG(INLINE));
3689 #ifdef MLX5_PMD_SOFT_COUNTERS
3690 /* Update sent data bytes counter. */
3691 txq->stats.obytes += slen;
3695 loc->elts_free -= ds;
3696 loc->pkts_sent += ds;
3698 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3699 txq->wqe_ci += (ds + 3) / 4;
3700 loc->wqe_free -= (ds + 3) / 4;
3701 /* Request CQE generation if limits are reached. */
3702 mlx5_tx_request_completion(txq, loc, olx);
3706 * Update send loop variables and WQE for eMPW loop
3707 * with data inlining. Gets the size of pushed descriptors
3708 * and data to the WQE.
3711 * Pointer to TX queue structure.
3713 * Pointer to burst routine local context.
3715 * Total size of descriptor/data in bytes.
3717 * Accumulated statistics, data bytes sent.
3719 * Configured Tx offloads mask. It is fully defined at
3720 * compile time and may be used for optimization.
3723 * true - packet match with eMPW batch attributes.
3724 * false - no match, eMPW should be restarted.
3726 static __rte_always_inline void
3727 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3728 struct mlx5_txq_local *restrict loc,
3731 unsigned int olx __rte_unused)
3733 assert(MLX5_TXOFF_CONFIG(INLINE));
3734 assert((len % MLX5_WSEG_SIZE) == 0);
3735 #ifdef MLX5_PMD_SOFT_COUNTERS
3736 /* Update sent data bytes counter. */
3737 txq->stats.obytes += slen;
3741 len = len / MLX5_WSEG_SIZE + 2;
3742 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3743 txq->wqe_ci += (len + 3) / 4;
3744 loc->wqe_free -= (len + 3) / 4;
3745 /* Request CQE generation if limits are reached. */
3746 mlx5_tx_request_completion(txq, loc, olx);
3750 * The set of Tx burst functions for single-segment packets
3751 * without TSO and with Multi-Packet Writing feature support.
3752 * Supports all types of Tx offloads, except multi-packets
3755 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3756 * as many packet per WQE as it can. If eMPW is not configured
3757 * or packet can not be sent with eMPW (VLAN insertion) the
3758 * ordinary SEND opcode is used and only one packet placed
3761 * Functions stop sending if it encounters the multi-segment
3762 * packet or packet with TSO requested.
3764 * The routines are responsible for storing processed mbuf
3765 * into elts ring buffer and update elts_head if inlining
3766 * offload is requested. Otherwise the copying mbufs to elts
3767 * can be postponed and completed at the end of burst routine.
3770 * Pointer to TX queue structure.
3772 * Packets to transmit.
3774 * Number of packets in array.
3776 * Pointer to burst routine local context.
3778 * Configured Tx offloads mask. It is fully defined at
3779 * compile time and may be used for optimization.
3782 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3783 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3784 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3785 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3786 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3787 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3789 * Local context variables updated.
3792 * The routine sends packets with MLX5_OPCODE_EMPW
3793 * without inlining, this is dedicated optimized branch.
3794 * No VLAN insertion is supported.
3796 static __rte_always_inline enum mlx5_txcmp_code
3797 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3798 struct rte_mbuf **restrict pkts,
3799 unsigned int pkts_n,
3800 struct mlx5_txq_local *restrict loc,
3804 * Subroutine is the part of mlx5_tx_burst_single()
3805 * and sends single-segment packet with eMPW opcode
3806 * without data inlining.
3808 assert(!MLX5_TXOFF_CONFIG(INLINE));
3809 assert(MLX5_TXOFF_CONFIG(EMPW));
3810 assert(loc->elts_free && loc->wqe_free);
3811 assert(pkts_n > loc->pkts_sent);
3812 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3813 pkts += loc->pkts_sent + 1;
3814 pkts_n -= loc->pkts_sent;
3816 struct mlx5_wqe_dseg *restrict dseg;
3817 struct mlx5_wqe_eseg *restrict eseg;
3818 enum mlx5_txcmp_code ret;
3819 unsigned int part, loop;
3820 unsigned int slen = 0;
3823 part = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3824 if (unlikely(loc->elts_free < part)) {
3825 /* We have no enough elts to save all mbufs. */
3826 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3827 return MLX5_TXCMP_CODE_EXIT;
3828 /* But we still able to send at least minimal eMPW. */
3829 part = loc->elts_free;
3831 /* Check whether we have enough WQEs */
3832 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3833 if (unlikely(loc->wqe_free <
3834 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3835 return MLX5_TXCMP_CODE_EXIT;
3836 part = (loc->wqe_free * 4) - 2;
3838 if (likely(part > 1))
3839 rte_prefetch0(*pkts);
3840 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3842 * Build eMPW title WQEBB:
3843 * - Control Segment, eMPW opcode
3844 * - Ethernet Segment, no inline
3846 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3847 MLX5_OPCODE_ENHANCED_MPSW, olx);
3848 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3849 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3850 eseg = &loc->wqe_last->eseg;
3851 dseg = &loc->wqe_last->dseg[0];
3854 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3855 #ifdef MLX5_PMD_SOFT_COUNTERS
3856 /* Update sent data bytes counter. */
3861 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3863 if (unlikely(--loop == 0))
3865 loc->mbuf = *pkts++;
3866 if (likely(loop > 1))
3867 rte_prefetch0(*pkts);
3868 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3870 * Unroll the completion code to avoid
3871 * returning variable value - it results in
3872 * unoptimized sequent checking in caller.
3874 if (ret == MLX5_TXCMP_CODE_MULTI) {
3876 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3877 if (unlikely(!loc->elts_free ||
3879 return MLX5_TXCMP_CODE_EXIT;
3880 return MLX5_TXCMP_CODE_MULTI;
3882 if (ret == MLX5_TXCMP_CODE_TSO) {
3884 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3885 if (unlikely(!loc->elts_free ||
3887 return MLX5_TXCMP_CODE_EXIT;
3888 return MLX5_TXCMP_CODE_TSO;
3890 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3892 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3893 if (unlikely(!loc->elts_free ||
3895 return MLX5_TXCMP_CODE_EXIT;
3896 return MLX5_TXCMP_CODE_SINGLE;
3898 if (ret != MLX5_TXCMP_CODE_EMPW) {
3901 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3902 return MLX5_TXCMP_CODE_ERROR;
3905 * Check whether packet parameters coincide
3906 * within assumed eMPW batch:
3907 * - check sum settings
3909 * - software parser settings
3911 if (!mlx5_tx_match_empw(txq, eseg, loc, olx)) {
3914 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3915 if (unlikely(!loc->elts_free ||
3917 return MLX5_TXCMP_CODE_EXIT;
3921 /* Packet attributes match, continue the same eMPW. */
3923 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3924 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3926 /* eMPW is built successfully, update loop parameters. */
3928 assert(pkts_n >= part);
3929 #ifdef MLX5_PMD_SOFT_COUNTERS
3930 /* Update sent data bytes counter. */
3931 txq->stats.obytes += slen;
3933 loc->elts_free -= part;
3934 loc->pkts_sent += part;
3935 txq->wqe_ci += (2 + part + 3) / 4;
3936 loc->wqe_free -= (2 + part + 3) / 4;
3938 /* Request CQE generation if limits are reached. */
3939 mlx5_tx_request_completion(txq, loc, olx);
3940 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3941 return MLX5_TXCMP_CODE_EXIT;
3942 loc->mbuf = *pkts++;
3943 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3944 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
3946 /* Continue sending eMPW batches. */
3952 * The routine sends packets with MLX5_OPCODE_EMPW
3953 * with inlining, optionally supports VLAN insertion.
3955 static __rte_always_inline enum mlx5_txcmp_code
3956 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
3957 struct rte_mbuf **restrict pkts,
3958 unsigned int pkts_n,
3959 struct mlx5_txq_local *restrict loc,
3963 * Subroutine is the part of mlx5_tx_burst_single()
3964 * and sends single-segment packet with eMPW opcode
3965 * with data inlining.
3967 assert(MLX5_TXOFF_CONFIG(INLINE));
3968 assert(MLX5_TXOFF_CONFIG(EMPW));
3969 assert(loc->elts_free && loc->wqe_free);
3970 assert(pkts_n > loc->pkts_sent);
3971 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3972 pkts += loc->pkts_sent + 1;
3973 pkts_n -= loc->pkts_sent;
3975 struct mlx5_wqe_dseg *restrict dseg;
3976 struct mlx5_wqe_eseg *restrict eseg;
3977 enum mlx5_txcmp_code ret;
3978 unsigned int room, part, nlim;
3979 unsigned int slen = 0;
3982 * Limits the amount of packets in one WQE
3983 * to improve CQE latency generation.
3985 nlim = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3986 /* Check whether we have minimal amount WQEs */
3987 if (unlikely(loc->wqe_free <
3988 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3989 return MLX5_TXCMP_CODE_EXIT;
3990 if (likely(pkts_n > 1))
3991 rte_prefetch0(*pkts);
3992 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3994 * Build eMPW title WQEBB:
3995 * - Control Segment, eMPW opcode, zero DS
3996 * - Ethernet Segment, no inline
3998 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
3999 MLX5_OPCODE_ENHANCED_MPSW, olx);
4000 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4001 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4002 eseg = &loc->wqe_last->eseg;
4003 dseg = &loc->wqe_last->dseg[0];
4004 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4005 loc->wqe_free) * MLX5_WQE_SIZE -
4006 MLX5_WQE_CSEG_SIZE -
4008 /* Build WQE till we have space, packets and resources. */
4011 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4012 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4015 assert(room >= MLX5_WQE_DSEG_SIZE);
4016 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
4017 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4019 * Some Tx offloads may cause an error if
4020 * packet is not long enough, check against
4021 * assumed minimal length.
4023 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4025 if (unlikely(!part))
4026 return MLX5_TXCMP_CODE_ERROR;
4028 * We have some successfully built
4029 * packet Data Segments to send.
4031 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4032 return MLX5_TXCMP_CODE_ERROR;
4034 /* Inline or not inline - that's the Question. */
4035 if (dlen > txq->inlen_empw)
4037 /* Inline entire packet, optional VLAN insertion. */
4038 tlen = sizeof(dseg->bcount) + dlen;
4039 if (MLX5_TXOFF_CONFIG(VLAN) &&
4040 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4042 * The packet length must be checked in
4043 * mlx5_tx_able_to_empw() and packet
4044 * fits into inline length guaranteed.
4046 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
4048 tlen += sizeof(struct rte_vlan_hdr);
4051 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4053 #ifdef MLX5_PMD_SOFT_COUNTERS
4054 /* Update sent data bytes counter. */
4055 slen += sizeof(struct rte_vlan_hdr);
4060 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4063 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4064 assert(room >= tlen);
4067 * Packet data are completely inlined,
4068 * free the packet immediately.
4070 rte_pktmbuf_free_seg(loc->mbuf);
4074 * Not inlinable VLAN packets are
4075 * proceeded outside of this routine.
4077 assert(room >= MLX5_WQE_DSEG_SIZE);
4078 if (MLX5_TXOFF_CONFIG(VLAN))
4079 assert(!(loc->mbuf->ol_flags &
4081 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4082 /* We have to store mbuf in elts.*/
4083 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4084 room -= MLX5_WQE_DSEG_SIZE;
4085 /* Ring buffer wraparound is checked at the loop end.*/
4088 #ifdef MLX5_PMD_SOFT_COUNTERS
4089 /* Update sent data bytes counter. */
4095 if (unlikely(!pkts_n || !loc->elts_free)) {
4097 * We have no resources/packets to
4098 * continue build descriptors.
4101 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4102 return MLX5_TXCMP_CODE_EXIT;
4104 loc->mbuf = *pkts++;
4105 if (likely(pkts_n > 1))
4106 rte_prefetch0(*pkts);
4107 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4109 * Unroll the completion code to avoid
4110 * returning variable value - it results in
4111 * unoptimized sequent checking in caller.
4113 if (ret == MLX5_TXCMP_CODE_MULTI) {
4115 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4116 if (unlikely(!loc->elts_free ||
4118 return MLX5_TXCMP_CODE_EXIT;
4119 return MLX5_TXCMP_CODE_MULTI;
4121 if (ret == MLX5_TXCMP_CODE_TSO) {
4123 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4124 if (unlikely(!loc->elts_free ||
4126 return MLX5_TXCMP_CODE_EXIT;
4127 return MLX5_TXCMP_CODE_TSO;
4129 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4131 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4132 if (unlikely(!loc->elts_free ||
4134 return MLX5_TXCMP_CODE_EXIT;
4135 return MLX5_TXCMP_CODE_SINGLE;
4137 if (ret != MLX5_TXCMP_CODE_EMPW) {
4140 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4141 return MLX5_TXCMP_CODE_ERROR;
4143 /* Check if we have minimal room left. */
4145 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4148 * Check whether packet parameters coincide
4149 * within assumed eMPW batch:
4150 * - check sum settings
4152 * - software parser settings
4154 if (!mlx5_tx_match_empw(txq, eseg, loc, olx))
4156 /* Packet attributes match, continue the same eMPW. */
4157 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4158 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4161 * We get here to close an existing eMPW
4162 * session and start the new one.
4166 if (unlikely(!part))
4167 return MLX5_TXCMP_CODE_EXIT;
4168 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4169 if (unlikely(!loc->elts_free ||
4171 return MLX5_TXCMP_CODE_EXIT;
4172 /* Continue the loop with new eMPW session. */
4178 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4179 * Data inlining and VLAN insertion are supported.
4181 static __rte_always_inline enum mlx5_txcmp_code
4182 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4183 struct rte_mbuf **restrict pkts,
4184 unsigned int pkts_n,
4185 struct mlx5_txq_local *restrict loc,
4189 * Subroutine is the part of mlx5_tx_burst_single()
4190 * and sends single-segment packet with SEND opcode.
4192 assert(loc->elts_free && loc->wqe_free);
4193 assert(pkts_n > loc->pkts_sent);
4194 pkts += loc->pkts_sent + 1;
4195 pkts_n -= loc->pkts_sent;
4197 struct mlx5_wqe *restrict wqe;
4198 enum mlx5_txcmp_code ret;
4200 assert(NB_SEGS(loc->mbuf) == 1);
4201 if (MLX5_TXOFF_CONFIG(INLINE)) {
4202 unsigned int inlen, vlan = 0;
4204 inlen = rte_pktmbuf_data_len(loc->mbuf);
4205 if (MLX5_TXOFF_CONFIG(VLAN) &&
4206 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4207 vlan = sizeof(struct rte_vlan_hdr);
4209 static_assert((sizeof(struct rte_vlan_hdr) +
4210 sizeof(struct rte_ether_hdr)) ==
4211 MLX5_ESEG_MIN_INLINE_SIZE,
4212 "invalid min inline data size");
4215 * If inlining is enabled at configuration time
4216 * the limit must be not less than minimal size.
4217 * Otherwise we would do extra check for data
4218 * size to avoid crashes due to length overflow.
4220 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4221 if (inlen <= txq->inlen_send) {
4222 unsigned int seg_n, wqe_n;
4224 rte_prefetch0(rte_pktmbuf_mtod
4225 (loc->mbuf, uint8_t *));
4226 /* Check against minimal length. */
4227 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4228 return MLX5_TXCMP_CODE_ERROR;
4230 * Completely inlined packet data WQE:
4231 * - Control Segment, SEND opcode
4232 * - Ethernet Segment, no VLAN insertion
4233 * - Data inlined, VLAN optionally inserted
4234 * - Alignment to MLX5_WSEG_SIZE
4235 * Have to estimate amount of WQEBBs
4237 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4238 MLX5_ESEG_MIN_INLINE_SIZE +
4239 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4240 /* Check if there are enough WQEBBs. */
4241 wqe_n = (seg_n + 3) / 4;
4242 if (wqe_n > loc->wqe_free)
4243 return MLX5_TXCMP_CODE_EXIT;
4244 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4245 loc->wqe_last = wqe;
4246 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4247 MLX5_OPCODE_SEND, olx);
4248 mlx5_tx_eseg_data(txq, loc, wqe,
4249 vlan, inlen, 0, olx);
4250 txq->wqe_ci += wqe_n;
4251 loc->wqe_free -= wqe_n;
4253 * Packet data are completely inlined,
4254 * free the packet immediately.
4256 rte_pktmbuf_free_seg(loc->mbuf);
4257 } else if (!MLX5_TXOFF_CONFIG(EMPW) &&
4260 * If minimal inlining is requested the eMPW
4261 * feature should be disabled due to data is
4262 * inlined into Ethernet Segment, which can
4263 * not contain inlined data for eMPW due to
4264 * segment shared for all packets.
4266 struct mlx5_wqe_dseg *restrict dseg;
4271 * The inline-mode settings require
4272 * to inline the specified amount of
4273 * data bytes to the Ethernet Segment.
4274 * We should check the free space in
4275 * WQE ring buffer to inline partially.
4277 assert(txq->inlen_send >= txq->inlen_mode);
4278 assert(inlen > txq->inlen_mode);
4279 assert(txq->inlen_mode >=
4280 MLX5_ESEG_MIN_INLINE_SIZE);
4282 * Check whether there are enough free WQEBBs:
4284 * - Ethernet Segment
4285 * - First Segment of inlined Ethernet data
4286 * - ... data continued ...
4287 * - Finishing Data Segment of pointer type
4289 ds = (MLX5_WQE_CSEG_SIZE +
4290 MLX5_WQE_ESEG_SIZE +
4291 MLX5_WQE_DSEG_SIZE +
4293 MLX5_ESEG_MIN_INLINE_SIZE +
4294 MLX5_WQE_DSEG_SIZE +
4295 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4296 if (loc->wqe_free < ((ds + 3) / 4))
4297 return MLX5_TXCMP_CODE_EXIT;
4299 * Build the ordinary SEND WQE:
4301 * - Ethernet Segment, inline inlen_mode bytes
4302 * - Data Segment of pointer type
4304 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4305 loc->wqe_last = wqe;
4306 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4307 MLX5_OPCODE_SEND, olx);
4308 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4311 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4312 txq->inlen_mode - vlan;
4313 inlen -= txq->inlen_mode;
4314 mlx5_tx_dseg_ptr(txq, loc, dseg,
4317 * WQE is built, update the loop parameters
4318 * and got to the next packet.
4320 txq->wqe_ci += (ds + 3) / 4;
4321 loc->wqe_free -= (ds + 3) / 4;
4322 /* We have to store mbuf in elts.*/
4323 assert(MLX5_TXOFF_CONFIG(INLINE));
4324 txq->elts[txq->elts_head++ & txq->elts_m] =
4332 * Partially inlined packet data WQE, we have
4333 * some space in title WQEBB, we can fill it
4334 * with some packet data. It takes one WQEBB,
4335 * it is available, no extra space check:
4336 * - Control Segment, SEND opcode
4337 * - Ethernet Segment, no VLAN insertion
4338 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4339 * - Data Segment, pointer type
4341 * We also get here if VLAN insertion is not
4342 * supported by HW, the inline is enabled.
4344 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4345 loc->wqe_last = wqe;
4346 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4347 MLX5_OPCODE_SEND, olx);
4348 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4349 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4350 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4352 * The length check is performed above, by
4353 * comparing with txq->inlen_send. We should
4354 * not get overflow here.
4356 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4357 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4358 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4362 /* We have to store mbuf in elts.*/
4363 assert(MLX5_TXOFF_CONFIG(INLINE));
4364 txq->elts[txq->elts_head++ & txq->elts_m] =
4368 #ifdef MLX5_PMD_SOFT_COUNTERS
4369 /* Update sent data bytes counter. */
4370 txq->stats.obytes += vlan +
4371 rte_pktmbuf_data_len(loc->mbuf);
4375 * No inline at all, it means the CPU cycles saving
4376 * is prioritized at configuration, we should not
4377 * copy any packet data to WQE.
4379 * SEND WQE, one WQEBB:
4380 * - Control Segment, SEND opcode
4381 * - Ethernet Segment, optional VLAN, no inline
4382 * - Data Segment, pointer type
4384 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4385 loc->wqe_last = wqe;
4386 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4387 MLX5_OPCODE_SEND, olx);
4388 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4390 (txq, loc, &wqe->dseg[0],
4391 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4392 rte_pktmbuf_data_len(loc->mbuf), olx);
4396 * We should not store mbuf pointer in elts
4397 * if no inlining is configured, this is done
4398 * by calling routine in a batch copy.
4400 assert(!MLX5_TXOFF_CONFIG(INLINE));
4402 #ifdef MLX5_PMD_SOFT_COUNTERS
4403 /* Update sent data bytes counter. */
4404 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4405 if (MLX5_TXOFF_CONFIG(VLAN) &&
4406 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4407 txq->stats.obytes +=
4408 sizeof(struct rte_vlan_hdr);
4413 /* Request CQE generation if limits are reached. */
4414 mlx5_tx_request_completion(txq, loc, olx);
4415 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4416 return MLX5_TXCMP_CODE_EXIT;
4417 loc->mbuf = *pkts++;
4419 rte_prefetch0(*pkts);
4420 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4421 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4427 static __rte_always_inline enum mlx5_txcmp_code
4428 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4429 struct rte_mbuf **restrict pkts,
4430 unsigned int pkts_n,
4431 struct mlx5_txq_local *restrict loc,
4434 enum mlx5_txcmp_code ret;
4436 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4437 if (ret == MLX5_TXCMP_CODE_SINGLE)
4439 assert(ret == MLX5_TXCMP_CODE_EMPW);
4441 /* Optimize for inline/no inline eMPW send. */
4442 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4443 mlx5_tx_burst_empw_inline
4444 (txq, pkts, pkts_n, loc, olx) :
4445 mlx5_tx_burst_empw_simple
4446 (txq, pkts, pkts_n, loc, olx);
4447 if (ret != MLX5_TXCMP_CODE_SINGLE)
4449 /* The resources to send one packet should remain. */
4450 assert(loc->elts_free && loc->wqe_free);
4452 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4453 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4454 if (ret != MLX5_TXCMP_CODE_EMPW)
4456 /* The resources to send one packet should remain. */
4457 assert(loc->elts_free && loc->wqe_free);
4462 * DPDK Tx callback template. This is configured template
4463 * used to generate routines optimized for specified offload setup.
4464 * One of this generated functions is chosen at SQ configuration
4468 * Generic pointer to TX queue structure.
4470 * Packets to transmit.
4472 * Number of packets in array.
4474 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4475 * values. Should be static to take compile time static configuration
4479 * Number of packets successfully transmitted (<= pkts_n).
4481 static __rte_always_inline uint16_t
4482 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4483 struct rte_mbuf **restrict pkts,
4487 struct mlx5_txq_local loc;
4488 enum mlx5_txcmp_code ret;
4491 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4492 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4494 * Check if there are some CQEs, if any:
4495 * - process an encountered errors
4496 * - process the completed WQEs
4497 * - free related mbufs
4498 * - doorbell the NIC about processed CQEs
4500 if (unlikely(!pkts_n))
4502 rte_prefetch0(*pkts);
4503 mlx5_tx_handle_completion(txq, olx);
4505 * Calculate the number of available resources - elts and WQEs.
4506 * There are two possible different scenarios:
4507 * - no data inlining into WQEs, one WQEBB may contains upto
4508 * four packets, in this case elts become scarce resource
4509 * - data inlining into WQEs, one packet may require multiple
4510 * WQEBBs, the WQEs become the limiting factor.
4512 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4513 loc.elts_free = txq->elts_s -
4514 (uint16_t)(txq->elts_head - txq->elts_tail);
4515 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4516 loc.wqe_free = txq->wqe_s -
4517 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4518 if (unlikely(!loc.elts_free || !loc.wqe_free))
4522 loc.wqe_last = NULL;
4525 * Fetch the packet from array. Usually this is
4526 * the first packet in series of multi/single
4529 loc.mbuf = *(pkts + loc.pkts_sent);
4530 /* Dedicated branch for multi-segment packets. */
4531 if (MLX5_TXOFF_CONFIG(MULTI) &&
4532 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4534 * Multi-segment packet encountered.
4535 * Hardware is able to process it only
4536 * with SEND/TSO opcodes, one packet
4537 * per WQE, do it in dedicated routine.
4540 assert(loc.pkts_sent >= loc.pkts_copy);
4541 part = loc.pkts_sent - loc.pkts_copy;
4542 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4544 * There are some single-segment mbufs not
4545 * stored in elts. The mbufs must be in the
4546 * same order as WQEs, so we must copy the
4547 * mbufs to elts here, before the coming
4548 * multi-segment packet mbufs is appended.
4550 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4552 loc.pkts_copy = loc.pkts_sent;
4554 assert(pkts_n > loc.pkts_sent);
4555 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4556 if (!MLX5_TXOFF_CONFIG(INLINE))
4557 loc.pkts_copy = loc.pkts_sent;
4559 * These returned code checks are supposed
4560 * to be optimized out due to routine inlining.
4562 if (ret == MLX5_TXCMP_CODE_EXIT) {
4564 * The routine returns this code when
4565 * all packets are sent or there is no
4566 * enough resources to complete request.
4570 if (ret == MLX5_TXCMP_CODE_ERROR) {
4572 * The routine returns this code when
4573 * some error in the incoming packets
4576 txq->stats.oerrors++;
4579 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4581 * The single-segment packet was encountered
4582 * in the array, try to send it with the
4583 * best optimized way, possible engaging eMPW.
4585 goto enter_send_single;
4587 if (MLX5_TXOFF_CONFIG(TSO) &&
4588 ret == MLX5_TXCMP_CODE_TSO) {
4590 * The single-segment TSO packet was
4591 * encountered in the array.
4593 goto enter_send_tso;
4595 /* We must not get here. Something is going wrong. */
4597 txq->stats.oerrors++;
4600 /* Dedicated branch for single-segment TSO packets. */
4601 if (MLX5_TXOFF_CONFIG(TSO) &&
4602 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4604 * TSO might require special way for inlining
4605 * (dedicated parameters) and is sent with
4606 * MLX5_OPCODE_TSO opcode only, provide this
4607 * in dedicated branch.
4610 assert(NB_SEGS(loc.mbuf) == 1);
4611 assert(pkts_n > loc.pkts_sent);
4612 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4614 * These returned code checks are supposed
4615 * to be optimized out due to routine inlining.
4617 if (ret == MLX5_TXCMP_CODE_EXIT)
4619 if (ret == MLX5_TXCMP_CODE_ERROR) {
4620 txq->stats.oerrors++;
4623 if (ret == MLX5_TXCMP_CODE_SINGLE)
4624 goto enter_send_single;
4625 if (MLX5_TXOFF_CONFIG(MULTI) &&
4626 ret == MLX5_TXCMP_CODE_MULTI) {
4628 * The multi-segment packet was
4629 * encountered in the array.
4631 goto enter_send_multi;
4633 /* We must not get here. Something is going wrong. */
4635 txq->stats.oerrors++;
4639 * The dedicated branch for the single-segment packets
4640 * without TSO. Often these ones can be sent using
4641 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4642 * The routine builds the WQEs till it encounters
4643 * the TSO or multi-segment packet (in case if these
4644 * offloads are requested at SQ configuration time).
4647 assert(pkts_n > loc.pkts_sent);
4648 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4650 * These returned code checks are supposed
4651 * to be optimized out due to routine inlining.
4653 if (ret == MLX5_TXCMP_CODE_EXIT)
4655 if (ret == MLX5_TXCMP_CODE_ERROR) {
4656 txq->stats.oerrors++;
4659 if (MLX5_TXOFF_CONFIG(MULTI) &&
4660 ret == MLX5_TXCMP_CODE_MULTI) {
4662 * The multi-segment packet was
4663 * encountered in the array.
4665 goto enter_send_multi;
4667 if (MLX5_TXOFF_CONFIG(TSO) &&
4668 ret == MLX5_TXCMP_CODE_TSO) {
4670 * The single-segment TSO packet was
4671 * encountered in the array.
4673 goto enter_send_tso;
4675 /* We must not get here. Something is going wrong. */
4677 txq->stats.oerrors++;
4681 * Main Tx loop is completed, do the rest:
4682 * - set completion request if thresholds are reached
4683 * - doorbell the hardware
4684 * - copy the rest of mbufs to elts (if any)
4686 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4687 /* Take a shortcut if nothing is sent. */
4688 if (unlikely(loc.pkts_sent == 0))
4691 * Ring QP doorbell immediately after WQE building completion
4692 * to improve latencies. The pure software related data treatment
4693 * can be completed after doorbell. Tx CQEs for this SQ are
4694 * processed in this thread only by the polling.
4696 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);
4697 /* Not all of the mbufs may be stored into elts yet. */
4698 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent -
4699 (MLX5_TXOFF_CONFIG(MULTI) ? loc.pkts_copy : 0);
4700 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4702 * There are some single-segment mbufs not stored in elts.
4703 * It can be only if the last packet was single-segment.
4704 * The copying is gathered into one place due to it is
4705 * a good opportunity to optimize that with SIMD.
4706 * Unfortunately if inlining is enabled the gaps in
4707 * pointer array may happen due to early freeing of the
4710 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4712 #ifdef MLX5_PMD_SOFT_COUNTERS
4713 /* Increment sent packets counter. */
4714 txq->stats.opackets += loc.pkts_sent;
4716 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4717 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4718 return loc.pkts_sent;
4721 /* Generate routines with Enhanced Multi-Packet Write support. */
4722 MLX5_TXOFF_DECL(full_empw,
4723 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4725 MLX5_TXOFF_DECL(none_empw,
4726 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4728 MLX5_TXOFF_DECL(md_empw,
4729 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4731 MLX5_TXOFF_DECL(mt_empw,
4732 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4733 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4735 MLX5_TXOFF_DECL(mtsc_empw,
4736 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4737 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4738 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4740 MLX5_TXOFF_DECL(mti_empw,
4741 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4742 MLX5_TXOFF_CONFIG_INLINE |
4743 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4745 MLX5_TXOFF_DECL(mtv_empw,
4746 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4747 MLX5_TXOFF_CONFIG_VLAN |
4748 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4750 MLX5_TXOFF_DECL(mtiv_empw,
4751 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4752 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4753 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4755 MLX5_TXOFF_DECL(sc_empw,
4756 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4757 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4759 MLX5_TXOFF_DECL(sci_empw,
4760 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4761 MLX5_TXOFF_CONFIG_INLINE |
4762 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4764 MLX5_TXOFF_DECL(scv_empw,
4765 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4766 MLX5_TXOFF_CONFIG_VLAN |
4767 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4769 MLX5_TXOFF_DECL(sciv_empw,
4770 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4771 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4772 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4774 MLX5_TXOFF_DECL(i_empw,
4775 MLX5_TXOFF_CONFIG_INLINE |
4776 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4778 MLX5_TXOFF_DECL(v_empw,
4779 MLX5_TXOFF_CONFIG_VLAN |
4780 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4782 MLX5_TXOFF_DECL(iv_empw,
4783 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4784 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4786 /* Generate routines without Enhanced Multi-Packet Write support. */
4787 MLX5_TXOFF_DECL(full,
4788 MLX5_TXOFF_CONFIG_FULL)
4790 MLX5_TXOFF_DECL(none,
4791 MLX5_TXOFF_CONFIG_NONE)
4794 MLX5_TXOFF_CONFIG_METADATA)
4797 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4798 MLX5_TXOFF_CONFIG_METADATA)
4800 MLX5_TXOFF_DECL(mtsc,
4801 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4802 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4803 MLX5_TXOFF_CONFIG_METADATA)
4805 MLX5_TXOFF_DECL(mti,
4806 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4807 MLX5_TXOFF_CONFIG_INLINE |
4808 MLX5_TXOFF_CONFIG_METADATA)
4811 MLX5_TXOFF_DECL(mtv,
4812 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4813 MLX5_TXOFF_CONFIG_VLAN |
4814 MLX5_TXOFF_CONFIG_METADATA)
4817 MLX5_TXOFF_DECL(mtiv,
4818 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4819 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4820 MLX5_TXOFF_CONFIG_METADATA)
4823 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4824 MLX5_TXOFF_CONFIG_METADATA)
4826 MLX5_TXOFF_DECL(sci,
4827 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4828 MLX5_TXOFF_CONFIG_INLINE |
4829 MLX5_TXOFF_CONFIG_METADATA)
4832 MLX5_TXOFF_DECL(scv,
4833 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4834 MLX5_TXOFF_CONFIG_VLAN |
4835 MLX5_TXOFF_CONFIG_METADATA)
4838 MLX5_TXOFF_DECL(sciv,
4839 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4840 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4841 MLX5_TXOFF_CONFIG_METADATA)
4844 MLX5_TXOFF_CONFIG_INLINE |
4845 MLX5_TXOFF_CONFIG_METADATA)
4848 MLX5_TXOFF_CONFIG_VLAN |
4849 MLX5_TXOFF_CONFIG_METADATA)
4852 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4853 MLX5_TXOFF_CONFIG_METADATA)
4856 * Array of declared and compiled Tx burst function and corresponding
4857 * supported offloads set. The array is used to select the Tx burst
4858 * function for specified offloads set at Tx queue configuration time.
4861 eth_tx_burst_t func;
4864 MLX5_TXOFF_INFO(full_empw,
4865 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4866 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4867 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4868 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4870 MLX5_TXOFF_INFO(none_empw,
4871 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4873 MLX5_TXOFF_INFO(md_empw,
4874 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4876 MLX5_TXOFF_INFO(mt_empw,
4877 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4878 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4880 MLX5_TXOFF_INFO(mtsc_empw,
4881 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4882 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4883 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4885 MLX5_TXOFF_INFO(mti_empw,
4886 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4887 MLX5_TXOFF_CONFIG_INLINE |
4888 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4890 MLX5_TXOFF_INFO(mtv_empw,
4891 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4892 MLX5_TXOFF_CONFIG_VLAN |
4893 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4895 MLX5_TXOFF_INFO(mtiv_empw,
4896 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4897 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4898 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4900 MLX5_TXOFF_INFO(sc_empw,
4901 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4902 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4904 MLX5_TXOFF_INFO(sci_empw,
4905 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4906 MLX5_TXOFF_CONFIG_INLINE |
4907 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4909 MLX5_TXOFF_INFO(scv_empw,
4910 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4911 MLX5_TXOFF_CONFIG_VLAN |
4912 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4914 MLX5_TXOFF_INFO(sciv_empw,
4915 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4916 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4917 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4919 MLX5_TXOFF_INFO(i_empw,
4920 MLX5_TXOFF_CONFIG_INLINE |
4921 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4923 MLX5_TXOFF_INFO(v_empw,
4924 MLX5_TXOFF_CONFIG_VLAN |
4925 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4927 MLX5_TXOFF_INFO(iv_empw,
4928 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4929 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4931 MLX5_TXOFF_INFO(full,
4932 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4933 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4934 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4935 MLX5_TXOFF_CONFIG_METADATA)
4937 MLX5_TXOFF_INFO(none,
4938 MLX5_TXOFF_CONFIG_NONE)
4941 MLX5_TXOFF_CONFIG_METADATA)
4944 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4945 MLX5_TXOFF_CONFIG_METADATA)
4947 MLX5_TXOFF_INFO(mtsc,
4948 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4949 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4950 MLX5_TXOFF_CONFIG_METADATA)
4952 MLX5_TXOFF_INFO(mti,
4953 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4954 MLX5_TXOFF_CONFIG_INLINE |
4955 MLX5_TXOFF_CONFIG_METADATA)
4958 MLX5_TXOFF_INFO(mtv,
4959 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4960 MLX5_TXOFF_CONFIG_VLAN |
4961 MLX5_TXOFF_CONFIG_METADATA)
4963 MLX5_TXOFF_INFO(mtiv,
4964 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4965 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4966 MLX5_TXOFF_CONFIG_METADATA)
4969 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4970 MLX5_TXOFF_CONFIG_METADATA)
4972 MLX5_TXOFF_INFO(sci,
4973 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4974 MLX5_TXOFF_CONFIG_INLINE |
4975 MLX5_TXOFF_CONFIG_METADATA)
4977 MLX5_TXOFF_INFO(scv,
4978 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4979 MLX5_TXOFF_CONFIG_VLAN |
4980 MLX5_TXOFF_CONFIG_METADATA)
4982 MLX5_TXOFF_INFO(sciv,
4983 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4984 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4985 MLX5_TXOFF_CONFIG_METADATA)
4988 MLX5_TXOFF_CONFIG_INLINE |
4989 MLX5_TXOFF_CONFIG_METADATA)
4992 MLX5_TXOFF_CONFIG_VLAN |
4993 MLX5_TXOFF_CONFIG_METADATA)
4996 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4997 MLX5_TXOFF_CONFIG_METADATA)
5001 * Configure the Tx function to use. The routine checks configured
5002 * Tx offloads for the device and selects appropriate Tx burst
5003 * routine. There are multiple Tx burst routines compiled from
5004 * the same template in the most optimal way for the dedicated
5008 * Pointer to private data structure.
5011 * Pointer to selected Tx burst function.
5014 mlx5_select_tx_function(struct rte_eth_dev *dev)
5016 struct mlx5_priv *priv = dev->data->dev_private;
5017 struct mlx5_dev_config *config = &priv->config;
5018 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5019 unsigned int diff = 0, olx = 0, i, m;
5021 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5022 MLX5_DSEG_MAX, "invalid WQE max size");
5023 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5024 "invalid WQE Control Segment size");
5025 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5026 "invalid WQE Ethernet Segment size");
5027 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5028 "invalid WQE Data Segment size");
5029 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5030 "invalid WQE size");
5032 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5033 /* We should support Multi-Segment Packets. */
5034 olx |= MLX5_TXOFF_CONFIG_MULTI;
5036 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5037 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5038 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5039 DEV_TX_OFFLOAD_IP_TNL_TSO |
5040 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5041 /* We should support TCP Send Offload. */
5042 olx |= MLX5_TXOFF_CONFIG_TSO;
5044 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5045 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5046 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5047 /* We should support Software Parser for Tunnels. */
5048 olx |= MLX5_TXOFF_CONFIG_SWP;
5050 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5051 DEV_TX_OFFLOAD_UDP_CKSUM |
5052 DEV_TX_OFFLOAD_TCP_CKSUM |
5053 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5054 /* We should support IP/TCP/UDP Checksums. */
5055 olx |= MLX5_TXOFF_CONFIG_CSUM;
5057 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5058 /* We should support VLAN insertion. */
5059 olx |= MLX5_TXOFF_CONFIG_VLAN;
5061 if (priv->txqs_n && (*priv->txqs)[0]) {
5062 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5064 if (txd->inlen_send) {
5066 * Check the data inline requirements. Data inline
5067 * is enabled on per device basis, we can check
5068 * the first Tx queue only.
5070 * If device does not support VLAN insertion in WQE
5071 * and some queues are requested to perform VLAN
5072 * insertion offload than inline must be enabled.
5074 olx |= MLX5_TXOFF_CONFIG_INLINE;
5077 if (config->mps == MLX5_MPW_ENHANCED &&
5078 config->txq_inline_min <= 0) {
5080 * The NIC supports Enhanced Multi-Packet Write.
5081 * We do not support legacy MPW due to its
5082 * hardware related problems, so we just ignore
5083 * legacy MLX5_MPW settings. There should be no
5084 * minimal required inline data.
5086 olx |= MLX5_TXOFF_CONFIG_EMPW;
5088 if (tx_offloads & DEV_TX_OFFLOAD_MATCH_METADATA) {
5089 /* We should support Flow metadata. */
5090 olx |= MLX5_TXOFF_CONFIG_METADATA;
5093 * Scan the routines table to find the minimal
5094 * satisfying routine with requested offloads.
5096 m = RTE_DIM(txoff_func);
5097 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5100 tmp = txoff_func[i].olx;
5102 /* Meets requested offloads exactly.*/
5106 if ((tmp & olx) != olx) {
5107 /* Does not meet requested offloads at all. */
5110 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5111 /* Do not enable eMPW if not configured. */
5113 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5114 /* Do not enable inlining if not configured. */
5117 * Some routine meets the requirements.
5118 * Check whether it has minimal amount
5119 * of not requested offloads.
5121 tmp = __builtin_popcountl(tmp & ~olx);
5122 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5123 /* First or better match, save and continue. */
5129 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5130 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5131 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5132 /* Lighter not requested offload. */
5137 if (m >= RTE_DIM(txoff_func)) {
5138 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5139 " for requested offloads %04X",
5140 dev->data->port_id, olx);
5143 DRV_LOG(DEBUG, "port %u has selected Tx function"
5144 " supporting offloads %04X/%04X",
5145 dev->data->port_id, olx, txoff_func[m].olx);
5146 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5147 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5148 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5149 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5150 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5151 DRV_LOG(DEBUG, "\tSWP (software parser)");
5152 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5153 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5154 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5155 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5156 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5157 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5158 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5159 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5160 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW)
5161 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5162 return txoff_func[m].func;