4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 txq_complete(struct txq *txq) __attribute__((always_inline));
159 * Manage TX completions.
161 * When sending a burst, mlx5_tx_burst() posts several WRs.
164 * Pointer to TX queue structure.
167 txq_complete(struct txq *txq)
169 const unsigned int elts_n = txq->elts_n;
170 const unsigned int cqe_n = txq->cqe_n;
171 const unsigned int cqe_cnt = cqe_n - 1;
172 uint16_t elts_free = txq->elts_tail;
174 uint16_t cq_ci = txq->cq_ci;
175 volatile struct mlx5_cqe64 *cqe = NULL;
176 volatile union mlx5_wqe *wqe;
179 volatile struct mlx5_cqe64 *tmp;
181 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
182 if (check_cqe64(tmp, cqe_n, cq_ci))
186 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
187 if (!check_cqe64_seen(cqe))
188 ERROR("unexpected compressed CQE, TX stopped");
191 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
192 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
193 if (!check_cqe64_seen(cqe))
194 ERROR("unexpected error CQE, TX stopped");
200 if (unlikely(cqe == NULL))
202 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)];
203 elts_tail = wqe->wqe.ctrl.data[3];
204 assert(elts_tail < txq->wqe_n);
206 while (elts_free != elts_tail) {
207 struct rte_mbuf *elt = (*txq->elts)[elts_free];
208 unsigned int elts_free_next =
209 (elts_free + 1) & (elts_n - 1);
210 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
214 memset(&(*txq->elts)[elts_free],
216 sizeof((*txq->elts)[elts_free]));
218 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
219 /* Only one segment needs to be freed. */
220 rte_pktmbuf_free_seg(elt);
221 elts_free = elts_free_next;
224 txq->elts_tail = elts_tail;
225 /* Update the consumer index. */
227 *txq->cq_db = htonl(cq_ci);
231 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
232 * the cloned mbuf is allocated is returned instead.
238 * Memory pool where data is located for given mbuf.
240 static struct rte_mempool *
241 txq_mb2mp(struct rte_mbuf *buf)
243 if (unlikely(RTE_MBUF_INDIRECT(buf)))
244 return rte_mbuf_from_indirect(buf)->pool;
248 static inline uint32_t
249 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
250 __attribute__((always_inline));
253 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
254 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
255 * remove an entry first.
258 * Pointer to TX queue structure.
260 * Memory Pool for which a Memory Region lkey must be returned.
263 * mr->lkey on success, (uint32_t)-1 on failure.
265 static inline uint32_t
266 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
269 uint32_t lkey = (uint32_t)-1;
271 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
272 if (unlikely(txq->mp2mr[i].mp == NULL)) {
273 /* Unknown MP, add a new MR for it. */
276 if (txq->mp2mr[i].mp == mp) {
277 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
278 assert(htonl(txq->mp2mr[i].mr->lkey) ==
280 lkey = txq->mp2mr[i].lkey;
284 if (unlikely(lkey == (uint32_t)-1))
285 lkey = txq_mp2mr_reg(txq, mp, i);
290 * Write a regular WQE.
293 * Pointer to TX queue structure.
295 * Pointer to the WQE to fill.
297 * Buffer data address.
301 * Memory region lkey.
304 mlx5_wqe_write(struct txq *txq, volatile union mlx5_wqe *wqe,
305 uintptr_t addr, uint32_t length, uint32_t lkey)
307 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
308 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
309 wqe->wqe.ctrl.data[2] = 0;
310 wqe->wqe.ctrl.data[3] = 0;
311 wqe->inl.eseg.rsvd0 = 0;
312 wqe->inl.eseg.rsvd1 = 0;
313 wqe->inl.eseg.mss = 0;
314 wqe->inl.eseg.rsvd2 = 0;
315 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
316 /* Copy the first 16 bytes into inline header. */
317 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
318 (uint8_t *)(uintptr_t)addr,
319 MLX5_ETH_INLINE_HEADER_SIZE);
320 addr += MLX5_ETH_INLINE_HEADER_SIZE;
321 length -= MLX5_ETH_INLINE_HEADER_SIZE;
322 /* Store remaining data in data segment. */
323 wqe->wqe.dseg.byte_count = htonl(length);
324 wqe->wqe.dseg.lkey = lkey;
325 wqe->wqe.dseg.addr = htonll(addr);
326 /* Increment consumer index. */
331 * Write a regular WQE with VLAN.
334 * Pointer to TX queue structure.
336 * Pointer to the WQE to fill.
338 * Buffer data address.
342 * Memory region lkey.
344 * VLAN field to insert in packet.
347 mlx5_wqe_write_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
348 uintptr_t addr, uint32_t length, uint32_t lkey,
351 uint32_t vlan = htonl(0x81000000 | vlan_tci);
353 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
354 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
355 wqe->wqe.ctrl.data[2] = 0;
356 wqe->wqe.ctrl.data[3] = 0;
357 wqe->inl.eseg.rsvd0 = 0;
358 wqe->inl.eseg.rsvd1 = 0;
359 wqe->inl.eseg.mss = 0;
360 wqe->inl.eseg.rsvd2 = 0;
361 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
363 * Copy 12 bytes of source & destination MAC address.
364 * Copy 4 bytes of VLAN.
365 * Copy 2 bytes of Ether type.
367 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
368 (uint8_t *)(uintptr_t)addr, 12);
369 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 12),
370 &vlan, sizeof(vlan));
371 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 16),
372 (uint8_t *)((uintptr_t)addr + 12), 2);
373 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
374 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
375 /* Store remaining data in data segment. */
376 wqe->wqe.dseg.byte_count = htonl(length);
377 wqe->wqe.dseg.lkey = lkey;
378 wqe->wqe.dseg.addr = htonll(addr);
379 /* Increment consumer index. */
384 * Write a inline WQE.
387 * Pointer to TX queue structure.
389 * Pointer to the WQE to fill.
391 * Buffer data address.
395 * Memory region lkey.
398 mlx5_wqe_write_inline(struct txq *txq, volatile union mlx5_wqe *wqe,
399 uintptr_t addr, uint32_t length)
402 uint16_t wqe_cnt = txq->wqe_n - 1;
403 uint16_t wqe_ci = txq->wqe_ci + 1;
405 /* Copy the first 16 bytes into inline header. */
406 rte_memcpy((void *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
407 (void *)(uintptr_t)addr,
408 MLX5_ETH_INLINE_HEADER_SIZE);
409 addr += MLX5_ETH_INLINE_HEADER_SIZE;
410 length -= MLX5_ETH_INLINE_HEADER_SIZE;
411 size = 3 + ((4 + length + 15) / 16);
412 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
413 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
414 (void *)addr, MLX5_WQE64_INL_DATA);
415 addr += MLX5_WQE64_INL_DATA;
416 length -= MLX5_WQE64_INL_DATA;
418 volatile union mlx5_wqe *wqe_next =
419 &(*txq->wqes)[wqe_ci & wqe_cnt];
420 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
424 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
427 length -= copy_bytes;
431 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
432 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
433 wqe->inl.ctrl.data[2] = 0;
434 wqe->inl.ctrl.data[3] = 0;
435 wqe->inl.eseg.rsvd0 = 0;
436 wqe->inl.eseg.rsvd1 = 0;
437 wqe->inl.eseg.mss = 0;
438 wqe->inl.eseg.rsvd2 = 0;
439 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
440 /* Increment consumer index. */
441 txq->wqe_ci = wqe_ci;
445 * Write a inline WQE with VLAN.
448 * Pointer to TX queue structure.
450 * Pointer to the WQE to fill.
452 * Buffer data address.
456 * Memory region lkey.
458 * VLAN field to insert in packet.
461 mlx5_wqe_write_inline_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
462 uintptr_t addr, uint32_t length, uint16_t vlan_tci)
465 uint32_t wqe_cnt = txq->wqe_n - 1;
466 uint16_t wqe_ci = txq->wqe_ci + 1;
467 uint32_t vlan = htonl(0x81000000 | vlan_tci);
470 * Copy 12 bytes of source & destination MAC address.
471 * Copy 4 bytes of VLAN.
472 * Copy 2 bytes of Ether type.
474 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
475 (uint8_t *)addr, 12);
476 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 12,
477 &vlan, sizeof(vlan));
478 rte_memcpy((uint8_t *)((uintptr_t)wqe->inl.eseg.inline_hdr_start + 16),
479 (uint8_t *)(addr + 12), 2);
480 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
481 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
482 size = (sizeof(wqe->inl.ctrl.ctrl) +
483 sizeof(wqe->inl.eseg) +
484 sizeof(wqe->inl.byte_cnt) +
486 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
487 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
488 (void *)addr, MLX5_WQE64_INL_DATA);
489 addr += MLX5_WQE64_INL_DATA;
490 length -= MLX5_WQE64_INL_DATA;
492 volatile union mlx5_wqe *wqe_next =
493 &(*txq->wqes)[wqe_ci & wqe_cnt];
494 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
498 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
501 length -= copy_bytes;
505 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
506 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
507 wqe->inl.ctrl.data[2] = 0;
508 wqe->inl.ctrl.data[3] = 0;
509 wqe->inl.eseg.rsvd0 = 0;
510 wqe->inl.eseg.rsvd1 = 0;
511 wqe->inl.eseg.mss = 0;
512 wqe->inl.eseg.rsvd2 = 0;
513 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
514 /* Increment consumer index. */
515 txq->wqe_ci = wqe_ci;
519 * Ring TX queue doorbell.
522 * Pointer to TX queue structure.
525 mlx5_tx_dbrec(struct txq *txq)
527 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
529 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
530 htonl(txq->qp_num_8s),
535 *txq->qp_db = htonl(txq->wqe_ci);
536 /* Ensure ordering between DB record and BF copy. */
538 rte_mov16(dst, (uint8_t *)data);
539 txq->bf_offset ^= txq->bf_buf_size;
546 * Pointer to TX queue structure.
548 * CQE consumer index.
551 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
553 volatile struct mlx5_cqe64 *cqe;
555 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
563 * Pointer to TX queue structure.
565 * WQE consumer index.
568 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
570 volatile union mlx5_wqe *wqe;
572 wqe = &(*txq->wqes)[ci & (txq->wqe_n - 1)];
577 * DPDK callback for TX.
580 * Generic pointer to TX queue structure.
582 * Packets to transmit.
584 * Number of packets in array.
587 * Number of packets successfully transmitted (<= pkts_n).
590 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
592 struct txq *txq = (struct txq *)dpdk_txq;
593 uint16_t elts_head = txq->elts_head;
594 const unsigned int elts_n = txq->elts_n;
599 volatile union mlx5_wqe *wqe = NULL;
601 if (unlikely(!pkts_n))
603 /* Prefetch first packet cacheline. */
604 tx_prefetch_cqe(txq, txq->cq_ci);
605 tx_prefetch_cqe(txq, txq->cq_ci + 1);
606 rte_prefetch0(*pkts);
607 /* Start processing. */
609 max = (elts_n - (elts_head - txq->elts_tail));
613 struct rte_mbuf *buf = *(pkts++);
614 unsigned int elts_head_next;
618 unsigned int segs_n = buf->nb_segs;
619 volatile struct mlx5_wqe_data_seg *dseg;
620 unsigned int ds = sizeof(*wqe) / 16;
623 * Make sure there is enough room to store this packet and
624 * that one ring entry remains unused.
627 if (max < segs_n + 1)
631 elts_head_next = (elts_head + 1) & (elts_n - 1);
632 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
633 dseg = &wqe->wqe.dseg;
636 rte_prefetch0(*pkts);
637 /* Retrieve buffer information. */
638 addr = rte_pktmbuf_mtod(buf, uintptr_t);
639 length = DATA_LEN(buf);
640 /* Update element. */
641 (*txq->elts)[elts_head] = buf;
642 /* Prefetch next buffer data. */
644 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
646 /* Retrieve Memory Region key for this memory pool. */
647 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
648 if (buf->ol_flags & PKT_TX_VLAN_PKT)
649 mlx5_wqe_write_vlan(txq, wqe, addr, length, lkey,
652 mlx5_wqe_write(txq, wqe, addr, length, lkey);
653 /* Should we enable HW CKSUM offload */
655 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
656 wqe->wqe.eseg.cs_flags =
657 MLX5_ETH_WQE_L3_CSUM |
658 MLX5_ETH_WQE_L4_CSUM;
660 wqe->wqe.eseg.cs_flags = 0;
664 * Spill on next WQE when the current one does not have
665 * enough room left. Size of WQE must a be a multiple
666 * of data segment size.
668 assert(!(sizeof(*wqe) % sizeof(*dseg)));
669 if (!(ds % (sizeof(*wqe) / 16)))
670 dseg = (volatile void *)
671 &(*txq->wqes)[txq->wqe_ci++ &
678 /* Store segment information. */
679 dseg->byte_count = htonl(DATA_LEN(buf));
680 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
681 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
682 (*txq->elts)[elts_head_next] = buf;
683 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
684 #ifdef MLX5_PMD_SOFT_COUNTERS
685 length += DATA_LEN(buf);
689 /* Update DS field in WQE. */
690 wqe->wqe.ctrl.data[1] &= htonl(0xffffffc0);
691 wqe->wqe.ctrl.data[1] |= htonl(ds & 0x3f);
692 elts_head = elts_head_next;
693 #ifdef MLX5_PMD_SOFT_COUNTERS
694 /* Increment sent bytes counter. */
695 txq->stats.obytes += length;
697 elts_head = elts_head_next;
700 /* Take a shortcut if nothing must be sent. */
701 if (unlikely(i == 0))
703 /* Check whether completion threshold has been reached. */
704 comp = txq->elts_comp + i + j;
705 if (comp >= MLX5_TX_COMP_THRESH) {
706 /* Request completion on last WQE. */
707 wqe->wqe.ctrl.data[2] = htonl(8);
708 /* Save elts_head in unused "immediate" field of WQE. */
709 wqe->wqe.ctrl.data[3] = elts_head;
712 txq->elts_comp = comp;
714 #ifdef MLX5_PMD_SOFT_COUNTERS
715 /* Increment sent packets counter. */
716 txq->stats.opackets += i;
718 /* Ring QP doorbell. */
720 txq->elts_head = elts_head;
725 * DPDK callback for TX with inline support.
728 * Generic pointer to TX queue structure.
730 * Packets to transmit.
732 * Number of packets in array.
735 * Number of packets successfully transmitted (<= pkts_n).
738 mlx5_tx_burst_inline(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
740 struct txq *txq = (struct txq *)dpdk_txq;
741 uint16_t elts_head = txq->elts_head;
742 const unsigned int elts_n = txq->elts_n;
747 volatile union mlx5_wqe *wqe = NULL;
748 unsigned int max_inline = txq->max_inline;
750 if (unlikely(!pkts_n))
752 /* Prefetch first packet cacheline. */
753 tx_prefetch_cqe(txq, txq->cq_ci);
754 tx_prefetch_cqe(txq, txq->cq_ci + 1);
755 rte_prefetch0(*pkts);
756 /* Start processing. */
758 max = (elts_n - (elts_head - txq->elts_tail));
762 struct rte_mbuf *buf = *(pkts++);
763 unsigned int elts_head_next;
767 unsigned int segs_n = buf->nb_segs;
768 volatile struct mlx5_wqe_data_seg *dseg;
769 unsigned int ds = sizeof(*wqe) / 16;
772 * Make sure there is enough room to store this packet and
773 * that one ring entry remains unused.
776 if (max < segs_n + 1)
780 elts_head_next = (elts_head + 1) & (elts_n - 1);
781 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
782 dseg = &wqe->wqe.dseg;
783 tx_prefetch_wqe(txq, txq->wqe_ci);
784 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
786 rte_prefetch0(*pkts);
787 /* Should we enable HW CKSUM offload */
789 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
790 wqe->inl.eseg.cs_flags =
791 MLX5_ETH_WQE_L3_CSUM |
792 MLX5_ETH_WQE_L4_CSUM;
794 wqe->inl.eseg.cs_flags = 0;
796 /* Retrieve buffer information. */
797 addr = rte_pktmbuf_mtod(buf, uintptr_t);
798 length = DATA_LEN(buf);
799 /* Update element. */
800 (*txq->elts)[elts_head] = buf;
801 /* Prefetch next buffer data. */
803 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
805 if ((length <= max_inline) && (segs_n == 1)) {
806 if (buf->ol_flags & PKT_TX_VLAN_PKT)
807 mlx5_wqe_write_inline_vlan(txq, wqe,
811 mlx5_wqe_write_inline(txq, wqe, addr, length);
814 /* Retrieve Memory Region key for this memory pool. */
815 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
816 if (buf->ol_flags & PKT_TX_VLAN_PKT)
817 mlx5_wqe_write_vlan(txq, wqe, addr, length,
818 lkey, buf->vlan_tci);
820 mlx5_wqe_write(txq, wqe, addr, length, lkey);
824 * Spill on next WQE when the current one does not have
825 * enough room left. Size of WQE must a be a multiple
826 * of data segment size.
828 assert(!(sizeof(*wqe) % sizeof(*dseg)));
829 if (!(ds % (sizeof(*wqe) / 16)))
830 dseg = (volatile void *)
831 &(*txq->wqes)[txq->wqe_ci++ &
838 /* Store segment information. */
839 dseg->byte_count = htonl(DATA_LEN(buf));
840 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
841 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
842 (*txq->elts)[elts_head_next] = buf;
843 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
844 #ifdef MLX5_PMD_SOFT_COUNTERS
845 length += DATA_LEN(buf);
849 /* Update DS field in WQE. */
850 wqe->inl.ctrl.data[1] &= htonl(0xffffffc0);
851 wqe->inl.ctrl.data[1] |= htonl(ds & 0x3f);
853 elts_head = elts_head_next;
854 #ifdef MLX5_PMD_SOFT_COUNTERS
855 /* Increment sent bytes counter. */
856 txq->stats.obytes += length;
860 /* Take a shortcut if nothing must be sent. */
861 if (unlikely(i == 0))
863 /* Check whether completion threshold has been reached. */
864 comp = txq->elts_comp + i + j;
865 if (comp >= MLX5_TX_COMP_THRESH) {
866 /* Request completion on last WQE. */
867 wqe->inl.ctrl.data[2] = htonl(8);
868 /* Save elts_head in unused "immediate" field of WQE. */
869 wqe->inl.ctrl.data[3] = elts_head;
872 txq->elts_comp = comp;
874 #ifdef MLX5_PMD_SOFT_COUNTERS
875 /* Increment sent packets counter. */
876 txq->stats.opackets += i;
878 /* Ring QP doorbell. */
880 txq->elts_head = elts_head;
885 * Open a MPW session.
888 * Pointer to TX queue structure.
890 * Pointer to MPW session structure.
895 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
897 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
898 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
899 (volatile struct mlx5_wqe_data_seg (*)[])
900 (uintptr_t)&(*txq->wqes)[(idx + 1) & (txq->wqe_n - 1)];
902 mpw->state = MLX5_MPW_STATE_OPENED;
906 mpw->wqe = &(*txq->wqes)[idx];
907 mpw->wqe->mpw.eseg.mss = htons(length);
908 mpw->wqe->mpw.eseg.inline_hdr_sz = 0;
909 mpw->wqe->mpw.eseg.rsvd0 = 0;
910 mpw->wqe->mpw.eseg.rsvd1 = 0;
911 mpw->wqe->mpw.eseg.rsvd2 = 0;
912 mpw->wqe->mpw.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
914 MLX5_OPCODE_LSO_MPW);
915 mpw->wqe->mpw.ctrl.data[2] = 0;
916 mpw->wqe->mpw.ctrl.data[3] = 0;
917 mpw->data.dseg[0] = &mpw->wqe->mpw.dseg[0];
918 mpw->data.dseg[1] = &mpw->wqe->mpw.dseg[1];
919 mpw->data.dseg[2] = &(*dseg)[0];
920 mpw->data.dseg[3] = &(*dseg)[1];
921 mpw->data.dseg[4] = &(*dseg)[2];
925 * Close a MPW session.
928 * Pointer to TX queue structure.
930 * Pointer to MPW session structure.
933 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
935 unsigned int num = mpw->pkts_n;
938 * Store size in multiple of 16 bytes. Control and Ethernet segments
941 mpw->wqe->mpw.ctrl.data[1] = htonl(txq->qp_num_8s | (2 + num));
942 mpw->state = MLX5_MPW_STATE_CLOSED;
947 tx_prefetch_wqe(txq, txq->wqe_ci);
948 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
952 * DPDK callback for TX with MPW support.
955 * Generic pointer to TX queue structure.
957 * Packets to transmit.
959 * Number of packets in array.
962 * Number of packets successfully transmitted (<= pkts_n).
965 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
967 struct txq *txq = (struct txq *)dpdk_txq;
968 uint16_t elts_head = txq->elts_head;
969 const unsigned int elts_n = txq->elts_n;
974 struct mlx5_mpw mpw = {
975 .state = MLX5_MPW_STATE_CLOSED,
978 if (unlikely(!pkts_n))
980 /* Prefetch first packet cacheline. */
981 tx_prefetch_cqe(txq, txq->cq_ci);
982 tx_prefetch_wqe(txq, txq->wqe_ci);
983 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
984 /* Start processing. */
986 max = (elts_n - (elts_head - txq->elts_tail));
990 struct rte_mbuf *buf = *(pkts++);
991 unsigned int elts_head_next;
993 unsigned int segs_n = buf->nb_segs;
994 uint32_t cs_flags = 0;
997 * Make sure there is enough room to store this packet and
998 * that one ring entry remains unused.
1001 if (max < segs_n + 1)
1003 /* Do not bother with large packets MPW cannot handle. */
1004 if (segs_n > MLX5_MPW_DSEG_MAX)
1008 /* Should we enable HW CKSUM offload */
1010 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1011 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1012 /* Retrieve packet information. */
1013 length = PKT_LEN(buf);
1015 /* Start new session if packet differs. */
1016 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1017 ((mpw.len != length) ||
1019 (mpw.wqe->mpw.eseg.cs_flags != cs_flags)))
1020 mlx5_mpw_close(txq, &mpw);
1021 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1022 mlx5_mpw_new(txq, &mpw, length);
1023 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
1025 /* Multi-segment packets must be alone in their MPW. */
1026 assert((segs_n == 1) || (mpw.pkts_n == 0));
1027 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1031 volatile struct mlx5_wqe_data_seg *dseg;
1034 elts_head_next = (elts_head + 1) & (elts_n - 1);
1036 (*txq->elts)[elts_head] = buf;
1037 dseg = mpw.data.dseg[mpw.pkts_n];
1038 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1039 *dseg = (struct mlx5_wqe_data_seg){
1040 .byte_count = htonl(DATA_LEN(buf)),
1041 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1042 .addr = htonll(addr),
1044 elts_head = elts_head_next;
1045 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1046 length += DATA_LEN(buf);
1052 assert(length == mpw.len);
1053 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1054 mlx5_mpw_close(txq, &mpw);
1055 elts_head = elts_head_next;
1056 #ifdef MLX5_PMD_SOFT_COUNTERS
1057 /* Increment sent bytes counter. */
1058 txq->stats.obytes += length;
1062 /* Take a shortcut if nothing must be sent. */
1063 if (unlikely(i == 0))
1065 /* Check whether completion threshold has been reached. */
1066 /* "j" includes both packets and segments. */
1067 comp = txq->elts_comp + j;
1068 if (comp >= MLX5_TX_COMP_THRESH) {
1069 volatile union mlx5_wqe *wqe = mpw.wqe;
1071 /* Request completion on last WQE. */
1072 wqe->mpw.ctrl.data[2] = htonl(8);
1073 /* Save elts_head in unused "immediate" field of WQE. */
1074 wqe->mpw.ctrl.data[3] = elts_head;
1077 txq->elts_comp = comp;
1079 #ifdef MLX5_PMD_SOFT_COUNTERS
1080 /* Increment sent packets counter. */
1081 txq->stats.opackets += i;
1083 /* Ring QP doorbell. */
1084 if (mpw.state == MLX5_MPW_STATE_OPENED)
1085 mlx5_mpw_close(txq, &mpw);
1087 txq->elts_head = elts_head;
1092 * Open a MPW inline session.
1095 * Pointer to TX queue structure.
1097 * Pointer to MPW session structure.
1102 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1104 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
1106 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1110 mpw->wqe = &(*txq->wqes)[idx];
1111 mpw->wqe->mpw_inl.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1112 (txq->wqe_ci << 8) |
1113 MLX5_OPCODE_LSO_MPW);
1114 mpw->wqe->mpw_inl.ctrl.data[2] = 0;
1115 mpw->wqe->mpw_inl.ctrl.data[3] = 0;
1116 mpw->wqe->mpw_inl.eseg.mss = htons(length);
1117 mpw->wqe->mpw_inl.eseg.inline_hdr_sz = 0;
1118 mpw->wqe->mpw_inl.eseg.cs_flags = 0;
1119 mpw->wqe->mpw_inl.eseg.rsvd0 = 0;
1120 mpw->wqe->mpw_inl.eseg.rsvd1 = 0;
1121 mpw->wqe->mpw_inl.eseg.rsvd2 = 0;
1122 mpw->data.raw = &mpw->wqe->mpw_inl.data[0];
1126 * Close a MPW inline session.
1129 * Pointer to TX queue structure.
1131 * Pointer to MPW session structure.
1134 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1138 size = sizeof(*mpw->wqe) - MLX5_MWQE64_INL_DATA + mpw->total_len;
1140 * Store size in multiple of 16 bytes. Control and Ethernet segments
1143 mpw->wqe->mpw_inl.ctrl.data[1] =
1144 htonl(txq->qp_num_8s | ((size + 15) / 16));
1145 mpw->state = MLX5_MPW_STATE_CLOSED;
1146 mpw->wqe->mpw_inl.byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1147 txq->wqe_ci += (size + (sizeof(*mpw->wqe) - 1)) / sizeof(*mpw->wqe);
1151 * DPDK callback for TX with MPW inline support.
1154 * Generic pointer to TX queue structure.
1156 * Packets to transmit.
1158 * Number of packets in array.
1161 * Number of packets successfully transmitted (<= pkts_n).
1164 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1167 struct txq *txq = (struct txq *)dpdk_txq;
1168 uint16_t elts_head = txq->elts_head;
1169 const unsigned int elts_n = txq->elts_n;
1174 unsigned int inline_room = txq->max_inline;
1175 struct mlx5_mpw mpw = {
1176 .state = MLX5_MPW_STATE_CLOSED,
1179 if (unlikely(!pkts_n))
1181 /* Prefetch first packet cacheline. */
1182 tx_prefetch_cqe(txq, txq->cq_ci);
1183 tx_prefetch_wqe(txq, txq->wqe_ci);
1184 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
1185 /* Start processing. */
1187 max = (elts_n - (elts_head - txq->elts_tail));
1191 struct rte_mbuf *buf = *(pkts++);
1192 unsigned int elts_head_next;
1195 unsigned int segs_n = buf->nb_segs;
1196 uint32_t cs_flags = 0;
1199 * Make sure there is enough room to store this packet and
1200 * that one ring entry remains unused.
1203 if (max < segs_n + 1)
1205 /* Do not bother with large packets MPW cannot handle. */
1206 if (segs_n > MLX5_MPW_DSEG_MAX)
1210 /* Should we enable HW CKSUM offload */
1212 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1213 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1214 /* Retrieve packet information. */
1215 length = PKT_LEN(buf);
1216 /* Start new session if packet differs. */
1217 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1218 if ((mpw.len != length) ||
1220 (mpw.wqe->mpw.eseg.cs_flags != cs_flags))
1221 mlx5_mpw_close(txq, &mpw);
1222 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1223 if ((mpw.len != length) ||
1225 (length > inline_room) ||
1226 (mpw.wqe->mpw_inl.eseg.cs_flags != cs_flags)) {
1227 mlx5_mpw_inline_close(txq, &mpw);
1228 inline_room = txq->max_inline;
1231 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1232 if ((segs_n != 1) ||
1233 (length > inline_room)) {
1234 mlx5_mpw_new(txq, &mpw, length);
1235 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
1237 mlx5_mpw_inline_new(txq, &mpw, length);
1238 mpw.wqe->mpw_inl.eseg.cs_flags = cs_flags;
1241 /* Multi-segment packets must be alone in their MPW. */
1242 assert((segs_n == 1) || (mpw.pkts_n == 0));
1243 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1244 assert(inline_room == txq->max_inline);
1245 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1249 volatile struct mlx5_wqe_data_seg *dseg;
1252 (elts_head + 1) & (elts_n - 1);
1254 (*txq->elts)[elts_head] = buf;
1255 dseg = mpw.data.dseg[mpw.pkts_n];
1256 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1257 *dseg = (struct mlx5_wqe_data_seg){
1258 .byte_count = htonl(DATA_LEN(buf)),
1259 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1260 .addr = htonll(addr),
1262 elts_head = elts_head_next;
1263 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1264 length += DATA_LEN(buf);
1270 assert(length == mpw.len);
1271 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1272 mlx5_mpw_close(txq, &mpw);
1276 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1277 assert(length <= inline_room);
1278 assert(length == DATA_LEN(buf));
1279 elts_head_next = (elts_head + 1) & (elts_n - 1);
1280 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1281 (*txq->elts)[elts_head] = buf;
1282 /* Maximum number of bytes before wrapping. */
1283 max = ((uintptr_t)&(*txq->wqes)[txq->wqe_n] -
1284 (uintptr_t)mpw.data.raw);
1286 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1290 (volatile void *)&(*txq->wqes)[0];
1291 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1292 (void *)(addr + max),
1294 mpw.data.raw += length - max;
1296 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1299 mpw.data.raw += length;
1301 if ((uintptr_t)mpw.data.raw ==
1302 (uintptr_t)&(*txq->wqes)[txq->wqe_n])
1304 (volatile void *)&(*txq->wqes)[0];
1307 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1308 mlx5_mpw_inline_close(txq, &mpw);
1309 inline_room = txq->max_inline;
1311 inline_room -= length;
1314 mpw.total_len += length;
1315 elts_head = elts_head_next;
1316 #ifdef MLX5_PMD_SOFT_COUNTERS
1317 /* Increment sent bytes counter. */
1318 txq->stats.obytes += length;
1322 /* Take a shortcut if nothing must be sent. */
1323 if (unlikely(i == 0))
1325 /* Check whether completion threshold has been reached. */
1326 /* "j" includes both packets and segments. */
1327 comp = txq->elts_comp + j;
1328 if (comp >= MLX5_TX_COMP_THRESH) {
1329 volatile union mlx5_wqe *wqe = mpw.wqe;
1331 /* Request completion on last WQE. */
1332 wqe->mpw_inl.ctrl.data[2] = htonl(8);
1333 /* Save elts_head in unused "immediate" field of WQE. */
1334 wqe->mpw_inl.ctrl.data[3] = elts_head;
1337 txq->elts_comp = comp;
1339 #ifdef MLX5_PMD_SOFT_COUNTERS
1340 /* Increment sent packets counter. */
1341 txq->stats.opackets += i;
1343 /* Ring QP doorbell. */
1344 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1345 mlx5_mpw_inline_close(txq, &mpw);
1346 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1347 mlx5_mpw_close(txq, &mpw);
1349 txq->elts_head = elts_head;
1354 * Translate RX completion flags to packet type.
1359 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1362 * Packet type for struct rte_mbuf.
1364 static inline uint32_t
1365 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
1368 uint8_t flags = cqe->l4_hdr_type_etc;
1369 uint8_t info = cqe->rsvd0[0];
1371 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
1374 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
1375 RTE_PTYPE_L3_IPV4) |
1377 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
1378 RTE_PTYPE_L3_IPV6) |
1380 IBV_EXP_CQ_RX_IPV4_PACKET,
1381 RTE_PTYPE_INNER_L3_IPV4) |
1383 IBV_EXP_CQ_RX_IPV6_PACKET,
1384 RTE_PTYPE_INNER_L3_IPV6);
1388 MLX5_CQE_L3_HDR_TYPE_IPV6,
1389 RTE_PTYPE_L3_IPV6) |
1391 MLX5_CQE_L3_HDR_TYPE_IPV4,
1397 * Get size of the next packet for a given CQE. For compressed CQEs, the
1398 * consumer index is updated only once all packets of the current one have
1402 * Pointer to RX queue.
1407 * Packet size in bytes (0 if there is none), -1 in case of completion
1411 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
1414 struct rxq_zip *zip = &rxq->zip;
1415 uint16_t cqe_n = cqe_cnt + 1;
1418 /* Process compressed data in the CQE and mini arrays. */
1420 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1421 (volatile struct mlx5_mini_cqe8 (*)[8])
1422 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
1424 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1425 if ((++zip->ai & 7) == 0) {
1427 * Increment consumer index to skip the number of
1428 * CQEs consumed. Hardware leaves holes in the CQ
1429 * ring for software use.
1434 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1435 uint16_t idx = rxq->cq_ci;
1436 uint16_t end = zip->cq_ci;
1438 while (idx != end) {
1439 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
1440 MLX5_CQE_INVALIDATE;
1443 rxq->cq_ci = zip->cq_ci;
1446 /* No compressed data, get next CQE and verify if it is compressed. */
1451 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
1452 if (unlikely(ret == 1))
1455 op_own = cqe->op_own;
1456 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1457 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1458 (volatile struct mlx5_mini_cqe8 (*)[8])
1459 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1462 /* Fix endianness. */
1463 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1465 * Current mini array position is the one returned by
1468 * If completion comprises several mini arrays, as a
1469 * special case the second one is located 7 CQEs after
1470 * the initial CQE instead of 8 for subsequent ones.
1472 zip->ca = rxq->cq_ci & cqe_cnt;
1473 zip->na = zip->ca + 7;
1474 /* Compute the next non compressed CQE. */
1476 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1477 /* Get packet size to return. */
1478 len = ntohl((*mc)[0].byte_cnt);
1481 len = ntohl(cqe->byte_cnt);
1483 /* Error while receiving packet. */
1484 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1491 * Translate RX completion flags to offload flags.
1494 * Pointer to RX queue structure.
1499 * Offload flags (ol_flags) for struct rte_mbuf.
1501 static inline uint32_t
1502 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
1504 uint32_t ol_flags = 0;
1505 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1506 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1507 uint8_t info = cqe->rsvd0[0];
1509 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1510 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1512 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
1513 PKT_RX_IP_CKSUM_BAD);
1514 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1515 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1516 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1517 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1519 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
1520 PKT_RX_L4_CKSUM_BAD);
1522 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
1523 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
1526 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1528 TRANSPOSE(~cqe->l4_hdr_type_etc,
1529 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
1530 PKT_RX_IP_CKSUM_BAD) |
1531 TRANSPOSE(~cqe->l4_hdr_type_etc,
1532 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
1533 PKT_RX_L4_CKSUM_BAD);
1538 * DPDK callback for RX.
1541 * Generic pointer to RX queue structure.
1543 * Array to store received packets.
1545 * Maximum number of packets in array.
1548 * Number of packets successfully received (<= pkts_n).
1551 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1553 struct rxq *rxq = dpdk_rxq;
1554 const unsigned int wqe_cnt = rxq->elts_n - 1;
1555 const unsigned int cqe_cnt = rxq->cqe_n - 1;
1556 const unsigned int sges_n = rxq->sges_n;
1557 struct rte_mbuf *pkt = NULL;
1558 struct rte_mbuf *seg = NULL;
1559 volatile struct mlx5_cqe64 *cqe =
1560 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1562 unsigned int rq_ci = rxq->rq_ci << sges_n;
1566 unsigned int idx = rq_ci & wqe_cnt;
1567 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1568 struct rte_mbuf *rep = (*rxq->elts)[idx];
1576 rep = rte_mbuf_raw_alloc(rxq->mp);
1577 if (unlikely(rep == NULL)) {
1578 ++rxq->stats.rx_nombuf;
1581 * no buffers before we even started,
1582 * bail out silently.
1586 while (pkt != seg) {
1587 assert(pkt != (*rxq->elts)[idx]);
1589 rte_mbuf_refcnt_set(pkt, 0);
1590 __rte_mbuf_raw_free(pkt);
1596 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1597 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1599 rte_mbuf_refcnt_set(rep, 0);
1600 __rte_mbuf_raw_free(rep);
1603 if (unlikely(len == -1)) {
1604 /* RX error, packet is likely too large. */
1605 rte_mbuf_refcnt_set(rep, 0);
1606 __rte_mbuf_raw_free(rep);
1607 ++rxq->stats.idropped;
1611 assert(len >= (rxq->crc_present << 2));
1612 /* Update packet information. */
1613 pkt->packet_type = 0;
1615 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1619 rxq_cq_to_pkt_type(cqe);
1621 rxq_cq_to_ol_flags(rxq, cqe);
1623 if (cqe->l4_hdr_type_etc &
1624 MLX5_CQE_VLAN_STRIPPED) {
1625 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1626 PKT_RX_VLAN_STRIPPED;
1627 pkt->vlan_tci = ntohs(cqe->vlan_info);
1629 if (rxq->crc_present)
1630 len -= ETHER_CRC_LEN;
1634 DATA_LEN(rep) = DATA_LEN(seg);
1635 PKT_LEN(rep) = PKT_LEN(seg);
1636 SET_DATA_OFF(rep, DATA_OFF(seg));
1637 NB_SEGS(rep) = NB_SEGS(seg);
1638 PORT(rep) = PORT(seg);
1640 (*rxq->elts)[idx] = rep;
1642 * Fill NIC descriptor with the new buffer. The lkey and size
1643 * of the buffers are already known, only the buffer address
1646 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1647 if (len > DATA_LEN(seg)) {
1648 len -= DATA_LEN(seg);
1653 DATA_LEN(seg) = len;
1654 #ifdef MLX5_PMD_SOFT_COUNTERS
1655 /* Increment bytes counter. */
1656 rxq->stats.ibytes += PKT_LEN(pkt);
1658 /* Return packet. */
1664 /* Align consumer index to the next stride. */
1669 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1671 /* Update the consumer index. */
1672 rxq->rq_ci = rq_ci >> sges_n;
1674 *rxq->cq_db = htonl(rxq->cq_ci);
1676 *rxq->rq_db = htonl(rxq->rq_ci);
1677 #ifdef MLX5_PMD_SOFT_COUNTERS
1678 /* Increment packets counter. */
1679 rxq->stats.ipackets += i;
1685 * Dummy DPDK callback for TX.
1687 * This function is used to temporarily replace the real callback during
1688 * unsafe control operations on the queue, or in case of error.
1691 * Generic pointer to TX queue structure.
1693 * Packets to transmit.
1695 * Number of packets in array.
1698 * Number of packets successfully transmitted (<= pkts_n).
1701 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1710 * Dummy DPDK callback for RX.
1712 * This function is used to temporarily replace the real callback during
1713 * unsafe control operations on the queue, or in case of error.
1716 * Generic pointer to RX queue structure.
1718 * Array to store received packets.
1720 * Maximum number of packets in array.
1723 * Number of packets successfully received (<= pkts_n).
1726 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)