4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Return the size of tailroom of WQ.
201 * Pointer to TX queue structure.
203 * Pointer to tail of WQ.
209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
212 tailroom = (uintptr_t)(txq->wqes) +
213 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
219 * Copy data to tailroom of circular queue.
222 * Pointer to destination.
226 * Number of bytes to copy.
228 * Pointer to head of queue.
230 * Size of tailroom from dst.
233 * Pointer after copied data.
236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
237 void *base, size_t tailroom)
242 rte_memcpy(dst, src, tailroom);
243 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
245 ret = (uint8_t *)base + n - tailroom;
247 rte_memcpy(dst, src, n);
248 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
254 * Manage TX completions.
256 * When sending a burst, mlx5_tx_burst() posts several WRs.
259 * Pointer to TX queue structure.
262 txq_complete(struct txq *txq)
264 const unsigned int elts_n = 1 << txq->elts_n;
265 const unsigned int cqe_n = 1 << txq->cqe_n;
266 const unsigned int cqe_cnt = cqe_n - 1;
267 uint16_t elts_free = txq->elts_tail;
269 uint16_t cq_ci = txq->cq_ci;
270 volatile struct mlx5_cqe *cqe = NULL;
271 volatile struct mlx5_wqe_ctrl *ctrl;
274 volatile struct mlx5_cqe *tmp;
276 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
277 if (check_cqe(tmp, cqe_n, cq_ci))
281 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
282 if (!check_cqe_seen(cqe))
283 ERROR("unexpected compressed CQE, TX stopped");
286 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
287 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
288 if (!check_cqe_seen(cqe))
289 ERROR("unexpected error CQE, TX stopped");
295 if (unlikely(cqe == NULL))
297 txq->wqe_pi = ntohs(cqe->wqe_counter);
298 ctrl = (volatile struct mlx5_wqe_ctrl *)
299 tx_mlx5_wqe(txq, txq->wqe_pi);
300 elts_tail = ctrl->ctrl3;
301 assert(elts_tail < (1 << txq->wqe_n));
303 while (elts_free != elts_tail) {
304 struct rte_mbuf *elt = (*txq->elts)[elts_free];
305 unsigned int elts_free_next =
306 (elts_free + 1) & (elts_n - 1);
307 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
311 memset(&(*txq->elts)[elts_free],
313 sizeof((*txq->elts)[elts_free]));
315 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
316 /* Only one segment needs to be freed. */
317 rte_pktmbuf_free_seg(elt);
318 elts_free = elts_free_next;
321 txq->elts_tail = elts_tail;
322 /* Update the consumer index. */
324 *txq->cq_db = htonl(cq_ci);
328 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
329 * the cloned mbuf is allocated is returned instead.
335 * Memory pool where data is located for given mbuf.
337 static struct rte_mempool *
338 txq_mb2mp(struct rte_mbuf *buf)
340 if (unlikely(RTE_MBUF_INDIRECT(buf)))
341 return rte_mbuf_from_indirect(buf)->pool;
346 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
347 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
348 * remove an entry first.
351 * Pointer to TX queue structure.
353 * Memory Pool for which a Memory Region lkey must be returned.
356 * mr->lkey on success, (uint32_t)-1 on failure.
358 static inline uint32_t
359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
362 uint32_t lkey = (uint32_t)-1;
364 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
365 if (unlikely(txq->mp2mr[i].mp == NULL)) {
366 /* Unknown MP, add a new MR for it. */
369 if (txq->mp2mr[i].mp == mp) {
370 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
371 assert(htonl(txq->mp2mr[i].mr->lkey) ==
373 lkey = txq->mp2mr[i].lkey;
377 if (unlikely(lkey == (uint32_t)-1))
378 lkey = txq_mp2mr_reg(txq, mp, i);
383 * Ring TX queue doorbell.
386 * Pointer to TX queue structure.
388 * Pointer to the last WQE posted in the NIC.
391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
393 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
394 volatile uint64_t *src = ((volatile uint64_t *)wqe);
397 *txq->qp_db = htonl(txq->wqe_ci);
398 /* Ensure ordering between DB record and BF copy. */
404 * DPDK callback to check the status of a tx descriptor.
409 * The index of the descriptor in the ring.
412 * The status of the tx descriptor.
415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
417 struct txq *txq = tx_queue;
418 const unsigned int elts_n = 1 << txq->elts_n;
419 const unsigned int elts_cnt = elts_n - 1;
423 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
425 return RTE_ETH_TX_DESC_FULL;
426 return RTE_ETH_TX_DESC_DONE;
430 * DPDK callback to check the status of a rx descriptor.
435 * The index of the descriptor in the ring.
438 * The status of the tx descriptor.
441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
443 struct rxq *rxq = rx_queue;
444 struct rxq_zip *zip = &rxq->zip;
445 volatile struct mlx5_cqe *cqe;
446 const unsigned int cqe_n = (1 << rxq->cqe_n);
447 const unsigned int cqe_cnt = cqe_n - 1;
451 /* if we are processing a compressed cqe */
453 used = zip->cqe_cnt - zip->ca;
459 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
460 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
464 op_own = cqe->op_own;
465 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
466 n = ntohl(cqe->byte_cnt);
471 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
473 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
475 return RTE_ETH_RX_DESC_DONE;
476 return RTE_ETH_RX_DESC_AVAIL;
480 * DPDK callback for TX.
483 * Generic pointer to TX queue structure.
485 * Packets to transmit.
487 * Number of packets in array.
490 * Number of packets successfully transmitted (<= pkts_n).
493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
495 struct txq *txq = (struct txq *)dpdk_txq;
496 uint16_t elts_head = txq->elts_head;
497 const unsigned int elts_n = 1 << txq->elts_n;
502 unsigned int max_inline = txq->max_inline;
503 const unsigned int inline_en = !!max_inline && txq->inline_en;
506 volatile struct mlx5_wqe_v *wqe = NULL;
507 unsigned int segs_n = 0;
508 struct rte_mbuf *buf = NULL;
511 if (unlikely(!pkts_n))
513 /* Prefetch first packet cacheline. */
514 rte_prefetch0(*pkts);
515 /* Start processing. */
517 max = (elts_n - (elts_head - txq->elts_tail));
520 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
521 if (unlikely(!max_wqe))
524 volatile rte_v128u32_t *dseg = NULL;
529 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
530 uint16_t tso_header_sz = 0;
532 uint8_t cs_flags = 0;
534 #ifdef MLX5_PMD_SOFT_COUNTERS
535 uint32_t total_length = 0;
540 segs_n = buf->nb_segs;
542 * Make sure there is enough room to store this packet and
543 * that one ring entry remains unused.
546 if (max < segs_n + 1)
552 if (unlikely(--max_wqe == 0))
554 wqe = (volatile struct mlx5_wqe_v *)
555 tx_mlx5_wqe(txq, txq->wqe_ci);
556 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
558 rte_prefetch0(*pkts);
559 addr = rte_pktmbuf_mtod(buf, uintptr_t);
560 length = DATA_LEN(buf);
561 ehdr = (((uint8_t *)addr)[1] << 8) |
562 ((uint8_t *)addr)[0];
563 #ifdef MLX5_PMD_SOFT_COUNTERS
564 total_length = length;
566 if (length < (MLX5_WQE_DWORD_SIZE + 2))
568 /* Update element. */
569 (*txq->elts)[elts_head] = buf;
570 elts_head = (elts_head + 1) & (elts_n - 1);
571 /* Prefetch next buffer data. */
573 volatile void *pkt_addr;
575 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
576 rte_prefetch0(pkt_addr);
578 /* Should we enable HW CKSUM offload */
580 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
581 const uint64_t is_tunneled = buf->ol_flags &
583 PKT_TX_TUNNEL_VXLAN);
585 if (is_tunneled && txq->tunnel_en) {
586 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
587 MLX5_ETH_WQE_L4_INNER_CSUM;
588 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
589 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
591 cs_flags = MLX5_ETH_WQE_L3_CSUM |
592 MLX5_ETH_WQE_L4_CSUM;
595 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
596 /* Replace the Ethernet type by the VLAN if necessary. */
597 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
598 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
599 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
603 /* Copy Destination and source mac address. */
604 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
606 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
607 /* Copy missing two bytes to end the DSeg. */
608 memcpy((uint8_t *)raw + len + sizeof(vlan),
609 ((uint8_t *)addr) + len, 2);
613 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
614 MLX5_WQE_DWORD_SIZE);
615 length -= pkt_inline_sz;
616 addr += pkt_inline_sz;
619 tso = buf->ol_flags & PKT_TX_TCP_SEG;
621 uintptr_t end = (uintptr_t)
622 (((uintptr_t)txq->wqes) +
626 uint8_t vlan_sz = (buf->ol_flags &
627 PKT_TX_VLAN_PKT) ? 4 : 0;
628 const uint64_t is_tunneled =
631 PKT_TX_TUNNEL_VXLAN);
633 tso_header_sz = buf->l2_len + vlan_sz +
634 buf->l3_len + buf->l4_len;
636 if (is_tunneled && txq->tunnel_en) {
637 tso_header_sz += buf->outer_l2_len +
639 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
641 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
643 if (unlikely(tso_header_sz >
644 MLX5_MAX_TSO_HEADER))
646 copy_b = tso_header_sz - pkt_inline_sz;
647 /* First seg must contain all headers. */
648 assert(copy_b <= length);
649 raw += MLX5_WQE_DWORD_SIZE;
651 ((end - (uintptr_t)raw) > copy_b)) {
652 uint16_t n = (MLX5_WQE_DS(copy_b) -
655 if (unlikely(max_wqe < n))
658 rte_memcpy((void *)raw,
659 (void *)addr, copy_b);
662 pkt_inline_sz += copy_b;
664 * Another DWORD will be added
665 * in the inline part.
667 raw += MLX5_WQE_DS(copy_b) *
668 MLX5_WQE_DWORD_SIZE -
672 wqe->ctrl = (rte_v128u32_t){
673 htonl(txq->wqe_ci << 8),
674 htonl(txq->qp_num_8s | 1),
682 elts_head = (elts_head - 1) &
689 /* Inline if enough room. */
690 if (inline_en || tso) {
691 uintptr_t end = (uintptr_t)
692 (((uintptr_t)txq->wqes) +
693 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
694 unsigned int inline_room = max_inline *
695 RTE_CACHE_LINE_SIZE -
697 uintptr_t addr_end = (addr + inline_room) &
698 ~(RTE_CACHE_LINE_SIZE - 1);
699 unsigned int copy_b = (addr_end > addr) ?
700 RTE_MIN((addr_end - addr), length) :
703 raw += MLX5_WQE_DWORD_SIZE;
704 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
706 * One Dseg remains in the current WQE. To
707 * keep the computation positive, it is
708 * removed after the bytes to Dseg conversion.
710 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
712 if (unlikely(max_wqe < n))
717 htonl(copy_b | MLX5_INLINE_SEG);
720 MLX5_WQE_DS(tso_header_sz) *
722 rte_memcpy((void *)raw,
723 (void *)&inl, sizeof(inl));
725 pkt_inline_sz += sizeof(inl);
727 rte_memcpy((void *)raw, (void *)addr, copy_b);
730 pkt_inline_sz += copy_b;
733 * 2 DWORDs consumed by the WQE header + ETH segment +
734 * the size of the inline part of the packet.
736 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
738 if (ds % (MLX5_WQE_SIZE /
739 MLX5_WQE_DWORD_SIZE) == 0) {
740 if (unlikely(--max_wqe == 0))
742 dseg = (volatile rte_v128u32_t *)
743 tx_mlx5_wqe(txq, txq->wqe_ci +
746 dseg = (volatile rte_v128u32_t *)
748 (ds * MLX5_WQE_DWORD_SIZE));
751 } else if (!segs_n) {
754 /* dseg will be advance as part of next_seg */
755 dseg = (volatile rte_v128u32_t *)
757 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
762 * No inline has been done in the packet, only the
763 * Ethernet Header as been stored.
765 dseg = (volatile rte_v128u32_t *)
766 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
769 /* Add the remaining packet as a simple ds. */
770 naddr = htonll(addr);
771 *dseg = (rte_v128u32_t){
773 txq_mp2mr(txq, txq_mb2mp(buf)),
786 * Spill on next WQE when the current one does not have
787 * enough room left. Size of WQE must a be a multiple
788 * of data segment size.
790 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
791 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
792 if (unlikely(--max_wqe == 0))
794 dseg = (volatile rte_v128u32_t *)
795 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
796 rte_prefetch0(tx_mlx5_wqe(txq,
797 txq->wqe_ci + ds / 4 + 1));
804 length = DATA_LEN(buf);
805 #ifdef MLX5_PMD_SOFT_COUNTERS
806 total_length += length;
808 /* Store segment information. */
809 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
810 *dseg = (rte_v128u32_t){
812 txq_mp2mr(txq, txq_mb2mp(buf)),
816 (*txq->elts)[elts_head] = buf;
817 elts_head = (elts_head + 1) & (elts_n - 1);
826 /* Initialize known and common part of the WQE structure. */
828 wqe->ctrl = (rte_v128u32_t){
829 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
830 htonl(txq->qp_num_8s | ds),
834 wqe->eseg = (rte_v128u32_t){
836 cs_flags | (htons(buf->tso_segsz) << 16),
838 (ehdr << 16) | htons(tso_header_sz),
841 wqe->ctrl = (rte_v128u32_t){
842 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
843 htonl(txq->qp_num_8s | ds),
847 wqe->eseg = (rte_v128u32_t){
851 (ehdr << 16) | htons(pkt_inline_sz),
855 txq->wqe_ci += (ds + 3) / 4;
856 #ifdef MLX5_PMD_SOFT_COUNTERS
857 /* Increment sent bytes counter. */
858 txq->stats.obytes += total_length;
861 /* Take a shortcut if nothing must be sent. */
862 if (unlikely((i + k) == 0))
864 /* Check whether completion threshold has been reached. */
865 comp = txq->elts_comp + i + j + k;
866 if (comp >= MLX5_TX_COMP_THRESH) {
867 volatile struct mlx5_wqe_ctrl *w =
868 (volatile struct mlx5_wqe_ctrl *)wqe;
870 /* Request completion on last WQE. */
872 /* Save elts_head in unused "immediate" field of WQE. */
873 w->ctrl3 = elts_head;
876 txq->elts_comp = comp;
878 #ifdef MLX5_PMD_SOFT_COUNTERS
879 /* Increment sent packets counter. */
880 txq->stats.opackets += i;
882 /* Ring QP doorbell. */
883 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
884 txq->elts_head = elts_head;
889 * Open a MPW session.
892 * Pointer to TX queue structure.
894 * Pointer to MPW session structure.
899 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
901 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
902 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
903 (volatile struct mlx5_wqe_data_seg (*)[])
904 tx_mlx5_wqe(txq, idx + 1);
906 mpw->state = MLX5_MPW_STATE_OPENED;
910 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
911 mpw->wqe->eseg.mss = htons(length);
912 mpw->wqe->eseg.inline_hdr_sz = 0;
913 mpw->wqe->eseg.rsvd0 = 0;
914 mpw->wqe->eseg.rsvd1 = 0;
915 mpw->wqe->eseg.rsvd2 = 0;
916 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
917 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
918 mpw->wqe->ctrl[2] = 0;
919 mpw->wqe->ctrl[3] = 0;
920 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
921 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
922 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
923 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
924 mpw->data.dseg[2] = &(*dseg)[0];
925 mpw->data.dseg[3] = &(*dseg)[1];
926 mpw->data.dseg[4] = &(*dseg)[2];
930 * Close a MPW session.
933 * Pointer to TX queue structure.
935 * Pointer to MPW session structure.
938 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
940 unsigned int num = mpw->pkts_n;
943 * Store size in multiple of 16 bytes. Control and Ethernet segments
946 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
947 mpw->state = MLX5_MPW_STATE_CLOSED;
952 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
953 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
957 * DPDK callback for TX with MPW support.
960 * Generic pointer to TX queue structure.
962 * Packets to transmit.
964 * Number of packets in array.
967 * Number of packets successfully transmitted (<= pkts_n).
970 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
972 struct txq *txq = (struct txq *)dpdk_txq;
973 uint16_t elts_head = txq->elts_head;
974 const unsigned int elts_n = 1 << txq->elts_n;
980 struct mlx5_mpw mpw = {
981 .state = MLX5_MPW_STATE_CLOSED,
984 if (unlikely(!pkts_n))
986 /* Prefetch first packet cacheline. */
987 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
988 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
989 /* Start processing. */
991 max = (elts_n - (elts_head - txq->elts_tail));
994 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
995 if (unlikely(!max_wqe))
998 struct rte_mbuf *buf = *(pkts++);
999 unsigned int elts_head_next;
1001 unsigned int segs_n = buf->nb_segs;
1002 uint32_t cs_flags = 0;
1005 * Make sure there is enough room to store this packet and
1006 * that one ring entry remains unused.
1009 if (max < segs_n + 1)
1011 /* Do not bother with large packets MPW cannot handle. */
1012 if (segs_n > MLX5_MPW_DSEG_MAX)
1016 /* Should we enable HW CKSUM offload */
1018 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1019 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1020 /* Retrieve packet information. */
1021 length = PKT_LEN(buf);
1023 /* Start new session if packet differs. */
1024 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1025 ((mpw.len != length) ||
1027 (mpw.wqe->eseg.cs_flags != cs_flags)))
1028 mlx5_mpw_close(txq, &mpw);
1029 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1031 * Multi-Packet WQE consumes at most two WQE.
1032 * mlx5_mpw_new() expects to be able to use such
1035 if (unlikely(max_wqe < 2))
1038 mlx5_mpw_new(txq, &mpw, length);
1039 mpw.wqe->eseg.cs_flags = cs_flags;
1041 /* Multi-segment packets must be alone in their MPW. */
1042 assert((segs_n == 1) || (mpw.pkts_n == 0));
1043 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1047 volatile struct mlx5_wqe_data_seg *dseg;
1050 elts_head_next = (elts_head + 1) & (elts_n - 1);
1052 (*txq->elts)[elts_head] = buf;
1053 dseg = mpw.data.dseg[mpw.pkts_n];
1054 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1055 *dseg = (struct mlx5_wqe_data_seg){
1056 .byte_count = htonl(DATA_LEN(buf)),
1057 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1058 .addr = htonll(addr),
1060 elts_head = elts_head_next;
1061 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1062 length += DATA_LEN(buf);
1068 assert(length == mpw.len);
1069 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1070 mlx5_mpw_close(txq, &mpw);
1071 elts_head = elts_head_next;
1072 #ifdef MLX5_PMD_SOFT_COUNTERS
1073 /* Increment sent bytes counter. */
1074 txq->stats.obytes += length;
1078 /* Take a shortcut if nothing must be sent. */
1079 if (unlikely(i == 0))
1081 /* Check whether completion threshold has been reached. */
1082 /* "j" includes both packets and segments. */
1083 comp = txq->elts_comp + j;
1084 if (comp >= MLX5_TX_COMP_THRESH) {
1085 volatile struct mlx5_wqe *wqe = mpw.wqe;
1087 /* Request completion on last WQE. */
1088 wqe->ctrl[2] = htonl(8);
1089 /* Save elts_head in unused "immediate" field of WQE. */
1090 wqe->ctrl[3] = elts_head;
1093 txq->elts_comp = comp;
1095 #ifdef MLX5_PMD_SOFT_COUNTERS
1096 /* Increment sent packets counter. */
1097 txq->stats.opackets += i;
1099 /* Ring QP doorbell. */
1100 if (mpw.state == MLX5_MPW_STATE_OPENED)
1101 mlx5_mpw_close(txq, &mpw);
1102 mlx5_tx_dbrec(txq, mpw.wqe);
1103 txq->elts_head = elts_head;
1108 * Open a MPW inline session.
1111 * Pointer to TX queue structure.
1113 * Pointer to MPW session structure.
1118 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1120 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1121 struct mlx5_wqe_inl_small *inl;
1123 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1127 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1128 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1129 (txq->wqe_ci << 8) |
1131 mpw->wqe->ctrl[2] = 0;
1132 mpw->wqe->ctrl[3] = 0;
1133 mpw->wqe->eseg.mss = htons(length);
1134 mpw->wqe->eseg.inline_hdr_sz = 0;
1135 mpw->wqe->eseg.cs_flags = 0;
1136 mpw->wqe->eseg.rsvd0 = 0;
1137 mpw->wqe->eseg.rsvd1 = 0;
1138 mpw->wqe->eseg.rsvd2 = 0;
1139 inl = (struct mlx5_wqe_inl_small *)
1140 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1141 mpw->data.raw = (uint8_t *)&inl->raw;
1145 * Close a MPW inline session.
1148 * Pointer to TX queue structure.
1150 * Pointer to MPW session structure.
1153 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1156 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1157 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1159 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1161 * Store size in multiple of 16 bytes. Control and Ethernet segments
1164 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1165 mpw->state = MLX5_MPW_STATE_CLOSED;
1166 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1167 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1171 * DPDK callback for TX with MPW inline support.
1174 * Generic pointer to TX queue structure.
1176 * Packets to transmit.
1178 * Number of packets in array.
1181 * Number of packets successfully transmitted (<= pkts_n).
1184 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1187 struct txq *txq = (struct txq *)dpdk_txq;
1188 uint16_t elts_head = txq->elts_head;
1189 const unsigned int elts_n = 1 << txq->elts_n;
1195 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1196 struct mlx5_mpw mpw = {
1197 .state = MLX5_MPW_STATE_CLOSED,
1200 * Compute the maximum number of WQE which can be consumed by inline
1203 * - 1 control segment,
1204 * - 1 Ethernet segment,
1205 * - N Dseg from the inline request.
1207 const unsigned int wqe_inl_n =
1208 ((2 * MLX5_WQE_DWORD_SIZE +
1209 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1210 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1212 if (unlikely(!pkts_n))
1214 /* Prefetch first packet cacheline. */
1215 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1216 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1217 /* Start processing. */
1219 max = (elts_n - (elts_head - txq->elts_tail));
1223 struct rte_mbuf *buf = *(pkts++);
1224 unsigned int elts_head_next;
1227 unsigned int segs_n = buf->nb_segs;
1228 uint32_t cs_flags = 0;
1231 * Make sure there is enough room to store this packet and
1232 * that one ring entry remains unused.
1235 if (max < segs_n + 1)
1237 /* Do not bother with large packets MPW cannot handle. */
1238 if (segs_n > MLX5_MPW_DSEG_MAX)
1243 * Compute max_wqe in case less WQE were consumed in previous
1246 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1247 /* Should we enable HW CKSUM offload */
1249 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1250 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1251 /* Retrieve packet information. */
1252 length = PKT_LEN(buf);
1253 /* Start new session if packet differs. */
1254 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1255 if ((mpw.len != length) ||
1257 (mpw.wqe->eseg.cs_flags != cs_flags))
1258 mlx5_mpw_close(txq, &mpw);
1259 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1260 if ((mpw.len != length) ||
1262 (length > inline_room) ||
1263 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1264 mlx5_mpw_inline_close(txq, &mpw);
1266 txq->max_inline * RTE_CACHE_LINE_SIZE;
1269 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1270 if ((segs_n != 1) ||
1271 (length > inline_room)) {
1273 * Multi-Packet WQE consumes at most two WQE.
1274 * mlx5_mpw_new() expects to be able to use
1277 if (unlikely(max_wqe < 2))
1280 mlx5_mpw_new(txq, &mpw, length);
1281 mpw.wqe->eseg.cs_flags = cs_flags;
1283 if (unlikely(max_wqe < wqe_inl_n))
1285 max_wqe -= wqe_inl_n;
1286 mlx5_mpw_inline_new(txq, &mpw, length);
1287 mpw.wqe->eseg.cs_flags = cs_flags;
1290 /* Multi-segment packets must be alone in their MPW. */
1291 assert((segs_n == 1) || (mpw.pkts_n == 0));
1292 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1293 assert(inline_room ==
1294 txq->max_inline * RTE_CACHE_LINE_SIZE);
1295 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1299 volatile struct mlx5_wqe_data_seg *dseg;
1302 (elts_head + 1) & (elts_n - 1);
1304 (*txq->elts)[elts_head] = buf;
1305 dseg = mpw.data.dseg[mpw.pkts_n];
1306 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1307 *dseg = (struct mlx5_wqe_data_seg){
1308 .byte_count = htonl(DATA_LEN(buf)),
1309 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1310 .addr = htonll(addr),
1312 elts_head = elts_head_next;
1313 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1314 length += DATA_LEN(buf);
1320 assert(length == mpw.len);
1321 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1322 mlx5_mpw_close(txq, &mpw);
1326 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1327 assert(length <= inline_room);
1328 assert(length == DATA_LEN(buf));
1329 elts_head_next = (elts_head + 1) & (elts_n - 1);
1330 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1331 (*txq->elts)[elts_head] = buf;
1332 /* Maximum number of bytes before wrapping. */
1333 max = ((((uintptr_t)(txq->wqes)) +
1336 (uintptr_t)mpw.data.raw);
1338 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1341 mpw.data.raw = (volatile void *)txq->wqes;
1342 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1343 (void *)(addr + max),
1345 mpw.data.raw += length - max;
1347 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1353 (volatile void *)txq->wqes;
1355 mpw.data.raw += length;
1358 mpw.total_len += length;
1360 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1361 mlx5_mpw_inline_close(txq, &mpw);
1363 txq->max_inline * RTE_CACHE_LINE_SIZE;
1365 inline_room -= length;
1368 elts_head = elts_head_next;
1369 #ifdef MLX5_PMD_SOFT_COUNTERS
1370 /* Increment sent bytes counter. */
1371 txq->stats.obytes += length;
1375 /* Take a shortcut if nothing must be sent. */
1376 if (unlikely(i == 0))
1378 /* Check whether completion threshold has been reached. */
1379 /* "j" includes both packets and segments. */
1380 comp = txq->elts_comp + j;
1381 if (comp >= MLX5_TX_COMP_THRESH) {
1382 volatile struct mlx5_wqe *wqe = mpw.wqe;
1384 /* Request completion on last WQE. */
1385 wqe->ctrl[2] = htonl(8);
1386 /* Save elts_head in unused "immediate" field of WQE. */
1387 wqe->ctrl[3] = elts_head;
1390 txq->elts_comp = comp;
1392 #ifdef MLX5_PMD_SOFT_COUNTERS
1393 /* Increment sent packets counter. */
1394 txq->stats.opackets += i;
1396 /* Ring QP doorbell. */
1397 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1398 mlx5_mpw_inline_close(txq, &mpw);
1399 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1400 mlx5_mpw_close(txq, &mpw);
1401 mlx5_tx_dbrec(txq, mpw.wqe);
1402 txq->elts_head = elts_head;
1407 * Open an Enhanced MPW session.
1410 * Pointer to TX queue structure.
1412 * Pointer to MPW session structure.
1417 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1419 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1421 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1423 mpw->total_len = sizeof(struct mlx5_wqe);
1424 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1425 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1426 (txq->wqe_ci << 8) |
1427 MLX5_OPCODE_ENHANCED_MPSW);
1428 mpw->wqe->ctrl[2] = 0;
1429 mpw->wqe->ctrl[3] = 0;
1430 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1431 if (unlikely(padding)) {
1432 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1434 /* Pad the first 2 DWORDs with zero-length inline header. */
1435 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1436 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1437 htonl(MLX5_INLINE_SEG);
1438 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1439 /* Start from the next WQEBB. */
1440 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1442 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1447 * Close an Enhanced MPW session.
1450 * Pointer to TX queue structure.
1452 * Pointer to MPW session structure.
1455 * Number of consumed WQEs.
1457 static inline uint16_t
1458 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1462 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1465 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1466 mpw->state = MLX5_MPW_STATE_CLOSED;
1467 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1473 * DPDK callback for TX with Enhanced MPW support.
1476 * Generic pointer to TX queue structure.
1478 * Packets to transmit.
1480 * Number of packets in array.
1483 * Number of packets successfully transmitted (<= pkts_n).
1486 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1488 struct txq *txq = (struct txq *)dpdk_txq;
1489 uint16_t elts_head = txq->elts_head;
1490 const unsigned int elts_n = 1 << txq->elts_n;
1493 unsigned int max_elts;
1495 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1496 unsigned int mpw_room = 0;
1497 unsigned int inl_pad = 0;
1499 struct mlx5_mpw mpw = {
1500 .state = MLX5_MPW_STATE_CLOSED,
1503 if (unlikely(!pkts_n))
1505 /* Start processing. */
1507 max_elts = (elts_n - (elts_head - txq->elts_tail));
1508 if (max_elts > elts_n)
1510 /* A CQE slot must always be available. */
1511 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1512 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1513 if (unlikely(!max_wqe))
1516 struct rte_mbuf *buf = *(pkts++);
1517 unsigned int elts_head_next;
1521 unsigned int do_inline = 0; /* Whether inline is possible. */
1523 unsigned int segs_n = buf->nb_segs;
1524 uint32_t cs_flags = 0;
1527 * Make sure there is enough room to store this packet and
1528 * that one ring entry remains unused.
1531 if (max_elts - j < segs_n + 1)
1533 /* Do not bother with large packets MPW cannot handle. */
1534 if (segs_n > MLX5_MPW_DSEG_MAX)
1536 /* Should we enable HW CKSUM offload. */
1538 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1539 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1540 /* Retrieve packet information. */
1541 length = PKT_LEN(buf);
1542 /* Start new session if:
1543 * - multi-segment packet
1544 * - no space left even for a dseg
1545 * - next packet can be inlined with a new WQE
1547 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1550 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1551 if ((segs_n != 1) ||
1552 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1554 (length <= txq->inline_max_packet_sz &&
1555 inl_pad + sizeof(inl_hdr) + length >
1557 (mpw.wqe->eseg.cs_flags != cs_flags))
1558 max_wqe -= mlx5_empw_close(txq, &mpw);
1560 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1561 if (unlikely(segs_n != 1)) {
1562 /* Fall back to legacy MPW.
1563 * A MPW session consumes 2 WQEs at most to
1564 * include MLX5_MPW_DSEG_MAX pointers.
1566 if (unlikely(max_wqe < 2))
1568 mlx5_mpw_new(txq, &mpw, length);
1570 /* In Enhanced MPW, inline as much as the budget
1571 * is allowed. The remaining space is to be
1572 * filled with dsegs. If the title WQEBB isn't
1573 * padded, it will have 2 dsegs there.
1575 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1576 (max_inline ? max_inline :
1577 pkts_n * MLX5_WQE_DWORD_SIZE) +
1579 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1582 /* Don't pad the title WQEBB to not waste WQ. */
1583 mlx5_empw_new(txq, &mpw, 0);
1584 mpw_room -= mpw.total_len;
1587 length <= txq->inline_max_packet_sz &&
1588 sizeof(inl_hdr) + length <= mpw_room &&
1591 mpw.wqe->eseg.cs_flags = cs_flags;
1593 /* Evaluate whether the next packet can be inlined.
1594 * Inlininig is possible when:
1595 * - length is less than configured value
1596 * - length fits for remaining space
1597 * - not required to fill the title WQEBB with dsegs
1600 length <= txq->inline_max_packet_sz &&
1601 inl_pad + sizeof(inl_hdr) + length <=
1603 (!txq->mpw_hdr_dseg ||
1604 mpw.total_len >= MLX5_WQE_SIZE);
1606 /* Multi-segment packets must be alone in their MPW. */
1607 assert((segs_n == 1) || (mpw.pkts_n == 0));
1608 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1609 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1613 volatile struct mlx5_wqe_data_seg *dseg;
1616 (elts_head + 1) & (elts_n - 1);
1618 (*txq->elts)[elts_head] = buf;
1619 dseg = mpw.data.dseg[mpw.pkts_n];
1620 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1621 *dseg = (struct mlx5_wqe_data_seg){
1622 .byte_count = htonl(DATA_LEN(buf)),
1623 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1624 .addr = htonll(addr),
1626 elts_head = elts_head_next;
1627 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1628 length += DATA_LEN(buf);
1634 /* A multi-segmented packet takes one MPW session.
1635 * TODO: Pack more multi-segmented packets if possible.
1637 mlx5_mpw_close(txq, &mpw);
1642 } else if (do_inline) {
1643 /* Inline packet into WQE. */
1646 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1647 assert(length == DATA_LEN(buf));
1648 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1649 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1650 mpw.data.raw = (volatile void *)
1651 ((uintptr_t)mpw.data.raw + inl_pad);
1652 max = tx_mlx5_wq_tailroom(txq,
1653 (void *)(uintptr_t)mpw.data.raw);
1654 /* Copy inline header. */
1655 mpw.data.raw = (volatile void *)
1657 (void *)(uintptr_t)mpw.data.raw,
1660 (void *)(uintptr_t)txq->wqes,
1662 max = tx_mlx5_wq_tailroom(txq,
1663 (void *)(uintptr_t)mpw.data.raw);
1664 /* Copy packet data. */
1665 mpw.data.raw = (volatile void *)
1667 (void *)(uintptr_t)mpw.data.raw,
1670 (void *)(uintptr_t)txq->wqes,
1673 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1674 /* No need to get completion as the entire packet is
1675 * copied to WQ. Free the buf right away.
1677 elts_head_next = elts_head;
1678 rte_pktmbuf_free_seg(buf);
1679 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1680 /* Add pad in the next packet if any. */
1681 inl_pad = (((uintptr_t)mpw.data.raw +
1682 (MLX5_WQE_DWORD_SIZE - 1)) &
1683 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1684 (uintptr_t)mpw.data.raw;
1686 /* No inline. Load a dseg of packet pointer. */
1687 volatile rte_v128u32_t *dseg;
1689 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1690 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1691 assert(length == DATA_LEN(buf));
1692 if (!tx_mlx5_wq_tailroom(txq,
1693 (void *)((uintptr_t)mpw.data.raw
1695 dseg = (volatile void *)txq->wqes;
1697 dseg = (volatile void *)
1698 ((uintptr_t)mpw.data.raw +
1700 elts_head_next = (elts_head + 1) & (elts_n - 1);
1701 (*txq->elts)[elts_head] = buf;
1702 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1703 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1704 rte_prefetch2((void *)(addr +
1705 n * RTE_CACHE_LINE_SIZE));
1706 naddr = htonll(addr);
1707 *dseg = (rte_v128u32_t) {
1709 txq_mp2mr(txq, txq_mb2mp(buf)),
1713 mpw.data.raw = (volatile void *)(dseg + 1);
1714 mpw.total_len += (inl_pad + sizeof(*dseg));
1717 mpw_room -= (inl_pad + sizeof(*dseg));
1720 elts_head = elts_head_next;
1721 #ifdef MLX5_PMD_SOFT_COUNTERS
1722 /* Increment sent bytes counter. */
1723 txq->stats.obytes += length;
1726 } while (i < pkts_n);
1727 /* Take a shortcut if nothing must be sent. */
1728 if (unlikely(i == 0))
1730 /* Check whether completion threshold has been reached. */
1731 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1732 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1733 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1734 volatile struct mlx5_wqe *wqe = mpw.wqe;
1736 /* Request completion on last WQE. */
1737 wqe->ctrl[2] = htonl(8);
1738 /* Save elts_head in unused "immediate" field of WQE. */
1739 wqe->ctrl[3] = elts_head;
1741 txq->mpw_comp = txq->wqe_ci;
1744 txq->elts_comp += j;
1746 #ifdef MLX5_PMD_SOFT_COUNTERS
1747 /* Increment sent packets counter. */
1748 txq->stats.opackets += i;
1750 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1751 mlx5_empw_close(txq, &mpw);
1752 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1753 mlx5_mpw_close(txq, &mpw);
1754 /* Ring QP doorbell. */
1755 mlx5_tx_dbrec(txq, mpw.wqe);
1756 txq->elts_head = elts_head;
1761 * Translate RX completion flags to packet type.
1766 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1769 * Packet type for struct rte_mbuf.
1771 static inline uint32_t
1772 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1775 uint16_t flags = ntohs(cqe->hdr_type_etc);
1777 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1780 MLX5_CQE_RX_IPV4_PACKET,
1781 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1783 MLX5_CQE_RX_IPV6_PACKET,
1784 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1785 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1786 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1787 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1791 MLX5_CQE_L3_HDR_TYPE_IPV6,
1792 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1794 MLX5_CQE_L3_HDR_TYPE_IPV4,
1795 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1801 * Get size of the next packet for a given CQE. For compressed CQEs, the
1802 * consumer index is updated only once all packets of the current one have
1806 * Pointer to RX queue.
1809 * @param[out] rss_hash
1810 * Packet RSS Hash result.
1813 * Packet size in bytes (0 if there is none), -1 in case of completion
1817 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1818 uint16_t cqe_cnt, uint32_t *rss_hash)
1820 struct rxq_zip *zip = &rxq->zip;
1821 uint16_t cqe_n = cqe_cnt + 1;
1825 /* Process compressed data in the CQE and mini arrays. */
1827 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1828 (volatile struct mlx5_mini_cqe8 (*)[8])
1829 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1831 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1832 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1833 if ((++zip->ai & 7) == 0) {
1834 /* Invalidate consumed CQEs */
1837 while (idx != end) {
1838 (*rxq->cqes)[idx & cqe_cnt].op_own =
1839 MLX5_CQE_INVALIDATE;
1843 * Increment consumer index to skip the number of
1844 * CQEs consumed. Hardware leaves holes in the CQ
1845 * ring for software use.
1850 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1851 /* Invalidate the rest */
1855 while (idx != end) {
1856 (*rxq->cqes)[idx & cqe_cnt].op_own =
1857 MLX5_CQE_INVALIDATE;
1860 rxq->cq_ci = zip->cq_ci;
1863 /* No compressed data, get next CQE and verify if it is compressed. */
1868 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1869 if (unlikely(ret == 1))
1872 op_own = cqe->op_own;
1873 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1874 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1875 (volatile struct mlx5_mini_cqe8 (*)[8])
1876 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1879 /* Fix endianness. */
1880 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1882 * Current mini array position is the one returned by
1885 * If completion comprises several mini arrays, as a
1886 * special case the second one is located 7 CQEs after
1887 * the initial CQE instead of 8 for subsequent ones.
1889 zip->ca = rxq->cq_ci;
1890 zip->na = zip->ca + 7;
1891 /* Compute the next non compressed CQE. */
1893 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1894 /* Get packet size to return. */
1895 len = ntohl((*mc)[0].byte_cnt);
1896 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1898 /* Prefetch all the entries to be invalidated */
1901 while (idx != end) {
1902 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1906 len = ntohl(cqe->byte_cnt);
1907 *rss_hash = ntohl(cqe->rx_hash_res);
1909 /* Error while receiving packet. */
1910 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1917 * Translate RX completion flags to offload flags.
1920 * Pointer to RX queue structure.
1925 * Offload flags (ol_flags) for struct rte_mbuf.
1927 static inline uint32_t
1928 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1930 uint32_t ol_flags = 0;
1931 uint16_t flags = ntohs(cqe->hdr_type_etc);
1935 MLX5_CQE_RX_L3_HDR_VALID,
1936 PKT_RX_IP_CKSUM_GOOD) |
1938 MLX5_CQE_RX_L4_HDR_VALID,
1939 PKT_RX_L4_CKSUM_GOOD);
1940 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1943 MLX5_CQE_RX_L3_HDR_VALID,
1944 PKT_RX_IP_CKSUM_GOOD) |
1946 MLX5_CQE_RX_L4_HDR_VALID,
1947 PKT_RX_L4_CKSUM_GOOD);
1952 * DPDK callback for RX.
1955 * Generic pointer to RX queue structure.
1957 * Array to store received packets.
1959 * Maximum number of packets in array.
1962 * Number of packets successfully received (<= pkts_n).
1965 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1967 struct rxq *rxq = dpdk_rxq;
1968 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1969 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1970 const unsigned int sges_n = rxq->sges_n;
1971 struct rte_mbuf *pkt = NULL;
1972 struct rte_mbuf *seg = NULL;
1973 volatile struct mlx5_cqe *cqe =
1974 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1976 unsigned int rq_ci = rxq->rq_ci << sges_n;
1977 int len = 0; /* keep its value across iterations. */
1980 unsigned int idx = rq_ci & wqe_cnt;
1981 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1982 struct rte_mbuf *rep = (*rxq->elts)[idx];
1983 uint32_t rss_hash_res = 0;
1991 rep = rte_mbuf_raw_alloc(rxq->mp);
1992 if (unlikely(rep == NULL)) {
1993 ++rxq->stats.rx_nombuf;
1996 * no buffers before we even started,
1997 * bail out silently.
2001 while (pkt != seg) {
2002 assert(pkt != (*rxq->elts)[idx]);
2006 rte_mbuf_raw_free(pkt);
2012 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2013 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2016 rte_mbuf_raw_free(rep);
2019 if (unlikely(len == -1)) {
2020 /* RX error, packet is likely too large. */
2021 rte_mbuf_raw_free(rep);
2022 ++rxq->stats.idropped;
2026 assert(len >= (rxq->crc_present << 2));
2027 /* Update packet information. */
2028 pkt->packet_type = 0;
2030 if (rss_hash_res && rxq->rss_hash) {
2031 pkt->hash.rss = rss_hash_res;
2032 pkt->ol_flags = PKT_RX_RSS_HASH;
2035 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2036 pkt->ol_flags |= PKT_RX_FDIR;
2037 if (cqe->sop_drop_qpn !=
2038 htonl(MLX5_FLOW_MARK_DEFAULT)) {
2039 uint32_t mark = cqe->sop_drop_qpn;
2041 pkt->ol_flags |= PKT_RX_FDIR_ID;
2043 mlx5_flow_mark_get(mark);
2046 if (rxq->csum | rxq->csum_l2tun) {
2047 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
2048 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
2050 if (rxq->vlan_strip &&
2051 (cqe->hdr_type_etc &
2052 htons(MLX5_CQE_VLAN_STRIPPED))) {
2053 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2054 PKT_RX_VLAN_STRIPPED;
2055 pkt->vlan_tci = ntohs(cqe->vlan_info);
2057 if (rxq->crc_present)
2058 len -= ETHER_CRC_LEN;
2061 DATA_LEN(rep) = DATA_LEN(seg);
2062 PKT_LEN(rep) = PKT_LEN(seg);
2063 SET_DATA_OFF(rep, DATA_OFF(seg));
2064 NB_SEGS(rep) = NB_SEGS(seg);
2065 PORT(rep) = PORT(seg);
2067 (*rxq->elts)[idx] = rep;
2069 * Fill NIC descriptor with the new buffer. The lkey and size
2070 * of the buffers are already known, only the buffer address
2073 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2074 if (len > DATA_LEN(seg)) {
2075 len -= DATA_LEN(seg);
2080 DATA_LEN(seg) = len;
2081 #ifdef MLX5_PMD_SOFT_COUNTERS
2082 /* Increment bytes counter. */
2083 rxq->stats.ibytes += PKT_LEN(pkt);
2085 /* Return packet. */
2091 /* Align consumer index to the next stride. */
2096 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2098 /* Update the consumer index. */
2099 rxq->rq_ci = rq_ci >> sges_n;
2101 *rxq->cq_db = htonl(rxq->cq_ci);
2103 *rxq->rq_db = htonl(rxq->rq_ci);
2104 #ifdef MLX5_PMD_SOFT_COUNTERS
2105 /* Increment packets counter. */
2106 rxq->stats.ipackets += i;
2112 * Dummy DPDK callback for TX.
2114 * This function is used to temporarily replace the real callback during
2115 * unsafe control operations on the queue, or in case of error.
2118 * Generic pointer to TX queue structure.
2120 * Packets to transmit.
2122 * Number of packets in array.
2125 * Number of packets successfully transmitted (<= pkts_n).
2128 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2137 * Dummy DPDK callback for RX.
2139 * This function is used to temporarily replace the real callback during
2140 * unsafe control operations on the queue, or in case of error.
2143 * Generic pointer to RX queue structure.
2145 * Array to store received packets.
2147 * Maximum number of packets in array.
2150 * Number of packets successfully received (<= pkts_n).
2153 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2162 * DPDK callback for rx queue interrupt enable.
2165 * Pointer to Ethernet device structure.
2166 * @param rx_queue_id
2170 * 0 on success, negative on failure.
2173 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2175 #ifdef HAVE_UPDATE_CQ_CI
2176 struct priv *priv = mlx5_get_priv(dev);
2177 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2178 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2179 struct ibv_cq *cq = rxq_ctrl->cq;
2180 uint16_t ci = rxq->cq_ci;
2183 ibv_mlx5_exp_update_cq_ci(cq, ci);
2184 ret = ibv_req_notify_cq(cq, 0);
2191 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2196 * DPDK callback for rx queue interrupt disable.
2199 * Pointer to Ethernet device structure.
2200 * @param rx_queue_id
2204 * 0 on success, negative on failure.
2207 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2209 #ifdef HAVE_UPDATE_CQ_CI
2210 struct priv *priv = mlx5_get_priv(dev);
2211 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2212 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2213 struct ibv_cq *cq = rxq_ctrl->cq;
2214 struct ibv_cq *ev_cq;
2218 ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2219 if (ret || ev_cq != cq)
2222 ibv_ack_cq_events(cq, 1);
2229 WARN("unable to disable interrupt on rx queue %d",