4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 txq->wqe_pi = ntohs(cqe->wqe_counter);
242 ctrl = (volatile struct mlx5_wqe_ctrl *)
243 tx_mlx5_wqe(txq, txq->wqe_pi);
244 elts_tail = ctrl->ctrl3;
245 assert(elts_tail < (1 << txq->wqe_n));
247 while (elts_free != elts_tail) {
248 struct rte_mbuf *elt = (*txq->elts)[elts_free];
249 unsigned int elts_free_next =
250 (elts_free + 1) & (elts_n - 1);
251 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
255 memset(&(*txq->elts)[elts_free],
257 sizeof((*txq->elts)[elts_free]));
259 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
260 /* Only one segment needs to be freed. */
261 rte_pktmbuf_free_seg(elt);
262 elts_free = elts_free_next;
265 txq->elts_tail = elts_tail;
266 /* Update the consumer index. */
268 *txq->cq_db = htonl(cq_ci);
272 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
273 * the cloned mbuf is allocated is returned instead.
279 * Memory pool where data is located for given mbuf.
281 static struct rte_mempool *
282 txq_mb2mp(struct rte_mbuf *buf)
284 if (unlikely(RTE_MBUF_INDIRECT(buf)))
285 return rte_mbuf_from_indirect(buf)->pool;
290 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
291 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
292 * remove an entry first.
295 * Pointer to TX queue structure.
297 * Memory Pool for which a Memory Region lkey must be returned.
300 * mr->lkey on success, (uint32_t)-1 on failure.
302 static inline uint32_t
303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
306 uint32_t lkey = (uint32_t)-1;
308 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
309 if (unlikely(txq->mp2mr[i].mp == NULL)) {
310 /* Unknown MP, add a new MR for it. */
313 if (txq->mp2mr[i].mp == mp) {
314 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
315 assert(htonl(txq->mp2mr[i].mr->lkey) ==
317 lkey = txq->mp2mr[i].lkey;
321 if (unlikely(lkey == (uint32_t)-1))
322 lkey = txq_mp2mr_reg(txq, mp, i);
327 * Ring TX queue doorbell.
330 * Pointer to TX queue structure.
332 * Pointer to the last WQE posted in the NIC.
335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
337 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
338 volatile uint64_t *src = ((volatile uint64_t *)wqe);
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
348 * DPDK callback to check the status of a tx descriptor.
353 * The index of the descriptor in the ring.
356 * The status of the tx descriptor.
359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
361 struct txq *txq = tx_queue;
362 const unsigned int elts_n = 1 << txq->elts_n;
363 const unsigned int elts_cnt = elts_n - 1;
367 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
369 return RTE_ETH_TX_DESC_FULL;
370 return RTE_ETH_TX_DESC_DONE;
374 * DPDK callback to check the status of a rx descriptor.
379 * The index of the descriptor in the ring.
382 * The status of the tx descriptor.
385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
387 struct rxq *rxq = rx_queue;
388 struct rxq_zip *zip = &rxq->zip;
389 volatile struct mlx5_cqe *cqe;
390 const unsigned int cqe_n = (1 << rxq->cqe_n);
391 const unsigned int cqe_cnt = cqe_n - 1;
395 /* if we are processing a compressed cqe */
397 used = zip->cqe_cnt - zip->ca;
403 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
404 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
408 op_own = cqe->op_own;
409 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
410 n = ntohl(cqe->byte_cnt);
415 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
417 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
419 return RTE_ETH_RX_DESC_DONE;
420 return RTE_ETH_RX_DESC_AVAIL;
424 * DPDK callback for TX.
427 * Generic pointer to TX queue structure.
429 * Packets to transmit.
431 * Number of packets in array.
434 * Number of packets successfully transmitted (<= pkts_n).
437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
439 struct txq *txq = (struct txq *)dpdk_txq;
440 uint16_t elts_head = txq->elts_head;
441 const unsigned int elts_n = 1 << txq->elts_n;
448 volatile struct mlx5_wqe_v *wqe = NULL;
449 unsigned int segs_n = 0;
450 struct rte_mbuf *buf = NULL;
453 if (unlikely(!pkts_n))
455 /* Prefetch first packet cacheline. */
456 rte_prefetch0(*pkts);
457 /* Start processing. */
459 max = (elts_n - (elts_head - txq->elts_tail));
462 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
463 if (unlikely(!max_wqe))
466 volatile rte_v128u32_t *dseg = NULL;
471 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
472 uint16_t tso_header_sz = 0;
474 uint8_t cs_flags = 0;
476 #ifdef MLX5_PMD_SOFT_COUNTERS
477 uint32_t total_length = 0;
482 segs_n = buf->nb_segs;
484 * Make sure there is enough room to store this packet and
485 * that one ring entry remains unused.
488 if (max < segs_n + 1)
494 if (unlikely(--max_wqe == 0))
496 wqe = (volatile struct mlx5_wqe_v *)
497 tx_mlx5_wqe(txq, txq->wqe_ci);
498 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
500 rte_prefetch0(*pkts);
501 addr = rte_pktmbuf_mtod(buf, uintptr_t);
502 length = DATA_LEN(buf);
503 ehdr = (((uint8_t *)addr)[1] << 8) |
504 ((uint8_t *)addr)[0];
505 #ifdef MLX5_PMD_SOFT_COUNTERS
506 total_length = length;
508 assert(length >= MLX5_WQE_DWORD_SIZE);
509 /* Update element. */
510 (*txq->elts)[elts_head] = buf;
511 elts_head = (elts_head + 1) & (elts_n - 1);
512 /* Prefetch next buffer data. */
514 volatile void *pkt_addr;
516 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
517 rte_prefetch0(pkt_addr);
519 /* Should we enable HW CKSUM offload */
521 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
522 const uint64_t is_tunneled = buf->ol_flags &
524 PKT_TX_TUNNEL_VXLAN);
526 if (is_tunneled && txq->tunnel_en) {
527 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
528 MLX5_ETH_WQE_L4_INNER_CSUM;
529 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
530 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
532 cs_flags = MLX5_ETH_WQE_L3_CSUM |
533 MLX5_ETH_WQE_L4_CSUM;
536 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
537 /* Replace the Ethernet type by the VLAN if necessary. */
538 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
539 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
540 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
544 /* Copy Destination and source mac address. */
545 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
547 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
548 /* Copy missing two bytes to end the DSeg. */
549 memcpy((uint8_t *)raw + len + sizeof(vlan),
550 ((uint8_t *)addr) + len, 2);
554 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
555 MLX5_WQE_DWORD_SIZE);
556 length -= pkt_inline_sz;
557 addr += pkt_inline_sz;
560 tso = buf->ol_flags & PKT_TX_TCP_SEG;
562 uintptr_t end = (uintptr_t)
563 (((uintptr_t)txq->wqes) +
567 uint8_t vlan_sz = (buf->ol_flags &
568 PKT_TX_VLAN_PKT) ? 4 : 0;
569 const uint64_t is_tunneled =
572 PKT_TX_TUNNEL_VXLAN);
574 tso_header_sz = buf->l2_len + vlan_sz +
575 buf->l3_len + buf->l4_len;
577 if (is_tunneled && txq->tunnel_en) {
578 tso_header_sz += buf->outer_l2_len +
581 if (unlikely(tso_header_sz >
582 MLX5_MAX_TSO_HEADER))
584 copy_b = tso_header_sz - pkt_inline_sz;
585 /* First seg must contain all headers. */
586 assert(copy_b <= length);
587 raw += MLX5_WQE_DWORD_SIZE;
589 ((end - (uintptr_t)raw) > copy_b)) {
590 uint16_t n = (MLX5_WQE_DS(copy_b) -
593 if (unlikely(max_wqe < n))
596 rte_memcpy((void *)raw,
597 (void *)addr, copy_b);
600 pkt_inline_sz += copy_b;
602 * Another DWORD will be added
603 * in the inline part.
605 raw += MLX5_WQE_DS(copy_b) *
606 MLX5_WQE_DWORD_SIZE -
610 wqe->ctrl = (rte_v128u32_t){
611 htonl(txq->wqe_ci << 8),
612 htonl(txq->qp_num_8s | 1),
620 elts_head = (elts_head - 1) &
627 /* Inline if enough room. */
628 if (txq->inline_en || tso) {
629 uintptr_t end = (uintptr_t)
630 (((uintptr_t)txq->wqes) +
631 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
632 unsigned int max_inline = txq->max_inline *
633 RTE_CACHE_LINE_SIZE -
635 uintptr_t addr_end = (addr + max_inline) &
636 ~(RTE_CACHE_LINE_SIZE - 1);
637 unsigned int copy_b = (addr_end > addr) ?
638 RTE_MIN((addr_end - addr), length) :
641 raw += MLX5_WQE_DWORD_SIZE;
642 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
644 * One Dseg remains in the current WQE. To
645 * keep the computation positive, it is
646 * removed after the bytes to Dseg conversion.
648 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
650 if (unlikely(max_wqe < n))
655 htonl(copy_b | MLX5_INLINE_SEG);
658 MLX5_WQE_DS(tso_header_sz) *
660 rte_memcpy((void *)raw,
661 (void *)&inl, sizeof(inl));
663 pkt_inline_sz += sizeof(inl);
665 rte_memcpy((void *)raw, (void *)addr, copy_b);
668 pkt_inline_sz += copy_b;
671 * 2 DWORDs consumed by the WQE header + ETH segment +
672 * the size of the inline part of the packet.
674 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
676 if (ds % (MLX5_WQE_SIZE /
677 MLX5_WQE_DWORD_SIZE) == 0) {
678 if (unlikely(--max_wqe == 0))
680 dseg = (volatile rte_v128u32_t *)
681 tx_mlx5_wqe(txq, txq->wqe_ci +
684 dseg = (volatile rte_v128u32_t *)
686 (ds * MLX5_WQE_DWORD_SIZE));
689 } else if (!segs_n) {
692 /* dseg will be advance as part of next_seg */
693 dseg = (volatile rte_v128u32_t *)
695 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
700 * No inline has been done in the packet, only the
701 * Ethernet Header as been stored.
703 dseg = (volatile rte_v128u32_t *)
704 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
707 /* Add the remaining packet as a simple ds. */
708 naddr = htonll(addr);
709 *dseg = (rte_v128u32_t){
711 txq_mp2mr(txq, txq_mb2mp(buf)),
724 * Spill on next WQE when the current one does not have
725 * enough room left. Size of WQE must a be a multiple
726 * of data segment size.
728 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
729 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
730 if (unlikely(--max_wqe == 0))
732 dseg = (volatile rte_v128u32_t *)
733 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
734 rte_prefetch0(tx_mlx5_wqe(txq,
735 txq->wqe_ci + ds / 4 + 1));
742 length = DATA_LEN(buf);
743 #ifdef MLX5_PMD_SOFT_COUNTERS
744 total_length += length;
746 /* Store segment information. */
747 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
748 *dseg = (rte_v128u32_t){
750 txq_mp2mr(txq, txq_mb2mp(buf)),
754 (*txq->elts)[elts_head] = buf;
755 elts_head = (elts_head + 1) & (elts_n - 1);
764 /* Initialize known and common part of the WQE structure. */
766 wqe->ctrl = (rte_v128u32_t){
767 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
768 htonl(txq->qp_num_8s | ds),
772 wqe->eseg = (rte_v128u32_t){
774 cs_flags | (htons(buf->tso_segsz) << 16),
776 (ehdr << 16) | htons(tso_header_sz),
779 wqe->ctrl = (rte_v128u32_t){
780 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
781 htonl(txq->qp_num_8s | ds),
785 wqe->eseg = (rte_v128u32_t){
789 (ehdr << 16) | htons(pkt_inline_sz),
793 txq->wqe_ci += (ds + 3) / 4;
794 #ifdef MLX5_PMD_SOFT_COUNTERS
795 /* Increment sent bytes counter. */
796 txq->stats.obytes += total_length;
799 /* Take a shortcut if nothing must be sent. */
800 if (unlikely((i + k) == 0))
802 /* Check whether completion threshold has been reached. */
803 comp = txq->elts_comp + i + j + k;
804 if (comp >= MLX5_TX_COMP_THRESH) {
805 volatile struct mlx5_wqe_ctrl *w =
806 (volatile struct mlx5_wqe_ctrl *)wqe;
808 /* Request completion on last WQE. */
810 /* Save elts_head in unused "immediate" field of WQE. */
811 w->ctrl3 = elts_head;
814 txq->elts_comp = comp;
816 #ifdef MLX5_PMD_SOFT_COUNTERS
817 /* Increment sent packets counter. */
818 txq->stats.opackets += i;
820 /* Ring QP doorbell. */
821 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
822 txq->elts_head = elts_head;
827 * Open a MPW session.
830 * Pointer to TX queue structure.
832 * Pointer to MPW session structure.
837 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
839 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
840 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
841 (volatile struct mlx5_wqe_data_seg (*)[])
842 tx_mlx5_wqe(txq, idx + 1);
844 mpw->state = MLX5_MPW_STATE_OPENED;
848 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
849 mpw->wqe->eseg.mss = htons(length);
850 mpw->wqe->eseg.inline_hdr_sz = 0;
851 mpw->wqe->eseg.rsvd0 = 0;
852 mpw->wqe->eseg.rsvd1 = 0;
853 mpw->wqe->eseg.rsvd2 = 0;
854 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
855 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
856 mpw->wqe->ctrl[2] = 0;
857 mpw->wqe->ctrl[3] = 0;
858 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
859 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
860 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
861 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
862 mpw->data.dseg[2] = &(*dseg)[0];
863 mpw->data.dseg[3] = &(*dseg)[1];
864 mpw->data.dseg[4] = &(*dseg)[2];
868 * Close a MPW session.
871 * Pointer to TX queue structure.
873 * Pointer to MPW session structure.
876 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
878 unsigned int num = mpw->pkts_n;
881 * Store size in multiple of 16 bytes. Control and Ethernet segments
884 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
885 mpw->state = MLX5_MPW_STATE_CLOSED;
890 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
891 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
895 * DPDK callback for TX with MPW support.
898 * Generic pointer to TX queue structure.
900 * Packets to transmit.
902 * Number of packets in array.
905 * Number of packets successfully transmitted (<= pkts_n).
908 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
910 struct txq *txq = (struct txq *)dpdk_txq;
911 uint16_t elts_head = txq->elts_head;
912 const unsigned int elts_n = 1 << txq->elts_n;
918 struct mlx5_mpw mpw = {
919 .state = MLX5_MPW_STATE_CLOSED,
922 if (unlikely(!pkts_n))
924 /* Prefetch first packet cacheline. */
925 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
926 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
927 /* Start processing. */
929 max = (elts_n - (elts_head - txq->elts_tail));
932 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
933 if (unlikely(!max_wqe))
936 struct rte_mbuf *buf = *(pkts++);
937 unsigned int elts_head_next;
939 unsigned int segs_n = buf->nb_segs;
940 uint32_t cs_flags = 0;
943 * Make sure there is enough room to store this packet and
944 * that one ring entry remains unused.
947 if (max < segs_n + 1)
949 /* Do not bother with large packets MPW cannot handle. */
950 if (segs_n > MLX5_MPW_DSEG_MAX)
954 /* Should we enable HW CKSUM offload */
956 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
957 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
958 /* Retrieve packet information. */
959 length = PKT_LEN(buf);
961 /* Start new session if packet differs. */
962 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
963 ((mpw.len != length) ||
965 (mpw.wqe->eseg.cs_flags != cs_flags)))
966 mlx5_mpw_close(txq, &mpw);
967 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
969 * Multi-Packet WQE consumes at most two WQE.
970 * mlx5_mpw_new() expects to be able to use such
973 if (unlikely(max_wqe < 2))
976 mlx5_mpw_new(txq, &mpw, length);
977 mpw.wqe->eseg.cs_flags = cs_flags;
979 /* Multi-segment packets must be alone in their MPW. */
980 assert((segs_n == 1) || (mpw.pkts_n == 0));
981 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
985 volatile struct mlx5_wqe_data_seg *dseg;
988 elts_head_next = (elts_head + 1) & (elts_n - 1);
990 (*txq->elts)[elts_head] = buf;
991 dseg = mpw.data.dseg[mpw.pkts_n];
992 addr = rte_pktmbuf_mtod(buf, uintptr_t);
993 *dseg = (struct mlx5_wqe_data_seg){
994 .byte_count = htonl(DATA_LEN(buf)),
995 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
996 .addr = htonll(addr),
998 elts_head = elts_head_next;
999 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1000 length += DATA_LEN(buf);
1006 assert(length == mpw.len);
1007 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1008 mlx5_mpw_close(txq, &mpw);
1009 elts_head = elts_head_next;
1010 #ifdef MLX5_PMD_SOFT_COUNTERS
1011 /* Increment sent bytes counter. */
1012 txq->stats.obytes += length;
1016 /* Take a shortcut if nothing must be sent. */
1017 if (unlikely(i == 0))
1019 /* Check whether completion threshold has been reached. */
1020 /* "j" includes both packets and segments. */
1021 comp = txq->elts_comp + j;
1022 if (comp >= MLX5_TX_COMP_THRESH) {
1023 volatile struct mlx5_wqe *wqe = mpw.wqe;
1025 /* Request completion on last WQE. */
1026 wqe->ctrl[2] = htonl(8);
1027 /* Save elts_head in unused "immediate" field of WQE. */
1028 wqe->ctrl[3] = elts_head;
1031 txq->elts_comp = comp;
1033 #ifdef MLX5_PMD_SOFT_COUNTERS
1034 /* Increment sent packets counter. */
1035 txq->stats.opackets += i;
1037 /* Ring QP doorbell. */
1038 if (mpw.state == MLX5_MPW_STATE_OPENED)
1039 mlx5_mpw_close(txq, &mpw);
1040 mlx5_tx_dbrec(txq, mpw.wqe);
1041 txq->elts_head = elts_head;
1046 * Open a MPW inline session.
1049 * Pointer to TX queue structure.
1051 * Pointer to MPW session structure.
1056 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1058 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1059 struct mlx5_wqe_inl_small *inl;
1061 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1065 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1066 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1067 (txq->wqe_ci << 8) |
1069 mpw->wqe->ctrl[2] = 0;
1070 mpw->wqe->ctrl[3] = 0;
1071 mpw->wqe->eseg.mss = htons(length);
1072 mpw->wqe->eseg.inline_hdr_sz = 0;
1073 mpw->wqe->eseg.cs_flags = 0;
1074 mpw->wqe->eseg.rsvd0 = 0;
1075 mpw->wqe->eseg.rsvd1 = 0;
1076 mpw->wqe->eseg.rsvd2 = 0;
1077 inl = (struct mlx5_wqe_inl_small *)
1078 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1079 mpw->data.raw = (uint8_t *)&inl->raw;
1083 * Close a MPW inline session.
1086 * Pointer to TX queue structure.
1088 * Pointer to MPW session structure.
1091 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1094 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1095 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1097 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1099 * Store size in multiple of 16 bytes. Control and Ethernet segments
1102 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1103 mpw->state = MLX5_MPW_STATE_CLOSED;
1104 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1105 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1109 * DPDK callback for TX with MPW inline support.
1112 * Generic pointer to TX queue structure.
1114 * Packets to transmit.
1116 * Number of packets in array.
1119 * Number of packets successfully transmitted (<= pkts_n).
1122 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1125 struct txq *txq = (struct txq *)dpdk_txq;
1126 uint16_t elts_head = txq->elts_head;
1127 const unsigned int elts_n = 1 << txq->elts_n;
1133 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1134 struct mlx5_mpw mpw = {
1135 .state = MLX5_MPW_STATE_CLOSED,
1138 * Compute the maximum number of WQE which can be consumed by inline
1141 * - 1 control segment,
1142 * - 1 Ethernet segment,
1143 * - N Dseg from the inline request.
1145 const unsigned int wqe_inl_n =
1146 ((2 * MLX5_WQE_DWORD_SIZE +
1147 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1148 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1150 if (unlikely(!pkts_n))
1152 /* Prefetch first packet cacheline. */
1153 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1154 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1155 /* Start processing. */
1157 max = (elts_n - (elts_head - txq->elts_tail));
1161 struct rte_mbuf *buf = *(pkts++);
1162 unsigned int elts_head_next;
1165 unsigned int segs_n = buf->nb_segs;
1166 uint32_t cs_flags = 0;
1169 * Make sure there is enough room to store this packet and
1170 * that one ring entry remains unused.
1173 if (max < segs_n + 1)
1175 /* Do not bother with large packets MPW cannot handle. */
1176 if (segs_n > MLX5_MPW_DSEG_MAX)
1181 * Compute max_wqe in case less WQE were consumed in previous
1184 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1185 /* Should we enable HW CKSUM offload */
1187 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1188 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1189 /* Retrieve packet information. */
1190 length = PKT_LEN(buf);
1191 /* Start new session if packet differs. */
1192 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1193 if ((mpw.len != length) ||
1195 (mpw.wqe->eseg.cs_flags != cs_flags))
1196 mlx5_mpw_close(txq, &mpw);
1197 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1198 if ((mpw.len != length) ||
1200 (length > inline_room) ||
1201 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1202 mlx5_mpw_inline_close(txq, &mpw);
1204 txq->max_inline * RTE_CACHE_LINE_SIZE;
1207 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1208 if ((segs_n != 1) ||
1209 (length > inline_room)) {
1211 * Multi-Packet WQE consumes at most two WQE.
1212 * mlx5_mpw_new() expects to be able to use
1215 if (unlikely(max_wqe < 2))
1218 mlx5_mpw_new(txq, &mpw, length);
1219 mpw.wqe->eseg.cs_flags = cs_flags;
1221 if (unlikely(max_wqe < wqe_inl_n))
1223 max_wqe -= wqe_inl_n;
1224 mlx5_mpw_inline_new(txq, &mpw, length);
1225 mpw.wqe->eseg.cs_flags = cs_flags;
1228 /* Multi-segment packets must be alone in their MPW. */
1229 assert((segs_n == 1) || (mpw.pkts_n == 0));
1230 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1231 assert(inline_room ==
1232 txq->max_inline * RTE_CACHE_LINE_SIZE);
1233 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1237 volatile struct mlx5_wqe_data_seg *dseg;
1240 (elts_head + 1) & (elts_n - 1);
1242 (*txq->elts)[elts_head] = buf;
1243 dseg = mpw.data.dseg[mpw.pkts_n];
1244 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1245 *dseg = (struct mlx5_wqe_data_seg){
1246 .byte_count = htonl(DATA_LEN(buf)),
1247 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1248 .addr = htonll(addr),
1250 elts_head = elts_head_next;
1251 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1252 length += DATA_LEN(buf);
1258 assert(length == mpw.len);
1259 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1260 mlx5_mpw_close(txq, &mpw);
1264 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1265 assert(length <= inline_room);
1266 assert(length == DATA_LEN(buf));
1267 elts_head_next = (elts_head + 1) & (elts_n - 1);
1268 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1269 (*txq->elts)[elts_head] = buf;
1270 /* Maximum number of bytes before wrapping. */
1271 max = ((((uintptr_t)(txq->wqes)) +
1274 (uintptr_t)mpw.data.raw);
1276 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1279 mpw.data.raw = (volatile void *)txq->wqes;
1280 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1281 (void *)(addr + max),
1283 mpw.data.raw += length - max;
1285 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1291 (volatile void *)txq->wqes;
1293 mpw.data.raw += length;
1296 mpw.total_len += length;
1298 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1299 mlx5_mpw_inline_close(txq, &mpw);
1301 txq->max_inline * RTE_CACHE_LINE_SIZE;
1303 inline_room -= length;
1306 elts_head = elts_head_next;
1307 #ifdef MLX5_PMD_SOFT_COUNTERS
1308 /* Increment sent bytes counter. */
1309 txq->stats.obytes += length;
1313 /* Take a shortcut if nothing must be sent. */
1314 if (unlikely(i == 0))
1316 /* Check whether completion threshold has been reached. */
1317 /* "j" includes both packets and segments. */
1318 comp = txq->elts_comp + j;
1319 if (comp >= MLX5_TX_COMP_THRESH) {
1320 volatile struct mlx5_wqe *wqe = mpw.wqe;
1322 /* Request completion on last WQE. */
1323 wqe->ctrl[2] = htonl(8);
1324 /* Save elts_head in unused "immediate" field of WQE. */
1325 wqe->ctrl[3] = elts_head;
1328 txq->elts_comp = comp;
1330 #ifdef MLX5_PMD_SOFT_COUNTERS
1331 /* Increment sent packets counter. */
1332 txq->stats.opackets += i;
1334 /* Ring QP doorbell. */
1335 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1336 mlx5_mpw_inline_close(txq, &mpw);
1337 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1338 mlx5_mpw_close(txq, &mpw);
1339 mlx5_tx_dbrec(txq, mpw.wqe);
1340 txq->elts_head = elts_head;
1345 * Translate RX completion flags to packet type.
1350 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1353 * Packet type for struct rte_mbuf.
1355 static inline uint32_t
1356 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1359 uint16_t flags = ntohs(cqe->hdr_type_etc);
1361 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1364 MLX5_CQE_RX_IPV4_PACKET,
1365 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1367 MLX5_CQE_RX_IPV6_PACKET,
1368 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1369 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1370 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1371 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1375 MLX5_CQE_L3_HDR_TYPE_IPV6,
1376 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1378 MLX5_CQE_L3_HDR_TYPE_IPV4,
1379 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1385 * Get size of the next packet for a given CQE. For compressed CQEs, the
1386 * consumer index is updated only once all packets of the current one have
1390 * Pointer to RX queue.
1393 * @param[out] rss_hash
1394 * Packet RSS Hash result.
1397 * Packet size in bytes (0 if there is none), -1 in case of completion
1401 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1402 uint16_t cqe_cnt, uint32_t *rss_hash)
1404 struct rxq_zip *zip = &rxq->zip;
1405 uint16_t cqe_n = cqe_cnt + 1;
1409 /* Process compressed data in the CQE and mini arrays. */
1411 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1412 (volatile struct mlx5_mini_cqe8 (*)[8])
1413 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1415 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1416 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1417 if ((++zip->ai & 7) == 0) {
1418 /* Invalidate consumed CQEs */
1421 while (idx != end) {
1422 (*rxq->cqes)[idx & cqe_cnt].op_own =
1423 MLX5_CQE_INVALIDATE;
1427 * Increment consumer index to skip the number of
1428 * CQEs consumed. Hardware leaves holes in the CQ
1429 * ring for software use.
1434 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1435 /* Invalidate the rest */
1439 while (idx != end) {
1440 (*rxq->cqes)[idx & cqe_cnt].op_own =
1441 MLX5_CQE_INVALIDATE;
1444 rxq->cq_ci = zip->cq_ci;
1447 /* No compressed data, get next CQE and verify if it is compressed. */
1452 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1453 if (unlikely(ret == 1))
1456 op_own = cqe->op_own;
1457 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1458 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1459 (volatile struct mlx5_mini_cqe8 (*)[8])
1460 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1463 /* Fix endianness. */
1464 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1466 * Current mini array position is the one returned by
1469 * If completion comprises several mini arrays, as a
1470 * special case the second one is located 7 CQEs after
1471 * the initial CQE instead of 8 for subsequent ones.
1473 zip->ca = rxq->cq_ci;
1474 zip->na = zip->ca + 7;
1475 /* Compute the next non compressed CQE. */
1477 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1478 /* Get packet size to return. */
1479 len = ntohl((*mc)[0].byte_cnt);
1480 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1482 /* Prefetch all the entries to be invalidated */
1485 while (idx != end) {
1486 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1490 len = ntohl(cqe->byte_cnt);
1491 *rss_hash = ntohl(cqe->rx_hash_res);
1493 /* Error while receiving packet. */
1494 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1501 * Translate RX completion flags to offload flags.
1504 * Pointer to RX queue structure.
1509 * Offload flags (ol_flags) for struct rte_mbuf.
1511 static inline uint32_t
1512 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1514 uint32_t ol_flags = 0;
1515 uint16_t flags = ntohs(cqe->hdr_type_etc);
1519 MLX5_CQE_RX_L3_HDR_VALID,
1520 PKT_RX_IP_CKSUM_GOOD) |
1522 MLX5_CQE_RX_L4_HDR_VALID,
1523 PKT_RX_L4_CKSUM_GOOD);
1524 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1527 MLX5_CQE_RX_L3_HDR_VALID,
1528 PKT_RX_IP_CKSUM_GOOD) |
1530 MLX5_CQE_RX_L4_HDR_VALID,
1531 PKT_RX_L4_CKSUM_GOOD);
1536 * DPDK callback for RX.
1539 * Generic pointer to RX queue structure.
1541 * Array to store received packets.
1543 * Maximum number of packets in array.
1546 * Number of packets successfully received (<= pkts_n).
1549 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1551 struct rxq *rxq = dpdk_rxq;
1552 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1553 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1554 const unsigned int sges_n = rxq->sges_n;
1555 struct rte_mbuf *pkt = NULL;
1556 struct rte_mbuf *seg = NULL;
1557 volatile struct mlx5_cqe *cqe =
1558 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1560 unsigned int rq_ci = rxq->rq_ci << sges_n;
1561 int len; /* keep its value across iterations. */
1564 unsigned int idx = rq_ci & wqe_cnt;
1565 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1566 struct rte_mbuf *rep = (*rxq->elts)[idx];
1567 uint32_t rss_hash_res = 0;
1575 rep = rte_mbuf_raw_alloc(rxq->mp);
1576 if (unlikely(rep == NULL)) {
1577 ++rxq->stats.rx_nombuf;
1580 * no buffers before we even started,
1581 * bail out silently.
1585 while (pkt != seg) {
1586 assert(pkt != (*rxq->elts)[idx]);
1588 rte_mbuf_refcnt_set(pkt, 0);
1589 __rte_mbuf_raw_free(pkt);
1595 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1596 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1599 rte_mbuf_refcnt_set(rep, 0);
1600 __rte_mbuf_raw_free(rep);
1603 if (unlikely(len == -1)) {
1604 /* RX error, packet is likely too large. */
1605 rte_mbuf_refcnt_set(rep, 0);
1606 __rte_mbuf_raw_free(rep);
1607 ++rxq->stats.idropped;
1611 assert(len >= (rxq->crc_present << 2));
1612 /* Update packet information. */
1613 pkt->packet_type = 0;
1615 if (rss_hash_res && rxq->rss_hash) {
1616 pkt->hash.rss = rss_hash_res;
1617 pkt->ol_flags = PKT_RX_RSS_HASH;
1619 if (rxq->mark && (cqe->sop_drop_qpn !=
1620 htonl(MLX5_FLOW_MARK_INVALID))) {
1621 pkt->ol_flags |= PKT_RX_FDIR;
1622 if (cqe->sop_drop_qpn !=
1623 htonl(MLX5_FLOW_MARK_DEFAULT)) {
1624 uint32_t mark = cqe->sop_drop_qpn;
1626 pkt->ol_flags |= PKT_RX_FDIR_ID;
1628 mlx5_flow_mark_get(mark);
1631 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1635 rxq_cq_to_pkt_type(cqe);
1637 rxq_cq_to_ol_flags(rxq, cqe);
1639 if (ntohs(cqe->hdr_type_etc) &
1640 MLX5_CQE_VLAN_STRIPPED) {
1641 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1642 PKT_RX_VLAN_STRIPPED;
1643 pkt->vlan_tci = ntohs(cqe->vlan_info);
1645 if (rxq->crc_present)
1646 len -= ETHER_CRC_LEN;
1650 DATA_LEN(rep) = DATA_LEN(seg);
1651 PKT_LEN(rep) = PKT_LEN(seg);
1652 SET_DATA_OFF(rep, DATA_OFF(seg));
1653 NB_SEGS(rep) = NB_SEGS(seg);
1654 PORT(rep) = PORT(seg);
1656 (*rxq->elts)[idx] = rep;
1658 * Fill NIC descriptor with the new buffer. The lkey and size
1659 * of the buffers are already known, only the buffer address
1662 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1663 if (len > DATA_LEN(seg)) {
1664 len -= DATA_LEN(seg);
1669 DATA_LEN(seg) = len;
1670 #ifdef MLX5_PMD_SOFT_COUNTERS
1671 /* Increment bytes counter. */
1672 rxq->stats.ibytes += PKT_LEN(pkt);
1674 /* Return packet. */
1680 /* Align consumer index to the next stride. */
1685 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1687 /* Update the consumer index. */
1688 rxq->rq_ci = rq_ci >> sges_n;
1690 *rxq->cq_db = htonl(rxq->cq_ci);
1692 *rxq->rq_db = htonl(rxq->rq_ci);
1693 #ifdef MLX5_PMD_SOFT_COUNTERS
1694 /* Increment packets counter. */
1695 rxq->stats.ipackets += i;
1701 * Dummy DPDK callback for TX.
1703 * This function is used to temporarily replace the real callback during
1704 * unsafe control operations on the queue, or in case of error.
1707 * Generic pointer to TX queue structure.
1709 * Packets to transmit.
1711 * Number of packets in array.
1714 * Number of packets successfully transmitted (<= pkts_n).
1717 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1726 * Dummy DPDK callback for RX.
1728 * This function is used to temporarily replace the real callback during
1729 * unsafe control operations on the queue, or in case of error.
1732 * Generic pointer to RX queue structure.
1734 * Array to store received packets.
1736 * Maximum number of packets in array.
1739 * Number of packets successfully received (<= pkts_n).
1742 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)