1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
46 static __rte_always_inline void
47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
48 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
50 static __rte_always_inline void
51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
54 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
61 * Build a table to translate Rx completion flags to packet type.
63 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
66 mlx5_set_ptype_table(void)
69 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
71 /* Last entry must not be overwritten, reserved for errored packet. */
72 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
73 (*p)[i] = RTE_PTYPE_UNKNOWN;
75 * The index to the array should have:
76 * bit[1:0] = l3_hdr_type
77 * bit[4:2] = l4_hdr_type
80 * bit[7] = outer_l3_type
83 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
85 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
90 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
92 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
95 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
97 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
99 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
101 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
103 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
105 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
108 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
112 /* Repeat with outer_l3_type being set. Just in case. */
113 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 RTE_PTYPE_L4_NONFRAG;
115 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
116 RTE_PTYPE_L4_NONFRAG;
117 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
119 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
121 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
131 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
133 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
138 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L4_NONFRAG;
145 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
190 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L4_TCP;
193 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L4_TCP;
196 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_TCP;
199 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_TCP;
203 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_UDP;
206 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_UDP;
209 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_UDP;
212 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_UDP;
218 * Build a table to translate packet to checksum type of Verbs.
221 mlx5_set_cksum_table(void)
227 * The index should have:
228 * bit[0] = PKT_TX_TCP_SEG
229 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
230 * bit[4] = PKT_TX_IP_CKSUM
231 * bit[8] = PKT_TX_OUTER_IP_CKSUM
234 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
237 /* Tunneled packet. */
238 if (i & (1 << 8)) /* Outer IP. */
239 v |= MLX5_ETH_WQE_L3_CSUM;
240 if (i & (1 << 4)) /* Inner IP. */
241 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
242 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
243 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
246 if (i & (1 << 4)) /* IP. */
247 v |= MLX5_ETH_WQE_L3_CSUM;
248 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
249 v |= MLX5_ETH_WQE_L4_CSUM;
251 mlx5_cksum_table[i] = v;
256 * Build a table to translate packet type of mbuf to SWP type of Verbs.
259 mlx5_set_swp_types_table(void)
265 * The index should have:
266 * bit[0:1] = PKT_TX_L4_MASK
267 * bit[4] = PKT_TX_IPV6
268 * bit[8] = PKT_TX_OUTER_IPV6
269 * bit[9] = PKT_TX_OUTER_UDP
271 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
274 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
276 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
278 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
279 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
280 v |= MLX5_ETH_WQE_L4_INNER_UDP;
281 mlx5_swp_types_table[i] = v;
286 * Return the size of tailroom of WQ.
289 * Pointer to TX queue structure.
291 * Pointer to tail of WQ.
297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
300 tailroom = (uintptr_t)(txq->wqes) +
301 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
307 * Copy data to tailroom of circular queue.
310 * Pointer to destination.
314 * Number of bytes to copy.
316 * Pointer to head of queue.
318 * Size of tailroom from dst.
321 * Pointer after copied data.
324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
325 void *base, size_t tailroom)
330 rte_memcpy(dst, src, tailroom);
331 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
333 ret = (uint8_t *)base + n - tailroom;
335 rte_memcpy(dst, src, n);
336 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
342 * Inline TSO headers into WQE.
345 * 0 on success, negative errno value on failure.
348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
351 uint16_t *pkt_inline_sz,
355 uint16_t *tso_header_sz)
357 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
358 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
360 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
361 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
365 *tso_segsz = buf->tso_segsz;
366 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
367 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
368 txq->stats.oerrors++;
372 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
373 /* First seg must contain all TSO headers. */
374 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
375 *tso_header_sz > DATA_LEN(buf)) {
376 txq->stats.oerrors++;
379 copy_b = *tso_header_sz - *pkt_inline_sz;
380 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
382 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
383 if (unlikely(*max_wqe < n_wqe))
386 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
389 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
390 *pkt_inline_sz += copy_b;
396 * DPDK callback to check the status of a tx descriptor.
401 * The index of the descriptor in the ring.
404 * The status of the tx descriptor.
407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
409 struct mlx5_txq_data *txq = tx_queue;
412 mlx5_tx_complete(txq);
413 used = txq->elts_head - txq->elts_tail;
415 return RTE_ETH_TX_DESC_FULL;
416 return RTE_ETH_TX_DESC_DONE;
420 * Internal function to compute the number of used descriptors in an RX queue
426 * The number of used rx descriptor.
429 rx_queue_count(struct mlx5_rxq_data *rxq)
431 struct rxq_zip *zip = &rxq->zip;
432 volatile struct mlx5_cqe *cqe;
433 const unsigned int cqe_n = (1 << rxq->cqe_n);
434 const unsigned int cqe_cnt = cqe_n - 1;
438 /* if we are processing a compressed cqe */
440 used = zip->cqe_cnt - zip->ca;
446 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
447 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
451 op_own = cqe->op_own;
452 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
453 n = rte_be_to_cpu_32(cqe->byte_cnt);
458 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
460 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
465 * DPDK callback to check the status of a rx descriptor.
470 * The index of the descriptor in the ring.
473 * The status of the tx descriptor.
476 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
478 struct mlx5_rxq_data *rxq = rx_queue;
479 struct mlx5_rxq_ctrl *rxq_ctrl =
480 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
481 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
483 if (dev->rx_pkt_burst != mlx5_rx_burst) {
487 if (offset >= (1 << rxq->elts_n)) {
491 if (offset < rx_queue_count(rxq))
492 return RTE_ETH_RX_DESC_DONE;
493 return RTE_ETH_RX_DESC_AVAIL;
497 * DPDK callback to get the number of used descriptors in a RX queue
500 * Pointer to the device structure.
506 * The number of used rx descriptor.
507 * -EINVAL if the queue is invalid
510 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
512 struct mlx5_priv *priv = dev->data->dev_private;
513 struct mlx5_rxq_data *rxq;
515 if (dev->rx_pkt_burst != mlx5_rx_burst) {
519 rxq = (*priv->rxqs)[rx_queue_id];
524 return rx_queue_count(rxq);
527 #define MLX5_SYSTEM_LOG_DIR "/var/log"
529 * Dump debug information to log file.
534 * If not NULL this string is printed as a header to the output
535 * and the output will be in hexadecimal view.
537 * This is the buffer address to print out.
539 * The number of bytes to dump out.
542 mlx5_dump_debug_information(const char *fname, const char *hex_title,
543 const void *buf, unsigned int hex_len)
547 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
548 fd = fopen(path, "a+");
550 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
552 MKSTR(path2, "./%s", fname);
553 fd = fopen(path2, "a+");
555 DRV_LOG(ERR, "cannot open %s for debug dump\n",
559 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
561 DRV_LOG(INFO, "New debug dump in file %s\n", path);
564 rte_hexdump(fd, hex_title, buf, hex_len);
566 fprintf(fd, "%s", (const char *)buf);
567 fprintf(fd, "\n\n\n");
572 * DPDK callback for TX.
575 * Generic pointer to TX queue structure.
577 * Packets to transmit.
579 * Number of packets in array.
582 * Number of packets successfully transmitted (<= pkts_n).
585 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
587 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
588 uint16_t elts_head = txq->elts_head;
589 const uint16_t elts_n = 1 << txq->elts_n;
590 const uint16_t elts_m = elts_n - 1;
597 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
598 unsigned int segs_n = 0;
599 const unsigned int max_inline = txq->max_inline;
602 if (unlikely(!pkts_n))
604 /* Prefetch first packet cacheline. */
605 rte_prefetch0(*pkts);
606 /* Start processing. */
607 mlx5_tx_complete(txq);
608 max_elts = (elts_n - (elts_head - txq->elts_tail));
609 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
610 if (unlikely(!max_wqe))
613 struct rte_mbuf *buf = *pkts; /* First_seg. */
615 volatile struct mlx5_wqe_v *wqe = NULL;
616 volatile rte_v128u32_t *dseg = NULL;
619 unsigned int sg = 0; /* counter of additional segs attached. */
621 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
622 uint16_t tso_header_sz = 0;
625 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
626 uint32_t swp_offsets = 0;
627 uint8_t swp_types = 0;
629 uint16_t tso_segsz = 0;
630 #ifdef MLX5_PMD_SOFT_COUNTERS
631 uint32_t total_length = 0;
635 segs_n = buf->nb_segs;
637 * Make sure there is enough room to store this packet and
638 * that one ring entry remains unused.
641 if (max_elts < segs_n)
645 if (unlikely(--max_wqe == 0))
647 wqe = (volatile struct mlx5_wqe_v *)
648 tx_mlx5_wqe(txq, txq->wqe_ci);
649 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
651 rte_prefetch0(*(pkts + 1));
652 addr = rte_pktmbuf_mtod(buf, uintptr_t);
653 length = DATA_LEN(buf);
654 ehdr = (((uint8_t *)addr)[1] << 8) |
655 ((uint8_t *)addr)[0];
656 #ifdef MLX5_PMD_SOFT_COUNTERS
657 total_length = length;
659 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
660 txq->stats.oerrors++;
663 /* Update element. */
664 (*txq->elts)[elts_head & elts_m] = buf;
665 /* Prefetch next buffer data. */
668 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
669 cs_flags = txq_ol_cksum_to_cs(buf);
670 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
671 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
672 /* Copy metadata from mbuf if valid */
673 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
675 /* Replace the Ethernet type by the VLAN if necessary. */
676 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
677 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
679 unsigned int len = 2 * RTE_ETHER_ADDR_LEN - 2;
683 /* Copy Destination and source mac address. */
684 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
686 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
687 /* Copy missing two bytes to end the DSeg. */
688 memcpy((uint8_t *)raw + len + sizeof(vlan),
689 ((uint8_t *)addr) + len, 2);
693 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
694 MLX5_WQE_DWORD_SIZE);
695 length -= pkt_inline_sz;
696 addr += pkt_inline_sz;
698 raw += MLX5_WQE_DWORD_SIZE;
700 ret = inline_tso(txq, buf, &length,
701 &addr, &pkt_inline_sz,
703 &tso_segsz, &tso_header_sz);
704 if (ret == -EINVAL) {
706 } else if (ret == -EAGAIN) {
708 wqe->ctrl = (rte_v128u32_t){
709 rte_cpu_to_be_32(txq->wqe_ci << 8),
710 rte_cpu_to_be_32(txq->qp_num_8s | 1),
715 #ifdef MLX5_PMD_SOFT_COUNTERS
722 /* Inline if enough room. */
723 if (max_inline || tso) {
725 uintptr_t end = (uintptr_t)
726 (((uintptr_t)txq->wqes) +
727 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
728 unsigned int inline_room = max_inline *
729 RTE_CACHE_LINE_SIZE -
730 (pkt_inline_sz - 2) -
736 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
737 RTE_CACHE_LINE_SIZE);
738 copy_b = (addr_end > addr) ?
739 RTE_MIN((addr_end - addr), length) : 0;
740 if (copy_b && ((end - (uintptr_t)raw) >
741 (copy_b + sizeof(inl)))) {
743 * One Dseg remains in the current WQE. To
744 * keep the computation positive, it is
745 * removed after the bytes to Dseg conversion.
747 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
749 if (unlikely(max_wqe < n))
754 inl = rte_cpu_to_be_32(copy_b |
756 rte_memcpy((void *)raw,
757 (void *)&inl, sizeof(inl));
759 pkt_inline_sz += sizeof(inl);
761 rte_memcpy((void *)raw, (void *)addr, copy_b);
764 pkt_inline_sz += copy_b;
767 * 2 DWORDs consumed by the WQE header + ETH segment +
768 * the size of the inline part of the packet.
770 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
772 if (ds % (MLX5_WQE_SIZE /
773 MLX5_WQE_DWORD_SIZE) == 0) {
774 if (unlikely(--max_wqe == 0))
776 dseg = (volatile rte_v128u32_t *)
777 tx_mlx5_wqe(txq, txq->wqe_ci +
780 dseg = (volatile rte_v128u32_t *)
782 (ds * MLX5_WQE_DWORD_SIZE));
785 } else if (!segs_n) {
789 * Further inline the next segment only for
794 inline_room -= copy_b;
798 /* Move to the next segment. */
802 addr = rte_pktmbuf_mtod(buf, uintptr_t);
803 length = DATA_LEN(buf);
804 #ifdef MLX5_PMD_SOFT_COUNTERS
805 total_length += length;
807 (*txq->elts)[++elts_head & elts_m] = buf;
812 * No inline has been done in the packet, only the
813 * Ethernet Header as been stored.
815 dseg = (volatile rte_v128u32_t *)
816 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
819 /* Add the remaining packet as a simple ds. */
820 addr_64 = rte_cpu_to_be_64(addr);
821 *dseg = (rte_v128u32_t){
822 rte_cpu_to_be_32(length),
823 mlx5_tx_mb2mr(txq, buf),
836 * Spill on next WQE when the current one does not have
837 * enough room left. Size of WQE must a be a multiple
838 * of data segment size.
840 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
841 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
842 if (unlikely(--max_wqe == 0))
844 dseg = (volatile rte_v128u32_t *)
845 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
846 rte_prefetch0(tx_mlx5_wqe(txq,
847 txq->wqe_ci + ds / 4 + 1));
854 length = DATA_LEN(buf);
855 #ifdef MLX5_PMD_SOFT_COUNTERS
856 total_length += length;
858 /* Store segment information. */
859 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
860 *dseg = (rte_v128u32_t){
861 rte_cpu_to_be_32(length),
862 mlx5_tx_mb2mr(txq, buf),
866 (*txq->elts)[++elts_head & elts_m] = buf;
870 if (ds > MLX5_DSEG_MAX) {
871 txq->stats.oerrors++;
878 /* Initialize known and common part of the WQE structure. */
880 wqe->ctrl = (rte_v128u32_t){
881 rte_cpu_to_be_32((txq->wqe_ci << 8) |
883 rte_cpu_to_be_32(txq->qp_num_8s | ds),
887 wqe->eseg = (rte_v128u32_t){
889 cs_flags | (swp_types << 8) |
890 (rte_cpu_to_be_16(tso_segsz) << 16),
892 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
895 wqe->ctrl = (rte_v128u32_t){
896 rte_cpu_to_be_32((txq->wqe_ci << 8) |
898 rte_cpu_to_be_32(txq->qp_num_8s | ds),
902 wqe->eseg = (rte_v128u32_t){
904 cs_flags | (swp_types << 8),
906 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
910 txq->wqe_ci += (ds + 3) / 4;
911 /* Save the last successful WQE for completion request */
912 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
913 #ifdef MLX5_PMD_SOFT_COUNTERS
914 /* Increment sent bytes counter. */
915 txq->stats.obytes += total_length;
917 } while (i < pkts_n);
918 /* Take a shortcut if nothing must be sent. */
919 if (unlikely((i + k) == 0))
921 txq->elts_head += (i + j);
922 /* Check whether completion threshold has been reached. */
923 comp = txq->elts_comp + i + j + k;
924 if (comp >= MLX5_TX_COMP_THRESH) {
925 /* A CQE slot must always be available. */
926 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
927 /* Request completion on last WQE. */
928 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
929 /* Save elts_head in unused "immediate" field of WQE. */
930 last_wqe->ctrl3 = txq->elts_head;
933 txq->elts_comp = comp;
935 #ifdef MLX5_PMD_SOFT_COUNTERS
936 /* Increment sent packets counter. */
937 txq->stats.opackets += i;
939 /* Ring QP doorbell. */
940 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
945 * Open a MPW session.
948 * Pointer to TX queue structure.
950 * Pointer to MPW session structure.
955 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
957 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
958 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
959 (volatile struct mlx5_wqe_data_seg (*)[])
960 tx_mlx5_wqe(txq, idx + 1);
962 mpw->state = MLX5_MPW_STATE_OPENED;
966 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
967 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
968 mpw->wqe->eseg.inline_hdr_sz = 0;
969 mpw->wqe->eseg.rsvd0 = 0;
970 mpw->wqe->eseg.rsvd1 = 0;
971 mpw->wqe->eseg.flow_table_metadata = 0;
972 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
975 mpw->wqe->ctrl[2] = 0;
976 mpw->wqe->ctrl[3] = 0;
977 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
978 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
979 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
980 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
981 mpw->data.dseg[2] = &(*dseg)[0];
982 mpw->data.dseg[3] = &(*dseg)[1];
983 mpw->data.dseg[4] = &(*dseg)[2];
987 * Close a MPW session.
990 * Pointer to TX queue structure.
992 * Pointer to MPW session structure.
995 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
997 unsigned int num = mpw->pkts_n;
1000 * Store size in multiple of 16 bytes. Control and Ethernet segments
1003 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
1004 mpw->state = MLX5_MPW_STATE_CLOSED;
1009 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1010 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1014 * DPDK callback for TX with MPW support.
1017 * Generic pointer to TX queue structure.
1019 * Packets to transmit.
1021 * Number of packets in array.
1024 * Number of packets successfully transmitted (<= pkts_n).
1027 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1029 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1030 uint16_t elts_head = txq->elts_head;
1031 const uint16_t elts_n = 1 << txq->elts_n;
1032 const uint16_t elts_m = elts_n - 1;
1038 struct mlx5_mpw mpw = {
1039 .state = MLX5_MPW_STATE_CLOSED,
1042 if (unlikely(!pkts_n))
1044 /* Prefetch first packet cacheline. */
1045 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1046 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1047 /* Start processing. */
1048 mlx5_tx_complete(txq);
1049 max_elts = (elts_n - (elts_head - txq->elts_tail));
1050 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1051 if (unlikely(!max_wqe))
1054 struct rte_mbuf *buf = *(pkts++);
1056 unsigned int segs_n = buf->nb_segs;
1058 rte_be32_t metadata;
1061 * Make sure there is enough room to store this packet and
1062 * that one ring entry remains unused.
1065 if (max_elts < segs_n)
1067 /* Do not bother with large packets MPW cannot handle. */
1068 if (segs_n > MLX5_MPW_DSEG_MAX) {
1069 txq->stats.oerrors++;
1074 cs_flags = txq_ol_cksum_to_cs(buf);
1075 /* Copy metadata from mbuf if valid */
1076 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1078 /* Retrieve packet information. */
1079 length = PKT_LEN(buf);
1081 /* Start new session if packet differs. */
1082 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1083 ((mpw.len != length) ||
1085 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1086 (mpw.wqe->eseg.cs_flags != cs_flags)))
1087 mlx5_mpw_close(txq, &mpw);
1088 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1090 * Multi-Packet WQE consumes at most two WQE.
1091 * mlx5_mpw_new() expects to be able to use such
1094 if (unlikely(max_wqe < 2))
1097 mlx5_mpw_new(txq, &mpw, length);
1098 mpw.wqe->eseg.cs_flags = cs_flags;
1099 mpw.wqe->eseg.flow_table_metadata = metadata;
1101 /* Multi-segment packets must be alone in their MPW. */
1102 assert((segs_n == 1) || (mpw.pkts_n == 0));
1103 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1107 volatile struct mlx5_wqe_data_seg *dseg;
1111 (*txq->elts)[elts_head++ & elts_m] = buf;
1112 dseg = mpw.data.dseg[mpw.pkts_n];
1113 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1114 *dseg = (struct mlx5_wqe_data_seg){
1115 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1116 .lkey = mlx5_tx_mb2mr(txq, buf),
1117 .addr = rte_cpu_to_be_64(addr),
1119 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1120 length += DATA_LEN(buf);
1126 assert(length == mpw.len);
1127 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1128 mlx5_mpw_close(txq, &mpw);
1129 #ifdef MLX5_PMD_SOFT_COUNTERS
1130 /* Increment sent bytes counter. */
1131 txq->stats.obytes += length;
1135 /* Take a shortcut if nothing must be sent. */
1136 if (unlikely(i == 0))
1138 /* Check whether completion threshold has been reached. */
1139 /* "j" includes both packets and segments. */
1140 comp = txq->elts_comp + j;
1141 if (comp >= MLX5_TX_COMP_THRESH) {
1142 volatile struct mlx5_wqe *wqe = mpw.wqe;
1144 /* A CQE slot must always be available. */
1145 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1146 /* Request completion on last WQE. */
1147 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1148 /* Save elts_head in unused "immediate" field of WQE. */
1149 wqe->ctrl[3] = elts_head;
1152 txq->elts_comp = comp;
1154 #ifdef MLX5_PMD_SOFT_COUNTERS
1155 /* Increment sent packets counter. */
1156 txq->stats.opackets += i;
1158 /* Ring QP doorbell. */
1159 if (mpw.state == MLX5_MPW_STATE_OPENED)
1160 mlx5_mpw_close(txq, &mpw);
1161 mlx5_tx_dbrec(txq, mpw.wqe);
1162 txq->elts_head = elts_head;
1167 * Open a MPW inline session.
1170 * Pointer to TX queue structure.
1172 * Pointer to MPW session structure.
1177 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1180 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1181 struct mlx5_wqe_inl_small *inl;
1183 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1187 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1188 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1189 (txq->wqe_ci << 8) |
1191 mpw->wqe->ctrl[2] = 0;
1192 mpw->wqe->ctrl[3] = 0;
1193 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1194 mpw->wqe->eseg.inline_hdr_sz = 0;
1195 mpw->wqe->eseg.cs_flags = 0;
1196 mpw->wqe->eseg.rsvd0 = 0;
1197 mpw->wqe->eseg.rsvd1 = 0;
1198 mpw->wqe->eseg.flow_table_metadata = 0;
1199 inl = (struct mlx5_wqe_inl_small *)
1200 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1201 mpw->data.raw = (uint8_t *)&inl->raw;
1205 * Close a MPW inline session.
1208 * Pointer to TX queue structure.
1210 * Pointer to MPW session structure.
1213 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1216 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1217 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1219 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1221 * Store size in multiple of 16 bytes. Control and Ethernet segments
1224 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1226 mpw->state = MLX5_MPW_STATE_CLOSED;
1227 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1228 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1232 * DPDK callback for TX with MPW inline support.
1235 * Generic pointer to TX queue structure.
1237 * Packets to transmit.
1239 * Number of packets in array.
1242 * Number of packets successfully transmitted (<= pkts_n).
1245 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1248 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1249 uint16_t elts_head = txq->elts_head;
1250 const uint16_t elts_n = 1 << txq->elts_n;
1251 const uint16_t elts_m = elts_n - 1;
1257 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1258 struct mlx5_mpw mpw = {
1259 .state = MLX5_MPW_STATE_CLOSED,
1262 * Compute the maximum number of WQE which can be consumed by inline
1265 * - 1 control segment,
1266 * - 1 Ethernet segment,
1267 * - N Dseg from the inline request.
1269 const unsigned int wqe_inl_n =
1270 ((2 * MLX5_WQE_DWORD_SIZE +
1271 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1272 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1274 if (unlikely(!pkts_n))
1276 /* Prefetch first packet cacheline. */
1277 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1278 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1279 /* Start processing. */
1280 mlx5_tx_complete(txq);
1281 max_elts = (elts_n - (elts_head - txq->elts_tail));
1283 struct rte_mbuf *buf = *(pkts++);
1286 unsigned int segs_n = buf->nb_segs;
1288 rte_be32_t metadata;
1291 * Make sure there is enough room to store this packet and
1292 * that one ring entry remains unused.
1295 if (max_elts < segs_n)
1297 /* Do not bother with large packets MPW cannot handle. */
1298 if (segs_n > MLX5_MPW_DSEG_MAX) {
1299 txq->stats.oerrors++;
1305 * Compute max_wqe in case less WQE were consumed in previous
1308 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1309 cs_flags = txq_ol_cksum_to_cs(buf);
1310 /* Copy metadata from mbuf if valid */
1311 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1313 /* Retrieve packet information. */
1314 length = PKT_LEN(buf);
1315 /* Start new session if packet differs. */
1316 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1317 if ((mpw.len != length) ||
1319 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1320 (mpw.wqe->eseg.cs_flags != cs_flags))
1321 mlx5_mpw_close(txq, &mpw);
1322 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1323 if ((mpw.len != length) ||
1325 (length > inline_room) ||
1326 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1327 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1328 mlx5_mpw_inline_close(txq, &mpw);
1330 txq->max_inline * RTE_CACHE_LINE_SIZE;
1333 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1334 if ((segs_n != 1) ||
1335 (length > inline_room)) {
1337 * Multi-Packet WQE consumes at most two WQE.
1338 * mlx5_mpw_new() expects to be able to use
1341 if (unlikely(max_wqe < 2))
1344 mlx5_mpw_new(txq, &mpw, length);
1345 mpw.wqe->eseg.cs_flags = cs_flags;
1346 mpw.wqe->eseg.flow_table_metadata = metadata;
1348 if (unlikely(max_wqe < wqe_inl_n))
1350 max_wqe -= wqe_inl_n;
1351 mlx5_mpw_inline_new(txq, &mpw, length);
1352 mpw.wqe->eseg.cs_flags = cs_flags;
1353 mpw.wqe->eseg.flow_table_metadata = metadata;
1356 /* Multi-segment packets must be alone in their MPW. */
1357 assert((segs_n == 1) || (mpw.pkts_n == 0));
1358 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1359 assert(inline_room ==
1360 txq->max_inline * RTE_CACHE_LINE_SIZE);
1361 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1365 volatile struct mlx5_wqe_data_seg *dseg;
1368 (*txq->elts)[elts_head++ & elts_m] = buf;
1369 dseg = mpw.data.dseg[mpw.pkts_n];
1370 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1371 *dseg = (struct mlx5_wqe_data_seg){
1373 rte_cpu_to_be_32(DATA_LEN(buf)),
1374 .lkey = mlx5_tx_mb2mr(txq, buf),
1375 .addr = rte_cpu_to_be_64(addr),
1377 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1378 length += DATA_LEN(buf);
1384 assert(length == mpw.len);
1385 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1386 mlx5_mpw_close(txq, &mpw);
1390 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1391 assert(length <= inline_room);
1392 assert(length == DATA_LEN(buf));
1393 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1394 (*txq->elts)[elts_head++ & elts_m] = buf;
1395 /* Maximum number of bytes before wrapping. */
1396 max = ((((uintptr_t)(txq->wqes)) +
1399 (uintptr_t)mpw.data.raw);
1401 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1404 mpw.data.raw = (volatile void *)txq->wqes;
1405 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1406 (void *)(addr + max),
1408 mpw.data.raw += length - max;
1410 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1416 (volatile void *)txq->wqes;
1418 mpw.data.raw += length;
1421 mpw.total_len += length;
1423 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1424 mlx5_mpw_inline_close(txq, &mpw);
1426 txq->max_inline * RTE_CACHE_LINE_SIZE;
1428 inline_room -= length;
1431 #ifdef MLX5_PMD_SOFT_COUNTERS
1432 /* Increment sent bytes counter. */
1433 txq->stats.obytes += length;
1437 /* Take a shortcut if nothing must be sent. */
1438 if (unlikely(i == 0))
1440 /* Check whether completion threshold has been reached. */
1441 /* "j" includes both packets and segments. */
1442 comp = txq->elts_comp + j;
1443 if (comp >= MLX5_TX_COMP_THRESH) {
1444 volatile struct mlx5_wqe *wqe = mpw.wqe;
1446 /* A CQE slot must always be available. */
1447 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1448 /* Request completion on last WQE. */
1449 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1450 /* Save elts_head in unused "immediate" field of WQE. */
1451 wqe->ctrl[3] = elts_head;
1454 txq->elts_comp = comp;
1456 #ifdef MLX5_PMD_SOFT_COUNTERS
1457 /* Increment sent packets counter. */
1458 txq->stats.opackets += i;
1460 /* Ring QP doorbell. */
1461 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1462 mlx5_mpw_inline_close(txq, &mpw);
1463 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1464 mlx5_mpw_close(txq, &mpw);
1465 mlx5_tx_dbrec(txq, mpw.wqe);
1466 txq->elts_head = elts_head;
1471 * Open an Enhanced MPW session.
1474 * Pointer to TX queue structure.
1476 * Pointer to MPW session structure.
1481 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1483 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1485 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1487 mpw->total_len = sizeof(struct mlx5_wqe);
1488 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1490 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1491 (txq->wqe_ci << 8) |
1492 MLX5_OPCODE_ENHANCED_MPSW);
1493 mpw->wqe->ctrl[2] = 0;
1494 mpw->wqe->ctrl[3] = 0;
1495 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1496 if (unlikely(padding)) {
1497 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1499 /* Pad the first 2 DWORDs with zero-length inline header. */
1500 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1501 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1502 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1503 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1504 /* Start from the next WQEBB. */
1505 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1507 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1512 * Close an Enhanced MPW session.
1515 * Pointer to TX queue structure.
1517 * Pointer to MPW session structure.
1520 * Number of consumed WQEs.
1522 static inline uint16_t
1523 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1527 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1530 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1531 MLX5_WQE_DS(mpw->total_len));
1532 mpw->state = MLX5_MPW_STATE_CLOSED;
1533 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1539 * TX with Enhanced MPW support.
1542 * Pointer to TX queue structure.
1544 * Packets to transmit.
1546 * Number of packets in array.
1549 * Number of packets successfully transmitted (<= pkts_n).
1551 static inline uint16_t
1552 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1555 uint16_t elts_head = txq->elts_head;
1556 const uint16_t elts_n = 1 << txq->elts_n;
1557 const uint16_t elts_m = elts_n - 1;
1562 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1563 unsigned int mpw_room = 0;
1564 unsigned int inl_pad = 0;
1567 struct mlx5_mpw mpw = {
1568 .state = MLX5_MPW_STATE_CLOSED,
1571 if (unlikely(!pkts_n))
1573 /* Start processing. */
1574 mlx5_tx_complete(txq);
1575 max_elts = (elts_n - (elts_head - txq->elts_tail));
1576 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1577 if (unlikely(!max_wqe))
1580 struct rte_mbuf *buf = *(pkts++);
1582 unsigned int do_inline = 0; /* Whether inline is possible. */
1585 rte_be32_t metadata;
1587 /* Multi-segmented packet is handled in slow-path outside. */
1588 assert(NB_SEGS(buf) == 1);
1589 /* Make sure there is enough room to store this packet. */
1590 if (max_elts - j == 0)
1592 cs_flags = txq_ol_cksum_to_cs(buf);
1593 /* Copy metadata from mbuf if valid */
1594 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1596 /* Retrieve packet information. */
1597 length = PKT_LEN(buf);
1598 /* Start new session if:
1599 * - multi-segment packet
1600 * - no space left even for a dseg
1601 * - next packet can be inlined with a new WQE
1604 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1605 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1607 (length <= txq->inline_max_packet_sz &&
1608 inl_pad + sizeof(inl_hdr) + length >
1610 (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1611 (mpw.wqe->eseg.cs_flags != cs_flags))
1612 max_wqe -= mlx5_empw_close(txq, &mpw);
1614 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1615 /* In Enhanced MPW, inline as much as the budget is
1616 * allowed. The remaining space is to be filled with
1617 * dsegs. If the title WQEBB isn't padded, it will have
1620 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1621 (max_inline ? max_inline :
1622 pkts_n * MLX5_WQE_DWORD_SIZE) +
1624 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1626 /* Don't pad the title WQEBB to not waste WQ. */
1627 mlx5_empw_new(txq, &mpw, 0);
1628 mpw_room -= mpw.total_len;
1630 do_inline = length <= txq->inline_max_packet_sz &&
1631 sizeof(inl_hdr) + length <= mpw_room &&
1633 mpw.wqe->eseg.cs_flags = cs_flags;
1634 mpw.wqe->eseg.flow_table_metadata = metadata;
1636 /* Evaluate whether the next packet can be inlined.
1637 * Inlininig is possible when:
1638 * - length is less than configured value
1639 * - length fits for remaining space
1640 * - not required to fill the title WQEBB with dsegs
1643 length <= txq->inline_max_packet_sz &&
1644 inl_pad + sizeof(inl_hdr) + length <=
1646 (!txq->mpw_hdr_dseg ||
1647 mpw.total_len >= MLX5_WQE_SIZE);
1649 if (max_inline && do_inline) {
1650 /* Inline packet into WQE. */
1653 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1654 assert(length == DATA_LEN(buf));
1655 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1656 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1657 mpw.data.raw = (volatile void *)
1658 ((uintptr_t)mpw.data.raw + inl_pad);
1659 max = tx_mlx5_wq_tailroom(txq,
1660 (void *)(uintptr_t)mpw.data.raw);
1661 /* Copy inline header. */
1662 mpw.data.raw = (volatile void *)
1664 (void *)(uintptr_t)mpw.data.raw,
1667 (void *)(uintptr_t)txq->wqes,
1669 max = tx_mlx5_wq_tailroom(txq,
1670 (void *)(uintptr_t)mpw.data.raw);
1671 /* Copy packet data. */
1672 mpw.data.raw = (volatile void *)
1674 (void *)(uintptr_t)mpw.data.raw,
1677 (void *)(uintptr_t)txq->wqes,
1680 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1681 /* No need to get completion as the entire packet is
1682 * copied to WQ. Free the buf right away.
1684 rte_pktmbuf_free_seg(buf);
1685 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1686 /* Add pad in the next packet if any. */
1687 inl_pad = (((uintptr_t)mpw.data.raw +
1688 (MLX5_WQE_DWORD_SIZE - 1)) &
1689 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1690 (uintptr_t)mpw.data.raw;
1692 /* No inline. Load a dseg of packet pointer. */
1693 volatile rte_v128u32_t *dseg;
1695 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1696 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1697 assert(length == DATA_LEN(buf));
1698 if (!tx_mlx5_wq_tailroom(txq,
1699 (void *)((uintptr_t)mpw.data.raw
1701 dseg = (volatile void *)txq->wqes;
1703 dseg = (volatile void *)
1704 ((uintptr_t)mpw.data.raw +
1706 (*txq->elts)[elts_head++ & elts_m] = buf;
1707 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1709 *dseg = (rte_v128u32_t) {
1710 rte_cpu_to_be_32(length),
1711 mlx5_tx_mb2mr(txq, buf),
1715 mpw.data.raw = (volatile void *)(dseg + 1);
1716 mpw.total_len += (inl_pad + sizeof(*dseg));
1719 mpw_room -= (inl_pad + sizeof(*dseg));
1722 #ifdef MLX5_PMD_SOFT_COUNTERS
1723 /* Increment sent bytes counter. */
1724 txq->stats.obytes += length;
1727 } while (i < pkts_n);
1728 /* Take a shortcut if nothing must be sent. */
1729 if (unlikely(i == 0))
1731 /* Check whether completion threshold has been reached. */
1732 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1733 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1734 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1735 volatile struct mlx5_wqe *wqe = mpw.wqe;
1737 /* A CQE slot must always be available. */
1738 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1739 /* Request completion on last WQE. */
1740 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1741 /* Save elts_head in unused "immediate" field of WQE. */
1742 wqe->ctrl[3] = elts_head;
1744 txq->mpw_comp = txq->wqe_ci;
1746 txq->elts_comp += j;
1748 #ifdef MLX5_PMD_SOFT_COUNTERS
1749 /* Increment sent packets counter. */
1750 txq->stats.opackets += i;
1752 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1753 mlx5_empw_close(txq, &mpw);
1754 /* Ring QP doorbell. */
1755 mlx5_tx_dbrec(txq, mpw.wqe);
1756 txq->elts_head = elts_head;
1761 * DPDK callback for TX with Enhanced MPW support.
1764 * Generic pointer to TX queue structure.
1766 * Packets to transmit.
1768 * Number of packets in array.
1771 * Number of packets successfully transmitted (<= pkts_n).
1774 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1776 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1779 while (pkts_n > nb_tx) {
1783 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1785 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1790 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1792 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1802 * Translate RX completion flags to packet type.
1805 * Pointer to RX queue structure.
1809 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1812 * Packet type for struct rte_mbuf.
1814 static inline uint32_t
1815 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1818 uint8_t pinfo = cqe->pkt_info;
1819 uint16_t ptype = cqe->hdr_type_etc;
1822 * The index to the array should have:
1823 * bit[1:0] = l3_hdr_type
1824 * bit[4:2] = l4_hdr_type
1827 * bit[7] = outer_l3_type
1829 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1830 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1834 * Get size of the next packet for a given CQE. For compressed CQEs, the
1835 * consumer index is updated only once all packets of the current one have
1839 * Pointer to RX queue.
1843 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1847 * Packet size in bytes (0 if there is none), -1 in case of completion
1851 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1852 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1854 struct rxq_zip *zip = &rxq->zip;
1855 uint16_t cqe_n = cqe_cnt + 1;
1859 /* Process compressed data in the CQE and mini arrays. */
1861 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1862 (volatile struct mlx5_mini_cqe8 (*)[8])
1863 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1865 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1866 *mcqe = &(*mc)[zip->ai & 7];
1867 if ((++zip->ai & 7) == 0) {
1868 /* Invalidate consumed CQEs */
1871 while (idx != end) {
1872 (*rxq->cqes)[idx & cqe_cnt].op_own =
1873 MLX5_CQE_INVALIDATE;
1877 * Increment consumer index to skip the number of
1878 * CQEs consumed. Hardware leaves holes in the CQ
1879 * ring for software use.
1884 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1885 /* Invalidate the rest */
1889 while (idx != end) {
1890 (*rxq->cqes)[idx & cqe_cnt].op_own =
1891 MLX5_CQE_INVALIDATE;
1894 rxq->cq_ci = zip->cq_ci;
1897 /* No compressed data, get next CQE and verify if it is compressed. */
1902 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1903 if (unlikely(ret == 1))
1906 op_own = cqe->op_own;
1908 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1909 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1910 (volatile struct mlx5_mini_cqe8 (*)[8])
1911 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1914 /* Fix endianness. */
1915 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1917 * Current mini array position is the one returned by
1920 * If completion comprises several mini arrays, as a
1921 * special case the second one is located 7 CQEs after
1922 * the initial CQE instead of 8 for subsequent ones.
1924 zip->ca = rxq->cq_ci;
1925 zip->na = zip->ca + 7;
1926 /* Compute the next non compressed CQE. */
1928 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1929 /* Get packet size to return. */
1930 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1933 /* Prefetch all the entries to be invalidated */
1936 while (idx != end) {
1937 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1941 len = rte_be_to_cpu_32(cqe->byte_cnt);
1943 /* Error while receiving packet. */
1944 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1951 * Translate RX completion flags to offload flags.
1957 * Offload flags (ol_flags) for struct rte_mbuf.
1959 static inline uint32_t
1960 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1962 uint32_t ol_flags = 0;
1963 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1967 MLX5_CQE_RX_L3_HDR_VALID,
1968 PKT_RX_IP_CKSUM_GOOD) |
1970 MLX5_CQE_RX_L4_HDR_VALID,
1971 PKT_RX_L4_CKSUM_GOOD);
1976 * Fill in mbuf fields from RX completion flags.
1977 * Note that pkt->ol_flags should be initialized outside of this function.
1980 * Pointer to RX queue.
1985 * @param rss_hash_res
1986 * Packet RSS Hash result.
1989 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1990 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1992 /* Update packet information. */
1993 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1994 if (rss_hash_res && rxq->rss_hash) {
1995 pkt->hash.rss = rss_hash_res;
1996 pkt->ol_flags |= PKT_RX_RSS_HASH;
1998 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1999 pkt->ol_flags |= PKT_RX_FDIR;
2000 if (cqe->sop_drop_qpn !=
2001 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
2002 uint32_t mark = cqe->sop_drop_qpn;
2004 pkt->ol_flags |= PKT_RX_FDIR_ID;
2005 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
2009 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
2010 if (rxq->vlan_strip &&
2011 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
2012 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2013 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
2015 if (rxq->hw_timestamp) {
2016 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
2017 pkt->ol_flags |= PKT_RX_TIMESTAMP;
2022 * DPDK callback for RX.
2025 * Generic pointer to RX queue structure.
2027 * Array to store received packets.
2029 * Maximum number of packets in array.
2032 * Number of packets successfully received (<= pkts_n).
2035 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2037 struct mlx5_rxq_data *rxq = dpdk_rxq;
2038 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
2039 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
2040 const unsigned int sges_n = rxq->sges_n;
2041 struct rte_mbuf *pkt = NULL;
2042 struct rte_mbuf *seg = NULL;
2043 volatile struct mlx5_cqe *cqe =
2044 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2046 unsigned int rq_ci = rxq->rq_ci << sges_n;
2047 int len = 0; /* keep its value across iterations. */
2050 unsigned int idx = rq_ci & wqe_cnt;
2051 volatile struct mlx5_wqe_data_seg *wqe =
2052 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
2053 struct rte_mbuf *rep = (*rxq->elts)[idx];
2054 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2055 uint32_t rss_hash_res;
2063 rep = rte_mbuf_raw_alloc(rxq->mp);
2064 if (unlikely(rep == NULL)) {
2065 ++rxq->stats.rx_nombuf;
2068 * no buffers before we even started,
2069 * bail out silently.
2073 while (pkt != seg) {
2074 assert(pkt != (*rxq->elts)[idx]);
2078 rte_mbuf_raw_free(pkt);
2084 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2085 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
2087 rte_mbuf_raw_free(rep);
2090 if (unlikely(len == -1)) {
2091 /* RX error, packet is likely too large. */
2092 rte_mbuf_raw_free(rep);
2093 ++rxq->stats.idropped;
2097 assert(len >= (rxq->crc_present << 2));
2099 /* If compressed, take hash result from mini-CQE. */
2100 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
2102 mcqe->rx_hash_result);
2103 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2104 if (rxq->crc_present)
2105 len -= RTE_ETHER_CRC_LEN;
2108 DATA_LEN(rep) = DATA_LEN(seg);
2109 PKT_LEN(rep) = PKT_LEN(seg);
2110 SET_DATA_OFF(rep, DATA_OFF(seg));
2111 PORT(rep) = PORT(seg);
2112 (*rxq->elts)[idx] = rep;
2114 * Fill NIC descriptor with the new buffer. The lkey and size
2115 * of the buffers are already known, only the buffer address
2118 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2119 /* If there's only one MR, no need to replace LKey in WQE. */
2120 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2121 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2122 if (len > DATA_LEN(seg)) {
2123 len -= DATA_LEN(seg);
2128 DATA_LEN(seg) = len;
2129 #ifdef MLX5_PMD_SOFT_COUNTERS
2130 /* Increment bytes counter. */
2131 rxq->stats.ibytes += PKT_LEN(pkt);
2133 /* Return packet. */
2139 /* Align consumer index to the next stride. */
2144 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2146 /* Update the consumer index. */
2147 rxq->rq_ci = rq_ci >> sges_n;
2149 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2151 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2152 #ifdef MLX5_PMD_SOFT_COUNTERS
2153 /* Increment packets counter. */
2154 rxq->stats.ipackets += i;
2160 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2162 struct mlx5_mprq_buf *buf = opaque;
2164 if (rte_atomic16_read(&buf->refcnt) == 1) {
2165 rte_mempool_put(buf->mp, buf);
2166 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2167 rte_atomic16_set(&buf->refcnt, 1);
2168 rte_mempool_put(buf->mp, buf);
2173 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2175 mlx5_mprq_buf_free_cb(NULL, buf);
2179 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2181 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2182 volatile struct mlx5_wqe_data_seg *wqe =
2183 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2186 assert(rep != NULL);
2187 /* Replace MPRQ buf. */
2188 (*rxq->mprq_bufs)[rq_idx] = rep;
2190 addr = mlx5_mprq_buf_addr(rep);
2191 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2192 /* If there's only one MR, no need to replace LKey in WQE. */
2193 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2194 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2195 /* Stash a mbuf for next replacement. */
2196 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2197 rxq->mprq_repl = rep;
2199 rxq->mprq_repl = NULL;
2203 * DPDK callback for RX with Multi-Packet RQ support.
2206 * Generic pointer to RX queue structure.
2208 * Array to store received packets.
2210 * Maximum number of packets in array.
2213 * Number of packets successfully received (<= pkts_n).
2216 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2218 struct mlx5_rxq_data *rxq = dpdk_rxq;
2219 const unsigned int strd_n = 1 << rxq->strd_num_n;
2220 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2221 const unsigned int strd_shift =
2222 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2223 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2224 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2225 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2227 uint32_t rq_ci = rxq->rq_ci;
2228 uint16_t consumed_strd = rxq->consumed_strd;
2229 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2231 while (i < pkts_n) {
2232 struct rte_mbuf *pkt;
2240 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2241 uint32_t rss_hash_res = 0;
2243 if (consumed_strd == strd_n) {
2244 /* Replace WQE only if the buffer is still in use. */
2245 if (rte_atomic16_read(&buf->refcnt) > 1) {
2246 mprq_buf_replace(rxq, rq_ci & wq_mask);
2247 /* Release the old buffer. */
2248 mlx5_mprq_buf_free(buf);
2249 } else if (unlikely(rxq->mprq_repl == NULL)) {
2250 struct mlx5_mprq_buf *rep;
2253 * Currently, the MPRQ mempool is out of buffer
2254 * and doing memcpy regardless of the size of Rx
2255 * packet. Retry allocation to get back to
2258 if (!rte_mempool_get(rxq->mprq_mp,
2260 rxq->mprq_repl = rep;
2262 /* Advance to the next WQE. */
2265 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2267 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2268 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2271 if (unlikely(ret == -1)) {
2272 /* RX error, packet is likely too large. */
2273 ++rxq->stats.idropped;
2277 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2278 MLX5_MPRQ_STRIDE_NUM_SHIFT;
2280 consumed_strd += strd_cnt;
2281 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2284 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2285 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2287 /* mini-CQE for MPRQ doesn't have hash result. */
2288 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2290 assert(strd_idx < strd_n);
2291 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2293 * Currently configured to receive a packet per a stride. But if
2294 * MTU is adjusted through kernel interface, device could
2295 * consume multiple strides without raising an error. In this
2296 * case, the packet should be dropped because it is bigger than
2297 * the max_rx_pkt_len.
2299 if (unlikely(strd_cnt > 1)) {
2300 ++rxq->stats.idropped;
2303 pkt = rte_pktmbuf_alloc(rxq->mp);
2304 if (unlikely(pkt == NULL)) {
2305 ++rxq->stats.rx_nombuf;
2308 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2309 assert((int)len >= (rxq->crc_present << 2));
2310 if (rxq->crc_present)
2311 len -= RTE_ETHER_CRC_LEN;
2312 offset = strd_idx * strd_sz + strd_shift;
2313 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2314 /* Initialize the offload flag. */
2317 * Memcpy packets to the target mbuf if:
2318 * - The size of packet is smaller than mprq_max_memcpy_len.
2319 * - Out of buffer in the Mempool for Multi-Packet RQ.
2321 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2323 * When memcpy'ing packet due to out-of-buffer, the
2324 * packet must be smaller than the target mbuf.
2326 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2327 rte_pktmbuf_free_seg(pkt);
2328 ++rxq->stats.idropped;
2331 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2333 rte_iova_t buf_iova;
2334 struct rte_mbuf_ext_shared_info *shinfo;
2335 uint16_t buf_len = strd_cnt * strd_sz;
2337 /* Increment the refcnt of the whole chunk. */
2338 rte_atomic16_add_return(&buf->refcnt, 1);
2339 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2341 addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2343 * MLX5 device doesn't use iova but it is necessary in a
2344 * case where the Rx packet is transmitted via a
2347 buf_iova = rte_mempool_virt2iova(buf) +
2348 RTE_PTR_DIFF(addr, buf);
2349 shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2350 &buf_len, mlx5_mprq_buf_free_cb, buf);
2352 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2353 * attaching the stride to mbuf and more offload flags
2354 * will be added below by calling rxq_cq_to_mbuf().
2355 * Other fields will be overwritten.
2357 rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2359 rte_pktmbuf_reset_headroom(pkt);
2360 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2362 * Prevent potential overflow due to MTU change through
2365 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2366 rte_pktmbuf_free_seg(pkt);
2367 ++rxq->stats.idropped;
2371 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2373 DATA_LEN(pkt) = len;
2374 PORT(pkt) = rxq->port_id;
2375 #ifdef MLX5_PMD_SOFT_COUNTERS
2376 /* Increment bytes counter. */
2377 rxq->stats.ibytes += PKT_LEN(pkt);
2379 /* Return packet. */
2383 /* Update the consumer indexes. */
2384 rxq->consumed_strd = consumed_strd;
2386 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2387 if (rq_ci != rxq->rq_ci) {
2390 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2392 #ifdef MLX5_PMD_SOFT_COUNTERS
2393 /* Increment packets counter. */
2394 rxq->stats.ipackets += i;
2400 * Dummy DPDK callback for TX.
2402 * This function is used to temporarily replace the real callback during
2403 * unsafe control operations on the queue, or in case of error.
2406 * Generic pointer to TX queue structure.
2408 * Packets to transmit.
2410 * Number of packets in array.
2413 * Number of packets successfully transmitted (<= pkts_n).
2416 removed_tx_burst(void *dpdk_txq __rte_unused,
2417 struct rte_mbuf **pkts __rte_unused,
2418 uint16_t pkts_n __rte_unused)
2425 * Dummy DPDK callback for RX.
2427 * This function is used to temporarily replace the real callback during
2428 * unsafe control operations on the queue, or in case of error.
2431 * Generic pointer to RX queue structure.
2433 * Array to store received packets.
2435 * Maximum number of packets in array.
2438 * Number of packets successfully received (<= pkts_n).
2441 removed_rx_burst(void *dpdk_txq __rte_unused,
2442 struct rte_mbuf **pkts __rte_unused,
2443 uint16_t pkts_n __rte_unused)
2450 * Vectorized Rx/Tx routines are not compiled in when required vector
2451 * instructions are not supported on a target architecture. The following null
2452 * stubs are needed for linkage when those are not included outside of this file
2453 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2457 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2458 struct rte_mbuf **pkts __rte_unused,
2459 uint16_t pkts_n __rte_unused)
2465 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2466 struct rte_mbuf **pkts __rte_unused,
2467 uint16_t pkts_n __rte_unused)
2473 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2474 struct rte_mbuf **pkts __rte_unused,
2475 uint16_t pkts_n __rte_unused)
2481 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2487 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2493 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2499 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)