4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
103 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 /* Repeat with outer_l3_type being set. Just in case. */
123 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 RTE_PTYPE_L4_NONFRAG;
127 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
179 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_UDP;
182 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_UDP;
185 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_UDP;
188 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_UDP;
194 * Return the size of tailroom of WQ.
197 * Pointer to TX queue structure.
199 * Pointer to tail of WQ.
205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
208 tailroom = (uintptr_t)(txq->wqes) +
209 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
215 * Copy data to tailroom of circular queue.
218 * Pointer to destination.
222 * Number of bytes to copy.
224 * Pointer to head of queue.
226 * Size of tailroom from dst.
229 * Pointer after copied data.
232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
233 void *base, size_t tailroom)
238 rte_memcpy(dst, src, tailroom);
239 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
241 ret = (uint8_t *)base + n - tailroom;
243 rte_memcpy(dst, src, n);
244 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
250 * DPDK callback to check the status of a tx descriptor.
255 * The index of the descriptor in the ring.
258 * The status of the tx descriptor.
261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
263 struct mlx5_txq_data *txq = tx_queue;
266 mlx5_tx_complete(txq);
267 used = txq->elts_head - txq->elts_tail;
269 return RTE_ETH_TX_DESC_FULL;
270 return RTE_ETH_TX_DESC_DONE;
274 * DPDK callback to check the status of a rx descriptor.
279 * The index of the descriptor in the ring.
282 * The status of the tx descriptor.
285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
287 struct mlx5_rxq_data *rxq = rx_queue;
288 struct rxq_zip *zip = &rxq->zip;
289 volatile struct mlx5_cqe *cqe;
290 const unsigned int cqe_n = (1 << rxq->cqe_n);
291 const unsigned int cqe_cnt = cqe_n - 1;
295 /* if we are processing a compressed cqe */
297 used = zip->cqe_cnt - zip->ca;
303 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
304 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
308 op_own = cqe->op_own;
309 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
310 n = rte_be_to_cpu_32(cqe->byte_cnt);
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
317 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
319 return RTE_ETH_RX_DESC_DONE;
320 return RTE_ETH_RX_DESC_AVAIL;
324 * DPDK callback for TX.
327 * Generic pointer to TX queue structure.
329 * Packets to transmit.
331 * Number of packets in array.
334 * Number of packets successfully transmitted (<= pkts_n).
337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
339 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
340 uint16_t elts_head = txq->elts_head;
341 const uint16_t elts_n = 1 << txq->elts_n;
342 const uint16_t elts_m = elts_n - 1;
347 unsigned int max_inline = txq->max_inline;
348 const unsigned int inline_en = !!max_inline && txq->inline_en;
351 volatile struct mlx5_wqe_v *wqe = NULL;
352 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
353 unsigned int segs_n = 0;
354 struct rte_mbuf *buf = NULL;
357 if (unlikely(!pkts_n))
359 /* Prefetch first packet cacheline. */
360 rte_prefetch0(*pkts);
361 /* Start processing. */
362 mlx5_tx_complete(txq);
363 max_elts = (elts_n - (elts_head - txq->elts_tail));
364 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
365 if (unlikely(!max_wqe))
368 volatile rte_v128u32_t *dseg = NULL;
371 unsigned int sg = 0; /* counter of additional segs attached. */
373 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
374 uint16_t tso_header_sz = 0;
376 uint8_t cs_flags = 0;
378 uint16_t tso_segsz = 0;
379 #ifdef MLX5_PMD_SOFT_COUNTERS
380 uint32_t total_length = 0;
385 segs_n = buf->nb_segs;
387 * Make sure there is enough room to store this packet and
388 * that one ring entry remains unused.
391 if (max_elts < segs_n)
395 if (unlikely(--max_wqe == 0))
397 wqe = (volatile struct mlx5_wqe_v *)
398 tx_mlx5_wqe(txq, txq->wqe_ci);
399 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
401 rte_prefetch0(*(pkts + 1));
402 addr = rte_pktmbuf_mtod(buf, uintptr_t);
403 length = DATA_LEN(buf);
404 ehdr = (((uint8_t *)addr)[1] << 8) |
405 ((uint8_t *)addr)[0];
406 #ifdef MLX5_PMD_SOFT_COUNTERS
407 total_length = length;
409 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
410 txq->stats.oerrors++;
413 /* Update element. */
414 (*txq->elts)[elts_head & elts_m] = buf;
415 /* Prefetch next buffer data. */
418 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
419 /* Should we enable HW CKSUM offload */
421 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
422 const uint64_t is_tunneled = buf->ol_flags &
424 PKT_TX_TUNNEL_VXLAN);
426 if (is_tunneled && txq->tunnel_en) {
427 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
428 MLX5_ETH_WQE_L4_INNER_CSUM;
429 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
430 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
432 cs_flags = MLX5_ETH_WQE_L3_CSUM |
433 MLX5_ETH_WQE_L4_CSUM;
436 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
437 /* Replace the Ethernet type by the VLAN if necessary. */
438 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
439 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
441 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
445 /* Copy Destination and source mac address. */
446 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
448 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
449 /* Copy missing two bytes to end the DSeg. */
450 memcpy((uint8_t *)raw + len + sizeof(vlan),
451 ((uint8_t *)addr) + len, 2);
455 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
456 MLX5_WQE_DWORD_SIZE);
457 length -= pkt_inline_sz;
458 addr += pkt_inline_sz;
460 raw += MLX5_WQE_DWORD_SIZE;
462 tso = buf->ol_flags & PKT_TX_TCP_SEG;
464 uintptr_t end = (uintptr_t)
465 (((uintptr_t)txq->wqes) +
469 uint8_t vlan_sz = (buf->ol_flags &
470 PKT_TX_VLAN_PKT) ? 4 : 0;
471 const uint64_t is_tunneled =
474 PKT_TX_TUNNEL_VXLAN);
476 tso_header_sz = buf->l2_len + vlan_sz +
477 buf->l3_len + buf->l4_len;
478 tso_segsz = buf->tso_segsz;
479 if (unlikely(tso_segsz == 0)) {
480 txq->stats.oerrors++;
483 if (is_tunneled && txq->tunnel_en) {
484 tso_header_sz += buf->outer_l2_len +
486 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
488 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
490 if (unlikely(tso_header_sz >
491 MLX5_MAX_TSO_HEADER)) {
492 txq->stats.oerrors++;
495 copy_b = tso_header_sz - pkt_inline_sz;
496 /* First seg must contain all headers. */
497 assert(copy_b <= length);
499 ((end - (uintptr_t)raw) > copy_b)) {
500 uint16_t n = (MLX5_WQE_DS(copy_b) -
503 if (unlikely(max_wqe < n))
506 rte_memcpy((void *)raw,
507 (void *)addr, copy_b);
510 /* Include padding for TSO header. */
511 copy_b = MLX5_WQE_DS(copy_b) *
513 pkt_inline_sz += copy_b;
517 wqe->ctrl = (rte_v128u32_t){
526 #ifdef MLX5_PMD_SOFT_COUNTERS
534 /* Inline if enough room. */
535 if (inline_en || tso) {
537 uintptr_t end = (uintptr_t)
538 (((uintptr_t)txq->wqes) +
539 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
540 unsigned int inline_room = max_inline *
541 RTE_CACHE_LINE_SIZE -
542 (pkt_inline_sz - 2) -
544 uintptr_t addr_end = (addr + inline_room) &
545 ~(RTE_CACHE_LINE_SIZE - 1);
546 unsigned int copy_b = (addr_end > addr) ?
547 RTE_MIN((addr_end - addr), length) :
550 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
552 * One Dseg remains in the current WQE. To
553 * keep the computation positive, it is
554 * removed after the bytes to Dseg conversion.
556 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
558 if (unlikely(max_wqe < n))
562 inl = rte_cpu_to_be_32(copy_b |
564 rte_memcpy((void *)raw,
565 (void *)&inl, sizeof(inl));
567 pkt_inline_sz += sizeof(inl);
569 rte_memcpy((void *)raw, (void *)addr, copy_b);
572 pkt_inline_sz += copy_b;
575 * 2 DWORDs consumed by the WQE header + ETH segment +
576 * the size of the inline part of the packet.
578 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
580 if (ds % (MLX5_WQE_SIZE /
581 MLX5_WQE_DWORD_SIZE) == 0) {
582 if (unlikely(--max_wqe == 0))
584 dseg = (volatile rte_v128u32_t *)
585 tx_mlx5_wqe(txq, txq->wqe_ci +
588 dseg = (volatile rte_v128u32_t *)
590 (ds * MLX5_WQE_DWORD_SIZE));
593 } else if (!segs_n) {
596 /* dseg will be advance as part of next_seg */
597 dseg = (volatile rte_v128u32_t *)
599 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
604 * No inline has been done in the packet, only the
605 * Ethernet Header as been stored.
607 dseg = (volatile rte_v128u32_t *)
608 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
611 /* Add the remaining packet as a simple ds. */
612 addr = rte_cpu_to_be_64(addr);
613 *dseg = (rte_v128u32_t){
614 rte_cpu_to_be_32(length),
615 mlx5_tx_mb2mr(txq, buf),
628 * Spill on next WQE when the current one does not have
629 * enough room left. Size of WQE must a be a multiple
630 * of data segment size.
632 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
633 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
634 if (unlikely(--max_wqe == 0))
636 dseg = (volatile rte_v128u32_t *)
637 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
638 rte_prefetch0(tx_mlx5_wqe(txq,
639 txq->wqe_ci + ds / 4 + 1));
646 length = DATA_LEN(buf);
647 #ifdef MLX5_PMD_SOFT_COUNTERS
648 total_length += length;
650 /* Store segment information. */
651 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
652 *dseg = (rte_v128u32_t){
653 rte_cpu_to_be_32(length),
654 mlx5_tx_mb2mr(txq, buf),
658 (*txq->elts)[++elts_head & elts_m] = buf;
660 /* Advance counter only if all segs are successfully posted. */
666 if (ds > MLX5_DSEG_MAX) {
667 txq->stats.oerrors++;
673 /* Initialize known and common part of the WQE structure. */
675 wqe->ctrl = (rte_v128u32_t){
676 rte_cpu_to_be_32((txq->wqe_ci << 8) |
678 rte_cpu_to_be_32(txq->qp_num_8s | ds),
682 wqe->eseg = (rte_v128u32_t){
684 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
686 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
689 wqe->ctrl = (rte_v128u32_t){
690 rte_cpu_to_be_32((txq->wqe_ci << 8) |
692 rte_cpu_to_be_32(txq->qp_num_8s | ds),
696 wqe->eseg = (rte_v128u32_t){
700 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
704 txq->wqe_ci += (ds + 3) / 4;
705 /* Save the last successful WQE for completion request */
706 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
707 #ifdef MLX5_PMD_SOFT_COUNTERS
708 /* Increment sent bytes counter. */
709 txq->stats.obytes += total_length;
711 } while (i < pkts_n);
712 /* Take a shortcut if nothing must be sent. */
713 if (unlikely((i + k) == 0))
715 txq->elts_head += (i + j);
716 /* Check whether completion threshold has been reached. */
717 comp = txq->elts_comp + i + j + k;
718 if (comp >= MLX5_TX_COMP_THRESH) {
719 /* Request completion on last WQE. */
720 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
721 /* Save elts_head in unused "immediate" field of WQE. */
722 last_wqe->ctrl3 = txq->elts_head;
725 txq->elts_comp = comp;
727 #ifdef MLX5_PMD_SOFT_COUNTERS
728 /* Increment sent packets counter. */
729 txq->stats.opackets += i;
731 /* Ring QP doorbell. */
732 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
737 * Open a MPW session.
740 * Pointer to TX queue structure.
742 * Pointer to MPW session structure.
747 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
749 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
750 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
751 (volatile struct mlx5_wqe_data_seg (*)[])
752 tx_mlx5_wqe(txq, idx + 1);
754 mpw->state = MLX5_MPW_STATE_OPENED;
758 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
759 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
760 mpw->wqe->eseg.inline_hdr_sz = 0;
761 mpw->wqe->eseg.rsvd0 = 0;
762 mpw->wqe->eseg.rsvd1 = 0;
763 mpw->wqe->eseg.rsvd2 = 0;
764 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
767 mpw->wqe->ctrl[2] = 0;
768 mpw->wqe->ctrl[3] = 0;
769 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
770 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
771 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
772 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
773 mpw->data.dseg[2] = &(*dseg)[0];
774 mpw->data.dseg[3] = &(*dseg)[1];
775 mpw->data.dseg[4] = &(*dseg)[2];
779 * Close a MPW session.
782 * Pointer to TX queue structure.
784 * Pointer to MPW session structure.
787 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
789 unsigned int num = mpw->pkts_n;
792 * Store size in multiple of 16 bytes. Control and Ethernet segments
795 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
796 mpw->state = MLX5_MPW_STATE_CLOSED;
801 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
802 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
806 * DPDK callback for TX with MPW support.
809 * Generic pointer to TX queue structure.
811 * Packets to transmit.
813 * Number of packets in array.
816 * Number of packets successfully transmitted (<= pkts_n).
819 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
821 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
822 uint16_t elts_head = txq->elts_head;
823 const uint16_t elts_n = 1 << txq->elts_n;
824 const uint16_t elts_m = elts_n - 1;
830 struct mlx5_mpw mpw = {
831 .state = MLX5_MPW_STATE_CLOSED,
834 if (unlikely(!pkts_n))
836 /* Prefetch first packet cacheline. */
837 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
838 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
839 /* Start processing. */
840 mlx5_tx_complete(txq);
841 max_elts = (elts_n - (elts_head - txq->elts_tail));
842 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
843 if (unlikely(!max_wqe))
846 struct rte_mbuf *buf = *(pkts++);
848 unsigned int segs_n = buf->nb_segs;
849 uint32_t cs_flags = 0;
852 * Make sure there is enough room to store this packet and
853 * that one ring entry remains unused.
856 if (max_elts < segs_n)
858 /* Do not bother with large packets MPW cannot handle. */
859 if (segs_n > MLX5_MPW_DSEG_MAX) {
860 txq->stats.oerrors++;
865 /* Should we enable HW CKSUM offload */
867 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
868 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
869 /* Retrieve packet information. */
870 length = PKT_LEN(buf);
872 /* Start new session if packet differs. */
873 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
874 ((mpw.len != length) ||
876 (mpw.wqe->eseg.cs_flags != cs_flags)))
877 mlx5_mpw_close(txq, &mpw);
878 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
880 * Multi-Packet WQE consumes at most two WQE.
881 * mlx5_mpw_new() expects to be able to use such
884 if (unlikely(max_wqe < 2))
887 mlx5_mpw_new(txq, &mpw, length);
888 mpw.wqe->eseg.cs_flags = cs_flags;
890 /* Multi-segment packets must be alone in their MPW. */
891 assert((segs_n == 1) || (mpw.pkts_n == 0));
892 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
896 volatile struct mlx5_wqe_data_seg *dseg;
900 (*txq->elts)[elts_head++ & elts_m] = buf;
901 dseg = mpw.data.dseg[mpw.pkts_n];
902 addr = rte_pktmbuf_mtod(buf, uintptr_t);
903 *dseg = (struct mlx5_wqe_data_seg){
904 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
905 .lkey = mlx5_tx_mb2mr(txq, buf),
906 .addr = rte_cpu_to_be_64(addr),
908 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
909 length += DATA_LEN(buf);
915 assert(length == mpw.len);
916 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
917 mlx5_mpw_close(txq, &mpw);
918 #ifdef MLX5_PMD_SOFT_COUNTERS
919 /* Increment sent bytes counter. */
920 txq->stats.obytes += length;
924 /* Take a shortcut if nothing must be sent. */
925 if (unlikely(i == 0))
927 /* Check whether completion threshold has been reached. */
928 /* "j" includes both packets and segments. */
929 comp = txq->elts_comp + j;
930 if (comp >= MLX5_TX_COMP_THRESH) {
931 volatile struct mlx5_wqe *wqe = mpw.wqe;
933 /* Request completion on last WQE. */
934 wqe->ctrl[2] = rte_cpu_to_be_32(8);
935 /* Save elts_head in unused "immediate" field of WQE. */
936 wqe->ctrl[3] = elts_head;
939 txq->elts_comp = comp;
941 #ifdef MLX5_PMD_SOFT_COUNTERS
942 /* Increment sent packets counter. */
943 txq->stats.opackets += i;
945 /* Ring QP doorbell. */
946 if (mpw.state == MLX5_MPW_STATE_OPENED)
947 mlx5_mpw_close(txq, &mpw);
948 mlx5_tx_dbrec(txq, mpw.wqe);
949 txq->elts_head = elts_head;
954 * Open a MPW inline session.
957 * Pointer to TX queue structure.
959 * Pointer to MPW session structure.
964 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
967 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
968 struct mlx5_wqe_inl_small *inl;
970 mpw->state = MLX5_MPW_INL_STATE_OPENED;
974 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
975 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
978 mpw->wqe->ctrl[2] = 0;
979 mpw->wqe->ctrl[3] = 0;
980 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
981 mpw->wqe->eseg.inline_hdr_sz = 0;
982 mpw->wqe->eseg.cs_flags = 0;
983 mpw->wqe->eseg.rsvd0 = 0;
984 mpw->wqe->eseg.rsvd1 = 0;
985 mpw->wqe->eseg.rsvd2 = 0;
986 inl = (struct mlx5_wqe_inl_small *)
987 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
988 mpw->data.raw = (uint8_t *)&inl->raw;
992 * Close a MPW inline session.
995 * Pointer to TX queue structure.
997 * Pointer to MPW session structure.
1000 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1003 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1004 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1006 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1008 * Store size in multiple of 16 bytes. Control and Ethernet segments
1011 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1013 mpw->state = MLX5_MPW_STATE_CLOSED;
1014 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1015 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1019 * DPDK callback for TX with MPW inline support.
1022 * Generic pointer to TX queue structure.
1024 * Packets to transmit.
1026 * Number of packets in array.
1029 * Number of packets successfully transmitted (<= pkts_n).
1032 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1035 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1036 uint16_t elts_head = txq->elts_head;
1037 const uint16_t elts_n = 1 << txq->elts_n;
1038 const uint16_t elts_m = elts_n - 1;
1044 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1045 struct mlx5_mpw mpw = {
1046 .state = MLX5_MPW_STATE_CLOSED,
1049 * Compute the maximum number of WQE which can be consumed by inline
1052 * - 1 control segment,
1053 * - 1 Ethernet segment,
1054 * - N Dseg from the inline request.
1056 const unsigned int wqe_inl_n =
1057 ((2 * MLX5_WQE_DWORD_SIZE +
1058 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1059 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1061 if (unlikely(!pkts_n))
1063 /* Prefetch first packet cacheline. */
1064 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1065 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1066 /* Start processing. */
1067 mlx5_tx_complete(txq);
1068 max_elts = (elts_n - (elts_head - txq->elts_tail));
1070 struct rte_mbuf *buf = *(pkts++);
1073 unsigned int segs_n = buf->nb_segs;
1074 uint32_t cs_flags = 0;
1077 * Make sure there is enough room to store this packet and
1078 * that one ring entry remains unused.
1081 if (max_elts < segs_n)
1083 /* Do not bother with large packets MPW cannot handle. */
1084 if (segs_n > MLX5_MPW_DSEG_MAX) {
1085 txq->stats.oerrors++;
1091 * Compute max_wqe in case less WQE were consumed in previous
1094 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1095 /* Should we enable HW CKSUM offload */
1097 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1098 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1099 /* Retrieve packet information. */
1100 length = PKT_LEN(buf);
1101 /* Start new session if packet differs. */
1102 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1103 if ((mpw.len != length) ||
1105 (mpw.wqe->eseg.cs_flags != cs_flags))
1106 mlx5_mpw_close(txq, &mpw);
1107 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1108 if ((mpw.len != length) ||
1110 (length > inline_room) ||
1111 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1112 mlx5_mpw_inline_close(txq, &mpw);
1114 txq->max_inline * RTE_CACHE_LINE_SIZE;
1117 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1118 if ((segs_n != 1) ||
1119 (length > inline_room)) {
1121 * Multi-Packet WQE consumes at most two WQE.
1122 * mlx5_mpw_new() expects to be able to use
1125 if (unlikely(max_wqe < 2))
1128 mlx5_mpw_new(txq, &mpw, length);
1129 mpw.wqe->eseg.cs_flags = cs_flags;
1131 if (unlikely(max_wqe < wqe_inl_n))
1133 max_wqe -= wqe_inl_n;
1134 mlx5_mpw_inline_new(txq, &mpw, length);
1135 mpw.wqe->eseg.cs_flags = cs_flags;
1138 /* Multi-segment packets must be alone in their MPW. */
1139 assert((segs_n == 1) || (mpw.pkts_n == 0));
1140 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1141 assert(inline_room ==
1142 txq->max_inline * RTE_CACHE_LINE_SIZE);
1143 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1147 volatile struct mlx5_wqe_data_seg *dseg;
1150 (*txq->elts)[elts_head++ & elts_m] = buf;
1151 dseg = mpw.data.dseg[mpw.pkts_n];
1152 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1153 *dseg = (struct mlx5_wqe_data_seg){
1155 rte_cpu_to_be_32(DATA_LEN(buf)),
1156 .lkey = mlx5_tx_mb2mr(txq, buf),
1157 .addr = rte_cpu_to_be_64(addr),
1159 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1160 length += DATA_LEN(buf);
1166 assert(length == mpw.len);
1167 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1168 mlx5_mpw_close(txq, &mpw);
1172 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1173 assert(length <= inline_room);
1174 assert(length == DATA_LEN(buf));
1175 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1176 (*txq->elts)[elts_head++ & elts_m] = buf;
1177 /* Maximum number of bytes before wrapping. */
1178 max = ((((uintptr_t)(txq->wqes)) +
1181 (uintptr_t)mpw.data.raw);
1183 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1186 mpw.data.raw = (volatile void *)txq->wqes;
1187 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1188 (void *)(addr + max),
1190 mpw.data.raw += length - max;
1192 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1198 (volatile void *)txq->wqes;
1200 mpw.data.raw += length;
1203 mpw.total_len += length;
1205 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1206 mlx5_mpw_inline_close(txq, &mpw);
1208 txq->max_inline * RTE_CACHE_LINE_SIZE;
1210 inline_room -= length;
1213 #ifdef MLX5_PMD_SOFT_COUNTERS
1214 /* Increment sent bytes counter. */
1215 txq->stats.obytes += length;
1219 /* Take a shortcut if nothing must be sent. */
1220 if (unlikely(i == 0))
1222 /* Check whether completion threshold has been reached. */
1223 /* "j" includes both packets and segments. */
1224 comp = txq->elts_comp + j;
1225 if (comp >= MLX5_TX_COMP_THRESH) {
1226 volatile struct mlx5_wqe *wqe = mpw.wqe;
1228 /* Request completion on last WQE. */
1229 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1230 /* Save elts_head in unused "immediate" field of WQE. */
1231 wqe->ctrl[3] = elts_head;
1234 txq->elts_comp = comp;
1236 #ifdef MLX5_PMD_SOFT_COUNTERS
1237 /* Increment sent packets counter. */
1238 txq->stats.opackets += i;
1240 /* Ring QP doorbell. */
1241 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1242 mlx5_mpw_inline_close(txq, &mpw);
1243 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1244 mlx5_mpw_close(txq, &mpw);
1245 mlx5_tx_dbrec(txq, mpw.wqe);
1246 txq->elts_head = elts_head;
1251 * Open an Enhanced MPW session.
1254 * Pointer to TX queue structure.
1256 * Pointer to MPW session structure.
1261 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1263 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1265 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1267 mpw->total_len = sizeof(struct mlx5_wqe);
1268 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1270 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1271 (txq->wqe_ci << 8) |
1272 MLX5_OPCODE_ENHANCED_MPSW);
1273 mpw->wqe->ctrl[2] = 0;
1274 mpw->wqe->ctrl[3] = 0;
1275 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1276 if (unlikely(padding)) {
1277 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1279 /* Pad the first 2 DWORDs with zero-length inline header. */
1280 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1281 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1282 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1283 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1284 /* Start from the next WQEBB. */
1285 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1287 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1292 * Close an Enhanced MPW session.
1295 * Pointer to TX queue structure.
1297 * Pointer to MPW session structure.
1300 * Number of consumed WQEs.
1302 static inline uint16_t
1303 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1307 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1310 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1311 MLX5_WQE_DS(mpw->total_len));
1312 mpw->state = MLX5_MPW_STATE_CLOSED;
1313 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1319 * DPDK callback for TX with Enhanced MPW support.
1322 * Generic pointer to TX queue structure.
1324 * Packets to transmit.
1326 * Number of packets in array.
1329 * Number of packets successfully transmitted (<= pkts_n).
1332 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1334 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1335 uint16_t elts_head = txq->elts_head;
1336 const uint16_t elts_n = 1 << txq->elts_n;
1337 const uint16_t elts_m = elts_n - 1;
1342 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1343 unsigned int mpw_room = 0;
1344 unsigned int inl_pad = 0;
1346 struct mlx5_mpw mpw = {
1347 .state = MLX5_MPW_STATE_CLOSED,
1350 if (unlikely(!pkts_n))
1352 /* Start processing. */
1353 mlx5_tx_complete(txq);
1354 max_elts = (elts_n - (elts_head - txq->elts_tail));
1355 /* A CQE slot must always be available. */
1356 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1357 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1358 if (unlikely(!max_wqe))
1361 struct rte_mbuf *buf = *(pkts++);
1364 unsigned int do_inline = 0; /* Whether inline is possible. */
1366 unsigned int segs_n = buf->nb_segs;
1367 uint32_t cs_flags = 0;
1370 * Make sure there is enough room to store this packet and
1371 * that one ring entry remains unused.
1374 if (max_elts - j < segs_n)
1376 /* Do not bother with large packets MPW cannot handle. */
1377 if (segs_n > MLX5_MPW_DSEG_MAX) {
1378 txq->stats.oerrors++;
1381 /* Should we enable HW CKSUM offload. */
1383 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1384 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1385 /* Retrieve packet information. */
1386 length = PKT_LEN(buf);
1387 /* Start new session if:
1388 * - multi-segment packet
1389 * - no space left even for a dseg
1390 * - next packet can be inlined with a new WQE
1392 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1395 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1396 if ((segs_n != 1) ||
1397 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1399 (length <= txq->inline_max_packet_sz &&
1400 inl_pad + sizeof(inl_hdr) + length >
1402 (mpw.wqe->eseg.cs_flags != cs_flags))
1403 max_wqe -= mlx5_empw_close(txq, &mpw);
1405 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1406 if (unlikely(segs_n != 1)) {
1407 /* Fall back to legacy MPW.
1408 * A MPW session consumes 2 WQEs at most to
1409 * include MLX5_MPW_DSEG_MAX pointers.
1411 if (unlikely(max_wqe < 2))
1413 mlx5_mpw_new(txq, &mpw, length);
1415 /* In Enhanced MPW, inline as much as the budget
1416 * is allowed. The remaining space is to be
1417 * filled with dsegs. If the title WQEBB isn't
1418 * padded, it will have 2 dsegs there.
1420 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1421 (max_inline ? max_inline :
1422 pkts_n * MLX5_WQE_DWORD_SIZE) +
1424 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1427 /* Don't pad the title WQEBB to not waste WQ. */
1428 mlx5_empw_new(txq, &mpw, 0);
1429 mpw_room -= mpw.total_len;
1432 length <= txq->inline_max_packet_sz &&
1433 sizeof(inl_hdr) + length <= mpw_room &&
1436 mpw.wqe->eseg.cs_flags = cs_flags;
1438 /* Evaluate whether the next packet can be inlined.
1439 * Inlininig is possible when:
1440 * - length is less than configured value
1441 * - length fits for remaining space
1442 * - not required to fill the title WQEBB with dsegs
1445 length <= txq->inline_max_packet_sz &&
1446 inl_pad + sizeof(inl_hdr) + length <=
1448 (!txq->mpw_hdr_dseg ||
1449 mpw.total_len >= MLX5_WQE_SIZE);
1451 /* Multi-segment packets must be alone in their MPW. */
1452 assert((segs_n == 1) || (mpw.pkts_n == 0));
1453 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1454 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1458 volatile struct mlx5_wqe_data_seg *dseg;
1461 (*txq->elts)[elts_head++ & elts_m] = buf;
1462 dseg = mpw.data.dseg[mpw.pkts_n];
1463 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1464 *dseg = (struct mlx5_wqe_data_seg){
1465 .byte_count = rte_cpu_to_be_32(
1467 .lkey = mlx5_tx_mb2mr(txq, buf),
1468 .addr = rte_cpu_to_be_64(addr),
1470 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1471 length += DATA_LEN(buf);
1477 /* A multi-segmented packet takes one MPW session.
1478 * TODO: Pack more multi-segmented packets if possible.
1480 mlx5_mpw_close(txq, &mpw);
1485 } else if (do_inline) {
1486 /* Inline packet into WQE. */
1489 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1490 assert(length == DATA_LEN(buf));
1491 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1492 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1493 mpw.data.raw = (volatile void *)
1494 ((uintptr_t)mpw.data.raw + inl_pad);
1495 max = tx_mlx5_wq_tailroom(txq,
1496 (void *)(uintptr_t)mpw.data.raw);
1497 /* Copy inline header. */
1498 mpw.data.raw = (volatile void *)
1500 (void *)(uintptr_t)mpw.data.raw,
1503 (void *)(uintptr_t)txq->wqes,
1505 max = tx_mlx5_wq_tailroom(txq,
1506 (void *)(uintptr_t)mpw.data.raw);
1507 /* Copy packet data. */
1508 mpw.data.raw = (volatile void *)
1510 (void *)(uintptr_t)mpw.data.raw,
1513 (void *)(uintptr_t)txq->wqes,
1516 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1517 /* No need to get completion as the entire packet is
1518 * copied to WQ. Free the buf right away.
1520 rte_pktmbuf_free_seg(buf);
1521 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1522 /* Add pad in the next packet if any. */
1523 inl_pad = (((uintptr_t)mpw.data.raw +
1524 (MLX5_WQE_DWORD_SIZE - 1)) &
1525 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1526 (uintptr_t)mpw.data.raw;
1528 /* No inline. Load a dseg of packet pointer. */
1529 volatile rte_v128u32_t *dseg;
1531 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1532 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1533 assert(length == DATA_LEN(buf));
1534 if (!tx_mlx5_wq_tailroom(txq,
1535 (void *)((uintptr_t)mpw.data.raw
1537 dseg = (volatile void *)txq->wqes;
1539 dseg = (volatile void *)
1540 ((uintptr_t)mpw.data.raw +
1542 (*txq->elts)[elts_head++ & elts_m] = buf;
1543 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1544 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1545 rte_prefetch2((void *)(addr +
1546 n * RTE_CACHE_LINE_SIZE));
1547 addr = rte_cpu_to_be_64(addr);
1548 *dseg = (rte_v128u32_t) {
1549 rte_cpu_to_be_32(length),
1550 mlx5_tx_mb2mr(txq, buf),
1554 mpw.data.raw = (volatile void *)(dseg + 1);
1555 mpw.total_len += (inl_pad + sizeof(*dseg));
1558 mpw_room -= (inl_pad + sizeof(*dseg));
1561 #ifdef MLX5_PMD_SOFT_COUNTERS
1562 /* Increment sent bytes counter. */
1563 txq->stats.obytes += length;
1566 } while (i < pkts_n);
1567 /* Take a shortcut if nothing must be sent. */
1568 if (unlikely(i == 0))
1570 /* Check whether completion threshold has been reached. */
1571 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1572 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1573 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1574 volatile struct mlx5_wqe *wqe = mpw.wqe;
1576 /* Request completion on last WQE. */
1577 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1578 /* Save elts_head in unused "immediate" field of WQE. */
1579 wqe->ctrl[3] = elts_head;
1581 txq->mpw_comp = txq->wqe_ci;
1584 txq->elts_comp += j;
1586 #ifdef MLX5_PMD_SOFT_COUNTERS
1587 /* Increment sent packets counter. */
1588 txq->stats.opackets += i;
1590 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1591 mlx5_empw_close(txq, &mpw);
1592 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1593 mlx5_mpw_close(txq, &mpw);
1594 /* Ring QP doorbell. */
1595 mlx5_tx_dbrec(txq, mpw.wqe);
1596 txq->elts_head = elts_head;
1601 * Translate RX completion flags to packet type.
1606 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1609 * Packet type for struct rte_mbuf.
1611 static inline uint32_t
1612 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1615 uint8_t pinfo = cqe->pkt_info;
1616 uint16_t ptype = cqe->hdr_type_etc;
1619 * The index to the array should have:
1620 * bit[1:0] = l3_hdr_type
1621 * bit[4:2] = l4_hdr_type
1624 * bit[7] = outer_l3_type
1626 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1627 return mlx5_ptype_table[idx];
1631 * Get size of the next packet for a given CQE. For compressed CQEs, the
1632 * consumer index is updated only once all packets of the current one have
1636 * Pointer to RX queue.
1639 * @param[out] rss_hash
1640 * Packet RSS Hash result.
1643 * Packet size in bytes (0 if there is none), -1 in case of completion
1647 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1648 uint16_t cqe_cnt, uint32_t *rss_hash)
1650 struct rxq_zip *zip = &rxq->zip;
1651 uint16_t cqe_n = cqe_cnt + 1;
1655 /* Process compressed data in the CQE and mini arrays. */
1657 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1658 (volatile struct mlx5_mini_cqe8 (*)[8])
1659 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1661 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1662 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1663 if ((++zip->ai & 7) == 0) {
1664 /* Invalidate consumed CQEs */
1667 while (idx != end) {
1668 (*rxq->cqes)[idx & cqe_cnt].op_own =
1669 MLX5_CQE_INVALIDATE;
1673 * Increment consumer index to skip the number of
1674 * CQEs consumed. Hardware leaves holes in the CQ
1675 * ring for software use.
1680 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1681 /* Invalidate the rest */
1685 while (idx != end) {
1686 (*rxq->cqes)[idx & cqe_cnt].op_own =
1687 MLX5_CQE_INVALIDATE;
1690 rxq->cq_ci = zip->cq_ci;
1693 /* No compressed data, get next CQE and verify if it is compressed. */
1698 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1699 if (unlikely(ret == 1))
1702 op_own = cqe->op_own;
1703 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1704 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1705 (volatile struct mlx5_mini_cqe8 (*)[8])
1706 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1709 /* Fix endianness. */
1710 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1712 * Current mini array position is the one returned by
1715 * If completion comprises several mini arrays, as a
1716 * special case the second one is located 7 CQEs after
1717 * the initial CQE instead of 8 for subsequent ones.
1719 zip->ca = rxq->cq_ci;
1720 zip->na = zip->ca + 7;
1721 /* Compute the next non compressed CQE. */
1723 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1724 /* Get packet size to return. */
1725 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1726 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1728 /* Prefetch all the entries to be invalidated */
1731 while (idx != end) {
1732 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1736 len = rte_be_to_cpu_32(cqe->byte_cnt);
1737 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1739 /* Error while receiving packet. */
1740 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1747 * Translate RX completion flags to offload flags.
1750 * Pointer to RX queue structure.
1755 * Offload flags (ol_flags) for struct rte_mbuf.
1757 static inline uint32_t
1758 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1760 uint32_t ol_flags = 0;
1761 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1765 MLX5_CQE_RX_L3_HDR_VALID,
1766 PKT_RX_IP_CKSUM_GOOD) |
1768 MLX5_CQE_RX_L4_HDR_VALID,
1769 PKT_RX_L4_CKSUM_GOOD);
1770 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1773 MLX5_CQE_RX_L3_HDR_VALID,
1774 PKT_RX_IP_CKSUM_GOOD) |
1776 MLX5_CQE_RX_L4_HDR_VALID,
1777 PKT_RX_L4_CKSUM_GOOD);
1782 * DPDK callback for RX.
1785 * Generic pointer to RX queue structure.
1787 * Array to store received packets.
1789 * Maximum number of packets in array.
1792 * Number of packets successfully received (<= pkts_n).
1795 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1797 struct mlx5_rxq_data *rxq = dpdk_rxq;
1798 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1799 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1800 const unsigned int sges_n = rxq->sges_n;
1801 struct rte_mbuf *pkt = NULL;
1802 struct rte_mbuf *seg = NULL;
1803 volatile struct mlx5_cqe *cqe =
1804 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1806 unsigned int rq_ci = rxq->rq_ci << sges_n;
1807 int len = 0; /* keep its value across iterations. */
1810 unsigned int idx = rq_ci & wqe_cnt;
1811 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1812 struct rte_mbuf *rep = (*rxq->elts)[idx];
1813 uint32_t rss_hash_res = 0;
1821 rep = rte_mbuf_raw_alloc(rxq->mp);
1822 if (unlikely(rep == NULL)) {
1823 ++rxq->stats.rx_nombuf;
1826 * no buffers before we even started,
1827 * bail out silently.
1831 while (pkt != seg) {
1832 assert(pkt != (*rxq->elts)[idx]);
1836 rte_mbuf_raw_free(pkt);
1842 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1843 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1846 rte_mbuf_raw_free(rep);
1849 if (unlikely(len == -1)) {
1850 /* RX error, packet is likely too large. */
1851 rte_mbuf_raw_free(rep);
1852 ++rxq->stats.idropped;
1856 assert(len >= (rxq->crc_present << 2));
1857 /* Update packet information. */
1858 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1860 if (rss_hash_res && rxq->rss_hash) {
1861 pkt->hash.rss = rss_hash_res;
1862 pkt->ol_flags = PKT_RX_RSS_HASH;
1865 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1866 pkt->ol_flags |= PKT_RX_FDIR;
1867 if (cqe->sop_drop_qpn !=
1868 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1869 uint32_t mark = cqe->sop_drop_qpn;
1871 pkt->ol_flags |= PKT_RX_FDIR_ID;
1873 mlx5_flow_mark_get(mark);
1876 if (rxq->csum | rxq->csum_l2tun)
1877 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1878 if (rxq->vlan_strip &&
1879 (cqe->hdr_type_etc &
1880 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1881 pkt->ol_flags |= PKT_RX_VLAN |
1882 PKT_RX_VLAN_STRIPPED;
1884 rte_be_to_cpu_16(cqe->vlan_info);
1886 if (rxq->hw_timestamp) {
1888 rte_be_to_cpu_64(cqe->timestamp);
1889 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1891 if (rxq->crc_present)
1892 len -= ETHER_CRC_LEN;
1895 DATA_LEN(rep) = DATA_LEN(seg);
1896 PKT_LEN(rep) = PKT_LEN(seg);
1897 SET_DATA_OFF(rep, DATA_OFF(seg));
1898 PORT(rep) = PORT(seg);
1899 (*rxq->elts)[idx] = rep;
1901 * Fill NIC descriptor with the new buffer. The lkey and size
1902 * of the buffers are already known, only the buffer address
1905 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1906 if (len > DATA_LEN(seg)) {
1907 len -= DATA_LEN(seg);
1912 DATA_LEN(seg) = len;
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914 /* Increment bytes counter. */
1915 rxq->stats.ibytes += PKT_LEN(pkt);
1917 /* Return packet. */
1923 /* Align consumer index to the next stride. */
1928 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1930 /* Update the consumer index. */
1931 rxq->rq_ci = rq_ci >> sges_n;
1933 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1935 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1936 #ifdef MLX5_PMD_SOFT_COUNTERS
1937 /* Increment packets counter. */
1938 rxq->stats.ipackets += i;
1944 * Dummy DPDK callback for TX.
1946 * This function is used to temporarily replace the real callback during
1947 * unsafe control operations on the queue, or in case of error.
1950 * Generic pointer to TX queue structure.
1952 * Packets to transmit.
1954 * Number of packets in array.
1957 * Number of packets successfully transmitted (<= pkts_n).
1960 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1969 * Dummy DPDK callback for RX.
1971 * This function is used to temporarily replace the real callback during
1972 * unsafe control operations on the queue, or in case of error.
1975 * Generic pointer to RX queue structure.
1977 * Array to store received packets.
1979 * Maximum number of packets in array.
1982 * Number of packets successfully received (<= pkts_n).
1985 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1994 * Vectorized Rx/Tx routines are not compiled in when required vector
1995 * instructions are not supported on a target architecture. The following null
1996 * stubs are needed for linkage when those are not included outside of this file
1997 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2000 uint16_t __attribute__((weak))
2001 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2009 uint16_t __attribute__((weak))
2010 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2018 uint16_t __attribute__((weak))
2019 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2027 int __attribute__((weak))
2028 priv_check_raw_vec_tx_support(struct priv *priv)
2034 int __attribute__((weak))
2035 priv_check_vec_tx_support(struct priv *priv)
2041 int __attribute__((weak))
2042 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2048 int __attribute__((weak))
2049 priv_check_vec_rx_support(struct priv *priv)