4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 txq->wqe_pi = ntohs(cqe->wqe_counter);
242 ctrl = (volatile struct mlx5_wqe_ctrl *)
243 tx_mlx5_wqe(txq, txq->wqe_pi);
244 elts_tail = ctrl->ctrl3;
245 assert(elts_tail < (1 << txq->wqe_n));
247 while (elts_free != elts_tail) {
248 struct rte_mbuf *elt = (*txq->elts)[elts_free];
249 unsigned int elts_free_next =
250 (elts_free + 1) & (elts_n - 1);
251 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
255 memset(&(*txq->elts)[elts_free],
257 sizeof((*txq->elts)[elts_free]));
259 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
260 /* Only one segment needs to be freed. */
261 rte_pktmbuf_free_seg(elt);
262 elts_free = elts_free_next;
265 txq->elts_tail = elts_tail;
266 /* Update the consumer index. */
268 *txq->cq_db = htonl(cq_ci);
272 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
273 * the cloned mbuf is allocated is returned instead.
279 * Memory pool where data is located for given mbuf.
281 static struct rte_mempool *
282 txq_mb2mp(struct rte_mbuf *buf)
284 if (unlikely(RTE_MBUF_INDIRECT(buf)))
285 return rte_mbuf_from_indirect(buf)->pool;
290 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
291 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
292 * remove an entry first.
295 * Pointer to TX queue structure.
297 * Memory Pool for which a Memory Region lkey must be returned.
300 * mr->lkey on success, (uint32_t)-1 on failure.
302 static inline uint32_t
303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
306 uint32_t lkey = (uint32_t)-1;
308 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
309 if (unlikely(txq->mp2mr[i].mp == NULL)) {
310 /* Unknown MP, add a new MR for it. */
313 if (txq->mp2mr[i].mp == mp) {
314 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
315 assert(htonl(txq->mp2mr[i].mr->lkey) ==
317 lkey = txq->mp2mr[i].lkey;
321 if (unlikely(lkey == (uint32_t)-1))
322 lkey = txq_mp2mr_reg(txq, mp, i);
327 * Ring TX queue doorbell.
330 * Pointer to TX queue structure.
332 * Pointer to the last WQE posted in the NIC.
335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
337 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
338 volatile uint64_t *src = ((volatile uint64_t *)wqe);
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
348 * DPDK callback to check the status of a tx descriptor.
353 * The index of the descriptor in the ring.
356 * The status of the tx descriptor.
359 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
361 struct txq *txq = tx_queue;
362 const unsigned int elts_n = 1 << txq->elts_n;
363 const unsigned int elts_cnt = elts_n - 1;
367 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
369 return RTE_ETH_TX_DESC_FULL;
370 return RTE_ETH_TX_DESC_DONE;
374 * DPDK callback to check the status of a rx descriptor.
379 * The index of the descriptor in the ring.
382 * The status of the tx descriptor.
385 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
387 struct rxq *rxq = rx_queue;
388 struct rxq_zip *zip = &rxq->zip;
389 volatile struct mlx5_cqe *cqe;
390 const unsigned int cqe_n = (1 << rxq->cqe_n);
391 const unsigned int cqe_cnt = cqe_n - 1;
395 /* if we are processing a compressed cqe */
397 used = zip->cqe_cnt - zip->ca;
403 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
404 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
408 op_own = cqe->op_own;
409 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
410 n = ntohl(cqe->byte_cnt);
415 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
417 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
419 return RTE_ETH_RX_DESC_DONE;
420 return RTE_ETH_RX_DESC_AVAIL;
424 * DPDK callback for TX.
427 * Generic pointer to TX queue structure.
429 * Packets to transmit.
431 * Number of packets in array.
434 * Number of packets successfully transmitted (<= pkts_n).
437 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
439 struct txq *txq = (struct txq *)dpdk_txq;
440 uint16_t elts_head = txq->elts_head;
441 const unsigned int elts_n = 1 << txq->elts_n;
448 volatile struct mlx5_wqe_v *wqe = NULL;
449 unsigned int segs_n = 0;
450 struct rte_mbuf *buf = NULL;
453 if (unlikely(!pkts_n))
455 /* Prefetch first packet cacheline. */
456 rte_prefetch0(*pkts);
457 /* Start processing. */
459 max = (elts_n - (elts_head - txq->elts_tail));
462 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
463 if (unlikely(!max_wqe))
466 volatile rte_v128u32_t *dseg = NULL;
471 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
472 uint16_t tso_header_sz = 0;
474 uint8_t cs_flags = 0;
476 #ifdef MLX5_PMD_SOFT_COUNTERS
477 uint32_t total_length = 0;
482 segs_n = buf->nb_segs;
484 * Make sure there is enough room to store this packet and
485 * that one ring entry remains unused.
488 if (max < segs_n + 1)
494 if (unlikely(--max_wqe == 0))
496 wqe = (volatile struct mlx5_wqe_v *)
497 tx_mlx5_wqe(txq, txq->wqe_ci);
498 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
500 rte_prefetch0(*pkts);
501 addr = rte_pktmbuf_mtod(buf, uintptr_t);
502 length = DATA_LEN(buf);
503 ehdr = (((uint8_t *)addr)[1] << 8) |
504 ((uint8_t *)addr)[0];
505 #ifdef MLX5_PMD_SOFT_COUNTERS
506 total_length = length;
508 assert(length >= MLX5_WQE_DWORD_SIZE);
509 /* Update element. */
510 (*txq->elts)[elts_head] = buf;
511 elts_head = (elts_head + 1) & (elts_n - 1);
512 /* Prefetch next buffer data. */
514 volatile void *pkt_addr;
516 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
517 rte_prefetch0(pkt_addr);
519 /* Should we enable HW CKSUM offload */
521 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
522 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
524 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
525 /* Replace the Ethernet type by the VLAN if necessary. */
526 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
527 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
528 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
532 /* Copy Destination and source mac address. */
533 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
535 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
536 /* Copy missing two bytes to end the DSeg. */
537 memcpy((uint8_t *)raw + len + sizeof(vlan),
538 ((uint8_t *)addr) + len, 2);
542 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
543 MLX5_WQE_DWORD_SIZE);
544 length -= pkt_inline_sz;
545 addr += pkt_inline_sz;
548 tso = buf->ol_flags & PKT_TX_TCP_SEG;
550 uintptr_t end = (uintptr_t)
551 (((uintptr_t)txq->wqes) +
555 uint8_t vlan_sz = (buf->ol_flags &
556 PKT_TX_VLAN_PKT) ? 4 : 0;
558 tso_header_sz = buf->l2_len + vlan_sz +
559 buf->l3_len + buf->l4_len;
561 if (unlikely(tso_header_sz >
562 MLX5_MAX_TSO_HEADER))
564 copy_b = tso_header_sz - pkt_inline_sz;
565 /* First seg must contain all headers. */
566 assert(copy_b <= length);
567 raw += MLX5_WQE_DWORD_SIZE;
569 ((end - (uintptr_t)raw) > copy_b)) {
570 uint16_t n = (MLX5_WQE_DS(copy_b) -
573 if (unlikely(max_wqe < n))
576 rte_memcpy((void *)raw,
577 (void *)addr, copy_b);
580 pkt_inline_sz += copy_b;
582 * Another DWORD will be added
583 * in the inline part.
585 raw += MLX5_WQE_DS(copy_b) *
586 MLX5_WQE_DWORD_SIZE -
590 wqe->ctrl = (rte_v128u32_t){
591 htonl(txq->wqe_ci << 8),
592 htonl(txq->qp_num_8s | 1),
600 elts_head = (elts_head - 1) &
607 /* Inline if enough room. */
608 if (txq->inline_en || tso) {
609 uintptr_t end = (uintptr_t)
610 (((uintptr_t)txq->wqes) +
611 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
612 unsigned int max_inline = txq->max_inline *
613 RTE_CACHE_LINE_SIZE -
615 uintptr_t addr_end = (addr + max_inline) &
616 ~(RTE_CACHE_LINE_SIZE - 1);
617 unsigned int copy_b = (addr_end > addr) ?
618 RTE_MIN((addr_end - addr), length) :
621 raw += MLX5_WQE_DWORD_SIZE;
622 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
624 * One Dseg remains in the current WQE. To
625 * keep the computation positive, it is
626 * removed after the bytes to Dseg conversion.
628 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
630 if (unlikely(max_wqe < n))
635 htonl(copy_b | MLX5_INLINE_SEG);
638 MLX5_WQE_DS(tso_header_sz) *
640 rte_memcpy((void *)raw,
641 (void *)&inl, sizeof(inl));
643 pkt_inline_sz += sizeof(inl);
645 rte_memcpy((void *)raw, (void *)addr, copy_b);
648 pkt_inline_sz += copy_b;
651 * 2 DWORDs consumed by the WQE header + ETH segment +
652 * the size of the inline part of the packet.
654 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
656 if (ds % (MLX5_WQE_SIZE /
657 MLX5_WQE_DWORD_SIZE) == 0) {
658 if (unlikely(--max_wqe == 0))
660 dseg = (volatile rte_v128u32_t *)
661 tx_mlx5_wqe(txq, txq->wqe_ci +
664 dseg = (volatile rte_v128u32_t *)
666 (ds * MLX5_WQE_DWORD_SIZE));
669 } else if (!segs_n) {
672 /* dseg will be advance as part of next_seg */
673 dseg = (volatile rte_v128u32_t *)
675 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
680 * No inline has been done in the packet, only the
681 * Ethernet Header as been stored.
683 dseg = (volatile rte_v128u32_t *)
684 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
687 /* Add the remaining packet as a simple ds. */
688 naddr = htonll(addr);
689 *dseg = (rte_v128u32_t){
691 txq_mp2mr(txq, txq_mb2mp(buf)),
704 * Spill on next WQE when the current one does not have
705 * enough room left. Size of WQE must a be a multiple
706 * of data segment size.
708 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
709 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
710 if (unlikely(--max_wqe == 0))
712 dseg = (volatile rte_v128u32_t *)
713 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
714 rte_prefetch0(tx_mlx5_wqe(txq,
715 txq->wqe_ci + ds / 4 + 1));
722 length = DATA_LEN(buf);
723 #ifdef MLX5_PMD_SOFT_COUNTERS
724 total_length += length;
726 /* Store segment information. */
727 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
728 *dseg = (rte_v128u32_t){
730 txq_mp2mr(txq, txq_mb2mp(buf)),
734 (*txq->elts)[elts_head] = buf;
735 elts_head = (elts_head + 1) & (elts_n - 1);
744 /* Initialize known and common part of the WQE structure. */
746 wqe->ctrl = (rte_v128u32_t){
747 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
748 htonl(txq->qp_num_8s | ds),
752 wqe->eseg = (rte_v128u32_t){
754 cs_flags | (htons(buf->tso_segsz) << 16),
756 (ehdr << 16) | htons(tso_header_sz),
759 wqe->ctrl = (rte_v128u32_t){
760 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
761 htonl(txq->qp_num_8s | ds),
765 wqe->eseg = (rte_v128u32_t){
769 (ehdr << 16) | htons(pkt_inline_sz),
773 txq->wqe_ci += (ds + 3) / 4;
774 #ifdef MLX5_PMD_SOFT_COUNTERS
775 /* Increment sent bytes counter. */
776 txq->stats.obytes += total_length;
779 /* Take a shortcut if nothing must be sent. */
780 if (unlikely((i + k) == 0))
782 /* Check whether completion threshold has been reached. */
783 comp = txq->elts_comp + i + j + k;
784 if (comp >= MLX5_TX_COMP_THRESH) {
785 volatile struct mlx5_wqe_ctrl *w =
786 (volatile struct mlx5_wqe_ctrl *)wqe;
788 /* Request completion on last WQE. */
790 /* Save elts_head in unused "immediate" field of WQE. */
791 w->ctrl3 = elts_head;
794 txq->elts_comp = comp;
796 #ifdef MLX5_PMD_SOFT_COUNTERS
797 /* Increment sent packets counter. */
798 txq->stats.opackets += i;
800 /* Ring QP doorbell. */
801 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
802 txq->elts_head = elts_head;
807 * Open a MPW session.
810 * Pointer to TX queue structure.
812 * Pointer to MPW session structure.
817 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
819 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
820 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
821 (volatile struct mlx5_wqe_data_seg (*)[])
822 tx_mlx5_wqe(txq, idx + 1);
824 mpw->state = MLX5_MPW_STATE_OPENED;
828 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
829 mpw->wqe->eseg.mss = htons(length);
830 mpw->wqe->eseg.inline_hdr_sz = 0;
831 mpw->wqe->eseg.rsvd0 = 0;
832 mpw->wqe->eseg.rsvd1 = 0;
833 mpw->wqe->eseg.rsvd2 = 0;
834 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
835 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
836 mpw->wqe->ctrl[2] = 0;
837 mpw->wqe->ctrl[3] = 0;
838 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
839 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
840 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
841 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
842 mpw->data.dseg[2] = &(*dseg)[0];
843 mpw->data.dseg[3] = &(*dseg)[1];
844 mpw->data.dseg[4] = &(*dseg)[2];
848 * Close a MPW session.
851 * Pointer to TX queue structure.
853 * Pointer to MPW session structure.
856 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
858 unsigned int num = mpw->pkts_n;
861 * Store size in multiple of 16 bytes. Control and Ethernet segments
864 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
865 mpw->state = MLX5_MPW_STATE_CLOSED;
870 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
871 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
875 * DPDK callback for TX with MPW support.
878 * Generic pointer to TX queue structure.
880 * Packets to transmit.
882 * Number of packets in array.
885 * Number of packets successfully transmitted (<= pkts_n).
888 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
890 struct txq *txq = (struct txq *)dpdk_txq;
891 uint16_t elts_head = txq->elts_head;
892 const unsigned int elts_n = 1 << txq->elts_n;
898 struct mlx5_mpw mpw = {
899 .state = MLX5_MPW_STATE_CLOSED,
902 if (unlikely(!pkts_n))
904 /* Prefetch first packet cacheline. */
905 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
906 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
907 /* Start processing. */
909 max = (elts_n - (elts_head - txq->elts_tail));
912 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
913 if (unlikely(!max_wqe))
916 struct rte_mbuf *buf = *(pkts++);
917 unsigned int elts_head_next;
919 unsigned int segs_n = buf->nb_segs;
920 uint32_t cs_flags = 0;
923 * Make sure there is enough room to store this packet and
924 * that one ring entry remains unused.
927 if (max < segs_n + 1)
929 /* Do not bother with large packets MPW cannot handle. */
930 if (segs_n > MLX5_MPW_DSEG_MAX)
934 /* Should we enable HW CKSUM offload */
936 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
937 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
938 /* Retrieve packet information. */
939 length = PKT_LEN(buf);
941 /* Start new session if packet differs. */
942 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
943 ((mpw.len != length) ||
945 (mpw.wqe->eseg.cs_flags != cs_flags)))
946 mlx5_mpw_close(txq, &mpw);
947 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
949 * Multi-Packet WQE consumes at most two WQE.
950 * mlx5_mpw_new() expects to be able to use such
953 if (unlikely(max_wqe < 2))
956 mlx5_mpw_new(txq, &mpw, length);
957 mpw.wqe->eseg.cs_flags = cs_flags;
959 /* Multi-segment packets must be alone in their MPW. */
960 assert((segs_n == 1) || (mpw.pkts_n == 0));
961 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
965 volatile struct mlx5_wqe_data_seg *dseg;
968 elts_head_next = (elts_head + 1) & (elts_n - 1);
970 (*txq->elts)[elts_head] = buf;
971 dseg = mpw.data.dseg[mpw.pkts_n];
972 addr = rte_pktmbuf_mtod(buf, uintptr_t);
973 *dseg = (struct mlx5_wqe_data_seg){
974 .byte_count = htonl(DATA_LEN(buf)),
975 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
976 .addr = htonll(addr),
978 elts_head = elts_head_next;
979 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
980 length += DATA_LEN(buf);
986 assert(length == mpw.len);
987 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
988 mlx5_mpw_close(txq, &mpw);
989 elts_head = elts_head_next;
990 #ifdef MLX5_PMD_SOFT_COUNTERS
991 /* Increment sent bytes counter. */
992 txq->stats.obytes += length;
996 /* Take a shortcut if nothing must be sent. */
997 if (unlikely(i == 0))
999 /* Check whether completion threshold has been reached. */
1000 /* "j" includes both packets and segments. */
1001 comp = txq->elts_comp + j;
1002 if (comp >= MLX5_TX_COMP_THRESH) {
1003 volatile struct mlx5_wqe *wqe = mpw.wqe;
1005 /* Request completion on last WQE. */
1006 wqe->ctrl[2] = htonl(8);
1007 /* Save elts_head in unused "immediate" field of WQE. */
1008 wqe->ctrl[3] = elts_head;
1011 txq->elts_comp = comp;
1013 #ifdef MLX5_PMD_SOFT_COUNTERS
1014 /* Increment sent packets counter. */
1015 txq->stats.opackets += i;
1017 /* Ring QP doorbell. */
1018 if (mpw.state == MLX5_MPW_STATE_OPENED)
1019 mlx5_mpw_close(txq, &mpw);
1020 mlx5_tx_dbrec(txq, mpw.wqe);
1021 txq->elts_head = elts_head;
1026 * Open a MPW inline session.
1029 * Pointer to TX queue structure.
1031 * Pointer to MPW session structure.
1036 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1038 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1039 struct mlx5_wqe_inl_small *inl;
1041 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1045 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1046 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1047 (txq->wqe_ci << 8) |
1049 mpw->wqe->ctrl[2] = 0;
1050 mpw->wqe->ctrl[3] = 0;
1051 mpw->wqe->eseg.mss = htons(length);
1052 mpw->wqe->eseg.inline_hdr_sz = 0;
1053 mpw->wqe->eseg.cs_flags = 0;
1054 mpw->wqe->eseg.rsvd0 = 0;
1055 mpw->wqe->eseg.rsvd1 = 0;
1056 mpw->wqe->eseg.rsvd2 = 0;
1057 inl = (struct mlx5_wqe_inl_small *)
1058 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1059 mpw->data.raw = (uint8_t *)&inl->raw;
1063 * Close a MPW inline session.
1066 * Pointer to TX queue structure.
1068 * Pointer to MPW session structure.
1071 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1074 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1075 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1077 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1079 * Store size in multiple of 16 bytes. Control and Ethernet segments
1082 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1083 mpw->state = MLX5_MPW_STATE_CLOSED;
1084 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1085 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1089 * DPDK callback for TX with MPW inline support.
1092 * Generic pointer to TX queue structure.
1094 * Packets to transmit.
1096 * Number of packets in array.
1099 * Number of packets successfully transmitted (<= pkts_n).
1102 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1105 struct txq *txq = (struct txq *)dpdk_txq;
1106 uint16_t elts_head = txq->elts_head;
1107 const unsigned int elts_n = 1 << txq->elts_n;
1113 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1114 struct mlx5_mpw mpw = {
1115 .state = MLX5_MPW_STATE_CLOSED,
1118 * Compute the maximum number of WQE which can be consumed by inline
1121 * - 1 control segment,
1122 * - 1 Ethernet segment,
1123 * - N Dseg from the inline request.
1125 const unsigned int wqe_inl_n =
1126 ((2 * MLX5_WQE_DWORD_SIZE +
1127 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1128 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1130 if (unlikely(!pkts_n))
1132 /* Prefetch first packet cacheline. */
1133 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1134 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1135 /* Start processing. */
1137 max = (elts_n - (elts_head - txq->elts_tail));
1141 struct rte_mbuf *buf = *(pkts++);
1142 unsigned int elts_head_next;
1145 unsigned int segs_n = buf->nb_segs;
1146 uint32_t cs_flags = 0;
1149 * Make sure there is enough room to store this packet and
1150 * that one ring entry remains unused.
1153 if (max < segs_n + 1)
1155 /* Do not bother with large packets MPW cannot handle. */
1156 if (segs_n > MLX5_MPW_DSEG_MAX)
1161 * Compute max_wqe in case less WQE were consumed in previous
1164 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1165 /* Should we enable HW CKSUM offload */
1167 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1168 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1169 /* Retrieve packet information. */
1170 length = PKT_LEN(buf);
1171 /* Start new session if packet differs. */
1172 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1173 if ((mpw.len != length) ||
1175 (mpw.wqe->eseg.cs_flags != cs_flags))
1176 mlx5_mpw_close(txq, &mpw);
1177 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1178 if ((mpw.len != length) ||
1180 (length > inline_room) ||
1181 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1182 mlx5_mpw_inline_close(txq, &mpw);
1184 txq->max_inline * RTE_CACHE_LINE_SIZE;
1187 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1188 if ((segs_n != 1) ||
1189 (length > inline_room)) {
1191 * Multi-Packet WQE consumes at most two WQE.
1192 * mlx5_mpw_new() expects to be able to use
1195 if (unlikely(max_wqe < 2))
1198 mlx5_mpw_new(txq, &mpw, length);
1199 mpw.wqe->eseg.cs_flags = cs_flags;
1201 if (unlikely(max_wqe < wqe_inl_n))
1203 max_wqe -= wqe_inl_n;
1204 mlx5_mpw_inline_new(txq, &mpw, length);
1205 mpw.wqe->eseg.cs_flags = cs_flags;
1208 /* Multi-segment packets must be alone in their MPW. */
1209 assert((segs_n == 1) || (mpw.pkts_n == 0));
1210 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1211 assert(inline_room ==
1212 txq->max_inline * RTE_CACHE_LINE_SIZE);
1213 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1217 volatile struct mlx5_wqe_data_seg *dseg;
1220 (elts_head + 1) & (elts_n - 1);
1222 (*txq->elts)[elts_head] = buf;
1223 dseg = mpw.data.dseg[mpw.pkts_n];
1224 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1225 *dseg = (struct mlx5_wqe_data_seg){
1226 .byte_count = htonl(DATA_LEN(buf)),
1227 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1228 .addr = htonll(addr),
1230 elts_head = elts_head_next;
1231 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1232 length += DATA_LEN(buf);
1238 assert(length == mpw.len);
1239 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1240 mlx5_mpw_close(txq, &mpw);
1244 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1245 assert(length <= inline_room);
1246 assert(length == DATA_LEN(buf));
1247 elts_head_next = (elts_head + 1) & (elts_n - 1);
1248 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1249 (*txq->elts)[elts_head] = buf;
1250 /* Maximum number of bytes before wrapping. */
1251 max = ((((uintptr_t)(txq->wqes)) +
1254 (uintptr_t)mpw.data.raw);
1256 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1259 mpw.data.raw = (volatile void *)txq->wqes;
1260 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1261 (void *)(addr + max),
1263 mpw.data.raw += length - max;
1265 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1271 (volatile void *)txq->wqes;
1273 mpw.data.raw += length;
1276 mpw.total_len += length;
1278 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1279 mlx5_mpw_inline_close(txq, &mpw);
1281 txq->max_inline * RTE_CACHE_LINE_SIZE;
1283 inline_room -= length;
1286 elts_head = elts_head_next;
1287 #ifdef MLX5_PMD_SOFT_COUNTERS
1288 /* Increment sent bytes counter. */
1289 txq->stats.obytes += length;
1293 /* Take a shortcut if nothing must be sent. */
1294 if (unlikely(i == 0))
1296 /* Check whether completion threshold has been reached. */
1297 /* "j" includes both packets and segments. */
1298 comp = txq->elts_comp + j;
1299 if (comp >= MLX5_TX_COMP_THRESH) {
1300 volatile struct mlx5_wqe *wqe = mpw.wqe;
1302 /* Request completion on last WQE. */
1303 wqe->ctrl[2] = htonl(8);
1304 /* Save elts_head in unused "immediate" field of WQE. */
1305 wqe->ctrl[3] = elts_head;
1308 txq->elts_comp = comp;
1310 #ifdef MLX5_PMD_SOFT_COUNTERS
1311 /* Increment sent packets counter. */
1312 txq->stats.opackets += i;
1314 /* Ring QP doorbell. */
1315 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1316 mlx5_mpw_inline_close(txq, &mpw);
1317 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1318 mlx5_mpw_close(txq, &mpw);
1319 mlx5_tx_dbrec(txq, mpw.wqe);
1320 txq->elts_head = elts_head;
1325 * Translate RX completion flags to packet type.
1330 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1333 * Packet type for struct rte_mbuf.
1335 static inline uint32_t
1336 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1339 uint16_t flags = ntohs(cqe->hdr_type_etc);
1341 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1344 MLX5_CQE_RX_IPV4_PACKET,
1345 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1347 MLX5_CQE_RX_IPV6_PACKET,
1348 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1349 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1350 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1351 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1355 MLX5_CQE_L3_HDR_TYPE_IPV6,
1356 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1358 MLX5_CQE_L3_HDR_TYPE_IPV4,
1359 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1365 * Get size of the next packet for a given CQE. For compressed CQEs, the
1366 * consumer index is updated only once all packets of the current one have
1370 * Pointer to RX queue.
1373 * @param[out] rss_hash
1374 * Packet RSS Hash result.
1377 * Packet size in bytes (0 if there is none), -1 in case of completion
1381 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1382 uint16_t cqe_cnt, uint32_t *rss_hash)
1384 struct rxq_zip *zip = &rxq->zip;
1385 uint16_t cqe_n = cqe_cnt + 1;
1389 /* Process compressed data in the CQE and mini arrays. */
1391 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1392 (volatile struct mlx5_mini_cqe8 (*)[8])
1393 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1395 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1396 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1397 if ((++zip->ai & 7) == 0) {
1398 /* Invalidate consumed CQEs */
1401 while (idx != end) {
1402 (*rxq->cqes)[idx & cqe_cnt].op_own =
1403 MLX5_CQE_INVALIDATE;
1407 * Increment consumer index to skip the number of
1408 * CQEs consumed. Hardware leaves holes in the CQ
1409 * ring for software use.
1414 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1415 /* Invalidate the rest */
1419 while (idx != end) {
1420 (*rxq->cqes)[idx & cqe_cnt].op_own =
1421 MLX5_CQE_INVALIDATE;
1424 rxq->cq_ci = zip->cq_ci;
1427 /* No compressed data, get next CQE and verify if it is compressed. */
1432 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1433 if (unlikely(ret == 1))
1436 op_own = cqe->op_own;
1437 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1438 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1439 (volatile struct mlx5_mini_cqe8 (*)[8])
1440 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1443 /* Fix endianness. */
1444 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1446 * Current mini array position is the one returned by
1449 * If completion comprises several mini arrays, as a
1450 * special case the second one is located 7 CQEs after
1451 * the initial CQE instead of 8 for subsequent ones.
1453 zip->ca = rxq->cq_ci;
1454 zip->na = zip->ca + 7;
1455 /* Compute the next non compressed CQE. */
1457 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1458 /* Get packet size to return. */
1459 len = ntohl((*mc)[0].byte_cnt);
1460 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1462 /* Prefetch all the entries to be invalidated */
1465 while (idx != end) {
1466 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1470 len = ntohl(cqe->byte_cnt);
1471 *rss_hash = ntohl(cqe->rx_hash_res);
1473 /* Error while receiving packet. */
1474 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1481 * Translate RX completion flags to offload flags.
1484 * Pointer to RX queue structure.
1489 * Offload flags (ol_flags) for struct rte_mbuf.
1491 static inline uint32_t
1492 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1494 uint32_t ol_flags = 0;
1495 uint16_t flags = ntohs(cqe->hdr_type_etc);
1499 MLX5_CQE_RX_L3_HDR_VALID,
1500 PKT_RX_IP_CKSUM_GOOD) |
1502 MLX5_CQE_RX_L4_HDR_VALID,
1503 PKT_RX_L4_CKSUM_GOOD);
1504 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1507 MLX5_CQE_RX_L3_HDR_VALID,
1508 PKT_RX_IP_CKSUM_GOOD) |
1510 MLX5_CQE_RX_L4_HDR_VALID,
1511 PKT_RX_L4_CKSUM_GOOD);
1516 * DPDK callback for RX.
1519 * Generic pointer to RX queue structure.
1521 * Array to store received packets.
1523 * Maximum number of packets in array.
1526 * Number of packets successfully received (<= pkts_n).
1529 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1531 struct rxq *rxq = dpdk_rxq;
1532 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1533 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1534 const unsigned int sges_n = rxq->sges_n;
1535 struct rte_mbuf *pkt = NULL;
1536 struct rte_mbuf *seg = NULL;
1537 volatile struct mlx5_cqe *cqe =
1538 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1540 unsigned int rq_ci = rxq->rq_ci << sges_n;
1541 int len; /* keep its value across iterations. */
1544 unsigned int idx = rq_ci & wqe_cnt;
1545 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1546 struct rte_mbuf *rep = (*rxq->elts)[idx];
1547 uint32_t rss_hash_res = 0;
1555 rep = rte_mbuf_raw_alloc(rxq->mp);
1556 if (unlikely(rep == NULL)) {
1557 ++rxq->stats.rx_nombuf;
1560 * no buffers before we even started,
1561 * bail out silently.
1565 while (pkt != seg) {
1566 assert(pkt != (*rxq->elts)[idx]);
1568 rte_mbuf_refcnt_set(pkt, 0);
1569 __rte_mbuf_raw_free(pkt);
1575 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1576 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1579 rte_mbuf_refcnt_set(rep, 0);
1580 __rte_mbuf_raw_free(rep);
1583 if (unlikely(len == -1)) {
1584 /* RX error, packet is likely too large. */
1585 rte_mbuf_refcnt_set(rep, 0);
1586 __rte_mbuf_raw_free(rep);
1587 ++rxq->stats.idropped;
1591 assert(len >= (rxq->crc_present << 2));
1592 /* Update packet information. */
1593 pkt->packet_type = 0;
1595 if (rss_hash_res && rxq->rss_hash) {
1596 pkt->hash.rss = rss_hash_res;
1597 pkt->ol_flags = PKT_RX_RSS_HASH;
1599 if (rxq->mark && (cqe->sop_drop_qpn !=
1600 htonl(MLX5_FLOW_MARK_INVALID))) {
1601 pkt->ol_flags |= PKT_RX_FDIR;
1602 if (cqe->sop_drop_qpn !=
1603 htonl(MLX5_FLOW_MARK_DEFAULT)) {
1604 uint32_t mark = cqe->sop_drop_qpn;
1606 pkt->ol_flags |= PKT_RX_FDIR_ID;
1608 mlx5_flow_mark_get(mark);
1611 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1615 rxq_cq_to_pkt_type(cqe);
1617 rxq_cq_to_ol_flags(rxq, cqe);
1619 if (ntohs(cqe->hdr_type_etc) &
1620 MLX5_CQE_VLAN_STRIPPED) {
1621 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1622 PKT_RX_VLAN_STRIPPED;
1623 pkt->vlan_tci = ntohs(cqe->vlan_info);
1625 if (rxq->crc_present)
1626 len -= ETHER_CRC_LEN;
1630 DATA_LEN(rep) = DATA_LEN(seg);
1631 PKT_LEN(rep) = PKT_LEN(seg);
1632 SET_DATA_OFF(rep, DATA_OFF(seg));
1633 NB_SEGS(rep) = NB_SEGS(seg);
1634 PORT(rep) = PORT(seg);
1636 (*rxq->elts)[idx] = rep;
1638 * Fill NIC descriptor with the new buffer. The lkey and size
1639 * of the buffers are already known, only the buffer address
1642 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1643 if (len > DATA_LEN(seg)) {
1644 len -= DATA_LEN(seg);
1649 DATA_LEN(seg) = len;
1650 #ifdef MLX5_PMD_SOFT_COUNTERS
1651 /* Increment bytes counter. */
1652 rxq->stats.ibytes += PKT_LEN(pkt);
1654 /* Return packet. */
1660 /* Align consumer index to the next stride. */
1665 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1667 /* Update the consumer index. */
1668 rxq->rq_ci = rq_ci >> sges_n;
1670 *rxq->cq_db = htonl(rxq->cq_ci);
1672 *rxq->rq_db = htonl(rxq->rq_ci);
1673 #ifdef MLX5_PMD_SOFT_COUNTERS
1674 /* Increment packets counter. */
1675 rxq->stats.ipackets += i;
1681 * Dummy DPDK callback for TX.
1683 * This function is used to temporarily replace the real callback during
1684 * unsafe control operations on the queue, or in case of error.
1687 * Generic pointer to TX queue structure.
1689 * Packets to transmit.
1691 * Number of packets in array.
1694 * Number of packets successfully transmitted (<= pkts_n).
1697 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1706 * Dummy DPDK callback for RX.
1708 * This function is used to temporarily replace the real callback during
1709 * unsafe control operations on the queue, or in case of error.
1712 * Generic pointer to RX queue structure.
1714 * Array to store received packets.
1716 * Maximum number of packets in array.
1719 * Number of packets successfully received (<= pkts_n).
1722 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)