drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28 #include <rte_cycles.h>
  29
  30 #include "mlx5.h"
  31 #include "mlx5_utils.h"
  32 #include "mlx5_rxtx.h"
  33 #include "mlx5_autoconf.h"
  34 #include "mlx5_defs.h"
  35 #include "mlx5_prm.h"
  36
  37 static __rte_always_inline uint32_t
  38 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  39
  40 static __rte_always_inline int
  41 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  42                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
  43
  44 static __rte_always_inline uint32_t
  45 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
  46
  47 static __rte_always_inline void
  48 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
  49                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
  50
  51 static __rte_always_inline void
  52 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
  53
  54 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  55         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  56 };
  57
  58 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
  59 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
  60
  61 /**
  62  * Build a table to translate Rx completion flags to packet type.
  63  *
  64  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  65  */
  66 void
  67 mlx5_set_ptype_table(void)
  68 {
  69         unsigned int i;
  70         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  71
  72         /* Last entry must not be overwritten, reserved for errored packet. */
  73         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  74                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  75         /*
  76          * The index to the array should have:
  77          * bit[1:0] = l3_hdr_type
  78          * bit[4:2] = l4_hdr_type
  79          * bit[5] = ip_frag
  80          * bit[6] = tunneled
  81          * bit[7] = outer_l3_type
  82          */
  83         /* L2 */
  84         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  85         /* L3 */
  86         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  87                      RTE_PTYPE_L4_NONFRAG;
  88         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  89                      RTE_PTYPE_L4_NONFRAG;
  90         /* Fragmented */
  91         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  92                      RTE_PTYPE_L4_FRAG;
  93         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  94                      RTE_PTYPE_L4_FRAG;
  95         /* TCP */
  96         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  97                      RTE_PTYPE_L4_TCP;
  98         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  99                      RTE_PTYPE_L4_TCP;
 100         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_TCP;
 102         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 103                      RTE_PTYPE_L4_TCP;
 104         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 105                      RTE_PTYPE_L4_TCP;
 106         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 107                      RTE_PTYPE_L4_TCP;
 108         /* UDP */
 109         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_UDP;
 111         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 112                      RTE_PTYPE_L4_UDP;
 113         /* Repeat with outer_l3_type being set. Just in case. */
 114         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 115                      RTE_PTYPE_L4_NONFRAG;
 116         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 117                      RTE_PTYPE_L4_NONFRAG;
 118         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 119                      RTE_PTYPE_L4_FRAG;
 120         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 121                      RTE_PTYPE_L4_FRAG;
 122         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 123                      RTE_PTYPE_L4_TCP;
 124         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 125                      RTE_PTYPE_L4_TCP;
 126         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 127                      RTE_PTYPE_L4_TCP;
 128         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_L4_TCP;
 130         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 131                      RTE_PTYPE_L4_TCP;
 132         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_L4_TCP;
 134         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_L4_UDP;
 136         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 137                      RTE_PTYPE_L4_UDP;
 138         /* Tunneled - L3 */
 139         (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
 140         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 141                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L4_NONFRAG;
 143         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 144                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L4_NONFRAG;
 146         (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
 147         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L4_NONFRAG;
 150         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_NONFRAG;
 153         /* Tunneled - Fragmented */
 154         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_FRAG;
 157         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L4_FRAG;
 160         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L4_FRAG;
 163         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L4_FRAG;
 166         /* Tunneled - TCP */
 167         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 169                      RTE_PTYPE_INNER_L4_TCP;
 170         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 172                      RTE_PTYPE_INNER_L4_TCP;
 173         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 175                      RTE_PTYPE_INNER_L4_TCP;
 176         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 178                      RTE_PTYPE_INNER_L4_TCP;
 179         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 181                      RTE_PTYPE_INNER_L4_TCP;
 182         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 184                      RTE_PTYPE_INNER_L4_TCP;
 185         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 187                      RTE_PTYPE_INNER_L4_TCP;
 188         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 190                      RTE_PTYPE_INNER_L4_TCP;
 191         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L4_TCP;
 194         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_TCP;
 197         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_TCP;
 200         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L4_TCP;
 203         /* Tunneled - UDP */
 204         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 205                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 206                      RTE_PTYPE_INNER_L4_UDP;
 207         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 208                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 209                      RTE_PTYPE_INNER_L4_UDP;
 210         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 211                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 212                      RTE_PTYPE_INNER_L4_UDP;
 213         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 214                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 215                      RTE_PTYPE_INNER_L4_UDP;
 216 }
 217
 218 /**
 219  * Build a table to translate packet to checksum type of Verbs.
 220  */
 221 void
 222 mlx5_set_cksum_table(void)
 223 {
 224         unsigned int i;
 225         uint8_t v;
 226
 227         /*
 228          * The index should have:
 229          * bit[0] = PKT_TX_TCP_SEG
 230          * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
 231          * bit[4] = PKT_TX_IP_CKSUM
 232          * bit[8] = PKT_TX_OUTER_IP_CKSUM
 233          * bit[9] = tunnel
 234          */
 235         for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
 236                 v = 0;
 237                 if (i & (1 << 9)) {
 238                         /* Tunneled packet. */
 239                         if (i & (1 << 8)) /* Outer IP. */
 240                                 v |= MLX5_ETH_WQE_L3_CSUM;
 241                         if (i & (1 << 4)) /* Inner IP. */
 242                                 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
 243                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 244                                 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
 245                 } else {
 246                         /* No tunnel. */
 247                         if (i & (1 << 4)) /* IP. */
 248                                 v |= MLX5_ETH_WQE_L3_CSUM;
 249                         if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
 250                                 v |= MLX5_ETH_WQE_L4_CSUM;
 251                 }
 252                 mlx5_cksum_table[i] = v;
 253         }
 254 }
 255
 256 /**
 257  * Build a table to translate packet type of mbuf to SWP type of Verbs.
 258  */
 259 void
 260 mlx5_set_swp_types_table(void)
 261 {
 262         unsigned int i;
 263         uint8_t v;
 264
 265         /*
 266          * The index should have:
 267          * bit[0:1] = PKT_TX_L4_MASK
 268          * bit[4] = PKT_TX_IPV6
 269          * bit[8] = PKT_TX_OUTER_IPV6
 270          * bit[9] = PKT_TX_OUTER_UDP
 271          */
 272         for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
 273                 v = 0;
 274                 if (i & (1 << 8))
 275                         v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
 276                 if (i & (1 << 9))
 277                         v |= MLX5_ETH_WQE_L4_OUTER_UDP;
 278                 if (i & (1 << 4))
 279                         v |= MLX5_ETH_WQE_L3_INNER_IPV6;
 280                 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
 281                         v |= MLX5_ETH_WQE_L4_INNER_UDP;
 282                 mlx5_swp_types_table[i] = v;
 283         }
 284 }
 285
 286 /**
 287  * Return the size of tailroom of WQ.
 288  *
 289  * @param txq
 290  *   Pointer to TX queue structure.
 291  * @param addr
 292  *   Pointer to tail of WQ.
 293  *
 294  * @return
 295  *   Size of tailroom.
 296  */
 297 static inline size_t
 298 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 299 {
 300         size_t tailroom;
 301         tailroom = (uintptr_t)(txq->wqes) +
 302                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 303                    (uintptr_t)addr;
 304         return tailroom;
 305 }
 306
 307 /**
 308  * Copy data to tailroom of circular queue.
 309  *
 310  * @param dst
 311  *   Pointer to destination.
 312  * @param src
 313  *   Pointer to source.
 314  * @param n
 315  *   Number of bytes to copy.
 316  * @param base
 317  *   Pointer to head of queue.
 318  * @param tailroom
 319  *   Size of tailroom from dst.
 320  *
 321  * @return
 322  *   Pointer after copied data.
 323  */
 324 static inline void *
 325 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 326                 void *base, size_t tailroom)
 327 {
 328         void *ret;
 329
 330         if (n > tailroom) {
 331                 rte_memcpy(dst, src, tailroom);
 332                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 333                            n - tailroom);
 334                 ret = (uint8_t *)base + n - tailroom;
 335         } else {
 336                 rte_memcpy(dst, src, n);
 337                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 338         }
 339         return ret;
 340 }
 341
 342 /**
 343  * Inline TSO headers into WQE.
 344  *
 345  * @return
 346  *   0 on success, negative errno value on failure.
 347  */
 348 static int
 349 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 350            uint32_t *length,
 351            uintptr_t *addr,
 352            uint16_t *pkt_inline_sz,
 353            uint8_t **raw,
 354            uint16_t *max_wqe,
 355            uint16_t *tso_segsz,
 356            uint16_t *tso_header_sz)
 357 {
 358         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 359                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 360         unsigned int copy_b;
 361         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 362         const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
 363                                  PKT_TX_TUNNEL_MASK);
 364         uint16_t n_wqe;
 365
 366         *tso_segsz = buf->tso_segsz;
 367         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 368         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 369                 txq->stats.oerrors++;
 370                 return -EINVAL;
 371         }
 372         if (tunneled)
 373                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 374         /* First seg must contain all TSO headers. */
 375         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
 376                      *tso_header_sz > DATA_LEN(buf)) {
 377                 txq->stats.oerrors++;
 378                 return -EINVAL;
 379         }
 380         copy_b = *tso_header_sz - *pkt_inline_sz;
 381         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 382                 return -EAGAIN;
 383         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 384         if (unlikely(*max_wqe < n_wqe))
 385                 return -EINVAL;
 386         *max_wqe -= n_wqe;
 387         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 388         *length -= copy_b;
 389         *addr += copy_b;
 390         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 391         *pkt_inline_sz += copy_b;
 392         *raw += copy_b;
 393         return 0;
 394 }
 395
 396 /**
 397  * DPDK callback to check the status of a tx descriptor.
 398  *
 399  * @param tx_queue
 400  *   The tx queue.
 401  * @param[in] offset
 402  *   The index of the descriptor in the ring.
 403  *
 404  * @return
 405  *   The status of the tx descriptor.
 406  */
 407 int
 408 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 409 {
 410         struct mlx5_txq_data *txq = tx_queue;
 411         uint16_t used;
 412
 413         mlx5_tx_complete(txq);
 414         used = txq->elts_head - txq->elts_tail;
 415         if (offset < used)
 416                 return RTE_ETH_TX_DESC_FULL;
 417         return RTE_ETH_TX_DESC_DONE;
 418 }
 419
 420 /**
 421  * Internal function to compute the number of used descriptors in an RX queue
 422  *
 423  * @param rxq
 424  *   The Rx queue.
 425  *
 426  * @return
 427  *   The number of used rx descriptor.
 428  */
 429 static uint32_t
 430 rx_queue_count(struct mlx5_rxq_data *rxq)
 431 {
 432         struct rxq_zip *zip = &rxq->zip;
 433         volatile struct mlx5_cqe *cqe;
 434         const unsigned int cqe_n = (1 << rxq->cqe_n);
 435         const unsigned int cqe_cnt = cqe_n - 1;
 436         unsigned int cq_ci;
 437         unsigned int used;
 438
 439         /* if we are processing a compressed cqe */
 440         if (zip->ai) {
 441                 used = zip->cqe_cnt - zip->ca;
 442                 cq_ci = zip->cq_ci;
 443         } else {
 444                 used = 0;
 445                 cq_ci = rxq->cq_ci;
 446         }
 447         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 448         while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
 449                 int8_t op_own;
 450                 unsigned int n;
 451
 452                 op_own = cqe->op_own;
 453                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 454                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 455                 else
 456                         n = 1;
 457                 cq_ci += n;
 458                 used += n;
 459                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 460         }
 461         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 462         return used;
 463 }
 464
 465 /**
 466  * DPDK callback to check the status of a rx descriptor.
 467  *
 468  * @param rx_queue
 469  *   The Rx queue.
 470  * @param[in] offset
 471  *   The index of the descriptor in the ring.
 472  *
 473  * @return
 474  *   The status of the tx descriptor.
 475  */
 476 int
 477 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 478 {
 479         struct mlx5_rxq_data *rxq = rx_queue;
 480         struct mlx5_rxq_ctrl *rxq_ctrl =
 481                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
 482         struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
 483
 484         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 485                 rte_errno = ENOTSUP;
 486                 return -rte_errno;
 487         }
 488         if (offset >= (1 << rxq->elts_n)) {
 489                 rte_errno = EINVAL;
 490                 return -rte_errno;
 491         }
 492         if (offset < rx_queue_count(rxq))
 493                 return RTE_ETH_RX_DESC_DONE;
 494         return RTE_ETH_RX_DESC_AVAIL;
 495 }
 496
 497 /**
 498  * DPDK callback to get the number of used descriptors in a RX queue
 499  *
 500  * @param dev
 501  *   Pointer to the device structure.
 502  *
 503  * @param rx_queue_id
 504  *   The Rx queue.
 505  *
 506  * @return
 507  *   The number of used rx descriptor.
 508  *   -EINVAL if the queue is invalid
 509  */
 510 uint32_t
 511 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 512 {
 513         struct mlx5_priv *priv = dev->data->dev_private;
 514         struct mlx5_rxq_data *rxq;
 515
 516         if (dev->rx_pkt_burst != mlx5_rx_burst) {
 517                 rte_errno = ENOTSUP;
 518                 return -rte_errno;
 519         }
 520         rxq = (*priv->rxqs)[rx_queue_id];
 521         if (!rxq) {
 522                 rte_errno = EINVAL;
 523                 return -rte_errno;
 524         }
 525         return rx_queue_count(rxq);
 526 }
 527
 528 #define MLX5_SYSTEM_LOG_DIR "/var/log"
 529 /**
 530  * Dump debug information to log file.
 531  *
 532  * @param fname
 533  *   The file name.
 534  * @param hex_title
 535  *   If not NULL this string is printed as a header to the output
 536  *   and the output will be in hexadecimal view.
 537  * @param buf
 538  *   This is the buffer address to print out.
 539  * @param len
 540  *   The number of bytes to dump out.
 541  */
 542 void
 543 mlx5_dump_debug_information(const char *fname, const char *hex_title,
 544                             const void *buf, unsigned int hex_len)
 545 {
 546         FILE *fd;
 547
 548         MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
 549         fd = fopen(path, "a+");
 550         if (!fd) {
 551                 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
 552                         path);
 553                 MKSTR(path2, "./%s", fname);
 554                 fd = fopen(path2, "a+");
 555                 if (!fd) {
 556                         DRV_LOG(ERR, "cannot open %s for debug dump\n",
 557                                 path2);
 558                         return;
 559                 }
 560                 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
 561         } else {
 562                 DRV_LOG(INFO, "New debug dump in file %s\n", path);
 563         }
 564         if (hex_title)
 565                 rte_hexdump(fd, hex_title, buf, hex_len);
 566         else
 567                 fprintf(fd, "%s", (const char *)buf);
 568         fprintf(fd, "\n\n\n");
 569         fclose(fd);
 570 }
 571
 572 /**
 573  * DPDK callback for TX.
 574  *
 575  * @param dpdk_txq
 576  *   Generic pointer to TX queue structure.
 577  * @param[in] pkts
 578  *   Packets to transmit.
 579  * @param pkts_n
 580  *   Number of packets in array.
 581  *
 582  * @return
 583  *   Number of packets successfully transmitted (<= pkts_n).
 584  */
 585 uint16_t
 586 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 587 {
 588         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 589         uint16_t elts_head = txq->elts_head;
 590         const uint16_t elts_n = 1 << txq->elts_n;
 591         const uint16_t elts_m = elts_n - 1;
 592         unsigned int i = 0;
 593         unsigned int j = 0;
 594         unsigned int k = 0;
 595         uint16_t max_elts;
 596         uint16_t max_wqe;
 597         unsigned int comp;
 598         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 599         unsigned int segs_n = 0;
 600         const unsigned int max_inline = txq->max_inline;
 601         uint64_t addr_64;
 602
 603         if (unlikely(!pkts_n))
 604                 return 0;
 605         /* Prefetch first packet cacheline. */
 606         rte_prefetch0(*pkts);
 607         /* Start processing. */
 608         mlx5_tx_complete(txq);
 609         max_elts = (elts_n - (elts_head - txq->elts_tail));
 610         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 611         if (unlikely(!max_wqe))
 612                 return 0;
 613         do {
 614                 struct rte_mbuf *buf = *pkts; /* First_seg. */
 615                 uint8_t *raw;
 616                 volatile struct mlx5_wqe_v *wqe = NULL;
 617                 volatile rte_v128u32_t *dseg = NULL;
 618                 uint32_t length;
 619                 unsigned int ds = 0;
 620                 unsigned int sg = 0; /* counter of additional segs attached. */
 621                 uintptr_t addr;
 622                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 623                 uint16_t tso_header_sz = 0;
 624                 uint16_t ehdr;
 625                 uint8_t cs_flags;
 626                 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 627                 uint32_t swp_offsets = 0;
 628                 uint8_t swp_types = 0;
 629                 rte_be32_t metadata;
 630                 uint16_t tso_segsz = 0;
 631 #ifdef MLX5_PMD_SOFT_COUNTERS
 632                 uint32_t total_length = 0;
 633 #endif
 634                 int ret;
 635
 636                 segs_n = buf->nb_segs;
 637                 /*
 638                  * Make sure there is enough room to store this packet and
 639                  * that one ring entry remains unused.
 640                  */
 641                 assert(segs_n);
 642                 if (max_elts < segs_n)
 643                         break;
 644                 max_elts -= segs_n;
 645                 sg = --segs_n;
 646                 if (unlikely(--max_wqe == 0))
 647                         break;
 648                 wqe = (volatile struct mlx5_wqe_v *)
 649                         tx_mlx5_wqe(txq, txq->wqe_ci);
 650                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 651                 if (pkts_n - i > 1)
 652                         rte_prefetch0(*(pkts + 1));
 653                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 654                 length = DATA_LEN(buf);
 655                 ehdr = (((uint8_t *)addr)[1] << 8) |
 656                        ((uint8_t *)addr)[0];
 657 #ifdef MLX5_PMD_SOFT_COUNTERS
 658                 total_length = length;
 659 #endif
 660                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 661                         txq->stats.oerrors++;
 662                         break;
 663                 }
 664                 /* Update element. */
 665                 (*txq->elts)[elts_head & elts_m] = buf;
 666                 /* Prefetch next buffer data. */
 667                 if (pkts_n - i > 1)
 668                         rte_prefetch0(
 669                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 670                 cs_flags = txq_ol_cksum_to_cs(buf);
 671                 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
 672                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 673                 /* Copy metadata from mbuf if valid */
 674                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
 675                                                              0;
 676                 /* Replace the Ethernet type by the VLAN if necessary. */
 677                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 678                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 679                                                          buf->vlan_tci);
 680                         unsigned int len = 2 * RTE_ETHER_ADDR_LEN - 2;
 681
 682                         addr += 2;
 683                         length -= 2;
 684                         /* Copy Destination and source mac address. */
 685                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 686                         /* Copy VLAN. */
 687                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 688                         /* Copy missing two bytes to end the DSeg. */
 689                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 690                                ((uint8_t *)addr) + len, 2);
 691                         addr += len + 2;
 692                         length -= (len + 2);
 693                 } else {
 694                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 695                                MLX5_WQE_DWORD_SIZE);
 696                         length -= pkt_inline_sz;
 697                         addr += pkt_inline_sz;
 698                 }
 699                 raw += MLX5_WQE_DWORD_SIZE;
 700                 if (tso) {
 701                         ret = inline_tso(txq, buf, &length,
 702                                          &addr, &pkt_inline_sz,
 703                                          &raw, &max_wqe,
 704                                          &tso_segsz, &tso_header_sz);
 705                         if (ret == -EINVAL) {
 706                                 break;
 707                         } else if (ret == -EAGAIN) {
 708                                 /* NOP WQE. */
 709                                 wqe->ctrl = (rte_v128u32_t){
 710                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 711                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 712                                         0,
 713                                         0,
 714                                 };
 715                                 ds = 1;
 716 #ifdef MLX5_PMD_SOFT_COUNTERS
 717                                 total_length = 0;
 718 #endif
 719                                 k++;
 720                                 goto next_wqe;
 721                         }
 722                 }
 723                 /* Inline if enough room. */
 724                 if (max_inline || tso) {
 725                         uint32_t inl = 0;
 726                         uintptr_t end = (uintptr_t)
 727                                 (((uintptr_t)txq->wqes) +
 728                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 729                         unsigned int inline_room = max_inline *
 730                                                    RTE_CACHE_LINE_SIZE -
 731                                                    (pkt_inline_sz - 2) -
 732                                                    !!tso * sizeof(inl);
 733                         uintptr_t addr_end;
 734                         unsigned int copy_b;
 735
 736 pkt_inline:
 737                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 738                                                    RTE_CACHE_LINE_SIZE);
 739                         copy_b = (addr_end > addr) ?
 740                                  RTE_MIN((addr_end - addr), length) : 0;
 741                         if (copy_b && ((end - (uintptr_t)raw) >
 742                                        (copy_b + sizeof(inl)))) {
 743                                 /*
 744                                  * One Dseg remains in the current WQE.  To
 745                                  * keep the computation positive, it is
 746                                  * removed after the bytes to Dseg conversion.
 747                                  */
 748                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 749
 750                                 if (unlikely(max_wqe < n))
 751                                         break;
 752                                 max_wqe -= n;
 753                                 if (tso) {
 754                                         assert(inl == 0);
 755                                         inl = rte_cpu_to_be_32(copy_b |
 756                                                                MLX5_INLINE_SEG);
 757                                         rte_memcpy((void *)raw,
 758                                                    (void *)&inl, sizeof(inl));
 759                                         raw += sizeof(inl);
 760                                         pkt_inline_sz += sizeof(inl);
 761                                 }
 762                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 763                                 addr += copy_b;
 764                                 length -= copy_b;
 765                                 pkt_inline_sz += copy_b;
 766                         }
 767                         /*
 768                          * 2 DWORDs consumed by the WQE header + ETH segment +
 769                          * the size of the inline part of the packet.
 770                          */
 771                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 772                         if (length > 0) {
 773                                 if (ds % (MLX5_WQE_SIZE /
 774                                           MLX5_WQE_DWORD_SIZE) == 0) {
 775                                         if (unlikely(--max_wqe == 0))
 776                                                 break;
 777                                         dseg = (volatile rte_v128u32_t *)
 778                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 779                                                            ds / 4);
 780                                 } else {
 781                                         dseg = (volatile rte_v128u32_t *)
 782                                                 ((uintptr_t)wqe +
 783                                                  (ds * MLX5_WQE_DWORD_SIZE));
 784                                 }
 785                                 goto use_dseg;
 786                         } else if (!segs_n) {
 787                                 goto next_pkt;
 788                         } else {
 789                                 /*
 790                                  * Further inline the next segment only for
 791                                  * non-TSO packets.
 792                                  */
 793                                 if (!tso) {
 794                                         raw += copy_b;
 795                                         inline_room -= copy_b;
 796                                 } else {
 797                                         inline_room = 0;
 798                                 }
 799                                 /* Move to the next segment. */
 800                                 --segs_n;
 801                                 buf = buf->next;
 802                                 assert(buf);
 803                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 804                                 length = DATA_LEN(buf);
 805 #ifdef MLX5_PMD_SOFT_COUNTERS
 806                                 total_length += length;
 807 #endif
 808                                 (*txq->elts)[++elts_head & elts_m] = buf;
 809                                 goto pkt_inline;
 810                         }
 811                 } else {
 812                         /*
 813                          * No inline has been done in the packet, only the
 814                          * Ethernet Header as been stored.
 815                          */
 816                         dseg = (volatile rte_v128u32_t *)
 817                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 818                         ds = 3;
 819 use_dseg:
 820                         /* Add the remaining packet as a simple ds. */
 821                         addr_64 = rte_cpu_to_be_64(addr);
 822                         *dseg = (rte_v128u32_t){
 823                                 rte_cpu_to_be_32(length),
 824                                 mlx5_tx_mb2mr(txq, buf),
 825                                 addr_64,
 826                                 addr_64 >> 32,
 827                         };
 828                         ++ds;
 829                         if (!segs_n)
 830                                 goto next_pkt;
 831                 }
 832 next_seg:
 833                 assert(buf);
 834                 assert(ds);
 835                 assert(wqe);
 836                 /*
 837                  * Spill on next WQE when the current one does not have
 838                  * enough room left. Size of WQE must a be a multiple
 839                  * of data segment size.
 840                  */
 841                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 842                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 843                         if (unlikely(--max_wqe == 0))
 844                                 break;
 845                         dseg = (volatile rte_v128u32_t *)
 846                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 847                         rte_prefetch0(tx_mlx5_wqe(txq,
 848                                                   txq->wqe_ci + ds / 4 + 1));
 849                 } else {
 850                         ++dseg;
 851                 }
 852                 ++ds;
 853                 buf = buf->next;
 854                 assert(buf);
 855                 length = DATA_LEN(buf);
 856 #ifdef MLX5_PMD_SOFT_COUNTERS
 857                 total_length += length;
 858 #endif
 859                 /* Store segment information. */
 860                 addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 861                 *dseg = (rte_v128u32_t){
 862                         rte_cpu_to_be_32(length),
 863                         mlx5_tx_mb2mr(txq, buf),
 864                         addr_64,
 865                         addr_64 >> 32,
 866                 };
 867                 (*txq->elts)[++elts_head & elts_m] = buf;
 868                 if (--segs_n)
 869                         goto next_seg;
 870 next_pkt:
 871                 if (ds > MLX5_DSEG_MAX) {
 872                         txq->stats.oerrors++;
 873                         break;
 874                 }
 875                 ++elts_head;
 876                 ++pkts;
 877                 ++i;
 878                 j += sg;
 879                 /* Initialize known and common part of the WQE structure. */
 880                 if (tso) {
 881                         wqe->ctrl = (rte_v128u32_t){
 882                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 883                                                  MLX5_OPCODE_TSO),
 884                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 885                                 0,
 886                                 0,
 887                         };
 888                         wqe->eseg = (rte_v128u32_t){
 889                                 swp_offsets,
 890                                 cs_flags | (swp_types << 8) |
 891                                 (rte_cpu_to_be_16(tso_segsz) << 16),
 892                                 metadata,
 893                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 894                         };
 895                 } else {
 896                         wqe->ctrl = (rte_v128u32_t){
 897                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 898                                                  MLX5_OPCODE_SEND),
 899                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 900                                 0,
 901                                 0,
 902                         };
 903                         wqe->eseg = (rte_v128u32_t){
 904                                 swp_offsets,
 905                                 cs_flags | (swp_types << 8),
 906                                 metadata,
 907                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 908                         };
 909                 }
 910 next_wqe:
 911                 txq->wqe_ci += (ds + 3) / 4;
 912                 /* Save the last successful WQE for completion request */
 913                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 914 #ifdef MLX5_PMD_SOFT_COUNTERS
 915                 /* Increment sent bytes counter. */
 916                 txq->stats.obytes += total_length;
 917 #endif
 918         } while (i < pkts_n);
 919         /* Take a shortcut if nothing must be sent. */
 920         if (unlikely((i + k) == 0))
 921                 return 0;
 922         txq->elts_head += (i + j);
 923         /* Check whether completion threshold has been reached. */
 924         comp = txq->elts_comp + i + j + k;
 925         if (comp >= MLX5_TX_COMP_THRESH) {
 926                 /* A CQE slot must always be available. */
 927                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
 928                 /* Request completion on last WQE. */
 929                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 930                 /* Save elts_head in unused "immediate" field of WQE. */
 931                 last_wqe->ctrl3 = txq->elts_head;
 932                 txq->elts_comp = 0;
 933         } else {
 934                 txq->elts_comp = comp;
 935         }
 936 #ifdef MLX5_PMD_SOFT_COUNTERS
 937         /* Increment sent packets counter. */
 938         txq->stats.opackets += i;
 939 #endif
 940         /* Ring QP doorbell. */
 941         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 942         return i;
 943 }
 944
 945 /**
 946  * Open a MPW session.
 947  *
 948  * @param txq
 949  *   Pointer to TX queue structure.
 950  * @param mpw
 951  *   Pointer to MPW session structure.
 952  * @param length
 953  *   Packet length.
 954  */
 955 static inline void
 956 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 957 {
 958         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 959         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 960                 (volatile struct mlx5_wqe_data_seg (*)[])
 961                 tx_mlx5_wqe(txq, idx + 1);
 962
 963         mpw->state = MLX5_MPW_STATE_OPENED;
 964         mpw->pkts_n = 0;
 965         mpw->len = length;
 966         mpw->total_len = 0;
 967         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 968         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 969         mpw->wqe->eseg.inline_hdr_sz = 0;
 970         mpw->wqe->eseg.rsvd0 = 0;
 971         mpw->wqe->eseg.rsvd1 = 0;
 972         mpw->wqe->eseg.flow_table_metadata = 0;
 973         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 974                                              (txq->wqe_ci << 8) |
 975                                              MLX5_OPCODE_TSO);
 976         mpw->wqe->ctrl[2] = 0;
 977         mpw->wqe->ctrl[3] = 0;
 978         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 979                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 980         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 981                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 982         mpw->data.dseg[2] = &(*dseg)[0];
 983         mpw->data.dseg[3] = &(*dseg)[1];
 984         mpw->data.dseg[4] = &(*dseg)[2];
 985 }
 986
 987 /**
 988  * Close a MPW session.
 989  *
 990  * @param txq
 991  *   Pointer to TX queue structure.
 992  * @param mpw
 993  *   Pointer to MPW session structure.
 994  */
 995 static inline void
 996 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 997 {
 998         unsigned int num = mpw->pkts_n;
 999
1000         /*
1001          * Store size in multiple of 16 bytes. Control and Ethernet segments
1002          * count as 2.
1003          */
1004         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
1005         mpw->state = MLX5_MPW_STATE_CLOSED;
1006         if (num < 3)
1007                 ++txq->wqe_ci;
1008         else
1009                 txq->wqe_ci += 2;
1010         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1011         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1012 }
1013
1014 /**
1015  * DPDK callback for TX with MPW support.
1016  *
1017  * @param dpdk_txq
1018  *   Generic pointer to TX queue structure.
1019  * @param[in] pkts
1020  *   Packets to transmit.
1021  * @param pkts_n
1022  *   Number of packets in array.
1023  *
1024  * @return
1025  *   Number of packets successfully transmitted (<= pkts_n).
1026  */
1027 uint16_t
1028 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1029 {
1030         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1031         uint16_t elts_head = txq->elts_head;
1032         const uint16_t elts_n = 1 << txq->elts_n;
1033         const uint16_t elts_m = elts_n - 1;
1034         unsigned int i = 0;
1035         unsigned int j = 0;
1036         uint16_t max_elts;
1037         uint16_t max_wqe;
1038         unsigned int comp;
1039         struct mlx5_mpw mpw = {
1040                 .state = MLX5_MPW_STATE_CLOSED,
1041         };
1042
1043         if (unlikely(!pkts_n))
1044                 return 0;
1045         /* Prefetch first packet cacheline. */
1046         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1047         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1048         /* Start processing. */
1049         mlx5_tx_complete(txq);
1050         max_elts = (elts_n - (elts_head - txq->elts_tail));
1051         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1052         if (unlikely(!max_wqe))
1053                 return 0;
1054         do {
1055                 struct rte_mbuf *buf = *(pkts++);
1056                 uint32_t length;
1057                 unsigned int segs_n = buf->nb_segs;
1058                 uint32_t cs_flags;
1059                 rte_be32_t metadata;
1060
1061                 /*
1062                  * Make sure there is enough room to store this packet and
1063                  * that one ring entry remains unused.
1064                  */
1065                 assert(segs_n);
1066                 if (max_elts < segs_n)
1067                         break;
1068                 /* Do not bother with large packets MPW cannot handle. */
1069                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1070                         txq->stats.oerrors++;
1071                         break;
1072                 }
1073                 max_elts -= segs_n;
1074                 --pkts_n;
1075                 cs_flags = txq_ol_cksum_to_cs(buf);
1076                 /* Copy metadata from mbuf if valid */
1077                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1078                                                              0;
1079                 /* Retrieve packet information. */
1080                 length = PKT_LEN(buf);
1081                 assert(length);
1082                 /* Start new session if packet differs. */
1083                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1084                     ((mpw.len != length) ||
1085                      (segs_n != 1) ||
1086                      (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1087                      (mpw.wqe->eseg.cs_flags != cs_flags)))
1088                         mlx5_mpw_close(txq, &mpw);
1089                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1090                         /*
1091                          * Multi-Packet WQE consumes at most two WQE.
1092                          * mlx5_mpw_new() expects to be able to use such
1093                          * resources.
1094                          */
1095                         if (unlikely(max_wqe < 2))
1096                                 break;
1097                         max_wqe -= 2;
1098                         mlx5_mpw_new(txq, &mpw, length);
1099                         mpw.wqe->eseg.cs_flags = cs_flags;
1100                         mpw.wqe->eseg.flow_table_metadata = metadata;
1101                 }
1102                 /* Multi-segment packets must be alone in their MPW. */
1103                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1104 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1105                 length = 0;
1106 #endif
1107                 do {
1108                         volatile struct mlx5_wqe_data_seg *dseg;
1109                         uintptr_t addr;
1110
1111                         assert(buf);
1112                         (*txq->elts)[elts_head++ & elts_m] = buf;
1113                         dseg = mpw.data.dseg[mpw.pkts_n];
1114                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1115                         *dseg = (struct mlx5_wqe_data_seg){
1116                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1117                                 .lkey = mlx5_tx_mb2mr(txq, buf),
1118                                 .addr = rte_cpu_to_be_64(addr),
1119                         };
1120 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1121                         length += DATA_LEN(buf);
1122 #endif
1123                         buf = buf->next;
1124                         ++mpw.pkts_n;
1125                         ++j;
1126                 } while (--segs_n);
1127                 assert(length == mpw.len);
1128                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1129                         mlx5_mpw_close(txq, &mpw);
1130 #ifdef MLX5_PMD_SOFT_COUNTERS
1131                 /* Increment sent bytes counter. */
1132                 txq->stats.obytes += length;
1133 #endif
1134                 ++i;
1135         } while (pkts_n);
1136         /* Take a shortcut if nothing must be sent. */
1137         if (unlikely(i == 0))
1138                 return 0;
1139         /* Check whether completion threshold has been reached. */
1140         /* "j" includes both packets and segments. */
1141         comp = txq->elts_comp + j;
1142         if (comp >= MLX5_TX_COMP_THRESH) {
1143                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1144
1145                 /* A CQE slot must always be available. */
1146                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1147                 /* Request completion on last WQE. */
1148                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1149                 /* Save elts_head in unused "immediate" field of WQE. */
1150                 wqe->ctrl[3] = elts_head;
1151                 txq->elts_comp = 0;
1152         } else {
1153                 txq->elts_comp = comp;
1154         }
1155 #ifdef MLX5_PMD_SOFT_COUNTERS
1156         /* Increment sent packets counter. */
1157         txq->stats.opackets += i;
1158 #endif
1159         /* Ring QP doorbell. */
1160         if (mpw.state == MLX5_MPW_STATE_OPENED)
1161                 mlx5_mpw_close(txq, &mpw);
1162         mlx5_tx_dbrec(txq, mpw.wqe);
1163         txq->elts_head = elts_head;
1164         return i;
1165 }
1166
1167 /**
1168  * Open a MPW inline session.
1169  *
1170  * @param txq
1171  *   Pointer to TX queue structure.
1172  * @param mpw
1173  *   Pointer to MPW session structure.
1174  * @param length
1175  *   Packet length.
1176  */
1177 static inline void
1178 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1179                     uint32_t length)
1180 {
1181         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1182         struct mlx5_wqe_inl_small *inl;
1183
1184         mpw->state = MLX5_MPW_INL_STATE_OPENED;
1185         mpw->pkts_n = 0;
1186         mpw->len = length;
1187         mpw->total_len = 0;
1188         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1189         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1190                                              (txq->wqe_ci << 8) |
1191                                              MLX5_OPCODE_TSO);
1192         mpw->wqe->ctrl[2] = 0;
1193         mpw->wqe->ctrl[3] = 0;
1194         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1195         mpw->wqe->eseg.inline_hdr_sz = 0;
1196         mpw->wqe->eseg.cs_flags = 0;
1197         mpw->wqe->eseg.rsvd0 = 0;
1198         mpw->wqe->eseg.rsvd1 = 0;
1199         mpw->wqe->eseg.flow_table_metadata = 0;
1200         inl = (struct mlx5_wqe_inl_small *)
1201                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1202         mpw->data.raw = (uint8_t *)&inl->raw;
1203 }
1204
1205 /**
1206  * Close a MPW inline session.
1207  *
1208  * @param txq
1209  *   Pointer to TX queue structure.
1210  * @param mpw
1211  *   Pointer to MPW session structure.
1212  */
1213 static inline void
1214 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1215 {
1216         unsigned int size;
1217         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1218                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1219
1220         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1221         /*
1222          * Store size in multiple of 16 bytes. Control and Ethernet segments
1223          * count as 2.
1224          */
1225         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1226                                              MLX5_WQE_DS(size));
1227         mpw->state = MLX5_MPW_STATE_CLOSED;
1228         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1229         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1230 }
1231
1232 /**
1233  * DPDK callback for TX with MPW inline support.
1234  *
1235  * @param dpdk_txq
1236  *   Generic pointer to TX queue structure.
1237  * @param[in] pkts
1238  *   Packets to transmit.
1239  * @param pkts_n
1240  *   Number of packets in array.
1241  *
1242  * @return
1243  *   Number of packets successfully transmitted (<= pkts_n).
1244  */
1245 uint16_t
1246 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1247                          uint16_t pkts_n)
1248 {
1249         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1250         uint16_t elts_head = txq->elts_head;
1251         const uint16_t elts_n = 1 << txq->elts_n;
1252         const uint16_t elts_m = elts_n - 1;
1253         unsigned int i = 0;
1254         unsigned int j = 0;
1255         uint16_t max_elts;
1256         uint16_t max_wqe;
1257         unsigned int comp;
1258         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1259         struct mlx5_mpw mpw = {
1260                 .state = MLX5_MPW_STATE_CLOSED,
1261         };
1262         /*
1263          * Compute the maximum number of WQE which can be consumed by inline
1264          * code.
1265          * - 2 DSEG for:
1266          *   - 1 control segment,
1267          *   - 1 Ethernet segment,
1268          * - N Dseg from the inline request.
1269          */
1270         const unsigned int wqe_inl_n =
1271                 ((2 * MLX5_WQE_DWORD_SIZE +
1272                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1273                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1274
1275         if (unlikely(!pkts_n))
1276                 return 0;
1277         /* Prefetch first packet cacheline. */
1278         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1279         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1280         /* Start processing. */
1281         mlx5_tx_complete(txq);
1282         max_elts = (elts_n - (elts_head - txq->elts_tail));
1283         do {
1284                 struct rte_mbuf *buf = *(pkts++);
1285                 uintptr_t addr;
1286                 uint32_t length;
1287                 unsigned int segs_n = buf->nb_segs;
1288                 uint8_t cs_flags;
1289                 rte_be32_t metadata;
1290
1291                 /*
1292                  * Make sure there is enough room to store this packet and
1293                  * that one ring entry remains unused.
1294                  */
1295                 assert(segs_n);
1296                 if (max_elts < segs_n)
1297                         break;
1298                 /* Do not bother with large packets MPW cannot handle. */
1299                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1300                         txq->stats.oerrors++;
1301                         break;
1302                 }
1303                 max_elts -= segs_n;
1304                 --pkts_n;
1305                 /*
1306                  * Compute max_wqe in case less WQE were consumed in previous
1307                  * iteration.
1308                  */
1309                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1310                 cs_flags = txq_ol_cksum_to_cs(buf);
1311                 /* Copy metadata from mbuf if valid */
1312                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1313                                                              0;
1314                 /* Retrieve packet information. */
1315                 length = PKT_LEN(buf);
1316                 /* Start new session if packet differs. */
1317                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1318                         if ((mpw.len != length) ||
1319                             (segs_n != 1) ||
1320                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1321                             (mpw.wqe->eseg.cs_flags != cs_flags))
1322                                 mlx5_mpw_close(txq, &mpw);
1323                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1324                         if ((mpw.len != length) ||
1325                             (segs_n != 1) ||
1326                             (length > inline_room) ||
1327                             (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1328                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1329                                 mlx5_mpw_inline_close(txq, &mpw);
1330                                 inline_room =
1331                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1332                         }
1333                 }
1334                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1335                         if ((segs_n != 1) ||
1336                             (length > inline_room)) {
1337                                 /*
1338                                  * Multi-Packet WQE consumes at most two WQE.
1339                                  * mlx5_mpw_new() expects to be able to use
1340                                  * such resources.
1341                                  */
1342                                 if (unlikely(max_wqe < 2))
1343                                         break;
1344                                 max_wqe -= 2;
1345                                 mlx5_mpw_new(txq, &mpw, length);
1346                                 mpw.wqe->eseg.cs_flags = cs_flags;
1347                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1348                         } else {
1349                                 if (unlikely(max_wqe < wqe_inl_n))
1350                                         break;
1351                                 max_wqe -= wqe_inl_n;
1352                                 mlx5_mpw_inline_new(txq, &mpw, length);
1353                                 mpw.wqe->eseg.cs_flags = cs_flags;
1354                                 mpw.wqe->eseg.flow_table_metadata = metadata;
1355                         }
1356                 }
1357                 /* Multi-segment packets must be alone in their MPW. */
1358                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1359                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1360                         assert(inline_room ==
1361                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1362 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1363                         length = 0;
1364 #endif
1365                         do {
1366                                 volatile struct mlx5_wqe_data_seg *dseg;
1367
1368                                 assert(buf);
1369                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1370                                 dseg = mpw.data.dseg[mpw.pkts_n];
1371                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1372                                 *dseg = (struct mlx5_wqe_data_seg){
1373                                         .byte_count =
1374                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1375                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1376                                         .addr = rte_cpu_to_be_64(addr),
1377                                 };
1378 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1379                                 length += DATA_LEN(buf);
1380 #endif
1381                                 buf = buf->next;
1382                                 ++mpw.pkts_n;
1383                                 ++j;
1384                         } while (--segs_n);
1385                         assert(length == mpw.len);
1386                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1387                                 mlx5_mpw_close(txq, &mpw);
1388                 } else {
1389                         unsigned int max;
1390
1391                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1392                         assert(length <= inline_room);
1393                         assert(length == DATA_LEN(buf));
1394                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1395                         (*txq->elts)[elts_head++ & elts_m] = buf;
1396                         /* Maximum number of bytes before wrapping. */
1397                         max = ((((uintptr_t)(txq->wqes)) +
1398                                 (1 << txq->wqe_n) *
1399                                 MLX5_WQE_SIZE) -
1400                                (uintptr_t)mpw.data.raw);
1401                         if (length > max) {
1402                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1403                                            (void *)addr,
1404                                            max);
1405                                 mpw.data.raw = (volatile void *)txq->wqes;
1406                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1407                                            (void *)(addr + max),
1408                                            length - max);
1409                                 mpw.data.raw += length - max;
1410                         } else {
1411                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1412                                            (void *)addr,
1413                                            length);
1414
1415                                 if (length == max)
1416                                         mpw.data.raw =
1417                                                 (volatile void *)txq->wqes;
1418                                 else
1419                                         mpw.data.raw += length;
1420                         }
1421                         ++mpw.pkts_n;
1422                         mpw.total_len += length;
1423                         ++j;
1424                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1425                                 mlx5_mpw_inline_close(txq, &mpw);
1426                                 inline_room =
1427                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1428                         } else {
1429                                 inline_room -= length;
1430                         }
1431                 }
1432 #ifdef MLX5_PMD_SOFT_COUNTERS
1433                 /* Increment sent bytes counter. */
1434                 txq->stats.obytes += length;
1435 #endif
1436                 ++i;
1437         } while (pkts_n);
1438         /* Take a shortcut if nothing must be sent. */
1439         if (unlikely(i == 0))
1440                 return 0;
1441         /* Check whether completion threshold has been reached. */
1442         /* "j" includes both packets and segments. */
1443         comp = txq->elts_comp + j;
1444         if (comp >= MLX5_TX_COMP_THRESH) {
1445                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1446
1447                 /* A CQE slot must always be available. */
1448                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1449                 /* Request completion on last WQE. */
1450                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1451                 /* Save elts_head in unused "immediate" field of WQE. */
1452                 wqe->ctrl[3] = elts_head;
1453                 txq->elts_comp = 0;
1454         } else {
1455                 txq->elts_comp = comp;
1456         }
1457 #ifdef MLX5_PMD_SOFT_COUNTERS
1458         /* Increment sent packets counter. */
1459         txq->stats.opackets += i;
1460 #endif
1461         /* Ring QP doorbell. */
1462         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1463                 mlx5_mpw_inline_close(txq, &mpw);
1464         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1465                 mlx5_mpw_close(txq, &mpw);
1466         mlx5_tx_dbrec(txq, mpw.wqe);
1467         txq->elts_head = elts_head;
1468         return i;
1469 }
1470
1471 /**
1472  * Open an Enhanced MPW session.
1473  *
1474  * @param txq
1475  *   Pointer to TX queue structure.
1476  * @param mpw
1477  *   Pointer to MPW session structure.
1478  * @param length
1479  *   Packet length.
1480  */
1481 static inline void
1482 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1483 {
1484         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1485
1486         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1487         mpw->pkts_n = 0;
1488         mpw->total_len = sizeof(struct mlx5_wqe);
1489         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1490         mpw->wqe->ctrl[0] =
1491                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1492                                  (txq->wqe_ci << 8) |
1493                                  MLX5_OPCODE_ENHANCED_MPSW);
1494         mpw->wqe->ctrl[2] = 0;
1495         mpw->wqe->ctrl[3] = 0;
1496         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1497         if (unlikely(padding)) {
1498                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1499
1500                 /* Pad the first 2 DWORDs with zero-length inline header. */
1501                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1502                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1503                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1504                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1505                 /* Start from the next WQEBB. */
1506                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1507         } else {
1508                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1509         }
1510 }
1511
1512 /**
1513  * Close an Enhanced MPW session.
1514  *
1515  * @param txq
1516  *   Pointer to TX queue structure.
1517  * @param mpw
1518  *   Pointer to MPW session structure.
1519  *
1520  * @return
1521  *   Number of consumed WQEs.
1522  */
1523 static inline uint16_t
1524 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1525 {
1526         uint16_t ret;
1527
1528         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1529          * count as 2.
1530          */
1531         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1532                                              MLX5_WQE_DS(mpw->total_len));
1533         mpw->state = MLX5_MPW_STATE_CLOSED;
1534         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1535         txq->wqe_ci += ret;
1536         return ret;
1537 }
1538
1539 /**
1540  * TX with Enhanced MPW support.
1541  *
1542  * @param txq
1543  *   Pointer to TX queue structure.
1544  * @param[in] pkts
1545  *   Packets to transmit.
1546  * @param pkts_n
1547  *   Number of packets in array.
1548  *
1549  * @return
1550  *   Number of packets successfully transmitted (<= pkts_n).
1551  */
1552 static inline uint16_t
1553 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1554                uint16_t pkts_n)
1555 {
1556         uint16_t elts_head = txq->elts_head;
1557         const uint16_t elts_n = 1 << txq->elts_n;
1558         const uint16_t elts_m = elts_n - 1;
1559         unsigned int i = 0;
1560         unsigned int j = 0;
1561         uint16_t max_elts;
1562         uint16_t max_wqe;
1563         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1564         unsigned int mpw_room = 0;
1565         unsigned int inl_pad = 0;
1566         uint32_t inl_hdr;
1567         uint64_t addr_64;
1568         struct mlx5_mpw mpw = {
1569                 .state = MLX5_MPW_STATE_CLOSED,
1570         };
1571
1572         if (unlikely(!pkts_n))
1573                 return 0;
1574         /* Start processing. */
1575         mlx5_tx_complete(txq);
1576         max_elts = (elts_n - (elts_head - txq->elts_tail));
1577         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1578         if (unlikely(!max_wqe))
1579                 return 0;
1580         do {
1581                 struct rte_mbuf *buf = *(pkts++);
1582                 uintptr_t addr;
1583                 unsigned int do_inline = 0; /* Whether inline is possible. */
1584                 uint32_t length;
1585                 uint8_t cs_flags;
1586                 rte_be32_t metadata;
1587
1588                 /* Multi-segmented packet is handled in slow-path outside. */
1589                 assert(NB_SEGS(buf) == 1);
1590                 /* Make sure there is enough room to store this packet. */
1591                 if (max_elts - j == 0)
1592                         break;
1593                 cs_flags = txq_ol_cksum_to_cs(buf);
1594                 /* Copy metadata from mbuf if valid */
1595                 metadata = buf->ol_flags & PKT_TX_METADATA ? buf->tx_metadata :
1596                                                              0;
1597                 /* Retrieve packet information. */
1598                 length = PKT_LEN(buf);
1599                 /* Start new session if:
1600                  * - multi-segment packet
1601                  * - no space left even for a dseg
1602                  * - next packet can be inlined with a new WQE
1603                  * - cs_flag differs
1604                  */
1605                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1606                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1607                              mpw_room) ||
1608                             (length <= txq->inline_max_packet_sz &&
1609                              inl_pad + sizeof(inl_hdr) + length >
1610                              mpw_room) ||
1611                              (mpw.wqe->eseg.flow_table_metadata != metadata) ||
1612                             (mpw.wqe->eseg.cs_flags != cs_flags))
1613                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1614                 }
1615                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1616                         /* In Enhanced MPW, inline as much as the budget is
1617                          * allowed. The remaining space is to be filled with
1618                          * dsegs. If the title WQEBB isn't padded, it will have
1619                          * 2 dsegs there.
1620                          */
1621                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1622                                            (max_inline ? max_inline :
1623                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1624                                            MLX5_WQE_SIZE);
1625                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1626                                 break;
1627                         /* Don't pad the title WQEBB to not waste WQ. */
1628                         mlx5_empw_new(txq, &mpw, 0);
1629                         mpw_room -= mpw.total_len;
1630                         inl_pad = 0;
1631                         do_inline = length <= txq->inline_max_packet_sz &&
1632                                     sizeof(inl_hdr) + length <= mpw_room &&
1633                                     !txq->mpw_hdr_dseg;
1634                         mpw.wqe->eseg.cs_flags = cs_flags;
1635                         mpw.wqe->eseg.flow_table_metadata = metadata;
1636                 } else {
1637                         /* Evaluate whether the next packet can be inlined.
1638                          * Inlininig is possible when:
1639                          * - length is less than configured value
1640                          * - length fits for remaining space
1641                          * - not required to fill the title WQEBB with dsegs
1642                          */
1643                         do_inline =
1644                                 length <= txq->inline_max_packet_sz &&
1645                                 inl_pad + sizeof(inl_hdr) + length <=
1646                                  mpw_room &&
1647                                 (!txq->mpw_hdr_dseg ||
1648                                  mpw.total_len >= MLX5_WQE_SIZE);
1649                 }
1650                 if (max_inline && do_inline) {
1651                         /* Inline packet into WQE. */
1652                         unsigned int max;
1653
1654                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1655                         assert(length == DATA_LEN(buf));
1656                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1657                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1658                         mpw.data.raw = (volatile void *)
1659                                 ((uintptr_t)mpw.data.raw + inl_pad);
1660                         max = tx_mlx5_wq_tailroom(txq,
1661                                         (void *)(uintptr_t)mpw.data.raw);
1662                         /* Copy inline header. */
1663                         mpw.data.raw = (volatile void *)
1664                                 mlx5_copy_to_wq(
1665                                           (void *)(uintptr_t)mpw.data.raw,
1666                                           &inl_hdr,
1667                                           sizeof(inl_hdr),
1668                                           (void *)(uintptr_t)txq->wqes,
1669                                           max);
1670                         max = tx_mlx5_wq_tailroom(txq,
1671                                         (void *)(uintptr_t)mpw.data.raw);
1672                         /* Copy packet data. */
1673                         mpw.data.raw = (volatile void *)
1674                                 mlx5_copy_to_wq(
1675                                           (void *)(uintptr_t)mpw.data.raw,
1676                                           (void *)addr,
1677                                           length,
1678                                           (void *)(uintptr_t)txq->wqes,
1679                                           max);
1680                         ++mpw.pkts_n;
1681                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1682                         /* No need to get completion as the entire packet is
1683                          * copied to WQ. Free the buf right away.
1684                          */
1685                         rte_pktmbuf_free_seg(buf);
1686                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1687                         /* Add pad in the next packet if any. */
1688                         inl_pad = (((uintptr_t)mpw.data.raw +
1689                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1690                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1691                                   (uintptr_t)mpw.data.raw;
1692                 } else {
1693                         /* No inline. Load a dseg of packet pointer. */
1694                         volatile rte_v128u32_t *dseg;
1695
1696                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1697                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1698                         assert(length == DATA_LEN(buf));
1699                         if (!tx_mlx5_wq_tailroom(txq,
1700                                         (void *)((uintptr_t)mpw.data.raw
1701                                                 + inl_pad)))
1702                                 dseg = (volatile void *)txq->wqes;
1703                         else
1704                                 dseg = (volatile void *)
1705                                         ((uintptr_t)mpw.data.raw +
1706                                          inl_pad);
1707                         (*txq->elts)[elts_head++ & elts_m] = buf;
1708                         addr_64 = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1709                                                                     uintptr_t));
1710                         *dseg = (rte_v128u32_t) {
1711                                 rte_cpu_to_be_32(length),
1712                                 mlx5_tx_mb2mr(txq, buf),
1713                                 addr_64,
1714                                 addr_64 >> 32,
1715                         };
1716                         mpw.data.raw = (volatile void *)(dseg + 1);
1717                         mpw.total_len += (inl_pad + sizeof(*dseg));
1718                         ++j;
1719                         ++mpw.pkts_n;
1720                         mpw_room -= (inl_pad + sizeof(*dseg));
1721                         inl_pad = 0;
1722                 }
1723 #ifdef MLX5_PMD_SOFT_COUNTERS
1724                 /* Increment sent bytes counter. */
1725                 txq->stats.obytes += length;
1726 #endif
1727                 ++i;
1728         } while (i < pkts_n);
1729         /* Take a shortcut if nothing must be sent. */
1730         if (unlikely(i == 0))
1731                 return 0;
1732         /* Check whether completion threshold has been reached. */
1733         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1734                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1735                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1736                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1737
1738                 /* A CQE slot must always be available. */
1739                 assert((1u << txq->cqe_n) - (txq->cq_pi++ - txq->cq_ci));
1740                 /* Request completion on last WQE. */
1741                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1742                 /* Save elts_head in unused "immediate" field of WQE. */
1743                 wqe->ctrl[3] = elts_head;
1744                 txq->elts_comp = 0;
1745                 txq->mpw_comp = txq->wqe_ci;
1746         } else {
1747                 txq->elts_comp += j;
1748         }
1749 #ifdef MLX5_PMD_SOFT_COUNTERS
1750         /* Increment sent packets counter. */
1751         txq->stats.opackets += i;
1752 #endif
1753         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1754                 mlx5_empw_close(txq, &mpw);
1755         /* Ring QP doorbell. */
1756         mlx5_tx_dbrec(txq, mpw.wqe);
1757         txq->elts_head = elts_head;
1758         return i;
1759 }
1760
1761 /**
1762  * DPDK callback for TX with Enhanced MPW support.
1763  *
1764  * @param dpdk_txq
1765  *   Generic pointer to TX queue structure.
1766  * @param[in] pkts
1767  *   Packets to transmit.
1768  * @param pkts_n
1769  *   Number of packets in array.
1770  *
1771  * @return
1772  *   Number of packets successfully transmitted (<= pkts_n).
1773  */
1774 uint16_t
1775 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1776 {
1777         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1778         uint16_t nb_tx = 0;
1779
1780         while (pkts_n > nb_tx) {
1781                 uint16_t n;
1782                 uint16_t ret;
1783
1784                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1785                 if (n) {
1786                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1787                         if (!ret)
1788                                 break;
1789                         nb_tx += ret;
1790                 }
1791                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1792                 if (n) {
1793                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1794                         if (!ret)
1795                                 break;
1796                         nb_tx += ret;
1797                 }
1798         }
1799         return nb_tx;
1800 }
1801
1802 /**
1803  * Translate RX completion flags to packet type.
1804  *
1805  * @param[in] rxq
1806  *   Pointer to RX queue structure.
1807  * @param[in] cqe
1808  *   Pointer to CQE.
1809  *
1810  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1811  *
1812  * @return
1813  *   Packet type for struct rte_mbuf.
1814  */
1815 static inline uint32_t
1816 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1817 {
1818         uint8_t idx;
1819         uint8_t pinfo = cqe->pkt_info;
1820         uint16_t ptype = cqe->hdr_type_etc;
1821
1822         /*
1823          * The index to the array should have:
1824          * bit[1:0] = l3_hdr_type
1825          * bit[4:2] = l4_hdr_type
1826          * bit[5] = ip_frag
1827          * bit[6] = tunneled
1828          * bit[7] = outer_l3_type
1829          */
1830         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1831         return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1832 }
1833
1834 /**
1835  * Initialize Rx WQ and indexes.
1836  *
1837  * @param[in] rxq
1838  *   Pointer to RX queue structure.
1839  */
1840 void
1841 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
1842 {
1843         const unsigned int wqe_n = 1 << rxq->elts_n;
1844         unsigned int i;
1845
1846         for (i = 0; (i != wqe_n); ++i) {
1847                 volatile struct mlx5_wqe_data_seg *scat;
1848                 uintptr_t addr;
1849                 uint32_t byte_count;
1850
1851                 if (mlx5_rxq_mprq_enabled(rxq)) {
1852                         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
1853
1854                         scat = &((volatile struct mlx5_wqe_mprq *)
1855                                 rxq->wqes)[i].dseg;
1856                         addr = (uintptr_t)mlx5_mprq_buf_addr(buf);
1857                         byte_count = (1 << rxq->strd_sz_n) *
1858                                         (1 << rxq->strd_num_n);
1859                 } else {
1860                         struct rte_mbuf *buf = (*rxq->elts)[i];
1861
1862                         scat = &((volatile struct mlx5_wqe_data_seg *)
1863                                         rxq->wqes)[i];
1864                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1865                         byte_count = DATA_LEN(buf);
1866                 }
1867                 /* scat->addr must be able to store a pointer. */
1868                 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
1869                 *scat = (struct mlx5_wqe_data_seg){
1870                         .addr = rte_cpu_to_be_64(addr),
1871                         .byte_count = rte_cpu_to_be_32(byte_count),
1872                         .lkey = mlx5_rx_addr2mr(rxq, addr),
1873                 };
1874         }
1875         rxq->consumed_strd = 0;
1876         rxq->decompressed = 0;
1877         rxq->rq_pi = 0;
1878         rxq->zip = (struct rxq_zip){
1879                 .ai = 0,
1880         };
1881         /* Update doorbell counter. */
1882         rxq->rq_ci = wqe_n >> rxq->sges_n;
1883         rte_cio_wmb();
1884         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1885 }
1886
1887 /**
1888  * Handle a Rx error.
1889  * The function inserts the RQ state to reset when the first error CQE is
1890  * shown, then drains the CQ by the caller function loop. When the CQ is empty,
1891  * it moves the RQ state to ready and initializes the RQ.
1892  * Next CQE identification and error counting are in the caller responsibility.
1893  *
1894  * @param[in] rxq
1895  *   Pointer to RX queue structure.
1896  * @param[in] mbuf_prepare
1897  *   Whether to prepare mbufs for the RQ.
1898  *
1899  * @return
1900  *   -1 in case of recovery error, otherwise the CQE status.
1901  */
1902 int
1903 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
1904 {
1905         const uint16_t cqe_n = 1 << rxq->cqe_n;
1906         const uint16_t cqe_mask = cqe_n - 1;
1907         const unsigned int wqe_n = 1 << rxq->elts_n;
1908         struct mlx5_rxq_ctrl *rxq_ctrl =
1909                         container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1910         struct ibv_wq_attr mod = {
1911                 .attr_mask = IBV_WQ_ATTR_STATE,
1912         };
1913         union {
1914                 volatile struct mlx5_cqe *cqe;
1915                 volatile struct mlx5_err_cqe *err_cqe;
1916         } u = {
1917                 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1918         };
1919         int ret;
1920
1921         switch (rxq->err_state) {
1922         case MLX5_RXQ_ERR_STATE_NO_ERROR:
1923                 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1924                 /* Fall-through */
1925         case MLX5_RXQ_ERR_STATE_NEED_RESET:
1926                 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1927                         return -1;
1928                 mod.wq_state = IBV_WQS_RESET;
1929                 ret = mlx5_glue->modify_wq(rxq_ctrl->ibv->wq, &mod);
1930                 if (ret) {
1931                         DRV_LOG(ERR, "Cannot change Rx WQ state to RESET %s\n",
1932                                 strerror(errno));
1933                         return -1;
1934                 }
1935                 if (rxq_ctrl->dump_file_n <
1936                     rxq_ctrl->priv->config.max_dump_files_num) {
1937                         MKSTR(err_str, "Unexpected CQE error syndrome "
1938                               "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1939                               " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1940                               rxq->cqn, rxq_ctrl->ibv->wq->wq_num,
1941                               rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1942                               rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1943                         MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1944                               rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1945                         mlx5_dump_debug_information(name, NULL, err_str, 0);
1946                         mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1947                                                     (const void *)((uintptr_t)
1948                                                                     rxq->cqes),
1949                                                     sizeof(*u.cqe) * cqe_n);
1950                         mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1951                                                     (const void *)((uintptr_t)
1952                                                                     rxq->wqes),
1953                                                     16 * wqe_n);
1954                         rxq_ctrl->dump_file_n++;
1955                 }
1956                 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1957                 /* Fall-through */
1958         case MLX5_RXQ_ERR_STATE_NEED_READY:
1959                 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1960                 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1961                         rte_cio_wmb();
1962                         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1963                         rte_cio_wmb();
1964                         /*
1965                          * The RQ consumer index must be zeroed while moving
1966                          * from RESET state to RDY state.
1967                          */
1968                         *rxq->rq_db = rte_cpu_to_be_32(0);
1969                         rte_cio_wmb();
1970                         mod.wq_state = IBV_WQS_RDY;
1971                         ret = mlx5_glue->modify_wq(rxq_ctrl->ibv->wq, &mod);
1972                         if (ret) {
1973                                 DRV_LOG(ERR, "Cannot change Rx WQ state to RDY"
1974                                         " %s\n", strerror(errno));
1975                                 return -1;
1976                         }
1977                         if (mbuf_prepare) {
1978                                 const uint16_t q_mask = wqe_n - 1;
1979                                 uint16_t elt_idx;
1980                                 struct rte_mbuf **elt;
1981                                 int i;
1982                                 unsigned int n = wqe_n - (rxq->rq_ci -
1983                                                           rxq->rq_pi);
1984
1985                                 for (i = 0; i < (int)n; ++i) {
1986                                         elt_idx = (rxq->rq_ci + i) & q_mask;
1987                                         elt = &(*rxq->elts)[elt_idx];
1988                                         *elt = rte_mbuf_raw_alloc(rxq->mp);
1989                                         if (!*elt) {
1990                                                 for (i--; i >= 0; --i) {
1991                                                         elt_idx = (rxq->rq_ci +
1992                                                                    i) & q_mask;
1993                                                         elt = &(*rxq->elts)
1994                                                                 [elt_idx];
1995                                                         rte_pktmbuf_free_seg
1996                                                                 (*elt);
1997                                                 }
1998                                                 return -1;
1999                                         }
2000                                 }
2001                         }
2002                         mlx5_rxq_initialize(rxq);
2003                         rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
2004                 }
2005                 return ret;
2006         default:
2007                 return -1;
2008         }
2009 }
2010
2011 /**
2012  * Get size of the next packet for a given CQE. For compressed CQEs, the
2013  * consumer index is updated only once all packets of the current one have
2014  * been processed.
2015  *
2016  * @param rxq
2017  *   Pointer to RX queue.
2018  * @param cqe
2019  *   CQE to process.
2020  * @param[out] mcqe
2021  *   Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
2022  *   written.
2023  *
2024  * @return
2025  *   0 in case of empty CQE, otherwise the packet size in bytes.
2026  */
2027 static inline int
2028 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
2029                  uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
2030 {
2031         struct rxq_zip *zip = &rxq->zip;
2032         uint16_t cqe_n = cqe_cnt + 1;
2033         int len;
2034         uint16_t idx, end;
2035
2036         do {
2037                 len = 0;
2038                 /* Process compressed data in the CQE and mini arrays. */
2039                 if (zip->ai) {
2040                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
2041                                 (volatile struct mlx5_mini_cqe8 (*)[8])
2042                                 (uintptr_t)(&(*rxq->cqes)[zip->ca &
2043                                                           cqe_cnt].pkt_info);
2044
2045                         len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
2046                         *mcqe = &(*mc)[zip->ai & 7];
2047                         if ((++zip->ai & 7) == 0) {
2048                                 /* Invalidate consumed CQEs */
2049                                 idx = zip->ca;
2050                                 end = zip->na;
2051                                 while (idx != end) {
2052                                         (*rxq->cqes)[idx & cqe_cnt].op_own =
2053                                                 MLX5_CQE_INVALIDATE;
2054                                         ++idx;
2055                                 }
2056                                 /*
2057                                  * Increment consumer index to skip the number
2058                                  * of CQEs consumed. Hardware leaves holes in
2059                                  * the CQ ring for software use.
2060                                  */
2061                                 zip->ca = zip->na;
2062                                 zip->na += 8;
2063                         }
2064                         if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
2065                                 /* Invalidate the rest */
2066                                 idx = zip->ca;
2067                                 end = zip->cq_ci;
2068
2069                                 while (idx != end) {
2070                                         (*rxq->cqes)[idx & cqe_cnt].op_own =
2071                                                 MLX5_CQE_INVALIDATE;
2072                                         ++idx;
2073                                 }
2074                                 rxq->cq_ci = zip->cq_ci;
2075                                 zip->ai = 0;
2076                         }
2077                 /*
2078                  * No compressed data, get next CQE and verify if it is
2079                  * compressed.
2080                  */
2081                 } else {
2082                         int ret;
2083                         int8_t op_own;
2084
2085                         ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
2086                         if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2087                                 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
2088                                              rxq->err_state)) {
2089                                         ret = mlx5_rx_err_handle(rxq, 0);
2090                                         if (ret == MLX5_CQE_STATUS_HW_OWN ||
2091                                             ret == -1)
2092                                                 return 0;
2093                                 } else {
2094                                         return 0;
2095                                 }
2096                         }
2097                         ++rxq->cq_ci;
2098                         op_own = cqe->op_own;
2099                         if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
2100                                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
2101                                         (volatile struct mlx5_mini_cqe8 (*)[8])
2102                                         (uintptr_t)(&(*rxq->cqes)
2103                                                 [rxq->cq_ci &
2104                                                  cqe_cnt].pkt_info);
2105
2106                                 /* Fix endianness. */
2107                                 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
2108                                 /*
2109                                  * Current mini array position is the one
2110                                  * returned by check_cqe64().
2111                                  *
2112                                  * If completion comprises several mini arrays,
2113                                  * as a special case the second one is located
2114                                  * 7 CQEs after the initial CQE instead of 8
2115                                  * for subsequent ones.
2116                                  */
2117                                 zip->ca = rxq->cq_ci;
2118                                 zip->na = zip->ca + 7;
2119                                 /* Compute the next non compressed CQE. */
2120                                 --rxq->cq_ci;
2121                                 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
2122                                 /* Get packet size to return. */
2123                                 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
2124                                 *mcqe = &(*mc)[0];
2125                                 zip->ai = 1;
2126                                 /* Prefetch all to be invalidated */
2127                                 idx = zip->ca;
2128                                 end = zip->cq_ci;
2129                                 while (idx != end) {
2130                                         rte_prefetch0(&(*rxq->cqes)[(idx) &
2131                                                                     cqe_cnt]);
2132                                         ++idx;
2133                                 }
2134                         } else {
2135                                 len = rte_be_to_cpu_32(cqe->byte_cnt);
2136                         }
2137                 }
2138                 if (unlikely(rxq->err_state)) {
2139                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2140                         ++rxq->stats.idropped;
2141                 } else {
2142                         return len;
2143                 }
2144         } while (1);
2145 }
2146
2147 /**
2148  * Translate RX completion flags to offload flags.
2149  *
2150  * @param[in] cqe
2151  *   Pointer to CQE.
2152  *
2153  * @return
2154  *   Offload flags (ol_flags) for struct rte_mbuf.
2155  */
2156 static inline uint32_t
2157 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
2158 {
2159         uint32_t ol_flags = 0;
2160         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
2161
2162         ol_flags =
2163                 TRANSPOSE(flags,
2164                           MLX5_CQE_RX_L3_HDR_VALID,
2165                           PKT_RX_IP_CKSUM_GOOD) |
2166                 TRANSPOSE(flags,
2167                           MLX5_CQE_RX_L4_HDR_VALID,
2168                           PKT_RX_L4_CKSUM_GOOD);
2169         return ol_flags;
2170 }
2171
2172 /**
2173  * Fill in mbuf fields from RX completion flags.
2174  * Note that pkt->ol_flags should be initialized outside of this function.
2175  *
2176  * @param rxq
2177  *   Pointer to RX queue.
2178  * @param pkt
2179  *   mbuf to fill.
2180  * @param cqe
2181  *   CQE to process.
2182  * @param rss_hash_res
2183  *   Packet RSS Hash result.
2184  */
2185 static inline void
2186 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
2187                volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
2188 {
2189         /* Update packet information. */
2190         pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
2191         if (rss_hash_res && rxq->rss_hash) {
2192                 pkt->hash.rss = rss_hash_res;
2193                 pkt->ol_flags |= PKT_RX_RSS_HASH;
2194         }
2195         if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2196                 pkt->ol_flags |= PKT_RX_FDIR;
2197                 if (cqe->sop_drop_qpn !=
2198                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
2199                         uint32_t mark = cqe->sop_drop_qpn;
2200
2201                         pkt->ol_flags |= PKT_RX_FDIR_ID;
2202                         pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
2203                 }
2204         }
2205         if (rxq->csum)
2206                 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
2207         if (rxq->vlan_strip &&
2208             (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
2209                 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
2210                 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
2211         }
2212         if (rxq->hw_timestamp) {
2213                 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
2214                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
2215         }
2216 }
2217
2218 /**
2219  * DPDK callback for RX.
2220  *
2221  * @param dpdk_rxq
2222  *   Generic pointer to RX queue structure.
2223  * @param[out] pkts
2224  *   Array to store received packets.
2225  * @param pkts_n
2226  *   Maximum number of packets in array.
2227  *
2228  * @return
2229  *   Number of packets successfully received (<= pkts_n).
2230  */
2231 uint16_t
2232 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2233 {
2234         struct mlx5_rxq_data *rxq = dpdk_rxq;
2235         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
2236         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
2237         const unsigned int sges_n = rxq->sges_n;
2238         struct rte_mbuf *pkt = NULL;
2239         struct rte_mbuf *seg = NULL;
2240         volatile struct mlx5_cqe *cqe =
2241                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2242         unsigned int i = 0;
2243         unsigned int rq_ci = rxq->rq_ci << sges_n;
2244         int len = 0; /* keep its value across iterations. */
2245
2246         while (pkts_n) {
2247                 unsigned int idx = rq_ci & wqe_cnt;
2248                 volatile struct mlx5_wqe_data_seg *wqe =
2249                         &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
2250                 struct rte_mbuf *rep = (*rxq->elts)[idx];
2251                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2252                 uint32_t rss_hash_res;
2253
2254                 if (pkt)
2255                         NEXT(seg) = rep;
2256                 seg = rep;
2257                 rte_prefetch0(seg);
2258                 rte_prefetch0(cqe);
2259                 rte_prefetch0(wqe);
2260                 rep = rte_mbuf_raw_alloc(rxq->mp);
2261                 if (unlikely(rep == NULL)) {
2262                         ++rxq->stats.rx_nombuf;
2263                         if (!pkt) {
2264                                 /*
2265                                  * no buffers before we even started,
2266                                  * bail out silently.
2267                                  */
2268                                 break;
2269                         }
2270                         while (pkt != seg) {
2271                                 assert(pkt != (*rxq->elts)[idx]);
2272                                 rep = NEXT(pkt);
2273                                 NEXT(pkt) = NULL;
2274                                 NB_SEGS(pkt) = 1;
2275                                 rte_mbuf_raw_free(pkt);
2276                                 pkt = rep;
2277                         }
2278                         break;
2279                 }
2280                 if (!pkt) {
2281                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2282                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
2283                         if (!len) {
2284                                 rte_mbuf_raw_free(rep);
2285                                 break;
2286                         }
2287                         pkt = seg;
2288                         assert(len >= (rxq->crc_present << 2));
2289                         pkt->ol_flags = 0;
2290                         /* If compressed, take hash result from mini-CQE. */
2291                         rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
2292                                                         cqe->rx_hash_res :
2293                                                         mcqe->rx_hash_result);
2294                         rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2295                         if (rxq->crc_present)
2296                                 len -= RTE_ETHER_CRC_LEN;
2297                         PKT_LEN(pkt) = len;
2298                 }
2299                 DATA_LEN(rep) = DATA_LEN(seg);
2300                 PKT_LEN(rep) = PKT_LEN(seg);
2301                 SET_DATA_OFF(rep, DATA_OFF(seg));
2302                 PORT(rep) = PORT(seg);
2303                 (*rxq->elts)[idx] = rep;
2304                 /*
2305                  * Fill NIC descriptor with the new buffer.  The lkey and size
2306                  * of the buffers are already known, only the buffer address
2307                  * changes.
2308                  */
2309                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2310                 /* If there's only one MR, no need to replace LKey in WQE. */
2311                 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2312                         wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2313                 if (len > DATA_LEN(seg)) {
2314                         len -= DATA_LEN(seg);
2315                         ++NB_SEGS(pkt);
2316                         ++rq_ci;
2317                         continue;
2318                 }
2319                 DATA_LEN(seg) = len;
2320 #ifdef MLX5_PMD_SOFT_COUNTERS
2321                 /* Increment bytes counter. */
2322                 rxq->stats.ibytes += PKT_LEN(pkt);
2323 #endif
2324                 /* Return packet. */
2325                 *(pkts++) = pkt;
2326                 pkt = NULL;
2327                 --pkts_n;
2328                 ++i;
2329                 /* Align consumer index to the next stride. */
2330                 rq_ci >>= sges_n;
2331                 ++rq_ci;
2332                 rq_ci <<= sges_n;
2333         }
2334         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2335                 return 0;
2336         /* Update the consumer index. */
2337         rxq->rq_ci = rq_ci >> sges_n;
2338         rte_cio_wmb();
2339         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2340         rte_cio_wmb();
2341         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2342 #ifdef MLX5_PMD_SOFT_COUNTERS
2343         /* Increment packets counter. */
2344         rxq->stats.ipackets += i;
2345 #endif
2346         return i;
2347 }
2348
2349 void
2350 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2351 {
2352         struct mlx5_mprq_buf *buf = opaque;
2353
2354         if (rte_atomic16_read(&buf->refcnt) == 1) {
2355                 rte_mempool_put(buf->mp, buf);
2356         } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2357                 rte_atomic16_set(&buf->refcnt, 1);
2358                 rte_mempool_put(buf->mp, buf);
2359         }
2360 }
2361
2362 void
2363 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2364 {
2365         mlx5_mprq_buf_free_cb(NULL, buf);
2366 }
2367
2368 static inline void
2369 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2370 {
2371         struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2372         volatile struct mlx5_wqe_data_seg *wqe =
2373                 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2374         void *addr;
2375
2376         assert(rep != NULL);
2377         /* Replace MPRQ buf. */
2378         (*rxq->mprq_bufs)[rq_idx] = rep;
2379         /* Replace WQE. */
2380         addr = mlx5_mprq_buf_addr(rep);
2381         wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2382         /* If there's only one MR, no need to replace LKey in WQE. */
2383         if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2384                 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2385         /* Stash a mbuf for next replacement. */
2386         if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2387                 rxq->mprq_repl = rep;
2388         else
2389                 rxq->mprq_repl = NULL;
2390 }
2391
2392 /**
2393  * DPDK callback for RX with Multi-Packet RQ support.
2394  *
2395  * @param dpdk_rxq
2396  *   Generic pointer to RX queue structure.
2397  * @param[out] pkts
2398  *   Array to store received packets.
2399  * @param pkts_n
2400  *   Maximum number of packets in array.
2401  *
2402  * @return
2403  *   Number of packets successfully received (<= pkts_n).
2404  */
2405 uint16_t
2406 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2407 {
2408         struct mlx5_rxq_data *rxq = dpdk_rxq;
2409         const unsigned int strd_n = 1 << rxq->strd_num_n;
2410         const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2411         const unsigned int strd_shift =
2412                 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2413         const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2414         const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2415         volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2416         unsigned int i = 0;
2417         uint32_t rq_ci = rxq->rq_ci;
2418         uint16_t consumed_strd = rxq->consumed_strd;
2419         struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2420
2421         while (i < pkts_n) {
2422                 struct rte_mbuf *pkt;
2423                 void *addr;
2424                 int ret;
2425                 unsigned int len;
2426                 uint16_t strd_cnt;
2427                 uint16_t strd_idx;
2428                 uint32_t offset;
2429                 uint32_t byte_cnt;
2430                 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2431                 uint32_t rss_hash_res = 0;
2432
2433                 if (consumed_strd == strd_n) {
2434                         /* Replace WQE only if the buffer is still in use. */
2435                         if (rte_atomic16_read(&buf->refcnt) > 1) {
2436                                 mprq_buf_replace(rxq, rq_ci & wq_mask);
2437                                 /* Release the old buffer. */
2438                                 mlx5_mprq_buf_free(buf);
2439                         } else if (unlikely(rxq->mprq_repl == NULL)) {
2440                                 struct mlx5_mprq_buf *rep;
2441
2442                                 /*
2443                                  * Currently, the MPRQ mempool is out of buffer
2444                                  * and doing memcpy regardless of the size of Rx
2445                                  * packet. Retry allocation to get back to
2446                                  * normal.
2447                                  */
2448                                 if (!rte_mempool_get(rxq->mprq_mp,
2449                                                      (void **)&rep))
2450                                         rxq->mprq_repl = rep;
2451                         }
2452                         /* Advance to the next WQE. */
2453                         consumed_strd = 0;
2454                         ++rq_ci;
2455                         buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2456                 }
2457                 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2458                 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2459                 if (!ret)
2460                         break;
2461                 byte_cnt = ret;
2462                 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2463                            MLX5_MPRQ_STRIDE_NUM_SHIFT;
2464                 assert(strd_cnt);
2465                 consumed_strd += strd_cnt;
2466                 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2467                         continue;
2468                 if (mcqe == NULL) {
2469                         rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2470                         strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2471                 } else {
2472                         /* mini-CQE for MPRQ doesn't have hash result. */
2473                         strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2474                 }
2475                 assert(strd_idx < strd_n);
2476                 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2477                 /*
2478                  * Currently configured to receive a packet per a stride. But if
2479                  * MTU is adjusted through kernel interface, device could
2480                  * consume multiple strides without raising an error. In this
2481                  * case, the packet should be dropped because it is bigger than
2482                  * the max_rx_pkt_len.
2483                  */
2484                 if (unlikely(strd_cnt > 1)) {
2485                         ++rxq->stats.idropped;
2486                         continue;
2487                 }
2488                 pkt = rte_pktmbuf_alloc(rxq->mp);
2489                 if (unlikely(pkt == NULL)) {
2490                         ++rxq->stats.rx_nombuf;
2491                         break;
2492                 }
2493                 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2494                 assert((int)len >= (rxq->crc_present << 2));
2495                 if (rxq->crc_present)
2496                         len -= RTE_ETHER_CRC_LEN;
2497                 offset = strd_idx * strd_sz + strd_shift;
2498                 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2499                 /* Initialize the offload flag. */
2500                 pkt->ol_flags = 0;
2501                 /*
2502                  * Memcpy packets to the target mbuf if:
2503                  * - The size of packet is smaller than mprq_max_memcpy_len.
2504                  * - Out of buffer in the Mempool for Multi-Packet RQ.
2505                  */
2506                 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2507                         /*
2508                          * When memcpy'ing packet due to out-of-buffer, the
2509                          * packet must be smaller than the target mbuf.
2510                          */
2511                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2512                                 rte_pktmbuf_free_seg(pkt);
2513                                 ++rxq->stats.idropped;
2514                                 continue;
2515                         }
2516                         rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2517                 } else {
2518                         rte_iova_t buf_iova;
2519                         struct rte_mbuf_ext_shared_info *shinfo;
2520                         uint16_t buf_len = strd_cnt * strd_sz;
2521
2522                         /* Increment the refcnt of the whole chunk. */
2523                         rte_atomic16_add_return(&buf->refcnt, 1);
2524                         assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2525                                strd_n + 1);
2526                         addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2527                         /*
2528                          * MLX5 device doesn't use iova but it is necessary in a
2529                          * case where the Rx packet is transmitted via a
2530                          * different PMD.
2531                          */
2532                         buf_iova = rte_mempool_virt2iova(buf) +
2533                                    RTE_PTR_DIFF(addr, buf);
2534                         shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2535                                         &buf_len, mlx5_mprq_buf_free_cb, buf);
2536                         /*
2537                          * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2538                          * attaching the stride to mbuf and more offload flags
2539                          * will be added below by calling rxq_cq_to_mbuf().
2540                          * Other fields will be overwritten.
2541                          */
2542                         rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2543                                                   shinfo);
2544                         rte_pktmbuf_reset_headroom(pkt);
2545                         assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2546                         /*
2547                          * Prevent potential overflow due to MTU change through
2548                          * kernel interface.
2549                          */
2550                         if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2551                                 rte_pktmbuf_free_seg(pkt);
2552                                 ++rxq->stats.idropped;
2553                                 continue;
2554                         }
2555                 }
2556                 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2557                 PKT_LEN(pkt) = len;
2558                 DATA_LEN(pkt) = len;
2559                 PORT(pkt) = rxq->port_id;
2560 #ifdef MLX5_PMD_SOFT_COUNTERS
2561                 /* Increment bytes counter. */
2562                 rxq->stats.ibytes += PKT_LEN(pkt);
2563 #endif
2564                 /* Return packet. */
2565                 *(pkts++) = pkt;
2566                 ++i;
2567         }
2568         /* Update the consumer indexes. */
2569         rxq->consumed_strd = consumed_strd;
2570         rte_cio_wmb();
2571         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2572         if (rq_ci != rxq->rq_ci) {
2573                 rxq->rq_ci = rq_ci;
2574                 rte_cio_wmb();
2575                 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2576         }
2577 #ifdef MLX5_PMD_SOFT_COUNTERS
2578         /* Increment packets counter. */
2579         rxq->stats.ipackets += i;
2580 #endif
2581         return i;
2582 }
2583
2584 /**
2585  * Dummy DPDK callback for TX.
2586  *
2587  * This function is used to temporarily replace the real callback during
2588  * unsafe control operations on the queue, or in case of error.
2589  *
2590  * @param dpdk_txq
2591  *   Generic pointer to TX queue structure.
2592  * @param[in] pkts
2593  *   Packets to transmit.
2594  * @param pkts_n
2595  *   Number of packets in array.
2596  *
2597  * @return
2598  *   Number of packets successfully transmitted (<= pkts_n).
2599  */
2600 uint16_t
2601 removed_tx_burst(void *dpdk_txq __rte_unused,
2602                  struct rte_mbuf **pkts __rte_unused,
2603                  uint16_t pkts_n __rte_unused)
2604 {
2605         rte_mb();
2606         return 0;
2607 }
2608
2609 /**
2610  * Dummy DPDK callback for RX.
2611  *
2612  * This function is used to temporarily replace the real callback during
2613  * unsafe control operations on the queue, or in case of error.
2614  *
2615  * @param dpdk_rxq
2616  *   Generic pointer to RX queue structure.
2617  * @param[out] pkts
2618  *   Array to store received packets.
2619  * @param pkts_n
2620  *   Maximum number of packets in array.
2621  *
2622  * @return
2623  *   Number of packets successfully received (<= pkts_n).
2624  */
2625 uint16_t
2626 removed_rx_burst(void *dpdk_txq __rte_unused,
2627                  struct rte_mbuf **pkts __rte_unused,
2628                  uint16_t pkts_n __rte_unused)
2629 {
2630         rte_mb();
2631         return 0;
2632 }
2633
2634 /*
2635  * Vectorized Rx/Tx routines are not compiled in when required vector
2636  * instructions are not supported on a target architecture. The following null
2637  * stubs are needed for linkage when those are not included outside of this file
2638  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
2639  */
2640
2641 __rte_weak uint16_t
2642 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2643                       struct rte_mbuf **pkts __rte_unused,
2644                       uint16_t pkts_n __rte_unused)
2645 {
2646         return 0;
2647 }
2648
2649 __rte_weak uint16_t
2650 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2651                   struct rte_mbuf **pkts __rte_unused,
2652                   uint16_t pkts_n __rte_unused)
2653 {
2654         return 0;
2655 }
2656
2657 __rte_weak uint16_t
2658 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2659                   struct rte_mbuf **pkts __rte_unused,
2660                   uint16_t pkts_n __rte_unused)
2661 {
2662         return 0;
2663 }
2664
2665 __rte_weak int
2666 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2667 {
2668         return -ENOTSUP;
2669 }
2670
2671 __rte_weak int
2672 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2673 {
2674         return -ENOTSUP;
2675 }
2676
2677 __rte_weak int
2678 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2679 {
2680         return -ENOTSUP;
2681 }
2682
2683 __rte_weak int
2684 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2685 {
2686         return -ENOTSUP;
2687 }