4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
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18 * contributors may be used to endorse or promote products derived
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Return the size of tailroom of WQ.
201 * Pointer to TX queue structure.
203 * Pointer to tail of WQ.
209 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
212 tailroom = (uintptr_t)(txq->wqes) +
213 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
219 * Copy data to tailroom of circular queue.
222 * Pointer to destination.
226 * Number of bytes to copy.
228 * Pointer to head of queue.
230 * Size of tailroom from dst.
233 * Pointer after copied data.
236 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
237 void *base, size_t tailroom)
242 rte_memcpy(dst, src, tailroom);
243 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
245 ret = (uint8_t *)base + n - tailroom;
247 rte_memcpy(dst, src, n);
248 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
254 * Manage TX completions.
256 * When sending a burst, mlx5_tx_burst() posts several WRs.
259 * Pointer to TX queue structure.
262 txq_complete(struct txq *txq)
264 const unsigned int elts_n = 1 << txq->elts_n;
265 const unsigned int cqe_n = 1 << txq->cqe_n;
266 const unsigned int cqe_cnt = cqe_n - 1;
267 uint16_t elts_free = txq->elts_tail;
269 uint16_t cq_ci = txq->cq_ci;
270 volatile struct mlx5_cqe *cqe = NULL;
271 volatile struct mlx5_wqe_ctrl *ctrl;
274 volatile struct mlx5_cqe *tmp;
276 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
277 if (check_cqe(tmp, cqe_n, cq_ci))
281 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
282 if (!check_cqe_seen(cqe))
283 ERROR("unexpected compressed CQE, TX stopped");
286 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
287 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
288 if (!check_cqe_seen(cqe))
289 ERROR("unexpected error CQE, TX stopped");
295 if (unlikely(cqe == NULL))
297 txq->wqe_pi = ntohs(cqe->wqe_counter);
298 ctrl = (volatile struct mlx5_wqe_ctrl *)
299 tx_mlx5_wqe(txq, txq->wqe_pi);
300 elts_tail = ctrl->ctrl3;
301 assert(elts_tail < (1 << txq->wqe_n));
303 while (elts_free != elts_tail) {
304 struct rte_mbuf *elt = (*txq->elts)[elts_free];
305 unsigned int elts_free_next =
306 (elts_free + 1) & (elts_n - 1);
307 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
311 memset(&(*txq->elts)[elts_free],
313 sizeof((*txq->elts)[elts_free]));
315 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
316 /* Only one segment needs to be freed. */
317 rte_pktmbuf_free_seg(elt);
318 elts_free = elts_free_next;
321 txq->elts_tail = elts_tail;
322 /* Update the consumer index. */
324 *txq->cq_db = htonl(cq_ci);
328 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
329 * the cloned mbuf is allocated is returned instead.
335 * Memory pool where data is located for given mbuf.
337 static struct rte_mempool *
338 txq_mb2mp(struct rte_mbuf *buf)
340 if (unlikely(RTE_MBUF_INDIRECT(buf)))
341 return rte_mbuf_from_indirect(buf)->pool;
346 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
347 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
348 * remove an entry first.
351 * Pointer to TX queue structure.
353 * Memory Pool for which a Memory Region lkey must be returned.
356 * mr->lkey on success, (uint32_t)-1 on failure.
358 static inline uint32_t
359 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
362 uint32_t lkey = (uint32_t)-1;
364 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
365 if (unlikely(txq->mp2mr[i].mp == NULL)) {
366 /* Unknown MP, add a new MR for it. */
369 if (txq->mp2mr[i].mp == mp) {
370 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
371 assert(htonl(txq->mp2mr[i].mr->lkey) ==
373 lkey = txq->mp2mr[i].lkey;
377 if (unlikely(lkey == (uint32_t)-1))
378 lkey = txq_mp2mr_reg(txq, mp, i);
383 * Ring TX queue doorbell.
386 * Pointer to TX queue structure.
388 * Pointer to the last WQE posted in the NIC.
391 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
393 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
394 volatile uint64_t *src = ((volatile uint64_t *)wqe);
397 *txq->qp_db = htonl(txq->wqe_ci);
398 /* Ensure ordering between DB record and BF copy. */
404 * DPDK callback to check the status of a tx descriptor.
409 * The index of the descriptor in the ring.
412 * The status of the tx descriptor.
415 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
417 struct txq *txq = tx_queue;
418 const unsigned int elts_n = 1 << txq->elts_n;
419 const unsigned int elts_cnt = elts_n - 1;
423 used = (txq->elts_head - txq->elts_tail) & elts_cnt;
425 return RTE_ETH_TX_DESC_FULL;
426 return RTE_ETH_TX_DESC_DONE;
430 * DPDK callback to check the status of a rx descriptor.
435 * The index of the descriptor in the ring.
438 * The status of the tx descriptor.
441 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
443 struct rxq *rxq = rx_queue;
444 struct rxq_zip *zip = &rxq->zip;
445 volatile struct mlx5_cqe *cqe;
446 const unsigned int cqe_n = (1 << rxq->cqe_n);
447 const unsigned int cqe_cnt = cqe_n - 1;
451 /* if we are processing a compressed cqe */
453 used = zip->cqe_cnt - zip->ca;
459 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
460 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
464 op_own = cqe->op_own;
465 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
466 n = ntohl(cqe->byte_cnt);
471 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
473 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
475 return RTE_ETH_RX_DESC_DONE;
476 return RTE_ETH_RX_DESC_AVAIL;
480 * DPDK callback for TX.
483 * Generic pointer to TX queue structure.
485 * Packets to transmit.
487 * Number of packets in array.
490 * Number of packets successfully transmitted (<= pkts_n).
493 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
495 struct txq *txq = (struct txq *)dpdk_txq;
496 uint16_t elts_head = txq->elts_head;
497 const unsigned int elts_n = 1 << txq->elts_n;
504 volatile struct mlx5_wqe_v *wqe = NULL;
505 unsigned int segs_n = 0;
506 struct rte_mbuf *buf = NULL;
509 if (unlikely(!pkts_n))
511 /* Prefetch first packet cacheline. */
512 rte_prefetch0(*pkts);
513 /* Start processing. */
515 max = (elts_n - (elts_head - txq->elts_tail));
518 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
519 if (unlikely(!max_wqe))
522 volatile rte_v128u32_t *dseg = NULL;
527 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
528 uint16_t tso_header_sz = 0;
530 uint8_t cs_flags = 0;
532 #ifdef MLX5_PMD_SOFT_COUNTERS
533 uint32_t total_length = 0;
538 segs_n = buf->nb_segs;
540 * Make sure there is enough room to store this packet and
541 * that one ring entry remains unused.
544 if (max < segs_n + 1)
550 if (unlikely(--max_wqe == 0))
552 wqe = (volatile struct mlx5_wqe_v *)
553 tx_mlx5_wqe(txq, txq->wqe_ci);
554 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
556 rte_prefetch0(*pkts);
557 addr = rte_pktmbuf_mtod(buf, uintptr_t);
558 length = DATA_LEN(buf);
559 ehdr = (((uint8_t *)addr)[1] << 8) |
560 ((uint8_t *)addr)[0];
561 #ifdef MLX5_PMD_SOFT_COUNTERS
562 total_length = length;
564 if (length < (MLX5_WQE_DWORD_SIZE + 2))
566 /* Update element. */
567 (*txq->elts)[elts_head] = buf;
568 elts_head = (elts_head + 1) & (elts_n - 1);
569 /* Prefetch next buffer data. */
571 volatile void *pkt_addr;
573 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
574 rte_prefetch0(pkt_addr);
576 /* Should we enable HW CKSUM offload */
578 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
579 const uint64_t is_tunneled = buf->ol_flags &
581 PKT_TX_TUNNEL_VXLAN);
583 if (is_tunneled && txq->tunnel_en) {
584 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
585 MLX5_ETH_WQE_L4_INNER_CSUM;
586 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
587 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
589 cs_flags = MLX5_ETH_WQE_L3_CSUM |
590 MLX5_ETH_WQE_L4_CSUM;
593 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
594 /* Replace the Ethernet type by the VLAN if necessary. */
595 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
596 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
597 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
601 /* Copy Destination and source mac address. */
602 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
604 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
605 /* Copy missing two bytes to end the DSeg. */
606 memcpy((uint8_t *)raw + len + sizeof(vlan),
607 ((uint8_t *)addr) + len, 2);
611 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
612 MLX5_WQE_DWORD_SIZE);
613 length -= pkt_inline_sz;
614 addr += pkt_inline_sz;
617 tso = buf->ol_flags & PKT_TX_TCP_SEG;
619 uintptr_t end = (uintptr_t)
620 (((uintptr_t)txq->wqes) +
624 uint8_t vlan_sz = (buf->ol_flags &
625 PKT_TX_VLAN_PKT) ? 4 : 0;
626 const uint64_t is_tunneled =
629 PKT_TX_TUNNEL_VXLAN);
631 tso_header_sz = buf->l2_len + vlan_sz +
632 buf->l3_len + buf->l4_len;
634 if (is_tunneled && txq->tunnel_en) {
635 tso_header_sz += buf->outer_l2_len +
637 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
639 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
641 if (unlikely(tso_header_sz >
642 MLX5_MAX_TSO_HEADER))
644 copy_b = tso_header_sz - pkt_inline_sz;
645 /* First seg must contain all headers. */
646 assert(copy_b <= length);
647 raw += MLX5_WQE_DWORD_SIZE;
649 ((end - (uintptr_t)raw) > copy_b)) {
650 uint16_t n = (MLX5_WQE_DS(copy_b) -
653 if (unlikely(max_wqe < n))
656 rte_memcpy((void *)raw,
657 (void *)addr, copy_b);
660 pkt_inline_sz += copy_b;
662 * Another DWORD will be added
663 * in the inline part.
665 raw += MLX5_WQE_DS(copy_b) *
666 MLX5_WQE_DWORD_SIZE -
670 wqe->ctrl = (rte_v128u32_t){
671 htonl(txq->wqe_ci << 8),
672 htonl(txq->qp_num_8s | 1),
680 elts_head = (elts_head - 1) &
687 /* Inline if enough room. */
688 if (txq->inline_en || tso) {
689 uintptr_t end = (uintptr_t)
690 (((uintptr_t)txq->wqes) +
691 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
692 unsigned int max_inline = txq->max_inline *
693 RTE_CACHE_LINE_SIZE -
695 uintptr_t addr_end = (addr + max_inline) &
696 ~(RTE_CACHE_LINE_SIZE - 1);
697 unsigned int copy_b = (addr_end > addr) ?
698 RTE_MIN((addr_end - addr), length) :
701 raw += MLX5_WQE_DWORD_SIZE;
702 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
704 * One Dseg remains in the current WQE. To
705 * keep the computation positive, it is
706 * removed after the bytes to Dseg conversion.
708 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
710 if (unlikely(max_wqe < n))
715 htonl(copy_b | MLX5_INLINE_SEG);
718 MLX5_WQE_DS(tso_header_sz) *
720 rte_memcpy((void *)raw,
721 (void *)&inl, sizeof(inl));
723 pkt_inline_sz += sizeof(inl);
725 rte_memcpy((void *)raw, (void *)addr, copy_b);
728 pkt_inline_sz += copy_b;
731 * 2 DWORDs consumed by the WQE header + ETH segment +
732 * the size of the inline part of the packet.
734 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
736 if (ds % (MLX5_WQE_SIZE /
737 MLX5_WQE_DWORD_SIZE) == 0) {
738 if (unlikely(--max_wqe == 0))
740 dseg = (volatile rte_v128u32_t *)
741 tx_mlx5_wqe(txq, txq->wqe_ci +
744 dseg = (volatile rte_v128u32_t *)
746 (ds * MLX5_WQE_DWORD_SIZE));
749 } else if (!segs_n) {
752 /* dseg will be advance as part of next_seg */
753 dseg = (volatile rte_v128u32_t *)
755 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
760 * No inline has been done in the packet, only the
761 * Ethernet Header as been stored.
763 dseg = (volatile rte_v128u32_t *)
764 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
767 /* Add the remaining packet as a simple ds. */
768 naddr = htonll(addr);
769 *dseg = (rte_v128u32_t){
771 txq_mp2mr(txq, txq_mb2mp(buf)),
784 * Spill on next WQE when the current one does not have
785 * enough room left. Size of WQE must a be a multiple
786 * of data segment size.
788 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
789 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
790 if (unlikely(--max_wqe == 0))
792 dseg = (volatile rte_v128u32_t *)
793 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
794 rte_prefetch0(tx_mlx5_wqe(txq,
795 txq->wqe_ci + ds / 4 + 1));
802 length = DATA_LEN(buf);
803 #ifdef MLX5_PMD_SOFT_COUNTERS
804 total_length += length;
806 /* Store segment information. */
807 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
808 *dseg = (rte_v128u32_t){
810 txq_mp2mr(txq, txq_mb2mp(buf)),
814 (*txq->elts)[elts_head] = buf;
815 elts_head = (elts_head + 1) & (elts_n - 1);
824 /* Initialize known and common part of the WQE structure. */
826 wqe->ctrl = (rte_v128u32_t){
827 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
828 htonl(txq->qp_num_8s | ds),
832 wqe->eseg = (rte_v128u32_t){
834 cs_flags | (htons(buf->tso_segsz) << 16),
836 (ehdr << 16) | htons(tso_header_sz),
839 wqe->ctrl = (rte_v128u32_t){
840 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
841 htonl(txq->qp_num_8s | ds),
845 wqe->eseg = (rte_v128u32_t){
849 (ehdr << 16) | htons(pkt_inline_sz),
853 txq->wqe_ci += (ds + 3) / 4;
854 #ifdef MLX5_PMD_SOFT_COUNTERS
855 /* Increment sent bytes counter. */
856 txq->stats.obytes += total_length;
859 /* Take a shortcut if nothing must be sent. */
860 if (unlikely((i + k) == 0))
862 /* Check whether completion threshold has been reached. */
863 comp = txq->elts_comp + i + j + k;
864 if (comp >= MLX5_TX_COMP_THRESH) {
865 volatile struct mlx5_wqe_ctrl *w =
866 (volatile struct mlx5_wqe_ctrl *)wqe;
868 /* Request completion on last WQE. */
870 /* Save elts_head in unused "immediate" field of WQE. */
871 w->ctrl3 = elts_head;
874 txq->elts_comp = comp;
876 #ifdef MLX5_PMD_SOFT_COUNTERS
877 /* Increment sent packets counter. */
878 txq->stats.opackets += i;
880 /* Ring QP doorbell. */
881 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
882 txq->elts_head = elts_head;
887 * Open a MPW session.
890 * Pointer to TX queue structure.
892 * Pointer to MPW session structure.
897 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
899 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
900 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
901 (volatile struct mlx5_wqe_data_seg (*)[])
902 tx_mlx5_wqe(txq, idx + 1);
904 mpw->state = MLX5_MPW_STATE_OPENED;
908 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
909 mpw->wqe->eseg.mss = htons(length);
910 mpw->wqe->eseg.inline_hdr_sz = 0;
911 mpw->wqe->eseg.rsvd0 = 0;
912 mpw->wqe->eseg.rsvd1 = 0;
913 mpw->wqe->eseg.rsvd2 = 0;
914 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
915 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
916 mpw->wqe->ctrl[2] = 0;
917 mpw->wqe->ctrl[3] = 0;
918 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
919 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
920 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
921 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
922 mpw->data.dseg[2] = &(*dseg)[0];
923 mpw->data.dseg[3] = &(*dseg)[1];
924 mpw->data.dseg[4] = &(*dseg)[2];
928 * Close a MPW session.
931 * Pointer to TX queue structure.
933 * Pointer to MPW session structure.
936 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
938 unsigned int num = mpw->pkts_n;
941 * Store size in multiple of 16 bytes. Control and Ethernet segments
944 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
945 mpw->state = MLX5_MPW_STATE_CLOSED;
950 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
951 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
955 * DPDK callback for TX with MPW support.
958 * Generic pointer to TX queue structure.
960 * Packets to transmit.
962 * Number of packets in array.
965 * Number of packets successfully transmitted (<= pkts_n).
968 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
970 struct txq *txq = (struct txq *)dpdk_txq;
971 uint16_t elts_head = txq->elts_head;
972 const unsigned int elts_n = 1 << txq->elts_n;
978 struct mlx5_mpw mpw = {
979 .state = MLX5_MPW_STATE_CLOSED,
982 if (unlikely(!pkts_n))
984 /* Prefetch first packet cacheline. */
985 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
986 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
987 /* Start processing. */
989 max = (elts_n - (elts_head - txq->elts_tail));
992 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
993 if (unlikely(!max_wqe))
996 struct rte_mbuf *buf = *(pkts++);
997 unsigned int elts_head_next;
999 unsigned int segs_n = buf->nb_segs;
1000 uint32_t cs_flags = 0;
1003 * Make sure there is enough room to store this packet and
1004 * that one ring entry remains unused.
1007 if (max < segs_n + 1)
1009 /* Do not bother with large packets MPW cannot handle. */
1010 if (segs_n > MLX5_MPW_DSEG_MAX)
1014 /* Should we enable HW CKSUM offload */
1016 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1017 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1018 /* Retrieve packet information. */
1019 length = PKT_LEN(buf);
1021 /* Start new session if packet differs. */
1022 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1023 ((mpw.len != length) ||
1025 (mpw.wqe->eseg.cs_flags != cs_flags)))
1026 mlx5_mpw_close(txq, &mpw);
1027 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1029 * Multi-Packet WQE consumes at most two WQE.
1030 * mlx5_mpw_new() expects to be able to use such
1033 if (unlikely(max_wqe < 2))
1036 mlx5_mpw_new(txq, &mpw, length);
1037 mpw.wqe->eseg.cs_flags = cs_flags;
1039 /* Multi-segment packets must be alone in their MPW. */
1040 assert((segs_n == 1) || (mpw.pkts_n == 0));
1041 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1045 volatile struct mlx5_wqe_data_seg *dseg;
1048 elts_head_next = (elts_head + 1) & (elts_n - 1);
1050 (*txq->elts)[elts_head] = buf;
1051 dseg = mpw.data.dseg[mpw.pkts_n];
1052 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1053 *dseg = (struct mlx5_wqe_data_seg){
1054 .byte_count = htonl(DATA_LEN(buf)),
1055 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1056 .addr = htonll(addr),
1058 elts_head = elts_head_next;
1059 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1060 length += DATA_LEN(buf);
1066 assert(length == mpw.len);
1067 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1068 mlx5_mpw_close(txq, &mpw);
1069 elts_head = elts_head_next;
1070 #ifdef MLX5_PMD_SOFT_COUNTERS
1071 /* Increment sent bytes counter. */
1072 txq->stats.obytes += length;
1076 /* Take a shortcut if nothing must be sent. */
1077 if (unlikely(i == 0))
1079 /* Check whether completion threshold has been reached. */
1080 /* "j" includes both packets and segments. */
1081 comp = txq->elts_comp + j;
1082 if (comp >= MLX5_TX_COMP_THRESH) {
1083 volatile struct mlx5_wqe *wqe = mpw.wqe;
1085 /* Request completion on last WQE. */
1086 wqe->ctrl[2] = htonl(8);
1087 /* Save elts_head in unused "immediate" field of WQE. */
1088 wqe->ctrl[3] = elts_head;
1091 txq->elts_comp = comp;
1093 #ifdef MLX5_PMD_SOFT_COUNTERS
1094 /* Increment sent packets counter. */
1095 txq->stats.opackets += i;
1097 /* Ring QP doorbell. */
1098 if (mpw.state == MLX5_MPW_STATE_OPENED)
1099 mlx5_mpw_close(txq, &mpw);
1100 mlx5_tx_dbrec(txq, mpw.wqe);
1101 txq->elts_head = elts_head;
1106 * Open a MPW inline session.
1109 * Pointer to TX queue structure.
1111 * Pointer to MPW session structure.
1116 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1118 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1119 struct mlx5_wqe_inl_small *inl;
1121 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1125 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1126 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1127 (txq->wqe_ci << 8) |
1129 mpw->wqe->ctrl[2] = 0;
1130 mpw->wqe->ctrl[3] = 0;
1131 mpw->wqe->eseg.mss = htons(length);
1132 mpw->wqe->eseg.inline_hdr_sz = 0;
1133 mpw->wqe->eseg.cs_flags = 0;
1134 mpw->wqe->eseg.rsvd0 = 0;
1135 mpw->wqe->eseg.rsvd1 = 0;
1136 mpw->wqe->eseg.rsvd2 = 0;
1137 inl = (struct mlx5_wqe_inl_small *)
1138 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1139 mpw->data.raw = (uint8_t *)&inl->raw;
1143 * Close a MPW inline session.
1146 * Pointer to TX queue structure.
1148 * Pointer to MPW session structure.
1151 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1154 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1155 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1157 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1159 * Store size in multiple of 16 bytes. Control and Ethernet segments
1162 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
1163 mpw->state = MLX5_MPW_STATE_CLOSED;
1164 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1165 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1169 * DPDK callback for TX with MPW inline support.
1172 * Generic pointer to TX queue structure.
1174 * Packets to transmit.
1176 * Number of packets in array.
1179 * Number of packets successfully transmitted (<= pkts_n).
1182 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1185 struct txq *txq = (struct txq *)dpdk_txq;
1186 uint16_t elts_head = txq->elts_head;
1187 const unsigned int elts_n = 1 << txq->elts_n;
1193 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1194 struct mlx5_mpw mpw = {
1195 .state = MLX5_MPW_STATE_CLOSED,
1198 * Compute the maximum number of WQE which can be consumed by inline
1201 * - 1 control segment,
1202 * - 1 Ethernet segment,
1203 * - N Dseg from the inline request.
1205 const unsigned int wqe_inl_n =
1206 ((2 * MLX5_WQE_DWORD_SIZE +
1207 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1208 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1210 if (unlikely(!pkts_n))
1212 /* Prefetch first packet cacheline. */
1213 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1214 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1215 /* Start processing. */
1217 max = (elts_n - (elts_head - txq->elts_tail));
1221 struct rte_mbuf *buf = *(pkts++);
1222 unsigned int elts_head_next;
1225 unsigned int segs_n = buf->nb_segs;
1226 uint32_t cs_flags = 0;
1229 * Make sure there is enough room to store this packet and
1230 * that one ring entry remains unused.
1233 if (max < segs_n + 1)
1235 /* Do not bother with large packets MPW cannot handle. */
1236 if (segs_n > MLX5_MPW_DSEG_MAX)
1241 * Compute max_wqe in case less WQE were consumed in previous
1244 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1245 /* Should we enable HW CKSUM offload */
1247 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1248 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1249 /* Retrieve packet information. */
1250 length = PKT_LEN(buf);
1251 /* Start new session if packet differs. */
1252 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1253 if ((mpw.len != length) ||
1255 (mpw.wqe->eseg.cs_flags != cs_flags))
1256 mlx5_mpw_close(txq, &mpw);
1257 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1258 if ((mpw.len != length) ||
1260 (length > inline_room) ||
1261 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1262 mlx5_mpw_inline_close(txq, &mpw);
1264 txq->max_inline * RTE_CACHE_LINE_SIZE;
1267 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1268 if ((segs_n != 1) ||
1269 (length > inline_room)) {
1271 * Multi-Packet WQE consumes at most two WQE.
1272 * mlx5_mpw_new() expects to be able to use
1275 if (unlikely(max_wqe < 2))
1278 mlx5_mpw_new(txq, &mpw, length);
1279 mpw.wqe->eseg.cs_flags = cs_flags;
1281 if (unlikely(max_wqe < wqe_inl_n))
1283 max_wqe -= wqe_inl_n;
1284 mlx5_mpw_inline_new(txq, &mpw, length);
1285 mpw.wqe->eseg.cs_flags = cs_flags;
1288 /* Multi-segment packets must be alone in their MPW. */
1289 assert((segs_n == 1) || (mpw.pkts_n == 0));
1290 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1291 assert(inline_room ==
1292 txq->max_inline * RTE_CACHE_LINE_SIZE);
1293 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1297 volatile struct mlx5_wqe_data_seg *dseg;
1300 (elts_head + 1) & (elts_n - 1);
1302 (*txq->elts)[elts_head] = buf;
1303 dseg = mpw.data.dseg[mpw.pkts_n];
1304 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1305 *dseg = (struct mlx5_wqe_data_seg){
1306 .byte_count = htonl(DATA_LEN(buf)),
1307 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1308 .addr = htonll(addr),
1310 elts_head = elts_head_next;
1311 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1312 length += DATA_LEN(buf);
1318 assert(length == mpw.len);
1319 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1320 mlx5_mpw_close(txq, &mpw);
1324 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1325 assert(length <= inline_room);
1326 assert(length == DATA_LEN(buf));
1327 elts_head_next = (elts_head + 1) & (elts_n - 1);
1328 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1329 (*txq->elts)[elts_head] = buf;
1330 /* Maximum number of bytes before wrapping. */
1331 max = ((((uintptr_t)(txq->wqes)) +
1334 (uintptr_t)mpw.data.raw);
1336 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1339 mpw.data.raw = (volatile void *)txq->wqes;
1340 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1341 (void *)(addr + max),
1343 mpw.data.raw += length - max;
1345 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1351 (volatile void *)txq->wqes;
1353 mpw.data.raw += length;
1356 mpw.total_len += length;
1358 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1359 mlx5_mpw_inline_close(txq, &mpw);
1361 txq->max_inline * RTE_CACHE_LINE_SIZE;
1363 inline_room -= length;
1366 elts_head = elts_head_next;
1367 #ifdef MLX5_PMD_SOFT_COUNTERS
1368 /* Increment sent bytes counter. */
1369 txq->stats.obytes += length;
1373 /* Take a shortcut if nothing must be sent. */
1374 if (unlikely(i == 0))
1376 /* Check whether completion threshold has been reached. */
1377 /* "j" includes both packets and segments. */
1378 comp = txq->elts_comp + j;
1379 if (comp >= MLX5_TX_COMP_THRESH) {
1380 volatile struct mlx5_wqe *wqe = mpw.wqe;
1382 /* Request completion on last WQE. */
1383 wqe->ctrl[2] = htonl(8);
1384 /* Save elts_head in unused "immediate" field of WQE. */
1385 wqe->ctrl[3] = elts_head;
1388 txq->elts_comp = comp;
1390 #ifdef MLX5_PMD_SOFT_COUNTERS
1391 /* Increment sent packets counter. */
1392 txq->stats.opackets += i;
1394 /* Ring QP doorbell. */
1395 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1396 mlx5_mpw_inline_close(txq, &mpw);
1397 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1398 mlx5_mpw_close(txq, &mpw);
1399 mlx5_tx_dbrec(txq, mpw.wqe);
1400 txq->elts_head = elts_head;
1405 * Open an Enhanced MPW session.
1408 * Pointer to TX queue structure.
1410 * Pointer to MPW session structure.
1415 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1417 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1419 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1421 mpw->total_len = sizeof(struct mlx5_wqe);
1422 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1423 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1424 (txq->wqe_ci << 8) |
1425 MLX5_OPCODE_ENHANCED_MPSW);
1426 mpw->wqe->ctrl[2] = 0;
1427 mpw->wqe->ctrl[3] = 0;
1428 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1429 if (unlikely(padding)) {
1430 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1432 /* Pad the first 2 DWORDs with zero-length inline header. */
1433 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1434 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1435 htonl(MLX5_INLINE_SEG);
1436 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1437 /* Start from the next WQEBB. */
1438 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1440 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1445 * Close an Enhanced MPW session.
1448 * Pointer to TX queue structure.
1450 * Pointer to MPW session structure.
1453 * Number of consumed WQEs.
1455 static inline uint16_t
1456 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1460 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1463 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1464 mpw->state = MLX5_MPW_STATE_CLOSED;
1465 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1471 * DPDK callback for TX with Enhanced MPW support.
1474 * Generic pointer to TX queue structure.
1476 * Packets to transmit.
1478 * Number of packets in array.
1481 * Number of packets successfully transmitted (<= pkts_n).
1484 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1486 struct txq *txq = (struct txq *)dpdk_txq;
1487 uint16_t elts_head = txq->elts_head;
1488 const unsigned int elts_n = 1 << txq->elts_n;
1491 unsigned int max_elts;
1493 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1494 unsigned int mpw_room = 0;
1495 unsigned int inl_pad = 0;
1497 struct mlx5_mpw mpw = {
1498 .state = MLX5_MPW_STATE_CLOSED,
1501 if (unlikely(!pkts_n))
1503 /* Start processing. */
1505 max_elts = (elts_n - (elts_head - txq->elts_tail));
1506 if (max_elts > elts_n)
1508 /* A CQE slot must always be available. */
1509 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1510 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1511 if (unlikely(!max_wqe))
1514 struct rte_mbuf *buf = *(pkts++);
1515 unsigned int elts_head_next;
1519 unsigned int do_inline = 0; /* Whether inline is possible. */
1521 unsigned int segs_n = buf->nb_segs;
1522 uint32_t cs_flags = 0;
1525 * Make sure there is enough room to store this packet and
1526 * that one ring entry remains unused.
1529 if (max_elts - j < segs_n + 1)
1531 /* Do not bother with large packets MPW cannot handle. */
1532 if (segs_n > MLX5_MPW_DSEG_MAX)
1534 /* Should we enable HW CKSUM offload. */
1536 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1537 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1538 /* Retrieve packet information. */
1539 length = PKT_LEN(buf);
1540 /* Start new session if:
1541 * - multi-segment packet
1542 * - no space left even for a dseg
1543 * - next packet can be inlined with a new WQE
1545 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1548 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1549 if ((segs_n != 1) ||
1550 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1552 (length <= txq->inline_max_packet_sz &&
1553 inl_pad + sizeof(inl_hdr) + length >
1555 (mpw.wqe->eseg.cs_flags != cs_flags))
1556 max_wqe -= mlx5_empw_close(txq, &mpw);
1558 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1559 if (unlikely(segs_n != 1)) {
1560 /* Fall back to legacy MPW.
1561 * A MPW session consumes 2 WQEs at most to
1562 * include MLX5_MPW_DSEG_MAX pointers.
1564 if (unlikely(max_wqe < 2))
1566 mlx5_mpw_new(txq, &mpw, length);
1568 /* In Enhanced MPW, inline as much as the budget
1569 * is allowed. The remaining space is to be
1570 * filled with dsegs. If the title WQEBB isn't
1571 * padded, it will have 2 dsegs there.
1573 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1574 (max_inline ? max_inline :
1575 pkts_n * MLX5_WQE_DWORD_SIZE) +
1577 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1580 /* Don't pad the title WQEBB to not waste WQ. */
1581 mlx5_empw_new(txq, &mpw, 0);
1582 mpw_room -= mpw.total_len;
1585 length <= txq->inline_max_packet_sz &&
1586 sizeof(inl_hdr) + length <= mpw_room &&
1589 mpw.wqe->eseg.cs_flags = cs_flags;
1591 /* Evaluate whether the next packet can be inlined.
1592 * Inlininig is possible when:
1593 * - length is less than configured value
1594 * - length fits for remaining space
1595 * - not required to fill the title WQEBB with dsegs
1598 length <= txq->inline_max_packet_sz &&
1599 inl_pad + sizeof(inl_hdr) + length <=
1601 (!txq->mpw_hdr_dseg ||
1602 mpw.total_len >= MLX5_WQE_SIZE);
1604 /* Multi-segment packets must be alone in their MPW. */
1605 assert((segs_n == 1) || (mpw.pkts_n == 0));
1606 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1607 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1611 volatile struct mlx5_wqe_data_seg *dseg;
1614 (elts_head + 1) & (elts_n - 1);
1616 (*txq->elts)[elts_head] = buf;
1617 dseg = mpw.data.dseg[mpw.pkts_n];
1618 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1619 *dseg = (struct mlx5_wqe_data_seg){
1620 .byte_count = htonl(DATA_LEN(buf)),
1621 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1622 .addr = htonll(addr),
1624 elts_head = elts_head_next;
1625 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1626 length += DATA_LEN(buf);
1632 /* A multi-segmented packet takes one MPW session.
1633 * TODO: Pack more multi-segmented packets if possible.
1635 mlx5_mpw_close(txq, &mpw);
1640 } else if (do_inline) {
1641 /* Inline packet into WQE. */
1644 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1645 assert(length == DATA_LEN(buf));
1646 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1647 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1648 mpw.data.raw = (volatile void *)
1649 ((uintptr_t)mpw.data.raw + inl_pad);
1650 max = tx_mlx5_wq_tailroom(txq,
1651 (void *)(uintptr_t)mpw.data.raw);
1652 /* Copy inline header. */
1653 mpw.data.raw = (volatile void *)
1655 (void *)(uintptr_t)mpw.data.raw,
1658 (void *)(uintptr_t)txq->wqes,
1660 max = tx_mlx5_wq_tailroom(txq,
1661 (void *)(uintptr_t)mpw.data.raw);
1662 /* Copy packet data. */
1663 mpw.data.raw = (volatile void *)
1665 (void *)(uintptr_t)mpw.data.raw,
1668 (void *)(uintptr_t)txq->wqes,
1671 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1672 /* No need to get completion as the entire packet is
1673 * copied to WQ. Free the buf right away.
1675 elts_head_next = elts_head;
1676 rte_pktmbuf_free_seg(buf);
1677 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1678 /* Add pad in the next packet if any. */
1679 inl_pad = (((uintptr_t)mpw.data.raw +
1680 (MLX5_WQE_DWORD_SIZE - 1)) &
1681 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1682 (uintptr_t)mpw.data.raw;
1684 /* No inline. Load a dseg of packet pointer. */
1685 volatile rte_v128u32_t *dseg;
1687 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1688 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1689 assert(length == DATA_LEN(buf));
1690 if (!tx_mlx5_wq_tailroom(txq,
1691 (void *)((uintptr_t)mpw.data.raw
1693 dseg = (volatile void *)txq->wqes;
1695 dseg = (volatile void *)
1696 ((uintptr_t)mpw.data.raw +
1698 elts_head_next = (elts_head + 1) & (elts_n - 1);
1699 (*txq->elts)[elts_head] = buf;
1700 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1701 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1702 rte_prefetch2((void *)(addr +
1703 n * RTE_CACHE_LINE_SIZE));
1704 naddr = htonll(addr);
1705 *dseg = (rte_v128u32_t) {
1707 txq_mp2mr(txq, txq_mb2mp(buf)),
1711 mpw.data.raw = (volatile void *)(dseg + 1);
1712 mpw.total_len += (inl_pad + sizeof(*dseg));
1715 mpw_room -= (inl_pad + sizeof(*dseg));
1718 elts_head = elts_head_next;
1719 #ifdef MLX5_PMD_SOFT_COUNTERS
1720 /* Increment sent bytes counter. */
1721 txq->stats.obytes += length;
1724 } while (i < pkts_n);
1725 /* Take a shortcut if nothing must be sent. */
1726 if (unlikely(i == 0))
1728 /* Check whether completion threshold has been reached. */
1729 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1730 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1731 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1732 volatile struct mlx5_wqe *wqe = mpw.wqe;
1734 /* Request completion on last WQE. */
1735 wqe->ctrl[2] = htonl(8);
1736 /* Save elts_head in unused "immediate" field of WQE. */
1737 wqe->ctrl[3] = elts_head;
1739 txq->mpw_comp = txq->wqe_ci;
1742 txq->elts_comp += j;
1744 #ifdef MLX5_PMD_SOFT_COUNTERS
1745 /* Increment sent packets counter. */
1746 txq->stats.opackets += i;
1748 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1749 mlx5_empw_close(txq, &mpw);
1750 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1751 mlx5_mpw_close(txq, &mpw);
1752 /* Ring QP doorbell. */
1753 mlx5_tx_dbrec(txq, mpw.wqe);
1754 txq->elts_head = elts_head;
1759 * Translate RX completion flags to packet type.
1764 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1767 * Packet type for struct rte_mbuf.
1769 static inline uint32_t
1770 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1773 uint16_t flags = ntohs(cqe->hdr_type_etc);
1775 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1778 MLX5_CQE_RX_IPV4_PACKET,
1779 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1781 MLX5_CQE_RX_IPV6_PACKET,
1782 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1783 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1784 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1785 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1789 MLX5_CQE_L3_HDR_TYPE_IPV6,
1790 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1792 MLX5_CQE_L3_HDR_TYPE_IPV4,
1793 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1799 * Get size of the next packet for a given CQE. For compressed CQEs, the
1800 * consumer index is updated only once all packets of the current one have
1804 * Pointer to RX queue.
1807 * @param[out] rss_hash
1808 * Packet RSS Hash result.
1811 * Packet size in bytes (0 if there is none), -1 in case of completion
1815 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1816 uint16_t cqe_cnt, uint32_t *rss_hash)
1818 struct rxq_zip *zip = &rxq->zip;
1819 uint16_t cqe_n = cqe_cnt + 1;
1823 /* Process compressed data in the CQE and mini arrays. */
1825 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1826 (volatile struct mlx5_mini_cqe8 (*)[8])
1827 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1829 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1830 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1831 if ((++zip->ai & 7) == 0) {
1832 /* Invalidate consumed CQEs */
1835 while (idx != end) {
1836 (*rxq->cqes)[idx & cqe_cnt].op_own =
1837 MLX5_CQE_INVALIDATE;
1841 * Increment consumer index to skip the number of
1842 * CQEs consumed. Hardware leaves holes in the CQ
1843 * ring for software use.
1848 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1849 /* Invalidate the rest */
1853 while (idx != end) {
1854 (*rxq->cqes)[idx & cqe_cnt].op_own =
1855 MLX5_CQE_INVALIDATE;
1858 rxq->cq_ci = zip->cq_ci;
1861 /* No compressed data, get next CQE and verify if it is compressed. */
1866 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1867 if (unlikely(ret == 1))
1870 op_own = cqe->op_own;
1871 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1872 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1873 (volatile struct mlx5_mini_cqe8 (*)[8])
1874 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1877 /* Fix endianness. */
1878 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1880 * Current mini array position is the one returned by
1883 * If completion comprises several mini arrays, as a
1884 * special case the second one is located 7 CQEs after
1885 * the initial CQE instead of 8 for subsequent ones.
1887 zip->ca = rxq->cq_ci;
1888 zip->na = zip->ca + 7;
1889 /* Compute the next non compressed CQE. */
1891 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1892 /* Get packet size to return. */
1893 len = ntohl((*mc)[0].byte_cnt);
1894 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1896 /* Prefetch all the entries to be invalidated */
1899 while (idx != end) {
1900 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1904 len = ntohl(cqe->byte_cnt);
1905 *rss_hash = ntohl(cqe->rx_hash_res);
1907 /* Error while receiving packet. */
1908 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1915 * Translate RX completion flags to offload flags.
1918 * Pointer to RX queue structure.
1923 * Offload flags (ol_flags) for struct rte_mbuf.
1925 static inline uint32_t
1926 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1928 uint32_t ol_flags = 0;
1929 uint16_t flags = ntohs(cqe->hdr_type_etc);
1933 MLX5_CQE_RX_L3_HDR_VALID,
1934 PKT_RX_IP_CKSUM_GOOD) |
1936 MLX5_CQE_RX_L4_HDR_VALID,
1937 PKT_RX_L4_CKSUM_GOOD);
1938 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1941 MLX5_CQE_RX_L3_HDR_VALID,
1942 PKT_RX_IP_CKSUM_GOOD) |
1944 MLX5_CQE_RX_L4_HDR_VALID,
1945 PKT_RX_L4_CKSUM_GOOD);
1950 * DPDK callback for RX.
1953 * Generic pointer to RX queue structure.
1955 * Array to store received packets.
1957 * Maximum number of packets in array.
1960 * Number of packets successfully received (<= pkts_n).
1963 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1965 struct rxq *rxq = dpdk_rxq;
1966 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1967 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1968 const unsigned int sges_n = rxq->sges_n;
1969 struct rte_mbuf *pkt = NULL;
1970 struct rte_mbuf *seg = NULL;
1971 volatile struct mlx5_cqe *cqe =
1972 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1974 unsigned int rq_ci = rxq->rq_ci << sges_n;
1975 int len; /* keep its value across iterations. */
1978 unsigned int idx = rq_ci & wqe_cnt;
1979 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1980 struct rte_mbuf *rep = (*rxq->elts)[idx];
1981 uint32_t rss_hash_res = 0;
1989 rep = rte_mbuf_raw_alloc(rxq->mp);
1990 if (unlikely(rep == NULL)) {
1991 ++rxq->stats.rx_nombuf;
1994 * no buffers before we even started,
1995 * bail out silently.
1999 while (pkt != seg) {
2000 assert(pkt != (*rxq->elts)[idx]);
2002 rte_mbuf_refcnt_set(pkt, 0);
2003 __rte_mbuf_raw_free(pkt);
2009 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
2010 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
2013 rte_mbuf_refcnt_set(rep, 0);
2014 __rte_mbuf_raw_free(rep);
2017 if (unlikely(len == -1)) {
2018 /* RX error, packet is likely too large. */
2019 rte_mbuf_refcnt_set(rep, 0);
2020 __rte_mbuf_raw_free(rep);
2021 ++rxq->stats.idropped;
2025 assert(len >= (rxq->crc_present << 2));
2026 /* Update packet information. */
2027 pkt->packet_type = 0;
2029 if (rss_hash_res && rxq->rss_hash) {
2030 pkt->hash.rss = rss_hash_res;
2031 pkt->ol_flags = PKT_RX_RSS_HASH;
2034 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
2035 pkt->ol_flags |= PKT_RX_FDIR;
2036 if (cqe->sop_drop_qpn !=
2037 htonl(MLX5_FLOW_MARK_DEFAULT)) {
2038 uint32_t mark = cqe->sop_drop_qpn;
2040 pkt->ol_flags |= PKT_RX_FDIR_ID;
2042 mlx5_flow_mark_get(mark);
2045 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
2049 rxq_cq_to_pkt_type(cqe);
2051 rxq_cq_to_ol_flags(rxq, cqe);
2053 if (ntohs(cqe->hdr_type_etc) &
2054 MLX5_CQE_VLAN_STRIPPED) {
2055 pkt->ol_flags |= PKT_RX_VLAN_PKT |
2056 PKT_RX_VLAN_STRIPPED;
2057 pkt->vlan_tci = ntohs(cqe->vlan_info);
2059 if (rxq->crc_present)
2060 len -= ETHER_CRC_LEN;
2064 DATA_LEN(rep) = DATA_LEN(seg);
2065 PKT_LEN(rep) = PKT_LEN(seg);
2066 SET_DATA_OFF(rep, DATA_OFF(seg));
2067 NB_SEGS(rep) = NB_SEGS(seg);
2068 PORT(rep) = PORT(seg);
2070 (*rxq->elts)[idx] = rep;
2072 * Fill NIC descriptor with the new buffer. The lkey and size
2073 * of the buffers are already known, only the buffer address
2076 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
2077 if (len > DATA_LEN(seg)) {
2078 len -= DATA_LEN(seg);
2083 DATA_LEN(seg) = len;
2084 #ifdef MLX5_PMD_SOFT_COUNTERS
2085 /* Increment bytes counter. */
2086 rxq->stats.ibytes += PKT_LEN(pkt);
2088 /* Return packet. */
2094 /* Align consumer index to the next stride. */
2099 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2101 /* Update the consumer index. */
2102 rxq->rq_ci = rq_ci >> sges_n;
2104 *rxq->cq_db = htonl(rxq->cq_ci);
2106 *rxq->rq_db = htonl(rxq->rq_ci);
2107 #ifdef MLX5_PMD_SOFT_COUNTERS
2108 /* Increment packets counter. */
2109 rxq->stats.ipackets += i;
2115 * Dummy DPDK callback for TX.
2117 * This function is used to temporarily replace the real callback during
2118 * unsafe control operations on the queue, or in case of error.
2121 * Generic pointer to TX queue structure.
2123 * Packets to transmit.
2125 * Number of packets in array.
2128 * Number of packets successfully transmitted (<= pkts_n).
2131 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2140 * Dummy DPDK callback for RX.
2142 * This function is used to temporarily replace the real callback during
2143 * unsafe control operations on the queue, or in case of error.
2146 * Generic pointer to RX queue structure.
2148 * Array to store received packets.
2150 * Maximum number of packets in array.
2153 * Number of packets successfully received (<= pkts_n).
2156 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2165 * DPDK callback for rx queue interrupt enable.
2168 * Pointer to Ethernet device structure.
2169 * @param rx_queue_id
2173 * 0 on success, negative on failure.
2176 mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2178 #ifdef HAVE_UPDATE_CQ_CI
2179 struct priv *priv = mlx5_get_priv(dev);
2180 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2181 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2182 struct ibv_cq *cq = rxq_ctrl->cq;
2183 uint16_t ci = rxq->cq_ci;
2186 ibv_mlx5_exp_update_cq_ci(cq, ci);
2187 ret = ibv_req_notify_cq(cq, 0);
2194 WARN("unable to arm interrupt on rx queue %d", rx_queue_id);
2199 * DPDK callback for rx queue interrupt disable.
2202 * Pointer to Ethernet device structure.
2203 * @param rx_queue_id
2207 * 0 on success, negative on failure.
2210 mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2212 #ifdef HAVE_UPDATE_CQ_CI
2213 struct priv *priv = mlx5_get_priv(dev);
2214 struct rxq *rxq = (*priv->rxqs)[rx_queue_id];
2215 struct rxq_ctrl *rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq);
2216 struct ibv_cq *cq = rxq_ctrl->cq;
2217 struct ibv_cq *ev_cq;
2221 ret = ibv_get_cq_event(cq->channel, &ev_cq, &ev_ctx);
2222 if (ret || ev_cq != cq)
2225 ibv_ack_cq_events(cq, 1);
2232 WARN("unable to disable interrupt on rx queue %d",