4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
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14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 txq->wqe_pi = ntohs(cqe->wqe_counter);
242 ctrl = (volatile struct mlx5_wqe_ctrl *)
243 tx_mlx5_wqe(txq, txq->wqe_pi);
244 elts_tail = ctrl->ctrl3;
245 assert(elts_tail < (1 << txq->wqe_n));
247 while (elts_free != elts_tail) {
248 struct rte_mbuf *elt = (*txq->elts)[elts_free];
249 unsigned int elts_free_next =
250 (elts_free + 1) & (elts_n - 1);
251 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
255 memset(&(*txq->elts)[elts_free],
257 sizeof((*txq->elts)[elts_free]));
259 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
260 /* Only one segment needs to be freed. */
261 rte_pktmbuf_free_seg(elt);
262 elts_free = elts_free_next;
265 txq->elts_tail = elts_tail;
266 /* Update the consumer index. */
268 *txq->cq_db = htonl(cq_ci);
272 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
273 * the cloned mbuf is allocated is returned instead.
279 * Memory pool where data is located for given mbuf.
281 static struct rte_mempool *
282 txq_mb2mp(struct rte_mbuf *buf)
284 if (unlikely(RTE_MBUF_INDIRECT(buf)))
285 return rte_mbuf_from_indirect(buf)->pool;
290 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
291 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
292 * remove an entry first.
295 * Pointer to TX queue structure.
297 * Memory Pool for which a Memory Region lkey must be returned.
300 * mr->lkey on success, (uint32_t)-1 on failure.
302 static inline uint32_t
303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
306 uint32_t lkey = (uint32_t)-1;
308 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
309 if (unlikely(txq->mp2mr[i].mp == NULL)) {
310 /* Unknown MP, add a new MR for it. */
313 if (txq->mp2mr[i].mp == mp) {
314 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
315 assert(htonl(txq->mp2mr[i].mr->lkey) ==
317 lkey = txq->mp2mr[i].lkey;
321 if (unlikely(lkey == (uint32_t)-1))
322 lkey = txq_mp2mr_reg(txq, mp, i);
327 * Ring TX queue doorbell.
330 * Pointer to TX queue structure.
332 * Pointer to the last WQE posted in the NIC.
335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
337 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
338 volatile uint64_t *src = ((volatile uint64_t *)wqe);
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
348 * DPDK callback for TX.
351 * Generic pointer to TX queue structure.
353 * Packets to transmit.
355 * Number of packets in array.
358 * Number of packets successfully transmitted (<= pkts_n).
361 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
363 struct txq *txq = (struct txq *)dpdk_txq;
364 uint16_t elts_head = txq->elts_head;
365 const unsigned int elts_n = 1 << txq->elts_n;
371 volatile struct mlx5_wqe_v *wqe = NULL;
372 unsigned int segs_n = 0;
373 struct rte_mbuf *buf = NULL;
376 if (unlikely(!pkts_n))
378 /* Prefetch first packet cacheline. */
379 rte_prefetch0(*pkts);
380 /* Start processing. */
382 max = (elts_n - (elts_head - txq->elts_tail));
385 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
386 if (unlikely(!max_wqe))
389 volatile rte_v128u32_t *dseg = NULL;
394 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
396 uint8_t cs_flags = 0;
397 #ifdef MLX5_PMD_SOFT_COUNTERS
398 uint32_t total_length = 0;
403 segs_n = buf->nb_segs;
405 * Make sure there is enough room to store this packet and
406 * that one ring entry remains unused.
409 if (max < segs_n + 1)
415 if (unlikely(--max_wqe == 0))
417 wqe = (volatile struct mlx5_wqe_v *)
418 tx_mlx5_wqe(txq, txq->wqe_ci);
419 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
421 rte_prefetch0(*pkts);
422 addr = rte_pktmbuf_mtod(buf, uintptr_t);
423 length = DATA_LEN(buf);
424 ehdr = (((uint8_t *)addr)[1] << 8) |
425 ((uint8_t *)addr)[0];
426 #ifdef MLX5_PMD_SOFT_COUNTERS
427 total_length = length;
429 assert(length >= MLX5_WQE_DWORD_SIZE);
430 /* Update element. */
431 (*txq->elts)[elts_head] = buf;
432 elts_head = (elts_head + 1) & (elts_n - 1);
433 /* Prefetch next buffer data. */
435 volatile void *pkt_addr;
437 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
438 rte_prefetch0(pkt_addr);
440 /* Should we enable HW CKSUM offload */
442 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
443 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
445 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
446 /* Replace the Ethernet type by the VLAN if necessary. */
447 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
448 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
449 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
453 /* Copy Destination and source mac address. */
454 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
456 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
457 /* Copy missing two bytes to end the DSeg. */
458 memcpy((uint8_t *)raw + len + sizeof(vlan),
459 ((uint8_t *)addr) + len, 2);
463 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
464 MLX5_WQE_DWORD_SIZE);
465 length -= pkt_inline_sz;
466 addr += pkt_inline_sz;
468 /* Inline if enough room. */
469 if (txq->max_inline) {
470 uintptr_t end = (uintptr_t)
471 (((uintptr_t)txq->wqes) +
472 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
473 unsigned int max_inline = txq->max_inline *
474 RTE_CACHE_LINE_SIZE -
476 uintptr_t addr_end = (addr + max_inline) &
477 ~(RTE_CACHE_LINE_SIZE - 1);
478 unsigned int copy_b = (addr_end > addr) ?
479 RTE_MIN((addr_end - addr), length) :
482 raw += MLX5_WQE_DWORD_SIZE;
483 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
485 * One Dseg remains in the current WQE. To
486 * keep the computation positive, it is
487 * removed after the bytes to Dseg conversion.
489 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
491 if (unlikely(max_wqe < n))
494 rte_memcpy((void *)raw, (void *)addr, copy_b);
497 pkt_inline_sz += copy_b;
500 * 2 DWORDs consumed by the WQE header + ETH segment +
501 * the size of the inline part of the packet.
503 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
505 if (ds % (MLX5_WQE_SIZE /
506 MLX5_WQE_DWORD_SIZE) == 0) {
507 if (unlikely(--max_wqe == 0))
509 dseg = (volatile rte_v128u32_t *)
510 tx_mlx5_wqe(txq, txq->wqe_ci +
513 dseg = (volatile rte_v128u32_t *)
515 (ds * MLX5_WQE_DWORD_SIZE));
518 } else if (!segs_n) {
521 /* dseg will be advance as part of next_seg */
522 dseg = (volatile rte_v128u32_t *)
524 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
529 * No inline has been done in the packet, only the
530 * Ethernet Header as been stored.
532 dseg = (volatile rte_v128u32_t *)
533 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
536 /* Add the remaining packet as a simple ds. */
537 naddr = htonll(addr);
538 *dseg = (rte_v128u32_t){
540 txq_mp2mr(txq, txq_mb2mp(buf)),
553 * Spill on next WQE when the current one does not have
554 * enough room left. Size of WQE must a be a multiple
555 * of data segment size.
557 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
558 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
559 if (unlikely(--max_wqe == 0))
561 dseg = (volatile rte_v128u32_t *)
562 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
563 rte_prefetch0(tx_mlx5_wqe(txq,
564 txq->wqe_ci + ds / 4 + 1));
571 length = DATA_LEN(buf);
572 #ifdef MLX5_PMD_SOFT_COUNTERS
573 total_length += length;
575 /* Store segment information. */
576 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
577 *dseg = (rte_v128u32_t){
579 txq_mp2mr(txq, txq_mb2mp(buf)),
583 (*txq->elts)[elts_head] = buf;
584 elts_head = (elts_head + 1) & (elts_n - 1);
593 /* Initialize known and common part of the WQE structure. */
594 wqe->ctrl = (rte_v128u32_t){
595 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
596 htonl(txq->qp_num_8s | ds),
600 wqe->eseg = (rte_v128u32_t){
604 (ehdr << 16) | htons(pkt_inline_sz),
606 txq->wqe_ci += (ds + 3) / 4;
607 #ifdef MLX5_PMD_SOFT_COUNTERS
608 /* Increment sent bytes counter. */
609 txq->stats.obytes += total_length;
612 /* Take a shortcut if nothing must be sent. */
613 if (unlikely(i == 0))
615 /* Check whether completion threshold has been reached. */
616 comp = txq->elts_comp + i + j;
617 if (comp >= MLX5_TX_COMP_THRESH) {
618 volatile struct mlx5_wqe_ctrl *w =
619 (volatile struct mlx5_wqe_ctrl *)wqe;
621 /* Request completion on last WQE. */
623 /* Save elts_head in unused "immediate" field of WQE. */
624 w->ctrl3 = elts_head;
627 txq->elts_comp = comp;
629 #ifdef MLX5_PMD_SOFT_COUNTERS
630 /* Increment sent packets counter. */
631 txq->stats.opackets += i;
633 /* Ring QP doorbell. */
634 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
635 txq->elts_head = elts_head;
640 * Open a MPW session.
643 * Pointer to TX queue structure.
645 * Pointer to MPW session structure.
650 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
652 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
653 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
654 (volatile struct mlx5_wqe_data_seg (*)[])
655 tx_mlx5_wqe(txq, idx + 1);
657 mpw->state = MLX5_MPW_STATE_OPENED;
661 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
662 mpw->wqe->eseg.mss = htons(length);
663 mpw->wqe->eseg.inline_hdr_sz = 0;
664 mpw->wqe->eseg.rsvd0 = 0;
665 mpw->wqe->eseg.rsvd1 = 0;
666 mpw->wqe->eseg.rsvd2 = 0;
667 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
668 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
669 mpw->wqe->ctrl[2] = 0;
670 mpw->wqe->ctrl[3] = 0;
671 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
672 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
673 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
674 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
675 mpw->data.dseg[2] = &(*dseg)[0];
676 mpw->data.dseg[3] = &(*dseg)[1];
677 mpw->data.dseg[4] = &(*dseg)[2];
681 * Close a MPW session.
684 * Pointer to TX queue structure.
686 * Pointer to MPW session structure.
689 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
691 unsigned int num = mpw->pkts_n;
694 * Store size in multiple of 16 bytes. Control and Ethernet segments
697 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
698 mpw->state = MLX5_MPW_STATE_CLOSED;
703 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
704 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
708 * DPDK callback for TX with MPW support.
711 * Generic pointer to TX queue structure.
713 * Packets to transmit.
715 * Number of packets in array.
718 * Number of packets successfully transmitted (<= pkts_n).
721 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
723 struct txq *txq = (struct txq *)dpdk_txq;
724 uint16_t elts_head = txq->elts_head;
725 const unsigned int elts_n = 1 << txq->elts_n;
731 struct mlx5_mpw mpw = {
732 .state = MLX5_MPW_STATE_CLOSED,
735 if (unlikely(!pkts_n))
737 /* Prefetch first packet cacheline. */
738 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
739 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
740 /* Start processing. */
742 max = (elts_n - (elts_head - txq->elts_tail));
745 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
746 if (unlikely(!max_wqe))
749 struct rte_mbuf *buf = *(pkts++);
750 unsigned int elts_head_next;
752 unsigned int segs_n = buf->nb_segs;
753 uint32_t cs_flags = 0;
756 * Make sure there is enough room to store this packet and
757 * that one ring entry remains unused.
760 if (max < segs_n + 1)
762 /* Do not bother with large packets MPW cannot handle. */
763 if (segs_n > MLX5_MPW_DSEG_MAX)
767 /* Should we enable HW CKSUM offload */
769 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
770 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
771 /* Retrieve packet information. */
772 length = PKT_LEN(buf);
774 /* Start new session if packet differs. */
775 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
776 ((mpw.len != length) ||
778 (mpw.wqe->eseg.cs_flags != cs_flags)))
779 mlx5_mpw_close(txq, &mpw);
780 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
782 * Multi-Packet WQE consumes at most two WQE.
783 * mlx5_mpw_new() expects to be able to use such
786 if (unlikely(max_wqe < 2))
789 mlx5_mpw_new(txq, &mpw, length);
790 mpw.wqe->eseg.cs_flags = cs_flags;
792 /* Multi-segment packets must be alone in their MPW. */
793 assert((segs_n == 1) || (mpw.pkts_n == 0));
794 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
798 volatile struct mlx5_wqe_data_seg *dseg;
801 elts_head_next = (elts_head + 1) & (elts_n - 1);
803 (*txq->elts)[elts_head] = buf;
804 dseg = mpw.data.dseg[mpw.pkts_n];
805 addr = rte_pktmbuf_mtod(buf, uintptr_t);
806 *dseg = (struct mlx5_wqe_data_seg){
807 .byte_count = htonl(DATA_LEN(buf)),
808 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
809 .addr = htonll(addr),
811 elts_head = elts_head_next;
812 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
813 length += DATA_LEN(buf);
819 assert(length == mpw.len);
820 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
821 mlx5_mpw_close(txq, &mpw);
822 elts_head = elts_head_next;
823 #ifdef MLX5_PMD_SOFT_COUNTERS
824 /* Increment sent bytes counter. */
825 txq->stats.obytes += length;
829 /* Take a shortcut if nothing must be sent. */
830 if (unlikely(i == 0))
832 /* Check whether completion threshold has been reached. */
833 /* "j" includes both packets and segments. */
834 comp = txq->elts_comp + j;
835 if (comp >= MLX5_TX_COMP_THRESH) {
836 volatile struct mlx5_wqe *wqe = mpw.wqe;
838 /* Request completion on last WQE. */
839 wqe->ctrl[2] = htonl(8);
840 /* Save elts_head in unused "immediate" field of WQE. */
841 wqe->ctrl[3] = elts_head;
844 txq->elts_comp = comp;
846 #ifdef MLX5_PMD_SOFT_COUNTERS
847 /* Increment sent packets counter. */
848 txq->stats.opackets += i;
850 /* Ring QP doorbell. */
851 if (mpw.state == MLX5_MPW_STATE_OPENED)
852 mlx5_mpw_close(txq, &mpw);
853 mlx5_tx_dbrec(txq, mpw.wqe);
854 txq->elts_head = elts_head;
859 * Open a MPW inline session.
862 * Pointer to TX queue structure.
864 * Pointer to MPW session structure.
869 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
871 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
872 struct mlx5_wqe_inl_small *inl;
874 mpw->state = MLX5_MPW_INL_STATE_OPENED;
878 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
879 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
882 mpw->wqe->ctrl[2] = 0;
883 mpw->wqe->ctrl[3] = 0;
884 mpw->wqe->eseg.mss = htons(length);
885 mpw->wqe->eseg.inline_hdr_sz = 0;
886 mpw->wqe->eseg.cs_flags = 0;
887 mpw->wqe->eseg.rsvd0 = 0;
888 mpw->wqe->eseg.rsvd1 = 0;
889 mpw->wqe->eseg.rsvd2 = 0;
890 inl = (struct mlx5_wqe_inl_small *)
891 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
892 mpw->data.raw = (uint8_t *)&inl->raw;
896 * Close a MPW inline session.
899 * Pointer to TX queue structure.
901 * Pointer to MPW session structure.
904 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
907 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
908 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
910 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
912 * Store size in multiple of 16 bytes. Control and Ethernet segments
915 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
916 mpw->state = MLX5_MPW_STATE_CLOSED;
917 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
918 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
922 * DPDK callback for TX with MPW inline support.
925 * Generic pointer to TX queue structure.
927 * Packets to transmit.
929 * Number of packets in array.
932 * Number of packets successfully transmitted (<= pkts_n).
935 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
938 struct txq *txq = (struct txq *)dpdk_txq;
939 uint16_t elts_head = txq->elts_head;
940 const unsigned int elts_n = 1 << txq->elts_n;
946 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
947 struct mlx5_mpw mpw = {
948 .state = MLX5_MPW_STATE_CLOSED,
951 * Compute the maximum number of WQE which can be consumed by inline
954 * - 1 control segment,
955 * - 1 Ethernet segment,
956 * - N Dseg from the inline request.
958 const unsigned int wqe_inl_n =
959 ((2 * MLX5_WQE_DWORD_SIZE +
960 txq->max_inline * RTE_CACHE_LINE_SIZE) +
961 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
963 if (unlikely(!pkts_n))
965 /* Prefetch first packet cacheline. */
966 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
967 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
968 /* Start processing. */
970 max = (elts_n - (elts_head - txq->elts_tail));
974 struct rte_mbuf *buf = *(pkts++);
975 unsigned int elts_head_next;
978 unsigned int segs_n = buf->nb_segs;
979 uint32_t cs_flags = 0;
982 * Make sure there is enough room to store this packet and
983 * that one ring entry remains unused.
986 if (max < segs_n + 1)
988 /* Do not bother with large packets MPW cannot handle. */
989 if (segs_n > MLX5_MPW_DSEG_MAX)
994 * Compute max_wqe in case less WQE were consumed in previous
997 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
998 /* Should we enable HW CKSUM offload */
1000 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1001 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1002 /* Retrieve packet information. */
1003 length = PKT_LEN(buf);
1004 /* Start new session if packet differs. */
1005 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1006 if ((mpw.len != length) ||
1008 (mpw.wqe->eseg.cs_flags != cs_flags))
1009 mlx5_mpw_close(txq, &mpw);
1010 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1011 if ((mpw.len != length) ||
1013 (length > inline_room) ||
1014 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1015 mlx5_mpw_inline_close(txq, &mpw);
1017 txq->max_inline * RTE_CACHE_LINE_SIZE;
1020 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1021 if ((segs_n != 1) ||
1022 (length > inline_room)) {
1024 * Multi-Packet WQE consumes at most two WQE.
1025 * mlx5_mpw_new() expects to be able to use
1028 if (unlikely(max_wqe < 2))
1031 mlx5_mpw_new(txq, &mpw, length);
1032 mpw.wqe->eseg.cs_flags = cs_flags;
1034 if (unlikely(max_wqe < wqe_inl_n))
1036 max_wqe -= wqe_inl_n;
1037 mlx5_mpw_inline_new(txq, &mpw, length);
1038 mpw.wqe->eseg.cs_flags = cs_flags;
1041 /* Multi-segment packets must be alone in their MPW. */
1042 assert((segs_n == 1) || (mpw.pkts_n == 0));
1043 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1044 assert(inline_room ==
1045 txq->max_inline * RTE_CACHE_LINE_SIZE);
1046 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1050 volatile struct mlx5_wqe_data_seg *dseg;
1053 (elts_head + 1) & (elts_n - 1);
1055 (*txq->elts)[elts_head] = buf;
1056 dseg = mpw.data.dseg[mpw.pkts_n];
1057 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1058 *dseg = (struct mlx5_wqe_data_seg){
1059 .byte_count = htonl(DATA_LEN(buf)),
1060 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1061 .addr = htonll(addr),
1063 elts_head = elts_head_next;
1064 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1065 length += DATA_LEN(buf);
1071 assert(length == mpw.len);
1072 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1073 mlx5_mpw_close(txq, &mpw);
1077 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1078 assert(length <= inline_room);
1079 assert(length == DATA_LEN(buf));
1080 elts_head_next = (elts_head + 1) & (elts_n - 1);
1081 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1082 (*txq->elts)[elts_head] = buf;
1083 /* Maximum number of bytes before wrapping. */
1084 max = ((((uintptr_t)(txq->wqes)) +
1087 (uintptr_t)mpw.data.raw);
1089 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1092 mpw.data.raw = (volatile void *)txq->wqes;
1093 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1094 (void *)(addr + max),
1096 mpw.data.raw += length - max;
1098 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1104 (volatile void *)txq->wqes;
1106 mpw.data.raw += length;
1109 mpw.total_len += length;
1111 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1112 mlx5_mpw_inline_close(txq, &mpw);
1114 txq->max_inline * RTE_CACHE_LINE_SIZE;
1116 inline_room -= length;
1119 elts_head = elts_head_next;
1120 #ifdef MLX5_PMD_SOFT_COUNTERS
1121 /* Increment sent bytes counter. */
1122 txq->stats.obytes += length;
1126 /* Take a shortcut if nothing must be sent. */
1127 if (unlikely(i == 0))
1129 /* Check whether completion threshold has been reached. */
1130 /* "j" includes both packets and segments. */
1131 comp = txq->elts_comp + j;
1132 if (comp >= MLX5_TX_COMP_THRESH) {
1133 volatile struct mlx5_wqe *wqe = mpw.wqe;
1135 /* Request completion on last WQE. */
1136 wqe->ctrl[2] = htonl(8);
1137 /* Save elts_head in unused "immediate" field of WQE. */
1138 wqe->ctrl[3] = elts_head;
1141 txq->elts_comp = comp;
1143 #ifdef MLX5_PMD_SOFT_COUNTERS
1144 /* Increment sent packets counter. */
1145 txq->stats.opackets += i;
1147 /* Ring QP doorbell. */
1148 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1149 mlx5_mpw_inline_close(txq, &mpw);
1150 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1151 mlx5_mpw_close(txq, &mpw);
1152 mlx5_tx_dbrec(txq, mpw.wqe);
1153 txq->elts_head = elts_head;
1158 * Translate RX completion flags to packet type.
1163 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1166 * Packet type for struct rte_mbuf.
1168 static inline uint32_t
1169 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1172 uint16_t flags = ntohs(cqe->hdr_type_etc);
1174 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1177 MLX5_CQE_RX_IPV4_PACKET,
1178 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1180 MLX5_CQE_RX_IPV6_PACKET,
1181 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1182 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1183 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1184 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1188 MLX5_CQE_L3_HDR_TYPE_IPV6,
1189 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1191 MLX5_CQE_L3_HDR_TYPE_IPV4,
1192 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1198 * Get size of the next packet for a given CQE. For compressed CQEs, the
1199 * consumer index is updated only once all packets of the current one have
1203 * Pointer to RX queue.
1206 * @param[out] rss_hash
1207 * Packet RSS Hash result.
1210 * Packet size in bytes (0 if there is none), -1 in case of completion
1214 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1215 uint16_t cqe_cnt, uint32_t *rss_hash)
1217 struct rxq_zip *zip = &rxq->zip;
1218 uint16_t cqe_n = cqe_cnt + 1;
1222 /* Process compressed data in the CQE and mini arrays. */
1224 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1225 (volatile struct mlx5_mini_cqe8 (*)[8])
1226 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1228 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1229 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1230 if ((++zip->ai & 7) == 0) {
1231 /* Invalidate consumed CQEs */
1234 while (idx != end) {
1235 (*rxq->cqes)[idx & cqe_cnt].op_own =
1236 MLX5_CQE_INVALIDATE;
1240 * Increment consumer index to skip the number of
1241 * CQEs consumed. Hardware leaves holes in the CQ
1242 * ring for software use.
1247 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1248 /* Invalidate the rest */
1252 while (idx != end) {
1253 (*rxq->cqes)[idx & cqe_cnt].op_own =
1254 MLX5_CQE_INVALIDATE;
1257 rxq->cq_ci = zip->cq_ci;
1260 /* No compressed data, get next CQE and verify if it is compressed. */
1265 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1266 if (unlikely(ret == 1))
1269 op_own = cqe->op_own;
1270 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1271 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1272 (volatile struct mlx5_mini_cqe8 (*)[8])
1273 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1276 /* Fix endianness. */
1277 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1279 * Current mini array position is the one returned by
1282 * If completion comprises several mini arrays, as a
1283 * special case the second one is located 7 CQEs after
1284 * the initial CQE instead of 8 for subsequent ones.
1286 zip->ca = rxq->cq_ci;
1287 zip->na = zip->ca + 7;
1288 /* Compute the next non compressed CQE. */
1290 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1291 /* Get packet size to return. */
1292 len = ntohl((*mc)[0].byte_cnt);
1293 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1295 /* Prefetch all the entries to be invalidated */
1298 while (idx != end) {
1299 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1303 len = ntohl(cqe->byte_cnt);
1304 *rss_hash = ntohl(cqe->rx_hash_res);
1306 /* Error while receiving packet. */
1307 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1314 * Translate RX completion flags to offload flags.
1317 * Pointer to RX queue structure.
1322 * Offload flags (ol_flags) for struct rte_mbuf.
1324 static inline uint32_t
1325 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1327 uint32_t ol_flags = 0;
1328 uint16_t flags = ntohs(cqe->hdr_type_etc);
1332 MLX5_CQE_RX_L3_HDR_VALID,
1333 PKT_RX_IP_CKSUM_GOOD) |
1335 MLX5_CQE_RX_L4_HDR_VALID,
1336 PKT_RX_L4_CKSUM_GOOD);
1337 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1340 MLX5_CQE_RX_L3_HDR_VALID,
1341 PKT_RX_IP_CKSUM_GOOD) |
1343 MLX5_CQE_RX_L4_HDR_VALID,
1344 PKT_RX_L4_CKSUM_GOOD);
1349 * DPDK callback for RX.
1352 * Generic pointer to RX queue structure.
1354 * Array to store received packets.
1356 * Maximum number of packets in array.
1359 * Number of packets successfully received (<= pkts_n).
1362 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1364 struct rxq *rxq = dpdk_rxq;
1365 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1366 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1367 const unsigned int sges_n = rxq->sges_n;
1368 struct rte_mbuf *pkt = NULL;
1369 struct rte_mbuf *seg = NULL;
1370 volatile struct mlx5_cqe *cqe =
1371 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1373 unsigned int rq_ci = rxq->rq_ci << sges_n;
1374 int len; /* keep its value across iterations. */
1377 unsigned int idx = rq_ci & wqe_cnt;
1378 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1379 struct rte_mbuf *rep = (*rxq->elts)[idx];
1380 uint32_t rss_hash_res = 0;
1388 rep = rte_mbuf_raw_alloc(rxq->mp);
1389 if (unlikely(rep == NULL)) {
1390 ++rxq->stats.rx_nombuf;
1393 * no buffers before we even started,
1394 * bail out silently.
1398 while (pkt != seg) {
1399 assert(pkt != (*rxq->elts)[idx]);
1401 rte_mbuf_refcnt_set(pkt, 0);
1402 __rte_mbuf_raw_free(pkt);
1408 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1409 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1412 rte_mbuf_refcnt_set(rep, 0);
1413 __rte_mbuf_raw_free(rep);
1416 if (unlikely(len == -1)) {
1417 /* RX error, packet is likely too large. */
1418 rte_mbuf_refcnt_set(rep, 0);
1419 __rte_mbuf_raw_free(rep);
1420 ++rxq->stats.idropped;
1424 assert(len >= (rxq->crc_present << 2));
1425 /* Update packet information. */
1426 pkt->packet_type = 0;
1428 if (rss_hash_res && rxq->rss_hash) {
1429 pkt->hash.rss = rss_hash_res;
1430 pkt->ol_flags = PKT_RX_RSS_HASH;
1433 ((cqe->sop_drop_qpn !=
1434 htonl(MLX5_FLOW_MARK_INVALID)) ||
1435 (cqe->sop_drop_qpn !=
1436 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1438 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1439 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1440 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1442 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1446 rxq_cq_to_pkt_type(cqe);
1448 rxq_cq_to_ol_flags(rxq, cqe);
1450 if (cqe->hdr_type_etc &
1451 MLX5_CQE_VLAN_STRIPPED) {
1452 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1453 PKT_RX_VLAN_STRIPPED;
1454 pkt->vlan_tci = ntohs(cqe->vlan_info);
1456 if (rxq->crc_present)
1457 len -= ETHER_CRC_LEN;
1461 DATA_LEN(rep) = DATA_LEN(seg);
1462 PKT_LEN(rep) = PKT_LEN(seg);
1463 SET_DATA_OFF(rep, DATA_OFF(seg));
1464 NB_SEGS(rep) = NB_SEGS(seg);
1465 PORT(rep) = PORT(seg);
1467 (*rxq->elts)[idx] = rep;
1469 * Fill NIC descriptor with the new buffer. The lkey and size
1470 * of the buffers are already known, only the buffer address
1473 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1474 if (len > DATA_LEN(seg)) {
1475 len -= DATA_LEN(seg);
1480 DATA_LEN(seg) = len;
1481 #ifdef MLX5_PMD_SOFT_COUNTERS
1482 /* Increment bytes counter. */
1483 rxq->stats.ibytes += PKT_LEN(pkt);
1485 /* Return packet. */
1491 /* Align consumer index to the next stride. */
1496 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1498 /* Update the consumer index. */
1499 rxq->rq_ci = rq_ci >> sges_n;
1501 *rxq->cq_db = htonl(rxq->cq_ci);
1503 *rxq->rq_db = htonl(rxq->rq_ci);
1504 #ifdef MLX5_PMD_SOFT_COUNTERS
1505 /* Increment packets counter. */
1506 rxq->stats.ipackets += i;
1512 * Dummy DPDK callback for TX.
1514 * This function is used to temporarily replace the real callback during
1515 * unsafe control operations on the queue, or in case of error.
1518 * Generic pointer to TX queue structure.
1520 * Packets to transmit.
1522 * Number of packets in array.
1525 * Number of packets successfully transmitted (<= pkts_n).
1528 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1537 * Dummy DPDK callback for RX.
1539 * This function is used to temporarily replace the real callback during
1540 * unsafe control operations on the queue, or in case of error.
1543 * Generic pointer to RX queue structure.
1545 * Array to store received packets.
1547 * Maximum number of packets in array.
1550 * Number of packets successfully received (<= pkts_n).
1553 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)