4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
103 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 /* Repeat with outer_l3_type being set. Just in case. */
123 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 RTE_PTYPE_L4_NONFRAG;
127 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
179 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_UDP;
182 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_UDP;
185 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_UDP;
188 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_UDP;
194 * Return the size of tailroom of WQ.
197 * Pointer to TX queue structure.
199 * Pointer to tail of WQ.
205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
208 tailroom = (uintptr_t)(txq->wqes) +
209 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
215 * Copy data to tailroom of circular queue.
218 * Pointer to destination.
222 * Number of bytes to copy.
224 * Pointer to head of queue.
226 * Size of tailroom from dst.
229 * Pointer after copied data.
232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
233 void *base, size_t tailroom)
238 rte_memcpy(dst, src, tailroom);
239 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
241 ret = (uint8_t *)base + n - tailroom;
243 rte_memcpy(dst, src, n);
244 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
250 * DPDK callback to check the status of a tx descriptor.
255 * The index of the descriptor in the ring.
258 * The status of the tx descriptor.
261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
263 struct mlx5_txq_data *txq = tx_queue;
266 mlx5_tx_complete(txq);
267 used = txq->elts_head - txq->elts_tail;
269 return RTE_ETH_TX_DESC_FULL;
270 return RTE_ETH_TX_DESC_DONE;
274 * DPDK callback to check the status of a rx descriptor.
279 * The index of the descriptor in the ring.
282 * The status of the tx descriptor.
285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
287 struct mlx5_rxq_data *rxq = rx_queue;
288 struct rxq_zip *zip = &rxq->zip;
289 volatile struct mlx5_cqe *cqe;
290 const unsigned int cqe_n = (1 << rxq->cqe_n);
291 const unsigned int cqe_cnt = cqe_n - 1;
295 /* if we are processing a compressed cqe */
297 used = zip->cqe_cnt - zip->ca;
303 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
304 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
308 op_own = cqe->op_own;
309 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
310 n = rte_be_to_cpu_32(cqe->byte_cnt);
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
317 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
319 return RTE_ETH_RX_DESC_DONE;
320 return RTE_ETH_RX_DESC_AVAIL;
324 * DPDK callback for TX.
327 * Generic pointer to TX queue structure.
329 * Packets to transmit.
331 * Number of packets in array.
334 * Number of packets successfully transmitted (<= pkts_n).
337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
339 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
340 uint16_t elts_head = txq->elts_head;
341 const uint16_t elts_n = 1 << txq->elts_n;
342 const uint16_t elts_m = elts_n - 1;
349 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
350 unsigned int segs_n = 0;
351 const unsigned int max_inline = txq->max_inline;
353 if (unlikely(!pkts_n))
355 /* Prefetch first packet cacheline. */
356 rte_prefetch0(*pkts);
357 /* Start processing. */
358 mlx5_tx_complete(txq);
359 max_elts = (elts_n - (elts_head - txq->elts_tail));
360 /* A CQE slot must always be available. */
361 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
362 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
363 if (unlikely(!max_wqe))
366 struct rte_mbuf *buf = NULL;
368 volatile struct mlx5_wqe_v *wqe = NULL;
369 volatile rte_v128u32_t *dseg = NULL;
372 unsigned int sg = 0; /* counter of additional segs attached. */
374 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
375 uint16_t tso_header_sz = 0;
379 uint16_t tso_segsz = 0;
380 #ifdef MLX5_PMD_SOFT_COUNTERS
381 uint32_t total_length = 0;
386 segs_n = buf->nb_segs;
388 * Make sure there is enough room to store this packet and
389 * that one ring entry remains unused.
392 if (max_elts < segs_n)
396 if (unlikely(--max_wqe == 0))
398 wqe = (volatile struct mlx5_wqe_v *)
399 tx_mlx5_wqe(txq, txq->wqe_ci);
400 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
402 rte_prefetch0(*(pkts + 1));
403 addr = rte_pktmbuf_mtod(buf, uintptr_t);
404 length = DATA_LEN(buf);
405 ehdr = (((uint8_t *)addr)[1] << 8) |
406 ((uint8_t *)addr)[0];
407 #ifdef MLX5_PMD_SOFT_COUNTERS
408 total_length = length;
410 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
411 txq->stats.oerrors++;
414 /* Update element. */
415 (*txq->elts)[elts_head & elts_m] = buf;
416 /* Prefetch next buffer data. */
419 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
420 cs_flags = txq_ol_cksum_to_cs(txq, buf);
421 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
422 /* Replace the Ethernet type by the VLAN if necessary. */
423 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
424 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
426 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
430 /* Copy Destination and source mac address. */
431 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
433 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
434 /* Copy missing two bytes to end the DSeg. */
435 memcpy((uint8_t *)raw + len + sizeof(vlan),
436 ((uint8_t *)addr) + len, 2);
440 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
441 MLX5_WQE_DWORD_SIZE);
442 length -= pkt_inline_sz;
443 addr += pkt_inline_sz;
445 raw += MLX5_WQE_DWORD_SIZE;
446 tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
449 (uintptr_t)(((uintptr_t)txq->wqes) +
450 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
453 (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
454 const uint64_t is_tunneled =
455 buf->ol_flags & (PKT_TX_TUNNEL_GRE |
456 PKT_TX_TUNNEL_VXLAN);
458 tso_header_sz = buf->l2_len + vlan_sz +
459 buf->l3_len + buf->l4_len;
460 tso_segsz = buf->tso_segsz;
461 if (unlikely(tso_segsz == 0)) {
462 txq->stats.oerrors++;
465 if (is_tunneled && txq->tunnel_en) {
466 tso_header_sz += buf->outer_l2_len +
468 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
470 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
472 if (unlikely(tso_header_sz > MLX5_MAX_TSO_HEADER)) {
473 txq->stats.oerrors++;
476 copy_b = tso_header_sz - pkt_inline_sz;
477 /* First seg must contain all headers. */
478 assert(copy_b <= length);
479 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
480 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
482 if (unlikely(max_wqe < n))
485 rte_memcpy((void *)raw, (void *)addr, copy_b);
488 /* Include padding for TSO header. */
489 copy_b = MLX5_WQE_DS(copy_b) *
491 pkt_inline_sz += copy_b;
495 wqe->ctrl = (rte_v128u32_t){
496 rte_cpu_to_be_32(txq->wqe_ci << 8),
497 rte_cpu_to_be_32(txq->qp_num_8s | 1),
502 #ifdef MLX5_PMD_SOFT_COUNTERS
509 /* Inline if enough room. */
510 if (max_inline || tso) {
512 uintptr_t end = (uintptr_t)
513 (((uintptr_t)txq->wqes) +
514 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
515 unsigned int inline_room = max_inline *
516 RTE_CACHE_LINE_SIZE -
517 (pkt_inline_sz - 2) -
523 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
524 RTE_CACHE_LINE_SIZE);
525 copy_b = (addr_end > addr) ?
526 RTE_MIN((addr_end - addr), length) : 0;
527 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
529 * One Dseg remains in the current WQE. To
530 * keep the computation positive, it is
531 * removed after the bytes to Dseg conversion.
533 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
535 if (unlikely(max_wqe < n))
539 inl = rte_cpu_to_be_32(copy_b |
541 rte_memcpy((void *)raw,
542 (void *)&inl, sizeof(inl));
544 pkt_inline_sz += sizeof(inl);
546 rte_memcpy((void *)raw, (void *)addr, copy_b);
549 pkt_inline_sz += copy_b;
552 * 2 DWORDs consumed by the WQE header + ETH segment +
553 * the size of the inline part of the packet.
555 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
557 if (ds % (MLX5_WQE_SIZE /
558 MLX5_WQE_DWORD_SIZE) == 0) {
559 if (unlikely(--max_wqe == 0))
561 dseg = (volatile rte_v128u32_t *)
562 tx_mlx5_wqe(txq, txq->wqe_ci +
565 dseg = (volatile rte_v128u32_t *)
567 (ds * MLX5_WQE_DWORD_SIZE));
570 } else if (!segs_n) {
574 inline_room -= copy_b;
578 addr = rte_pktmbuf_mtod(buf, uintptr_t);
579 length = DATA_LEN(buf);
580 #ifdef MLX5_PMD_SOFT_COUNTERS
581 total_length += length;
583 (*txq->elts)[++elts_head & elts_m] = buf;
588 * No inline has been done in the packet, only the
589 * Ethernet Header as been stored.
591 dseg = (volatile rte_v128u32_t *)
592 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
595 /* Add the remaining packet as a simple ds. */
596 addr = rte_cpu_to_be_64(addr);
597 *dseg = (rte_v128u32_t){
598 rte_cpu_to_be_32(length),
599 mlx5_tx_mb2mr(txq, buf),
612 * Spill on next WQE when the current one does not have
613 * enough room left. Size of WQE must a be a multiple
614 * of data segment size.
616 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
617 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
618 if (unlikely(--max_wqe == 0))
620 dseg = (volatile rte_v128u32_t *)
621 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
622 rte_prefetch0(tx_mlx5_wqe(txq,
623 txq->wqe_ci + ds / 4 + 1));
630 length = DATA_LEN(buf);
631 #ifdef MLX5_PMD_SOFT_COUNTERS
632 total_length += length;
634 /* Store segment information. */
635 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
636 *dseg = (rte_v128u32_t){
637 rte_cpu_to_be_32(length),
638 mlx5_tx_mb2mr(txq, buf),
642 (*txq->elts)[++elts_head & elts_m] = buf;
646 if (ds > MLX5_DSEG_MAX) {
647 txq->stats.oerrors++;
654 /* Initialize known and common part of the WQE structure. */
656 wqe->ctrl = (rte_v128u32_t){
657 rte_cpu_to_be_32((txq->wqe_ci << 8) |
659 rte_cpu_to_be_32(txq->qp_num_8s | ds),
663 wqe->eseg = (rte_v128u32_t){
665 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
667 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
670 wqe->ctrl = (rte_v128u32_t){
671 rte_cpu_to_be_32((txq->wqe_ci << 8) |
673 rte_cpu_to_be_32(txq->qp_num_8s | ds),
677 wqe->eseg = (rte_v128u32_t){
681 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
685 txq->wqe_ci += (ds + 3) / 4;
686 /* Save the last successful WQE for completion request */
687 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
688 #ifdef MLX5_PMD_SOFT_COUNTERS
689 /* Increment sent bytes counter. */
690 txq->stats.obytes += total_length;
692 } while (i < pkts_n);
693 /* Take a shortcut if nothing must be sent. */
694 if (unlikely((i + k) == 0))
696 txq->elts_head += (i + j);
697 /* Check whether completion threshold has been reached. */
698 comp = txq->elts_comp + i + j + k;
699 if (comp >= MLX5_TX_COMP_THRESH) {
700 /* Request completion on last WQE. */
701 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
702 /* Save elts_head in unused "immediate" field of WQE. */
703 last_wqe->ctrl3 = txq->elts_head;
709 txq->elts_comp = comp;
711 #ifdef MLX5_PMD_SOFT_COUNTERS
712 /* Increment sent packets counter. */
713 txq->stats.opackets += i;
715 /* Ring QP doorbell. */
716 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
721 * Open a MPW session.
724 * Pointer to TX queue structure.
726 * Pointer to MPW session structure.
731 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
733 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
734 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
735 (volatile struct mlx5_wqe_data_seg (*)[])
736 tx_mlx5_wqe(txq, idx + 1);
738 mpw->state = MLX5_MPW_STATE_OPENED;
742 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
743 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
744 mpw->wqe->eseg.inline_hdr_sz = 0;
745 mpw->wqe->eseg.rsvd0 = 0;
746 mpw->wqe->eseg.rsvd1 = 0;
747 mpw->wqe->eseg.rsvd2 = 0;
748 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
751 mpw->wqe->ctrl[2] = 0;
752 mpw->wqe->ctrl[3] = 0;
753 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
754 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
755 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
756 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
757 mpw->data.dseg[2] = &(*dseg)[0];
758 mpw->data.dseg[3] = &(*dseg)[1];
759 mpw->data.dseg[4] = &(*dseg)[2];
763 * Close a MPW session.
766 * Pointer to TX queue structure.
768 * Pointer to MPW session structure.
771 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
773 unsigned int num = mpw->pkts_n;
776 * Store size in multiple of 16 bytes. Control and Ethernet segments
779 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
780 mpw->state = MLX5_MPW_STATE_CLOSED;
785 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
786 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
790 * DPDK callback for TX with MPW support.
793 * Generic pointer to TX queue structure.
795 * Packets to transmit.
797 * Number of packets in array.
800 * Number of packets successfully transmitted (<= pkts_n).
803 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
805 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
806 uint16_t elts_head = txq->elts_head;
807 const uint16_t elts_n = 1 << txq->elts_n;
808 const uint16_t elts_m = elts_n - 1;
814 struct mlx5_mpw mpw = {
815 .state = MLX5_MPW_STATE_CLOSED,
818 if (unlikely(!pkts_n))
820 /* Prefetch first packet cacheline. */
821 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
822 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
823 /* Start processing. */
824 mlx5_tx_complete(txq);
825 max_elts = (elts_n - (elts_head - txq->elts_tail));
826 /* A CQE slot must always be available. */
827 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
828 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
829 if (unlikely(!max_wqe))
832 struct rte_mbuf *buf = *(pkts++);
834 unsigned int segs_n = buf->nb_segs;
838 * Make sure there is enough room to store this packet and
839 * that one ring entry remains unused.
842 if (max_elts < segs_n)
844 /* Do not bother with large packets MPW cannot handle. */
845 if (segs_n > MLX5_MPW_DSEG_MAX) {
846 txq->stats.oerrors++;
851 cs_flags = txq_ol_cksum_to_cs(txq, buf);
852 /* Retrieve packet information. */
853 length = PKT_LEN(buf);
855 /* Start new session if packet differs. */
856 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
857 ((mpw.len != length) ||
859 (mpw.wqe->eseg.cs_flags != cs_flags)))
860 mlx5_mpw_close(txq, &mpw);
861 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
863 * Multi-Packet WQE consumes at most two WQE.
864 * mlx5_mpw_new() expects to be able to use such
867 if (unlikely(max_wqe < 2))
870 mlx5_mpw_new(txq, &mpw, length);
871 mpw.wqe->eseg.cs_flags = cs_flags;
873 /* Multi-segment packets must be alone in their MPW. */
874 assert((segs_n == 1) || (mpw.pkts_n == 0));
875 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
879 volatile struct mlx5_wqe_data_seg *dseg;
883 (*txq->elts)[elts_head++ & elts_m] = buf;
884 dseg = mpw.data.dseg[mpw.pkts_n];
885 addr = rte_pktmbuf_mtod(buf, uintptr_t);
886 *dseg = (struct mlx5_wqe_data_seg){
887 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
888 .lkey = mlx5_tx_mb2mr(txq, buf),
889 .addr = rte_cpu_to_be_64(addr),
891 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
892 length += DATA_LEN(buf);
898 assert(length == mpw.len);
899 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
900 mlx5_mpw_close(txq, &mpw);
901 #ifdef MLX5_PMD_SOFT_COUNTERS
902 /* Increment sent bytes counter. */
903 txq->stats.obytes += length;
907 /* Take a shortcut if nothing must be sent. */
908 if (unlikely(i == 0))
910 /* Check whether completion threshold has been reached. */
911 /* "j" includes both packets and segments. */
912 comp = txq->elts_comp + j;
913 if (comp >= MLX5_TX_COMP_THRESH) {
914 volatile struct mlx5_wqe *wqe = mpw.wqe;
916 /* Request completion on last WQE. */
917 wqe->ctrl[2] = rte_cpu_to_be_32(8);
918 /* Save elts_head in unused "immediate" field of WQE. */
919 wqe->ctrl[3] = elts_head;
925 txq->elts_comp = comp;
927 #ifdef MLX5_PMD_SOFT_COUNTERS
928 /* Increment sent packets counter. */
929 txq->stats.opackets += i;
931 /* Ring QP doorbell. */
932 if (mpw.state == MLX5_MPW_STATE_OPENED)
933 mlx5_mpw_close(txq, &mpw);
934 mlx5_tx_dbrec(txq, mpw.wqe);
935 txq->elts_head = elts_head;
940 * Open a MPW inline session.
943 * Pointer to TX queue structure.
945 * Pointer to MPW session structure.
950 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
953 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
954 struct mlx5_wqe_inl_small *inl;
956 mpw->state = MLX5_MPW_INL_STATE_OPENED;
960 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
961 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
964 mpw->wqe->ctrl[2] = 0;
965 mpw->wqe->ctrl[3] = 0;
966 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
967 mpw->wqe->eseg.inline_hdr_sz = 0;
968 mpw->wqe->eseg.cs_flags = 0;
969 mpw->wqe->eseg.rsvd0 = 0;
970 mpw->wqe->eseg.rsvd1 = 0;
971 mpw->wqe->eseg.rsvd2 = 0;
972 inl = (struct mlx5_wqe_inl_small *)
973 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
974 mpw->data.raw = (uint8_t *)&inl->raw;
978 * Close a MPW inline session.
981 * Pointer to TX queue structure.
983 * Pointer to MPW session structure.
986 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
989 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
990 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
992 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
994 * Store size in multiple of 16 bytes. Control and Ethernet segments
997 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
999 mpw->state = MLX5_MPW_STATE_CLOSED;
1000 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1001 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1005 * DPDK callback for TX with MPW inline support.
1008 * Generic pointer to TX queue structure.
1010 * Packets to transmit.
1012 * Number of packets in array.
1015 * Number of packets successfully transmitted (<= pkts_n).
1018 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1021 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1022 uint16_t elts_head = txq->elts_head;
1023 const uint16_t elts_n = 1 << txq->elts_n;
1024 const uint16_t elts_m = elts_n - 1;
1030 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1031 struct mlx5_mpw mpw = {
1032 .state = MLX5_MPW_STATE_CLOSED,
1035 * Compute the maximum number of WQE which can be consumed by inline
1038 * - 1 control segment,
1039 * - 1 Ethernet segment,
1040 * - N Dseg from the inline request.
1042 const unsigned int wqe_inl_n =
1043 ((2 * MLX5_WQE_DWORD_SIZE +
1044 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1045 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1047 if (unlikely(!pkts_n))
1049 /* Prefetch first packet cacheline. */
1050 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1051 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1052 /* Start processing. */
1053 mlx5_tx_complete(txq);
1054 max_elts = (elts_n - (elts_head - txq->elts_tail));
1055 /* A CQE slot must always be available. */
1056 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1058 struct rte_mbuf *buf = *(pkts++);
1061 unsigned int segs_n = buf->nb_segs;
1065 * Make sure there is enough room to store this packet and
1066 * that one ring entry remains unused.
1069 if (max_elts < segs_n)
1071 /* Do not bother with large packets MPW cannot handle. */
1072 if (segs_n > MLX5_MPW_DSEG_MAX) {
1073 txq->stats.oerrors++;
1079 * Compute max_wqe in case less WQE were consumed in previous
1082 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1083 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1084 /* Retrieve packet information. */
1085 length = PKT_LEN(buf);
1086 /* Start new session if packet differs. */
1087 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1088 if ((mpw.len != length) ||
1090 (mpw.wqe->eseg.cs_flags != cs_flags))
1091 mlx5_mpw_close(txq, &mpw);
1092 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1093 if ((mpw.len != length) ||
1095 (length > inline_room) ||
1096 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1097 mlx5_mpw_inline_close(txq, &mpw);
1099 txq->max_inline * RTE_CACHE_LINE_SIZE;
1102 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1103 if ((segs_n != 1) ||
1104 (length > inline_room)) {
1106 * Multi-Packet WQE consumes at most two WQE.
1107 * mlx5_mpw_new() expects to be able to use
1110 if (unlikely(max_wqe < 2))
1113 mlx5_mpw_new(txq, &mpw, length);
1114 mpw.wqe->eseg.cs_flags = cs_flags;
1116 if (unlikely(max_wqe < wqe_inl_n))
1118 max_wqe -= wqe_inl_n;
1119 mlx5_mpw_inline_new(txq, &mpw, length);
1120 mpw.wqe->eseg.cs_flags = cs_flags;
1123 /* Multi-segment packets must be alone in their MPW. */
1124 assert((segs_n == 1) || (mpw.pkts_n == 0));
1125 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1126 assert(inline_room ==
1127 txq->max_inline * RTE_CACHE_LINE_SIZE);
1128 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1132 volatile struct mlx5_wqe_data_seg *dseg;
1135 (*txq->elts)[elts_head++ & elts_m] = buf;
1136 dseg = mpw.data.dseg[mpw.pkts_n];
1137 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1138 *dseg = (struct mlx5_wqe_data_seg){
1140 rte_cpu_to_be_32(DATA_LEN(buf)),
1141 .lkey = mlx5_tx_mb2mr(txq, buf),
1142 .addr = rte_cpu_to_be_64(addr),
1144 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1145 length += DATA_LEN(buf);
1151 assert(length == mpw.len);
1152 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1153 mlx5_mpw_close(txq, &mpw);
1157 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1158 assert(length <= inline_room);
1159 assert(length == DATA_LEN(buf));
1160 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1161 (*txq->elts)[elts_head++ & elts_m] = buf;
1162 /* Maximum number of bytes before wrapping. */
1163 max = ((((uintptr_t)(txq->wqes)) +
1166 (uintptr_t)mpw.data.raw);
1168 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1171 mpw.data.raw = (volatile void *)txq->wqes;
1172 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1173 (void *)(addr + max),
1175 mpw.data.raw += length - max;
1177 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1183 (volatile void *)txq->wqes;
1185 mpw.data.raw += length;
1188 mpw.total_len += length;
1190 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1191 mlx5_mpw_inline_close(txq, &mpw);
1193 txq->max_inline * RTE_CACHE_LINE_SIZE;
1195 inline_room -= length;
1198 #ifdef MLX5_PMD_SOFT_COUNTERS
1199 /* Increment sent bytes counter. */
1200 txq->stats.obytes += length;
1204 /* Take a shortcut if nothing must be sent. */
1205 if (unlikely(i == 0))
1207 /* Check whether completion threshold has been reached. */
1208 /* "j" includes both packets and segments. */
1209 comp = txq->elts_comp + j;
1210 if (comp >= MLX5_TX_COMP_THRESH) {
1211 volatile struct mlx5_wqe *wqe = mpw.wqe;
1213 /* Request completion on last WQE. */
1214 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1215 /* Save elts_head in unused "immediate" field of WQE. */
1216 wqe->ctrl[3] = elts_head;
1222 txq->elts_comp = comp;
1224 #ifdef MLX5_PMD_SOFT_COUNTERS
1225 /* Increment sent packets counter. */
1226 txq->stats.opackets += i;
1228 /* Ring QP doorbell. */
1229 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1230 mlx5_mpw_inline_close(txq, &mpw);
1231 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1232 mlx5_mpw_close(txq, &mpw);
1233 mlx5_tx_dbrec(txq, mpw.wqe);
1234 txq->elts_head = elts_head;
1239 * Open an Enhanced MPW session.
1242 * Pointer to TX queue structure.
1244 * Pointer to MPW session structure.
1249 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1251 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1253 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1255 mpw->total_len = sizeof(struct mlx5_wqe);
1256 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1258 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1259 (txq->wqe_ci << 8) |
1260 MLX5_OPCODE_ENHANCED_MPSW);
1261 mpw->wqe->ctrl[2] = 0;
1262 mpw->wqe->ctrl[3] = 0;
1263 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1264 if (unlikely(padding)) {
1265 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1267 /* Pad the first 2 DWORDs with zero-length inline header. */
1268 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1269 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1270 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1271 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1272 /* Start from the next WQEBB. */
1273 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1275 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1280 * Close an Enhanced MPW session.
1283 * Pointer to TX queue structure.
1285 * Pointer to MPW session structure.
1288 * Number of consumed WQEs.
1290 static inline uint16_t
1291 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1295 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1298 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1299 MLX5_WQE_DS(mpw->total_len));
1300 mpw->state = MLX5_MPW_STATE_CLOSED;
1301 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1307 * TX with Enhanced MPW support.
1310 * Pointer to TX queue structure.
1312 * Packets to transmit.
1314 * Number of packets in array.
1317 * Number of packets successfully transmitted (<= pkts_n).
1319 static inline uint16_t
1320 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1323 uint16_t elts_head = txq->elts_head;
1324 const uint16_t elts_n = 1 << txq->elts_n;
1325 const uint16_t elts_m = elts_n - 1;
1330 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1331 unsigned int mpw_room = 0;
1332 unsigned int inl_pad = 0;
1334 struct mlx5_mpw mpw = {
1335 .state = MLX5_MPW_STATE_CLOSED,
1338 if (unlikely(!pkts_n))
1340 /* Start processing. */
1341 mlx5_tx_complete(txq);
1342 max_elts = (elts_n - (elts_head - txq->elts_tail));
1343 /* A CQE slot must always be available. */
1344 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1345 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1346 if (unlikely(!max_wqe))
1349 struct rte_mbuf *buf = *(pkts++);
1352 unsigned int do_inline = 0; /* Whether inline is possible. */
1356 /* Multi-segmented packet is handled in slow-path outside. */
1357 assert(NB_SEGS(buf) == 1);
1358 /* Make sure there is enough room to store this packet. */
1359 if (max_elts - j == 0)
1361 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1362 /* Retrieve packet information. */
1363 length = PKT_LEN(buf);
1364 /* Start new session if:
1365 * - multi-segment packet
1366 * - no space left even for a dseg
1367 * - next packet can be inlined with a new WQE
1370 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1371 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1373 (length <= txq->inline_max_packet_sz &&
1374 inl_pad + sizeof(inl_hdr) + length >
1376 (mpw.wqe->eseg.cs_flags != cs_flags))
1377 max_wqe -= mlx5_empw_close(txq, &mpw);
1379 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1380 /* In Enhanced MPW, inline as much as the budget is
1381 * allowed. The remaining space is to be filled with
1382 * dsegs. If the title WQEBB isn't padded, it will have
1385 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1386 (max_inline ? max_inline :
1387 pkts_n * MLX5_WQE_DWORD_SIZE) +
1389 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1391 /* Don't pad the title WQEBB to not waste WQ. */
1392 mlx5_empw_new(txq, &mpw, 0);
1393 mpw_room -= mpw.total_len;
1395 do_inline = length <= txq->inline_max_packet_sz &&
1396 sizeof(inl_hdr) + length <= mpw_room &&
1398 mpw.wqe->eseg.cs_flags = cs_flags;
1400 /* Evaluate whether the next packet can be inlined.
1401 * Inlininig is possible when:
1402 * - length is less than configured value
1403 * - length fits for remaining space
1404 * - not required to fill the title WQEBB with dsegs
1407 length <= txq->inline_max_packet_sz &&
1408 inl_pad + sizeof(inl_hdr) + length <=
1410 (!txq->mpw_hdr_dseg ||
1411 mpw.total_len >= MLX5_WQE_SIZE);
1414 /* Inline packet into WQE. */
1417 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1418 assert(length == DATA_LEN(buf));
1419 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1420 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1421 mpw.data.raw = (volatile void *)
1422 ((uintptr_t)mpw.data.raw + inl_pad);
1423 max = tx_mlx5_wq_tailroom(txq,
1424 (void *)(uintptr_t)mpw.data.raw);
1425 /* Copy inline header. */
1426 mpw.data.raw = (volatile void *)
1428 (void *)(uintptr_t)mpw.data.raw,
1431 (void *)(uintptr_t)txq->wqes,
1433 max = tx_mlx5_wq_tailroom(txq,
1434 (void *)(uintptr_t)mpw.data.raw);
1435 /* Copy packet data. */
1436 mpw.data.raw = (volatile void *)
1438 (void *)(uintptr_t)mpw.data.raw,
1441 (void *)(uintptr_t)txq->wqes,
1444 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1445 /* No need to get completion as the entire packet is
1446 * copied to WQ. Free the buf right away.
1448 rte_pktmbuf_free_seg(buf);
1449 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1450 /* Add pad in the next packet if any. */
1451 inl_pad = (((uintptr_t)mpw.data.raw +
1452 (MLX5_WQE_DWORD_SIZE - 1)) &
1453 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1454 (uintptr_t)mpw.data.raw;
1456 /* No inline. Load a dseg of packet pointer. */
1457 volatile rte_v128u32_t *dseg;
1459 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1460 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1461 assert(length == DATA_LEN(buf));
1462 if (!tx_mlx5_wq_tailroom(txq,
1463 (void *)((uintptr_t)mpw.data.raw
1465 dseg = (volatile void *)txq->wqes;
1467 dseg = (volatile void *)
1468 ((uintptr_t)mpw.data.raw +
1470 (*txq->elts)[elts_head++ & elts_m] = buf;
1471 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1472 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1473 rte_prefetch2((void *)(addr +
1474 n * RTE_CACHE_LINE_SIZE));
1475 addr = rte_cpu_to_be_64(addr);
1476 *dseg = (rte_v128u32_t) {
1477 rte_cpu_to_be_32(length),
1478 mlx5_tx_mb2mr(txq, buf),
1482 mpw.data.raw = (volatile void *)(dseg + 1);
1483 mpw.total_len += (inl_pad + sizeof(*dseg));
1486 mpw_room -= (inl_pad + sizeof(*dseg));
1489 #ifdef MLX5_PMD_SOFT_COUNTERS
1490 /* Increment sent bytes counter. */
1491 txq->stats.obytes += length;
1494 } while (i < pkts_n);
1495 /* Take a shortcut if nothing must be sent. */
1496 if (unlikely(i == 0))
1498 /* Check whether completion threshold has been reached. */
1499 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1500 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1501 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1502 volatile struct mlx5_wqe *wqe = mpw.wqe;
1504 /* Request completion on last WQE. */
1505 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1506 /* Save elts_head in unused "immediate" field of WQE. */
1507 wqe->ctrl[3] = elts_head;
1509 txq->mpw_comp = txq->wqe_ci;
1514 txq->elts_comp += j;
1516 #ifdef MLX5_PMD_SOFT_COUNTERS
1517 /* Increment sent packets counter. */
1518 txq->stats.opackets += i;
1520 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1521 mlx5_empw_close(txq, &mpw);
1522 /* Ring QP doorbell. */
1523 mlx5_tx_dbrec(txq, mpw.wqe);
1524 txq->elts_head = elts_head;
1529 * DPDK callback for TX with Enhanced MPW support.
1532 * Generic pointer to TX queue structure.
1534 * Packets to transmit.
1536 * Number of packets in array.
1539 * Number of packets successfully transmitted (<= pkts_n).
1542 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1544 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1547 while (pkts_n > nb_tx) {
1551 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1553 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1558 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1560 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1570 * Translate RX completion flags to packet type.
1575 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1578 * Packet type for struct rte_mbuf.
1580 static inline uint32_t
1581 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1584 uint8_t pinfo = cqe->pkt_info;
1585 uint16_t ptype = cqe->hdr_type_etc;
1588 * The index to the array should have:
1589 * bit[1:0] = l3_hdr_type
1590 * bit[4:2] = l4_hdr_type
1593 * bit[7] = outer_l3_type
1595 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1596 return mlx5_ptype_table[idx];
1600 * Get size of the next packet for a given CQE. For compressed CQEs, the
1601 * consumer index is updated only once all packets of the current one have
1605 * Pointer to RX queue.
1608 * @param[out] rss_hash
1609 * Packet RSS Hash result.
1612 * Packet size in bytes (0 if there is none), -1 in case of completion
1616 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1617 uint16_t cqe_cnt, uint32_t *rss_hash)
1619 struct rxq_zip *zip = &rxq->zip;
1620 uint16_t cqe_n = cqe_cnt + 1;
1624 /* Process compressed data in the CQE and mini arrays. */
1626 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1627 (volatile struct mlx5_mini_cqe8 (*)[8])
1628 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1630 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1631 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1632 if ((++zip->ai & 7) == 0) {
1633 /* Invalidate consumed CQEs */
1636 while (idx != end) {
1637 (*rxq->cqes)[idx & cqe_cnt].op_own =
1638 MLX5_CQE_INVALIDATE;
1642 * Increment consumer index to skip the number of
1643 * CQEs consumed. Hardware leaves holes in the CQ
1644 * ring for software use.
1649 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1650 /* Invalidate the rest */
1654 while (idx != end) {
1655 (*rxq->cqes)[idx & cqe_cnt].op_own =
1656 MLX5_CQE_INVALIDATE;
1659 rxq->cq_ci = zip->cq_ci;
1662 /* No compressed data, get next CQE and verify if it is compressed. */
1667 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1668 if (unlikely(ret == 1))
1671 op_own = cqe->op_own;
1673 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1674 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1675 (volatile struct mlx5_mini_cqe8 (*)[8])
1676 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1679 /* Fix endianness. */
1680 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1682 * Current mini array position is the one returned by
1685 * If completion comprises several mini arrays, as a
1686 * special case the second one is located 7 CQEs after
1687 * the initial CQE instead of 8 for subsequent ones.
1689 zip->ca = rxq->cq_ci;
1690 zip->na = zip->ca + 7;
1691 /* Compute the next non compressed CQE. */
1693 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1694 /* Get packet size to return. */
1695 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1696 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1698 /* Prefetch all the entries to be invalidated */
1701 while (idx != end) {
1702 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1706 len = rte_be_to_cpu_32(cqe->byte_cnt);
1707 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1709 /* Error while receiving packet. */
1710 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1717 * Translate RX completion flags to offload flags.
1720 * Pointer to RX queue structure.
1725 * Offload flags (ol_flags) for struct rte_mbuf.
1727 static inline uint32_t
1728 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1730 uint32_t ol_flags = 0;
1731 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1735 MLX5_CQE_RX_L3_HDR_VALID,
1736 PKT_RX_IP_CKSUM_GOOD) |
1738 MLX5_CQE_RX_L4_HDR_VALID,
1739 PKT_RX_L4_CKSUM_GOOD);
1740 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1743 MLX5_CQE_RX_L3_HDR_VALID,
1744 PKT_RX_IP_CKSUM_GOOD) |
1746 MLX5_CQE_RX_L4_HDR_VALID,
1747 PKT_RX_L4_CKSUM_GOOD);
1752 * DPDK callback for RX.
1755 * Generic pointer to RX queue structure.
1757 * Array to store received packets.
1759 * Maximum number of packets in array.
1762 * Number of packets successfully received (<= pkts_n).
1765 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1767 struct mlx5_rxq_data *rxq = dpdk_rxq;
1768 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1769 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1770 const unsigned int sges_n = rxq->sges_n;
1771 struct rte_mbuf *pkt = NULL;
1772 struct rte_mbuf *seg = NULL;
1773 volatile struct mlx5_cqe *cqe =
1774 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1776 unsigned int rq_ci = rxq->rq_ci << sges_n;
1777 int len = 0; /* keep its value across iterations. */
1780 unsigned int idx = rq_ci & wqe_cnt;
1781 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1782 struct rte_mbuf *rep = (*rxq->elts)[idx];
1783 uint32_t rss_hash_res = 0;
1791 rep = rte_mbuf_raw_alloc(rxq->mp);
1792 if (unlikely(rep == NULL)) {
1793 ++rxq->stats.rx_nombuf;
1796 * no buffers before we even started,
1797 * bail out silently.
1801 while (pkt != seg) {
1802 assert(pkt != (*rxq->elts)[idx]);
1806 rte_mbuf_raw_free(pkt);
1812 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1813 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1816 rte_mbuf_raw_free(rep);
1819 if (unlikely(len == -1)) {
1820 /* RX error, packet is likely too large. */
1821 rte_mbuf_raw_free(rep);
1822 ++rxq->stats.idropped;
1826 assert(len >= (rxq->crc_present << 2));
1827 /* Update packet information. */
1828 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1830 if (rss_hash_res && rxq->rss_hash) {
1831 pkt->hash.rss = rss_hash_res;
1832 pkt->ol_flags = PKT_RX_RSS_HASH;
1835 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1836 pkt->ol_flags |= PKT_RX_FDIR;
1837 if (cqe->sop_drop_qpn !=
1838 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1839 uint32_t mark = cqe->sop_drop_qpn;
1841 pkt->ol_flags |= PKT_RX_FDIR_ID;
1843 mlx5_flow_mark_get(mark);
1846 if (rxq->csum | rxq->csum_l2tun)
1847 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1848 if (rxq->vlan_strip &&
1849 (cqe->hdr_type_etc &
1850 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1851 pkt->ol_flags |= PKT_RX_VLAN |
1852 PKT_RX_VLAN_STRIPPED;
1854 rte_be_to_cpu_16(cqe->vlan_info);
1856 if (rxq->hw_timestamp) {
1858 rte_be_to_cpu_64(cqe->timestamp);
1859 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1861 if (rxq->crc_present)
1862 len -= ETHER_CRC_LEN;
1865 DATA_LEN(rep) = DATA_LEN(seg);
1866 PKT_LEN(rep) = PKT_LEN(seg);
1867 SET_DATA_OFF(rep, DATA_OFF(seg));
1868 PORT(rep) = PORT(seg);
1869 (*rxq->elts)[idx] = rep;
1871 * Fill NIC descriptor with the new buffer. The lkey and size
1872 * of the buffers are already known, only the buffer address
1875 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1876 if (len > DATA_LEN(seg)) {
1877 len -= DATA_LEN(seg);
1882 DATA_LEN(seg) = len;
1883 #ifdef MLX5_PMD_SOFT_COUNTERS
1884 /* Increment bytes counter. */
1885 rxq->stats.ibytes += PKT_LEN(pkt);
1887 /* Return packet. */
1893 /* Align consumer index to the next stride. */
1898 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1900 /* Update the consumer index. */
1901 rxq->rq_ci = rq_ci >> sges_n;
1903 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1905 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1906 #ifdef MLX5_PMD_SOFT_COUNTERS
1907 /* Increment packets counter. */
1908 rxq->stats.ipackets += i;
1914 * Dummy DPDK callback for TX.
1916 * This function is used to temporarily replace the real callback during
1917 * unsafe control operations on the queue, or in case of error.
1920 * Generic pointer to TX queue structure.
1922 * Packets to transmit.
1924 * Number of packets in array.
1927 * Number of packets successfully transmitted (<= pkts_n).
1930 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1939 * Dummy DPDK callback for RX.
1941 * This function is used to temporarily replace the real callback during
1942 * unsafe control operations on the queue, or in case of error.
1945 * Generic pointer to RX queue structure.
1947 * Array to store received packets.
1949 * Maximum number of packets in array.
1952 * Number of packets successfully received (<= pkts_n).
1955 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1964 * Vectorized Rx/Tx routines are not compiled in when required vector
1965 * instructions are not supported on a target architecture. The following null
1966 * stubs are needed for linkage when those are not included outside of this file
1967 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1970 uint16_t __attribute__((weak))
1971 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1979 uint16_t __attribute__((weak))
1980 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1988 uint16_t __attribute__((weak))
1989 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1997 int __attribute__((weak))
1998 priv_check_raw_vec_tx_support(struct priv *priv, struct rte_eth_dev *dev)
2005 int __attribute__((weak))
2006 priv_check_vec_tx_support(struct priv *priv, struct rte_eth_dev *dev)
2013 int __attribute__((weak))
2014 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2020 int __attribute__((weak))
2021 priv_check_vec_rx_support(struct priv *priv)