4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
103 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 /* Repeat with outer_l3_type being set. Just in case. */
123 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 RTE_PTYPE_L4_NONFRAG;
127 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
179 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_UDP;
182 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_UDP;
185 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_UDP;
188 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_UDP;
194 * Return the size of tailroom of WQ.
197 * Pointer to TX queue structure.
199 * Pointer to tail of WQ.
205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
208 tailroom = (uintptr_t)(txq->wqes) +
209 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
215 * Copy data to tailroom of circular queue.
218 * Pointer to destination.
222 * Number of bytes to copy.
224 * Pointer to head of queue.
226 * Size of tailroom from dst.
229 * Pointer after copied data.
232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
233 void *base, size_t tailroom)
238 rte_memcpy(dst, src, tailroom);
239 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
241 ret = (uint8_t *)base + n - tailroom;
243 rte_memcpy(dst, src, n);
244 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
250 * DPDK callback to check the status of a tx descriptor.
255 * The index of the descriptor in the ring.
258 * The status of the tx descriptor.
261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
263 struct mlx5_txq_data *txq = tx_queue;
266 mlx5_tx_complete(txq);
267 used = txq->elts_head - txq->elts_tail;
269 return RTE_ETH_TX_DESC_FULL;
270 return RTE_ETH_TX_DESC_DONE;
274 * DPDK callback to check the status of a rx descriptor.
279 * The index of the descriptor in the ring.
282 * The status of the tx descriptor.
285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
287 struct mlx5_rxq_data *rxq = rx_queue;
288 struct rxq_zip *zip = &rxq->zip;
289 volatile struct mlx5_cqe *cqe;
290 const unsigned int cqe_n = (1 << rxq->cqe_n);
291 const unsigned int cqe_cnt = cqe_n - 1;
295 /* if we are processing a compressed cqe */
297 used = zip->cqe_cnt - zip->ca;
303 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
304 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
308 op_own = cqe->op_own;
309 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
310 n = rte_be_to_cpu_32(cqe->byte_cnt);
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
317 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
319 return RTE_ETH_RX_DESC_DONE;
320 return RTE_ETH_RX_DESC_AVAIL;
324 * DPDK callback for TX.
327 * Generic pointer to TX queue structure.
329 * Packets to transmit.
331 * Number of packets in array.
334 * Number of packets successfully transmitted (<= pkts_n).
337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
339 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
340 uint16_t elts_head = txq->elts_head;
341 const uint16_t elts_n = 1 << txq->elts_n;
342 const uint16_t elts_m = elts_n - 1;
349 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
350 unsigned int segs_n = 0;
351 const unsigned int max_inline = txq->max_inline;
353 if (unlikely(!pkts_n))
355 /* Prefetch first packet cacheline. */
356 rte_prefetch0(*pkts);
357 /* Start processing. */
358 mlx5_tx_complete(txq);
359 max_elts = (elts_n - (elts_head - txq->elts_tail));
360 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
361 if (unlikely(!max_wqe))
364 struct rte_mbuf *buf = NULL;
366 volatile struct mlx5_wqe_v *wqe = NULL;
367 volatile rte_v128u32_t *dseg = NULL;
370 unsigned int sg = 0; /* counter of additional segs attached. */
372 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
373 uint16_t tso_header_sz = 0;
375 uint8_t cs_flags = 0;
377 uint16_t tso_segsz = 0;
378 #ifdef MLX5_PMD_SOFT_COUNTERS
379 uint32_t total_length = 0;
384 segs_n = buf->nb_segs;
386 * Make sure there is enough room to store this packet and
387 * that one ring entry remains unused.
390 if (max_elts < segs_n)
394 if (unlikely(--max_wqe == 0))
396 wqe = (volatile struct mlx5_wqe_v *)
397 tx_mlx5_wqe(txq, txq->wqe_ci);
398 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
400 rte_prefetch0(*(pkts + 1));
401 addr = rte_pktmbuf_mtod(buf, uintptr_t);
402 length = DATA_LEN(buf);
403 ehdr = (((uint8_t *)addr)[1] << 8) |
404 ((uint8_t *)addr)[0];
405 #ifdef MLX5_PMD_SOFT_COUNTERS
406 total_length = length;
408 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
409 txq->stats.oerrors++;
412 /* Update element. */
413 (*txq->elts)[elts_head & elts_m] = buf;
414 /* Prefetch next buffer data. */
417 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
418 /* Should we enable HW CKSUM offload */
420 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
421 const uint64_t is_tunneled = buf->ol_flags &
423 PKT_TX_TUNNEL_VXLAN);
425 if (is_tunneled && txq->tunnel_en) {
426 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
427 MLX5_ETH_WQE_L4_INNER_CSUM;
428 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
429 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
431 cs_flags = MLX5_ETH_WQE_L3_CSUM |
432 MLX5_ETH_WQE_L4_CSUM;
435 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
436 /* Replace the Ethernet type by the VLAN if necessary. */
437 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
438 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
440 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
444 /* Copy Destination and source mac address. */
445 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
447 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
448 /* Copy missing two bytes to end the DSeg. */
449 memcpy((uint8_t *)raw + len + sizeof(vlan),
450 ((uint8_t *)addr) + len, 2);
454 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
455 MLX5_WQE_DWORD_SIZE);
456 length -= pkt_inline_sz;
457 addr += pkt_inline_sz;
459 raw += MLX5_WQE_DWORD_SIZE;
461 tso = buf->ol_flags & PKT_TX_TCP_SEG;
463 uintptr_t end = (uintptr_t)
464 (((uintptr_t)txq->wqes) +
468 uint8_t vlan_sz = (buf->ol_flags &
469 PKT_TX_VLAN_PKT) ? 4 : 0;
470 const uint64_t is_tunneled =
473 PKT_TX_TUNNEL_VXLAN);
475 tso_header_sz = buf->l2_len + vlan_sz +
476 buf->l3_len + buf->l4_len;
477 tso_segsz = buf->tso_segsz;
478 if (unlikely(tso_segsz == 0)) {
479 txq->stats.oerrors++;
482 if (is_tunneled && txq->tunnel_en) {
483 tso_header_sz += buf->outer_l2_len +
485 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
487 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
489 if (unlikely(tso_header_sz >
490 MLX5_MAX_TSO_HEADER)) {
491 txq->stats.oerrors++;
494 copy_b = tso_header_sz - pkt_inline_sz;
495 /* First seg must contain all headers. */
496 assert(copy_b <= length);
498 ((end - (uintptr_t)raw) > copy_b)) {
499 uint16_t n = (MLX5_WQE_DS(copy_b) -
502 if (unlikely(max_wqe < n))
505 rte_memcpy((void *)raw,
506 (void *)addr, copy_b);
509 /* Include padding for TSO header. */
510 copy_b = MLX5_WQE_DS(copy_b) *
512 pkt_inline_sz += copy_b;
516 wqe->ctrl = (rte_v128u32_t){
525 #ifdef MLX5_PMD_SOFT_COUNTERS
533 /* Inline if enough room. */
534 if (max_inline || tso) {
536 uintptr_t end = (uintptr_t)
537 (((uintptr_t)txq->wqes) +
538 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
539 unsigned int inline_room = max_inline *
540 RTE_CACHE_LINE_SIZE -
541 (pkt_inline_sz - 2) -
543 uintptr_t addr_end = (addr + inline_room) &
544 ~(RTE_CACHE_LINE_SIZE - 1);
545 unsigned int copy_b = (addr_end > addr) ?
546 RTE_MIN((addr_end - addr), length) :
549 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
551 * One Dseg remains in the current WQE. To
552 * keep the computation positive, it is
553 * removed after the bytes to Dseg conversion.
555 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
557 if (unlikely(max_wqe < n))
561 inl = rte_cpu_to_be_32(copy_b |
563 rte_memcpy((void *)raw,
564 (void *)&inl, sizeof(inl));
566 pkt_inline_sz += sizeof(inl);
568 rte_memcpy((void *)raw, (void *)addr, copy_b);
571 pkt_inline_sz += copy_b;
574 * 2 DWORDs consumed by the WQE header + ETH segment +
575 * the size of the inline part of the packet.
577 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
579 if (ds % (MLX5_WQE_SIZE /
580 MLX5_WQE_DWORD_SIZE) == 0) {
581 if (unlikely(--max_wqe == 0))
583 dseg = (volatile rte_v128u32_t *)
584 tx_mlx5_wqe(txq, txq->wqe_ci +
587 dseg = (volatile rte_v128u32_t *)
589 (ds * MLX5_WQE_DWORD_SIZE));
592 } else if (!segs_n) {
595 /* dseg will be advance as part of next_seg */
596 dseg = (volatile rte_v128u32_t *)
598 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
603 * No inline has been done in the packet, only the
604 * Ethernet Header as been stored.
606 dseg = (volatile rte_v128u32_t *)
607 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
610 /* Add the remaining packet as a simple ds. */
611 addr = rte_cpu_to_be_64(addr);
612 *dseg = (rte_v128u32_t){
613 rte_cpu_to_be_32(length),
614 mlx5_tx_mb2mr(txq, buf),
627 * Spill on next WQE when the current one does not have
628 * enough room left. Size of WQE must a be a multiple
629 * of data segment size.
631 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
632 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
633 if (unlikely(--max_wqe == 0))
635 dseg = (volatile rte_v128u32_t *)
636 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
637 rte_prefetch0(tx_mlx5_wqe(txq,
638 txq->wqe_ci + ds / 4 + 1));
645 length = DATA_LEN(buf);
646 #ifdef MLX5_PMD_SOFT_COUNTERS
647 total_length += length;
649 /* Store segment information. */
650 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
651 *dseg = (rte_v128u32_t){
652 rte_cpu_to_be_32(length),
653 mlx5_tx_mb2mr(txq, buf),
657 (*txq->elts)[++elts_head & elts_m] = buf;
659 /* Advance counter only if all segs are successfully posted. */
665 if (ds > MLX5_DSEG_MAX) {
666 txq->stats.oerrors++;
672 /* Initialize known and common part of the WQE structure. */
674 wqe->ctrl = (rte_v128u32_t){
675 rte_cpu_to_be_32((txq->wqe_ci << 8) |
677 rte_cpu_to_be_32(txq->qp_num_8s | ds),
681 wqe->eseg = (rte_v128u32_t){
683 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
685 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
688 wqe->ctrl = (rte_v128u32_t){
689 rte_cpu_to_be_32((txq->wqe_ci << 8) |
691 rte_cpu_to_be_32(txq->qp_num_8s | ds),
695 wqe->eseg = (rte_v128u32_t){
699 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
703 txq->wqe_ci += (ds + 3) / 4;
704 /* Save the last successful WQE for completion request */
705 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
706 #ifdef MLX5_PMD_SOFT_COUNTERS
707 /* Increment sent bytes counter. */
708 txq->stats.obytes += total_length;
710 } while (i < pkts_n);
711 /* Take a shortcut if nothing must be sent. */
712 if (unlikely((i + k) == 0))
714 txq->elts_head += (i + j);
715 /* Check whether completion threshold has been reached. */
716 comp = txq->elts_comp + i + j + k;
717 if (comp >= MLX5_TX_COMP_THRESH) {
718 /* Request completion on last WQE. */
719 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
720 /* Save elts_head in unused "immediate" field of WQE. */
721 last_wqe->ctrl3 = txq->elts_head;
724 txq->elts_comp = comp;
726 #ifdef MLX5_PMD_SOFT_COUNTERS
727 /* Increment sent packets counter. */
728 txq->stats.opackets += i;
730 /* Ring QP doorbell. */
731 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
736 * Open a MPW session.
739 * Pointer to TX queue structure.
741 * Pointer to MPW session structure.
746 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
748 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
749 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
750 (volatile struct mlx5_wqe_data_seg (*)[])
751 tx_mlx5_wqe(txq, idx + 1);
753 mpw->state = MLX5_MPW_STATE_OPENED;
757 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
758 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
759 mpw->wqe->eseg.inline_hdr_sz = 0;
760 mpw->wqe->eseg.rsvd0 = 0;
761 mpw->wqe->eseg.rsvd1 = 0;
762 mpw->wqe->eseg.rsvd2 = 0;
763 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
766 mpw->wqe->ctrl[2] = 0;
767 mpw->wqe->ctrl[3] = 0;
768 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
769 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
770 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
771 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
772 mpw->data.dseg[2] = &(*dseg)[0];
773 mpw->data.dseg[3] = &(*dseg)[1];
774 mpw->data.dseg[4] = &(*dseg)[2];
778 * Close a MPW session.
781 * Pointer to TX queue structure.
783 * Pointer to MPW session structure.
786 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
788 unsigned int num = mpw->pkts_n;
791 * Store size in multiple of 16 bytes. Control and Ethernet segments
794 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
795 mpw->state = MLX5_MPW_STATE_CLOSED;
800 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
801 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
805 * DPDK callback for TX with MPW support.
808 * Generic pointer to TX queue structure.
810 * Packets to transmit.
812 * Number of packets in array.
815 * Number of packets successfully transmitted (<= pkts_n).
818 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
820 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
821 uint16_t elts_head = txq->elts_head;
822 const uint16_t elts_n = 1 << txq->elts_n;
823 const uint16_t elts_m = elts_n - 1;
829 struct mlx5_mpw mpw = {
830 .state = MLX5_MPW_STATE_CLOSED,
833 if (unlikely(!pkts_n))
835 /* Prefetch first packet cacheline. */
836 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
837 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
838 /* Start processing. */
839 mlx5_tx_complete(txq);
840 max_elts = (elts_n - (elts_head - txq->elts_tail));
841 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
842 if (unlikely(!max_wqe))
845 struct rte_mbuf *buf = *(pkts++);
847 unsigned int segs_n = buf->nb_segs;
848 uint32_t cs_flags = 0;
851 * Make sure there is enough room to store this packet and
852 * that one ring entry remains unused.
855 if (max_elts < segs_n)
857 /* Do not bother with large packets MPW cannot handle. */
858 if (segs_n > MLX5_MPW_DSEG_MAX) {
859 txq->stats.oerrors++;
864 /* Should we enable HW CKSUM offload */
866 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
867 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
868 /* Retrieve packet information. */
869 length = PKT_LEN(buf);
871 /* Start new session if packet differs. */
872 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
873 ((mpw.len != length) ||
875 (mpw.wqe->eseg.cs_flags != cs_flags)))
876 mlx5_mpw_close(txq, &mpw);
877 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
879 * Multi-Packet WQE consumes at most two WQE.
880 * mlx5_mpw_new() expects to be able to use such
883 if (unlikely(max_wqe < 2))
886 mlx5_mpw_new(txq, &mpw, length);
887 mpw.wqe->eseg.cs_flags = cs_flags;
889 /* Multi-segment packets must be alone in their MPW. */
890 assert((segs_n == 1) || (mpw.pkts_n == 0));
891 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
895 volatile struct mlx5_wqe_data_seg *dseg;
899 (*txq->elts)[elts_head++ & elts_m] = buf;
900 dseg = mpw.data.dseg[mpw.pkts_n];
901 addr = rte_pktmbuf_mtod(buf, uintptr_t);
902 *dseg = (struct mlx5_wqe_data_seg){
903 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
904 .lkey = mlx5_tx_mb2mr(txq, buf),
905 .addr = rte_cpu_to_be_64(addr),
907 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
908 length += DATA_LEN(buf);
914 assert(length == mpw.len);
915 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
916 mlx5_mpw_close(txq, &mpw);
917 #ifdef MLX5_PMD_SOFT_COUNTERS
918 /* Increment sent bytes counter. */
919 txq->stats.obytes += length;
923 /* Take a shortcut if nothing must be sent. */
924 if (unlikely(i == 0))
926 /* Check whether completion threshold has been reached. */
927 /* "j" includes both packets and segments. */
928 comp = txq->elts_comp + j;
929 if (comp >= MLX5_TX_COMP_THRESH) {
930 volatile struct mlx5_wqe *wqe = mpw.wqe;
932 /* Request completion on last WQE. */
933 wqe->ctrl[2] = rte_cpu_to_be_32(8);
934 /* Save elts_head in unused "immediate" field of WQE. */
935 wqe->ctrl[3] = elts_head;
938 txq->elts_comp = comp;
940 #ifdef MLX5_PMD_SOFT_COUNTERS
941 /* Increment sent packets counter. */
942 txq->stats.opackets += i;
944 /* Ring QP doorbell. */
945 if (mpw.state == MLX5_MPW_STATE_OPENED)
946 mlx5_mpw_close(txq, &mpw);
947 mlx5_tx_dbrec(txq, mpw.wqe);
948 txq->elts_head = elts_head;
953 * Open a MPW inline session.
956 * Pointer to TX queue structure.
958 * Pointer to MPW session structure.
963 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
966 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
967 struct mlx5_wqe_inl_small *inl;
969 mpw->state = MLX5_MPW_INL_STATE_OPENED;
973 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
974 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
977 mpw->wqe->ctrl[2] = 0;
978 mpw->wqe->ctrl[3] = 0;
979 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
980 mpw->wqe->eseg.inline_hdr_sz = 0;
981 mpw->wqe->eseg.cs_flags = 0;
982 mpw->wqe->eseg.rsvd0 = 0;
983 mpw->wqe->eseg.rsvd1 = 0;
984 mpw->wqe->eseg.rsvd2 = 0;
985 inl = (struct mlx5_wqe_inl_small *)
986 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
987 mpw->data.raw = (uint8_t *)&inl->raw;
991 * Close a MPW inline session.
994 * Pointer to TX queue structure.
996 * Pointer to MPW session structure.
999 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1002 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1003 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1005 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1007 * Store size in multiple of 16 bytes. Control and Ethernet segments
1010 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1012 mpw->state = MLX5_MPW_STATE_CLOSED;
1013 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1014 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1018 * DPDK callback for TX with MPW inline support.
1021 * Generic pointer to TX queue structure.
1023 * Packets to transmit.
1025 * Number of packets in array.
1028 * Number of packets successfully transmitted (<= pkts_n).
1031 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1034 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1035 uint16_t elts_head = txq->elts_head;
1036 const uint16_t elts_n = 1 << txq->elts_n;
1037 const uint16_t elts_m = elts_n - 1;
1043 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1044 struct mlx5_mpw mpw = {
1045 .state = MLX5_MPW_STATE_CLOSED,
1048 * Compute the maximum number of WQE which can be consumed by inline
1051 * - 1 control segment,
1052 * - 1 Ethernet segment,
1053 * - N Dseg from the inline request.
1055 const unsigned int wqe_inl_n =
1056 ((2 * MLX5_WQE_DWORD_SIZE +
1057 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1058 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1060 if (unlikely(!pkts_n))
1062 /* Prefetch first packet cacheline. */
1063 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1064 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1065 /* Start processing. */
1066 mlx5_tx_complete(txq);
1067 max_elts = (elts_n - (elts_head - txq->elts_tail));
1069 struct rte_mbuf *buf = *(pkts++);
1072 unsigned int segs_n = buf->nb_segs;
1073 uint32_t cs_flags = 0;
1076 * Make sure there is enough room to store this packet and
1077 * that one ring entry remains unused.
1080 if (max_elts < segs_n)
1082 /* Do not bother with large packets MPW cannot handle. */
1083 if (segs_n > MLX5_MPW_DSEG_MAX) {
1084 txq->stats.oerrors++;
1090 * Compute max_wqe in case less WQE were consumed in previous
1093 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1094 /* Should we enable HW CKSUM offload */
1096 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1097 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1098 /* Retrieve packet information. */
1099 length = PKT_LEN(buf);
1100 /* Start new session if packet differs. */
1101 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1102 if ((mpw.len != length) ||
1104 (mpw.wqe->eseg.cs_flags != cs_flags))
1105 mlx5_mpw_close(txq, &mpw);
1106 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1107 if ((mpw.len != length) ||
1109 (length > inline_room) ||
1110 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1111 mlx5_mpw_inline_close(txq, &mpw);
1113 txq->max_inline * RTE_CACHE_LINE_SIZE;
1116 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1117 if ((segs_n != 1) ||
1118 (length > inline_room)) {
1120 * Multi-Packet WQE consumes at most two WQE.
1121 * mlx5_mpw_new() expects to be able to use
1124 if (unlikely(max_wqe < 2))
1127 mlx5_mpw_new(txq, &mpw, length);
1128 mpw.wqe->eseg.cs_flags = cs_flags;
1130 if (unlikely(max_wqe < wqe_inl_n))
1132 max_wqe -= wqe_inl_n;
1133 mlx5_mpw_inline_new(txq, &mpw, length);
1134 mpw.wqe->eseg.cs_flags = cs_flags;
1137 /* Multi-segment packets must be alone in their MPW. */
1138 assert((segs_n == 1) || (mpw.pkts_n == 0));
1139 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1140 assert(inline_room ==
1141 txq->max_inline * RTE_CACHE_LINE_SIZE);
1142 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1146 volatile struct mlx5_wqe_data_seg *dseg;
1149 (*txq->elts)[elts_head++ & elts_m] = buf;
1150 dseg = mpw.data.dseg[mpw.pkts_n];
1151 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1152 *dseg = (struct mlx5_wqe_data_seg){
1154 rte_cpu_to_be_32(DATA_LEN(buf)),
1155 .lkey = mlx5_tx_mb2mr(txq, buf),
1156 .addr = rte_cpu_to_be_64(addr),
1158 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1159 length += DATA_LEN(buf);
1165 assert(length == mpw.len);
1166 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1167 mlx5_mpw_close(txq, &mpw);
1171 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1172 assert(length <= inline_room);
1173 assert(length == DATA_LEN(buf));
1174 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1175 (*txq->elts)[elts_head++ & elts_m] = buf;
1176 /* Maximum number of bytes before wrapping. */
1177 max = ((((uintptr_t)(txq->wqes)) +
1180 (uintptr_t)mpw.data.raw);
1182 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1185 mpw.data.raw = (volatile void *)txq->wqes;
1186 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1187 (void *)(addr + max),
1189 mpw.data.raw += length - max;
1191 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1197 (volatile void *)txq->wqes;
1199 mpw.data.raw += length;
1202 mpw.total_len += length;
1204 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1205 mlx5_mpw_inline_close(txq, &mpw);
1207 txq->max_inline * RTE_CACHE_LINE_SIZE;
1209 inline_room -= length;
1212 #ifdef MLX5_PMD_SOFT_COUNTERS
1213 /* Increment sent bytes counter. */
1214 txq->stats.obytes += length;
1218 /* Take a shortcut if nothing must be sent. */
1219 if (unlikely(i == 0))
1221 /* Check whether completion threshold has been reached. */
1222 /* "j" includes both packets and segments. */
1223 comp = txq->elts_comp + j;
1224 if (comp >= MLX5_TX_COMP_THRESH) {
1225 volatile struct mlx5_wqe *wqe = mpw.wqe;
1227 /* Request completion on last WQE. */
1228 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1229 /* Save elts_head in unused "immediate" field of WQE. */
1230 wqe->ctrl[3] = elts_head;
1233 txq->elts_comp = comp;
1235 #ifdef MLX5_PMD_SOFT_COUNTERS
1236 /* Increment sent packets counter. */
1237 txq->stats.opackets += i;
1239 /* Ring QP doorbell. */
1240 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1241 mlx5_mpw_inline_close(txq, &mpw);
1242 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1243 mlx5_mpw_close(txq, &mpw);
1244 mlx5_tx_dbrec(txq, mpw.wqe);
1245 txq->elts_head = elts_head;
1250 * Open an Enhanced MPW session.
1253 * Pointer to TX queue structure.
1255 * Pointer to MPW session structure.
1260 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1262 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1264 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1266 mpw->total_len = sizeof(struct mlx5_wqe);
1267 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1269 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1270 (txq->wqe_ci << 8) |
1271 MLX5_OPCODE_ENHANCED_MPSW);
1272 mpw->wqe->ctrl[2] = 0;
1273 mpw->wqe->ctrl[3] = 0;
1274 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1275 if (unlikely(padding)) {
1276 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1278 /* Pad the first 2 DWORDs with zero-length inline header. */
1279 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1280 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1281 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1282 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1283 /* Start from the next WQEBB. */
1284 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1286 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1291 * Close an Enhanced MPW session.
1294 * Pointer to TX queue structure.
1296 * Pointer to MPW session structure.
1299 * Number of consumed WQEs.
1301 static inline uint16_t
1302 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1306 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1309 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1310 MLX5_WQE_DS(mpw->total_len));
1311 mpw->state = MLX5_MPW_STATE_CLOSED;
1312 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1318 * DPDK callback for TX with Enhanced MPW support.
1321 * Generic pointer to TX queue structure.
1323 * Packets to transmit.
1325 * Number of packets in array.
1328 * Number of packets successfully transmitted (<= pkts_n).
1331 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1333 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1334 uint16_t elts_head = txq->elts_head;
1335 const uint16_t elts_n = 1 << txq->elts_n;
1336 const uint16_t elts_m = elts_n - 1;
1341 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1342 unsigned int mpw_room = 0;
1343 unsigned int inl_pad = 0;
1345 struct mlx5_mpw mpw = {
1346 .state = MLX5_MPW_STATE_CLOSED,
1349 if (unlikely(!pkts_n))
1351 /* Start processing. */
1352 mlx5_tx_complete(txq);
1353 max_elts = (elts_n - (elts_head - txq->elts_tail));
1354 /* A CQE slot must always be available. */
1355 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1356 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1357 if (unlikely(!max_wqe))
1360 struct rte_mbuf *buf = *(pkts++);
1363 unsigned int do_inline = 0; /* Whether inline is possible. */
1365 unsigned int segs_n = buf->nb_segs;
1366 uint32_t cs_flags = 0;
1369 * Make sure there is enough room to store this packet and
1370 * that one ring entry remains unused.
1373 if (max_elts - j < segs_n)
1375 /* Do not bother with large packets MPW cannot handle. */
1376 if (segs_n > MLX5_MPW_DSEG_MAX) {
1377 txq->stats.oerrors++;
1380 /* Should we enable HW CKSUM offload. */
1382 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1383 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1384 /* Retrieve packet information. */
1385 length = PKT_LEN(buf);
1386 /* Start new session if:
1387 * - multi-segment packet
1388 * - no space left even for a dseg
1389 * - next packet can be inlined with a new WQE
1391 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1394 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1395 if ((segs_n != 1) ||
1396 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1398 (length <= txq->inline_max_packet_sz &&
1399 inl_pad + sizeof(inl_hdr) + length >
1401 (mpw.wqe->eseg.cs_flags != cs_flags))
1402 max_wqe -= mlx5_empw_close(txq, &mpw);
1404 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1405 if (unlikely(segs_n != 1)) {
1406 /* Fall back to legacy MPW.
1407 * A MPW session consumes 2 WQEs at most to
1408 * include MLX5_MPW_DSEG_MAX pointers.
1410 if (unlikely(max_wqe < 2))
1412 mlx5_mpw_new(txq, &mpw, length);
1414 /* In Enhanced MPW, inline as much as the budget
1415 * is allowed. The remaining space is to be
1416 * filled with dsegs. If the title WQEBB isn't
1417 * padded, it will have 2 dsegs there.
1419 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1420 (max_inline ? max_inline :
1421 pkts_n * MLX5_WQE_DWORD_SIZE) +
1423 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1426 /* Don't pad the title WQEBB to not waste WQ. */
1427 mlx5_empw_new(txq, &mpw, 0);
1428 mpw_room -= mpw.total_len;
1431 length <= txq->inline_max_packet_sz &&
1432 sizeof(inl_hdr) + length <= mpw_room &&
1435 mpw.wqe->eseg.cs_flags = cs_flags;
1437 /* Evaluate whether the next packet can be inlined.
1438 * Inlininig is possible when:
1439 * - length is less than configured value
1440 * - length fits for remaining space
1441 * - not required to fill the title WQEBB with dsegs
1444 length <= txq->inline_max_packet_sz &&
1445 inl_pad + sizeof(inl_hdr) + length <=
1447 (!txq->mpw_hdr_dseg ||
1448 mpw.total_len >= MLX5_WQE_SIZE);
1450 /* Multi-segment packets must be alone in their MPW. */
1451 assert((segs_n == 1) || (mpw.pkts_n == 0));
1452 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1453 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1457 volatile struct mlx5_wqe_data_seg *dseg;
1460 (*txq->elts)[elts_head++ & elts_m] = buf;
1461 dseg = mpw.data.dseg[mpw.pkts_n];
1462 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1463 *dseg = (struct mlx5_wqe_data_seg){
1464 .byte_count = rte_cpu_to_be_32(
1466 .lkey = mlx5_tx_mb2mr(txq, buf),
1467 .addr = rte_cpu_to_be_64(addr),
1469 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1470 length += DATA_LEN(buf);
1476 /* A multi-segmented packet takes one MPW session.
1477 * TODO: Pack more multi-segmented packets if possible.
1479 mlx5_mpw_close(txq, &mpw);
1484 } else if (do_inline) {
1485 /* Inline packet into WQE. */
1488 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1489 assert(length == DATA_LEN(buf));
1490 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1491 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1492 mpw.data.raw = (volatile void *)
1493 ((uintptr_t)mpw.data.raw + inl_pad);
1494 max = tx_mlx5_wq_tailroom(txq,
1495 (void *)(uintptr_t)mpw.data.raw);
1496 /* Copy inline header. */
1497 mpw.data.raw = (volatile void *)
1499 (void *)(uintptr_t)mpw.data.raw,
1502 (void *)(uintptr_t)txq->wqes,
1504 max = tx_mlx5_wq_tailroom(txq,
1505 (void *)(uintptr_t)mpw.data.raw);
1506 /* Copy packet data. */
1507 mpw.data.raw = (volatile void *)
1509 (void *)(uintptr_t)mpw.data.raw,
1512 (void *)(uintptr_t)txq->wqes,
1515 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1516 /* No need to get completion as the entire packet is
1517 * copied to WQ. Free the buf right away.
1519 rte_pktmbuf_free_seg(buf);
1520 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1521 /* Add pad in the next packet if any. */
1522 inl_pad = (((uintptr_t)mpw.data.raw +
1523 (MLX5_WQE_DWORD_SIZE - 1)) &
1524 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1525 (uintptr_t)mpw.data.raw;
1527 /* No inline. Load a dseg of packet pointer. */
1528 volatile rte_v128u32_t *dseg;
1530 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1531 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1532 assert(length == DATA_LEN(buf));
1533 if (!tx_mlx5_wq_tailroom(txq,
1534 (void *)((uintptr_t)mpw.data.raw
1536 dseg = (volatile void *)txq->wqes;
1538 dseg = (volatile void *)
1539 ((uintptr_t)mpw.data.raw +
1541 (*txq->elts)[elts_head++ & elts_m] = buf;
1542 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1543 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1544 rte_prefetch2((void *)(addr +
1545 n * RTE_CACHE_LINE_SIZE));
1546 addr = rte_cpu_to_be_64(addr);
1547 *dseg = (rte_v128u32_t) {
1548 rte_cpu_to_be_32(length),
1549 mlx5_tx_mb2mr(txq, buf),
1553 mpw.data.raw = (volatile void *)(dseg + 1);
1554 mpw.total_len += (inl_pad + sizeof(*dseg));
1557 mpw_room -= (inl_pad + sizeof(*dseg));
1560 #ifdef MLX5_PMD_SOFT_COUNTERS
1561 /* Increment sent bytes counter. */
1562 txq->stats.obytes += length;
1565 } while (i < pkts_n);
1566 /* Take a shortcut if nothing must be sent. */
1567 if (unlikely(i == 0))
1569 /* Check whether completion threshold has been reached. */
1570 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1571 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1572 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1573 volatile struct mlx5_wqe *wqe = mpw.wqe;
1575 /* Request completion on last WQE. */
1576 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1577 /* Save elts_head in unused "immediate" field of WQE. */
1578 wqe->ctrl[3] = elts_head;
1580 txq->mpw_comp = txq->wqe_ci;
1583 txq->elts_comp += j;
1585 #ifdef MLX5_PMD_SOFT_COUNTERS
1586 /* Increment sent packets counter. */
1587 txq->stats.opackets += i;
1589 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1590 mlx5_empw_close(txq, &mpw);
1591 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1592 mlx5_mpw_close(txq, &mpw);
1593 /* Ring QP doorbell. */
1594 mlx5_tx_dbrec(txq, mpw.wqe);
1595 txq->elts_head = elts_head;
1600 * Translate RX completion flags to packet type.
1605 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1608 * Packet type for struct rte_mbuf.
1610 static inline uint32_t
1611 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1614 uint8_t pinfo = cqe->pkt_info;
1615 uint16_t ptype = cqe->hdr_type_etc;
1618 * The index to the array should have:
1619 * bit[1:0] = l3_hdr_type
1620 * bit[4:2] = l4_hdr_type
1623 * bit[7] = outer_l3_type
1625 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1626 return mlx5_ptype_table[idx];
1630 * Get size of the next packet for a given CQE. For compressed CQEs, the
1631 * consumer index is updated only once all packets of the current one have
1635 * Pointer to RX queue.
1638 * @param[out] rss_hash
1639 * Packet RSS Hash result.
1642 * Packet size in bytes (0 if there is none), -1 in case of completion
1646 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1647 uint16_t cqe_cnt, uint32_t *rss_hash)
1649 struct rxq_zip *zip = &rxq->zip;
1650 uint16_t cqe_n = cqe_cnt + 1;
1654 /* Process compressed data in the CQE and mini arrays. */
1656 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1657 (volatile struct mlx5_mini_cqe8 (*)[8])
1658 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1660 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1661 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1662 if ((++zip->ai & 7) == 0) {
1663 /* Invalidate consumed CQEs */
1666 while (idx != end) {
1667 (*rxq->cqes)[idx & cqe_cnt].op_own =
1668 MLX5_CQE_INVALIDATE;
1672 * Increment consumer index to skip the number of
1673 * CQEs consumed. Hardware leaves holes in the CQ
1674 * ring for software use.
1679 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1680 /* Invalidate the rest */
1684 while (idx != end) {
1685 (*rxq->cqes)[idx & cqe_cnt].op_own =
1686 MLX5_CQE_INVALIDATE;
1689 rxq->cq_ci = zip->cq_ci;
1692 /* No compressed data, get next CQE and verify if it is compressed. */
1697 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1698 if (unlikely(ret == 1))
1701 op_own = cqe->op_own;
1702 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1703 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1704 (volatile struct mlx5_mini_cqe8 (*)[8])
1705 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1708 /* Fix endianness. */
1709 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1711 * Current mini array position is the one returned by
1714 * If completion comprises several mini arrays, as a
1715 * special case the second one is located 7 CQEs after
1716 * the initial CQE instead of 8 for subsequent ones.
1718 zip->ca = rxq->cq_ci;
1719 zip->na = zip->ca + 7;
1720 /* Compute the next non compressed CQE. */
1722 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1723 /* Get packet size to return. */
1724 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1725 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1727 /* Prefetch all the entries to be invalidated */
1730 while (idx != end) {
1731 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1735 len = rte_be_to_cpu_32(cqe->byte_cnt);
1736 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1738 /* Error while receiving packet. */
1739 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1746 * Translate RX completion flags to offload flags.
1749 * Pointer to RX queue structure.
1754 * Offload flags (ol_flags) for struct rte_mbuf.
1756 static inline uint32_t
1757 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1759 uint32_t ol_flags = 0;
1760 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1764 MLX5_CQE_RX_L3_HDR_VALID,
1765 PKT_RX_IP_CKSUM_GOOD) |
1767 MLX5_CQE_RX_L4_HDR_VALID,
1768 PKT_RX_L4_CKSUM_GOOD);
1769 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1772 MLX5_CQE_RX_L3_HDR_VALID,
1773 PKT_RX_IP_CKSUM_GOOD) |
1775 MLX5_CQE_RX_L4_HDR_VALID,
1776 PKT_RX_L4_CKSUM_GOOD);
1781 * DPDK callback for RX.
1784 * Generic pointer to RX queue structure.
1786 * Array to store received packets.
1788 * Maximum number of packets in array.
1791 * Number of packets successfully received (<= pkts_n).
1794 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1796 struct mlx5_rxq_data *rxq = dpdk_rxq;
1797 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1798 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1799 const unsigned int sges_n = rxq->sges_n;
1800 struct rte_mbuf *pkt = NULL;
1801 struct rte_mbuf *seg = NULL;
1802 volatile struct mlx5_cqe *cqe =
1803 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1805 unsigned int rq_ci = rxq->rq_ci << sges_n;
1806 int len = 0; /* keep its value across iterations. */
1809 unsigned int idx = rq_ci & wqe_cnt;
1810 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1811 struct rte_mbuf *rep = (*rxq->elts)[idx];
1812 uint32_t rss_hash_res = 0;
1820 rep = rte_mbuf_raw_alloc(rxq->mp);
1821 if (unlikely(rep == NULL)) {
1822 ++rxq->stats.rx_nombuf;
1825 * no buffers before we even started,
1826 * bail out silently.
1830 while (pkt != seg) {
1831 assert(pkt != (*rxq->elts)[idx]);
1835 rte_mbuf_raw_free(pkt);
1841 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1842 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1845 rte_mbuf_raw_free(rep);
1848 if (unlikely(len == -1)) {
1849 /* RX error, packet is likely too large. */
1850 rte_mbuf_raw_free(rep);
1851 ++rxq->stats.idropped;
1855 assert(len >= (rxq->crc_present << 2));
1856 /* Update packet information. */
1857 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1859 if (rss_hash_res && rxq->rss_hash) {
1860 pkt->hash.rss = rss_hash_res;
1861 pkt->ol_flags = PKT_RX_RSS_HASH;
1864 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1865 pkt->ol_flags |= PKT_RX_FDIR;
1866 if (cqe->sop_drop_qpn !=
1867 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1868 uint32_t mark = cqe->sop_drop_qpn;
1870 pkt->ol_flags |= PKT_RX_FDIR_ID;
1872 mlx5_flow_mark_get(mark);
1875 if (rxq->csum | rxq->csum_l2tun)
1876 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1877 if (rxq->vlan_strip &&
1878 (cqe->hdr_type_etc &
1879 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1880 pkt->ol_flags |= PKT_RX_VLAN |
1881 PKT_RX_VLAN_STRIPPED;
1883 rte_be_to_cpu_16(cqe->vlan_info);
1885 if (rxq->hw_timestamp) {
1887 rte_be_to_cpu_64(cqe->timestamp);
1888 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1890 if (rxq->crc_present)
1891 len -= ETHER_CRC_LEN;
1894 DATA_LEN(rep) = DATA_LEN(seg);
1895 PKT_LEN(rep) = PKT_LEN(seg);
1896 SET_DATA_OFF(rep, DATA_OFF(seg));
1897 PORT(rep) = PORT(seg);
1898 (*rxq->elts)[idx] = rep;
1900 * Fill NIC descriptor with the new buffer. The lkey and size
1901 * of the buffers are already known, only the buffer address
1904 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1905 if (len > DATA_LEN(seg)) {
1906 len -= DATA_LEN(seg);
1911 DATA_LEN(seg) = len;
1912 #ifdef MLX5_PMD_SOFT_COUNTERS
1913 /* Increment bytes counter. */
1914 rxq->stats.ibytes += PKT_LEN(pkt);
1916 /* Return packet. */
1922 /* Align consumer index to the next stride. */
1927 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1929 /* Update the consumer index. */
1930 rxq->rq_ci = rq_ci >> sges_n;
1932 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1934 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1935 #ifdef MLX5_PMD_SOFT_COUNTERS
1936 /* Increment packets counter. */
1937 rxq->stats.ipackets += i;
1943 * Dummy DPDK callback for TX.
1945 * This function is used to temporarily replace the real callback during
1946 * unsafe control operations on the queue, or in case of error.
1949 * Generic pointer to TX queue structure.
1951 * Packets to transmit.
1953 * Number of packets in array.
1956 * Number of packets successfully transmitted (<= pkts_n).
1959 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1968 * Dummy DPDK callback for RX.
1970 * This function is used to temporarily replace the real callback during
1971 * unsafe control operations on the queue, or in case of error.
1974 * Generic pointer to RX queue structure.
1976 * Array to store received packets.
1978 * Maximum number of packets in array.
1981 * Number of packets successfully received (<= pkts_n).
1984 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1993 * Vectorized Rx/Tx routines are not compiled in when required vector
1994 * instructions are not supported on a target architecture. The following null
1995 * stubs are needed for linkage when those are not included outside of this file
1996 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1999 uint16_t __attribute__((weak))
2000 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2008 uint16_t __attribute__((weak))
2009 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
2017 uint16_t __attribute__((weak))
2018 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2026 int __attribute__((weak))
2027 priv_check_raw_vec_tx_support(struct priv *priv)
2033 int __attribute__((weak))
2034 priv_check_vec_tx_support(struct priv *priv)
2040 int __attribute__((weak))
2041 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2047 int __attribute__((weak))
2048 priv_check_vec_rx_support(struct priv *priv)