1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
29 /* TX burst subroutines return codes. */
30 enum mlx5_txcmp_code {
31 MLX5_TXCMP_CODE_EXIT = 0,
32 MLX5_TXCMP_CODE_ERROR,
33 MLX5_TXCMP_CODE_SINGLE,
34 MLX5_TXCMP_CODE_MULTI,
40 * These defines are used to configure Tx burst routine option set
41 * supported at compile time. The not specified options are optimized out
42 * out due to if conditions can be explicitly calculated at compile time.
43 * The offloads with bigger runtime check (require more CPU cycles to
44 * skip) overhead should have the bigger index - this is needed to
45 * select the better matching routine function if no exact match and
46 * some offloads are not actually requested.
48 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
49 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
50 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
51 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
52 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
53 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
54 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
55 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
56 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
59 /* The most common offloads groups. */
60 #define MLX5_TXOFF_CONFIG_NONE 0
61 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
62 MLX5_TXOFF_CONFIG_TSO | \
63 MLX5_TXOFF_CONFIG_SWP | \
64 MLX5_TXOFF_CONFIG_CSUM | \
65 MLX5_TXOFF_CONFIG_INLINE | \
66 MLX5_TXOFF_CONFIG_VLAN | \
67 MLX5_TXOFF_CONFIG_METADATA)
69 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
71 #define MLX5_TXOFF_DECL(func, olx) \
72 static uint16_t mlx5_tx_burst_##func(void *txq, \
73 struct rte_mbuf **pkts, \
76 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
77 pkts, pkts_n, (olx)); \
80 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
83 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
84 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
85 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
87 sizeof(rte_v128u32_t)),
88 "invalid Ethernet Segment data size");
89 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
91 sizeof(struct rte_vlan_hdr) +
92 2 * RTE_ETHER_ADDR_LEN),
93 "invalid Ethernet Segment data size");
94 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
96 sizeof(rte_v128u32_t)),
97 "invalid Ethernet Segment data size");
98 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
100 sizeof(struct rte_vlan_hdr) +
101 2 * RTE_ETHER_ADDR_LEN),
102 "invalid Ethernet Segment data size");
103 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
105 sizeof(rte_v128u32_t)),
106 "invalid Ethernet Segment data size");
107 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
109 sizeof(struct rte_vlan_hdr) +
110 2 * RTE_ETHER_ADDR_LEN),
111 "invalid Ethernet Segment data size");
112 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
113 (2 * RTE_ETHER_ADDR_LEN),
114 "invalid Data Segment data size");
115 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
116 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
117 static_assert((sizeof(struct rte_vlan_hdr) +
118 sizeof(struct rte_ether_hdr)) ==
119 MLX5_ESEG_MIN_INLINE_SIZE,
120 "invalid min inline data size");
121 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
122 MLX5_DSEG_MAX, "invalid WQE max size");
123 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
124 "invalid WQE Control Segment size");
125 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
126 "invalid WQE Ethernet Segment size");
127 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
128 "invalid WQE Data Segment size");
129 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
132 static __rte_always_inline uint32_t
133 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
134 volatile struct mlx5_mini_cqe8 *mcqe);
136 static __rte_always_inline int
137 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
138 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
140 static __rte_always_inline uint32_t
141 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
143 static __rte_always_inline void
144 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
145 volatile struct mlx5_cqe *cqe,
146 volatile struct mlx5_mini_cqe8 *mcqe);
149 mlx5_queue_state_modify(struct rte_eth_dev *dev,
150 struct mlx5_mp_arg_queue_state_modify *sm);
153 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
154 volatile struct mlx5_cqe *__rte_restrict cqe,
155 uint32_t phcsum, uint8_t l4_type);
158 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
159 volatile struct mlx5_cqe *__rte_restrict cqe,
160 volatile struct mlx5_mini_cqe8 *mcqe,
161 struct mlx5_rxq_data *rxq, uint32_t len);
163 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
164 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
167 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
168 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
170 uint64_t rte_net_mlx5_dynf_inline_mask;
171 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
174 * Build a table to translate Rx completion flags to packet type.
176 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
179 mlx5_set_ptype_table(void)
182 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
184 /* Last entry must not be overwritten, reserved for errored packet. */
185 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
186 (*p)[i] = RTE_PTYPE_UNKNOWN;
188 * The index to the array should have:
189 * bit[1:0] = l3_hdr_type
190 * bit[4:2] = l4_hdr_type
193 * bit[7] = outer_l3_type
196 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
198 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
199 RTE_PTYPE_L4_NONFRAG;
200 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_L4_NONFRAG;
203 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
205 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
214 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
216 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
218 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
225 /* Repeat with outer_l3_type being set. Just in case. */
226 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_L4_NONFRAG;
228 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
229 RTE_PTYPE_L4_NONFRAG;
230 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
232 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
236 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
238 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
240 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
244 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
251 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
252 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L4_NONFRAG;
255 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L4_NONFRAG;
258 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
259 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_NONFRAG;
262 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_NONFRAG;
265 /* Tunneled - Fragmented */
266 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_FRAG;
269 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_FRAG;
272 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_FRAG;
275 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_FRAG;
279 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_TCP;
282 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
284 RTE_PTYPE_INNER_L4_TCP;
285 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
286 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
287 RTE_PTYPE_INNER_L4_TCP;
288 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
289 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
290 RTE_PTYPE_INNER_L4_TCP;
291 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
292 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
293 RTE_PTYPE_INNER_L4_TCP;
294 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
295 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
296 RTE_PTYPE_INNER_L4_TCP;
297 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
298 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
299 RTE_PTYPE_INNER_L4_TCP;
300 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
301 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
302 RTE_PTYPE_INNER_L4_TCP;
303 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
304 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
305 RTE_PTYPE_INNER_L4_TCP;
306 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
307 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
308 RTE_PTYPE_INNER_L4_TCP;
309 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
310 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
311 RTE_PTYPE_INNER_L4_TCP;
312 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
313 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
314 RTE_PTYPE_INNER_L4_TCP;
316 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
317 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
318 RTE_PTYPE_INNER_L4_UDP;
319 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
320 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
321 RTE_PTYPE_INNER_L4_UDP;
322 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
323 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
324 RTE_PTYPE_INNER_L4_UDP;
325 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
326 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
327 RTE_PTYPE_INNER_L4_UDP;
331 * Build a table to translate packet to checksum type of Verbs.
334 mlx5_set_cksum_table(void)
340 * The index should have:
341 * bit[0] = PKT_TX_TCP_SEG
342 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
343 * bit[4] = PKT_TX_IP_CKSUM
344 * bit[8] = PKT_TX_OUTER_IP_CKSUM
347 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
350 /* Tunneled packet. */
351 if (i & (1 << 8)) /* Outer IP. */
352 v |= MLX5_ETH_WQE_L3_CSUM;
353 if (i & (1 << 4)) /* Inner IP. */
354 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
355 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
356 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
359 if (i & (1 << 4)) /* IP. */
360 v |= MLX5_ETH_WQE_L3_CSUM;
361 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
362 v |= MLX5_ETH_WQE_L4_CSUM;
364 mlx5_cksum_table[i] = v;
369 * Build a table to translate packet type of mbuf to SWP type of Verbs.
372 mlx5_set_swp_types_table(void)
378 * The index should have:
379 * bit[0:1] = PKT_TX_L4_MASK
380 * bit[4] = PKT_TX_IPV6
381 * bit[8] = PKT_TX_OUTER_IPV6
382 * bit[9] = PKT_TX_OUTER_UDP
384 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
387 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
389 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
391 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
392 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
393 v |= MLX5_ETH_WQE_L4_INNER_UDP;
394 mlx5_swp_types_table[i] = v;
399 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
400 * Flags must be preliminary initialized to zero.
403 * Pointer to burst routine local context.
405 * Pointer to store Software Parser flags
407 * Configured Tx offloads mask. It is fully defined at
408 * compile time and may be used for optimization.
411 * Software Parser offsets packed in dword.
412 * Software Parser flags are set by pointer.
414 static __rte_always_inline uint32_t
415 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
420 unsigned int idx, off;
423 if (!MLX5_TXOFF_CONFIG(SWP))
425 ol = loc->mbuf->ol_flags;
426 tunnel = ol & PKT_TX_TUNNEL_MASK;
428 * Check whether Software Parser is required.
429 * Only customized tunnels may ask for.
431 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
434 * The index should have:
435 * bit[0:1] = PKT_TX_L4_MASK
436 * bit[4] = PKT_TX_IPV6
437 * bit[8] = PKT_TX_OUTER_IPV6
438 * bit[9] = PKT_TX_OUTER_UDP
440 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
441 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
442 *swp_flags = mlx5_swp_types_table[idx];
444 * Set offsets for SW parser. Since ConnectX-5, SW parser just
445 * complements HW parser. SW parser starts to engage only if HW parser
446 * can't reach a header. For the older devices, HW parser will not kick
447 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
448 * should be set regardless of HW offload.
450 off = loc->mbuf->outer_l2_len;
451 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
452 off += sizeof(struct rte_vlan_hdr);
453 set = (off >> 1) << 8; /* Outer L3 offset. */
454 off += loc->mbuf->outer_l3_len;
455 if (tunnel == PKT_TX_TUNNEL_UDP)
456 set |= off >> 1; /* Outer L4 offset. */
457 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
458 const uint64_t csum = ol & PKT_TX_L4_MASK;
459 off += loc->mbuf->l2_len;
460 set |= (off >> 1) << 24; /* Inner L3 offset. */
461 if (csum == PKT_TX_TCP_CKSUM ||
462 csum == PKT_TX_UDP_CKSUM ||
463 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
464 off += loc->mbuf->l3_len;
465 set |= (off >> 1) << 16; /* Inner L4 offset. */
468 set = rte_cpu_to_le_32(set);
473 * Convert the Checksum offloads to Verbs.
476 * Pointer to the mbuf.
479 * Converted checksum flags.
481 static __rte_always_inline uint8_t
482 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
485 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
486 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
487 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
490 * The index should have:
491 * bit[0] = PKT_TX_TCP_SEG
492 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
493 * bit[4] = PKT_TX_IP_CKSUM
494 * bit[8] = PKT_TX_OUTER_IP_CKSUM
497 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
498 return mlx5_cksum_table[idx];
502 * Internal function to compute the number of used descriptors in an RX queue
508 * The number of used rx descriptor.
511 rx_queue_count(struct mlx5_rxq_data *rxq)
513 struct rxq_zip *zip = &rxq->zip;
514 volatile struct mlx5_cqe *cqe;
515 const unsigned int cqe_n = (1 << rxq->cqe_n);
516 const unsigned int sges_n = (1 << rxq->sges_n);
517 const unsigned int elts_n = (1 << rxq->elts_n);
518 const unsigned int strd_n = (1 << rxq->strd_num_n);
519 const unsigned int cqe_cnt = cqe_n - 1;
520 unsigned int cq_ci, used;
522 /* if we are processing a compressed cqe */
524 used = zip->cqe_cnt - zip->ai;
530 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
531 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
535 op_own = cqe->op_own;
536 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
537 n = rte_be_to_cpu_32(cqe->byte_cnt);
542 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
544 used = RTE_MIN(used * sges_n, elts_n * strd_n);
549 * DPDK callback to check the status of a rx descriptor.
554 * The index of the descriptor in the ring.
557 * The status of the tx descriptor.
560 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
562 struct mlx5_rxq_data *rxq = rx_queue;
563 struct mlx5_rxq_ctrl *rxq_ctrl =
564 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
565 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
567 if (dev->rx_pkt_burst == NULL ||
568 dev->rx_pkt_burst == removed_rx_burst) {
572 if (offset >= (1 << rxq->cqe_n)) {
576 if (offset < rx_queue_count(rxq))
577 return RTE_ETH_RX_DESC_DONE;
578 return RTE_ETH_RX_DESC_AVAIL;
582 * DPDK callback to get the RX queue information
585 * Pointer to the device structure.
588 * Rx queue identificator.
591 * Pointer to the RX queue information structure.
598 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
599 struct rte_eth_rxq_info *qinfo)
601 struct mlx5_priv *priv = dev->data->dev_private;
602 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
603 struct mlx5_rxq_ctrl *rxq_ctrl =
604 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
608 qinfo->mp = mlx5_rxq_mprq_enabled(rxq) ?
609 rxq->mprq_mp : rxq->mp;
610 qinfo->conf.rx_thresh.pthresh = 0;
611 qinfo->conf.rx_thresh.hthresh = 0;
612 qinfo->conf.rx_thresh.wthresh = 0;
613 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
614 qinfo->conf.rx_drop_en = 1;
615 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
616 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
617 qinfo->scattered_rx = dev->data->scattered_rx;
618 qinfo->nb_desc = mlx5_rxq_mprq_enabled(rxq) ?
619 (1 << rxq->elts_n) * (1 << rxq->strd_num_n) :
624 * DPDK callback to get the RX packet burst mode information
627 * Pointer to the device structure.
630 * Rx queue identificatior.
633 * Pointer to the burts mode information.
636 * 0 as success, -EINVAL as failure.
640 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
641 uint16_t rx_queue_id __rte_unused,
642 struct rte_eth_burst_mode *mode)
644 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
645 struct mlx5_priv *priv = dev->data->dev_private;
646 struct mlx5_rxq_data *rxq;
648 rxq = (*priv->rxqs)[rx_queue_id];
653 if (pkt_burst == mlx5_rx_burst) {
654 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
655 } else if (pkt_burst == mlx5_rx_burst_mprq) {
656 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
657 } else if (pkt_burst == mlx5_rx_burst_vec) {
658 #if defined RTE_ARCH_X86_64
659 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
660 #elif defined RTE_ARCH_ARM64
661 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
662 #elif defined RTE_ARCH_PPC_64
663 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
667 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
668 #if defined RTE_ARCH_X86_64
669 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
670 #elif defined RTE_ARCH_ARM64
671 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
672 #elif defined RTE_ARCH_PPC_64
673 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
684 * DPDK callback to get the number of used descriptors in a RX queue
687 * Pointer to the device structure.
693 * The number of used rx descriptor.
694 * -EINVAL if the queue is invalid
697 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
699 struct mlx5_priv *priv = dev->data->dev_private;
700 struct mlx5_rxq_data *rxq;
702 if (dev->rx_pkt_burst == NULL ||
703 dev->rx_pkt_burst == removed_rx_burst) {
707 rxq = (*priv->rxqs)[rx_queue_id];
712 return rx_queue_count(rxq);
715 #define MLX5_SYSTEM_LOG_DIR "/var/log"
717 * Dump debug information to log file.
722 * If not NULL this string is printed as a header to the output
723 * and the output will be in hexadecimal view.
725 * This is the buffer address to print out.
727 * The number of bytes to dump out.
730 mlx5_dump_debug_information(const char *fname, const char *hex_title,
731 const void *buf, unsigned int hex_len)
735 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
736 fd = fopen(path, "a+");
738 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
739 MKSTR(path2, "./%s", fname);
740 fd = fopen(path2, "a+");
742 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
745 DRV_LOG(INFO, "New debug dump in file %s", path2);
747 DRV_LOG(INFO, "New debug dump in file %s", path);
750 rte_hexdump(fd, hex_title, buf, hex_len);
752 fprintf(fd, "%s", (const char *)buf);
753 fprintf(fd, "\n\n\n");
758 * Move QP from error state to running state and initialize indexes.
761 * Pointer to TX queue control structure.
764 * 0 on success, else -1.
767 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
769 struct mlx5_mp_arg_queue_state_modify sm = {
771 .queue_id = txq_ctrl->txq.idx,
774 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
776 txq_ctrl->txq.wqe_ci = 0;
777 txq_ctrl->txq.wqe_pi = 0;
778 txq_ctrl->txq.elts_comp = 0;
782 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
784 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
786 static const uint8_t magic[] = "seen";
790 for (i = 0; i < sizeof(magic); ++i)
791 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
793 err_cqe->rsvd1[i] = magic[i];
802 * Pointer to TX queue structure.
804 * Pointer to the error CQE.
807 * Negative value if queue recovery failed, otherwise
808 * the error completion entry is handled successfully.
811 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
812 volatile struct mlx5_err_cqe *err_cqe)
814 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
815 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
816 struct mlx5_txq_ctrl *txq_ctrl =
817 container_of(txq, struct mlx5_txq_ctrl, txq);
818 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
819 int seen = check_err_cqe_seen(err_cqe);
821 if (!seen && txq_ctrl->dump_file_n <
822 txq_ctrl->priv->config.max_dump_files_num) {
823 MKSTR(err_str, "Unexpected CQE error syndrome "
824 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
825 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
826 txq->cqe_s, txq->qp_num_8s >> 8,
827 rte_be_to_cpu_16(err_cqe->wqe_counter),
828 txq->wqe_ci, txq->cq_ci);
829 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
830 PORT_ID(txq_ctrl->priv), txq->idx,
831 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
832 mlx5_dump_debug_information(name, NULL, err_str, 0);
833 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
834 (const void *)((uintptr_t)
838 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
839 (const void *)((uintptr_t)
843 txq_ctrl->dump_file_n++;
847 * Count errors in WQEs units.
848 * Later it can be improved to count error packets,
849 * for example, by SQ parsing to find how much packets
850 * should be counted for each WQE.
852 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
854 if (tx_recover_qp(txq_ctrl)) {
855 /* Recovering failed - retry later on the same WQE. */
858 /* Release all the remaining buffers. */
859 txq_free_elts(txq_ctrl);
865 * Translate RX completion flags to packet type.
868 * Pointer to RX queue structure.
872 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
875 * Packet type for struct rte_mbuf.
877 static inline uint32_t
878 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
879 volatile struct mlx5_mini_cqe8 *mcqe)
883 uint8_t pinfo = (cqe->pkt_info & 0x3) << 6;
885 /* Get l3/l4 header from mini-CQE in case L3/L4 format*/
887 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
888 ptype = (cqe->hdr_type_etc & 0xfc00) >> 10;
890 ptype = mcqe->hdr_type >> 2;
892 * The index to the array should have:
893 * bit[1:0] = l3_hdr_type
894 * bit[4:2] = l4_hdr_type
897 * bit[7] = outer_l3_type
900 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
904 * Initialize Rx WQ and indexes.
907 * Pointer to RX queue structure.
910 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
912 const unsigned int wqe_n = 1 << rxq->elts_n;
915 for (i = 0; (i != wqe_n); ++i) {
916 volatile struct mlx5_wqe_data_seg *scat;
920 if (mlx5_rxq_mprq_enabled(rxq)) {
921 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
923 scat = &((volatile struct mlx5_wqe_mprq *)
925 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
926 1 << rxq->strd_num_n);
927 byte_count = (1 << rxq->strd_sz_n) *
928 (1 << rxq->strd_num_n);
930 struct rte_mbuf *buf = (*rxq->elts)[i];
932 scat = &((volatile struct mlx5_wqe_data_seg *)
934 addr = rte_pktmbuf_mtod(buf, uintptr_t);
935 byte_count = DATA_LEN(buf);
937 /* scat->addr must be able to store a pointer. */
938 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
939 *scat = (struct mlx5_wqe_data_seg){
940 .addr = rte_cpu_to_be_64(addr),
941 .byte_count = rte_cpu_to_be_32(byte_count),
942 .lkey = mlx5_rx_addr2mr(rxq, addr),
945 rxq->consumed_strd = 0;
946 rxq->decompressed = 0;
948 rxq->zip = (struct rxq_zip){
951 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
952 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
953 /* Update doorbell counter. */
954 rxq->rq_ci = wqe_n >> rxq->sges_n;
956 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
960 * Modify a Verbs/DevX queue state.
961 * This must be called from the primary process.
964 * Pointer to Ethernet device.
966 * State modify request parameters.
969 * 0 in case of success else non-zero value and rte_errno is set.
972 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
973 const struct mlx5_mp_arg_queue_state_modify *sm)
976 struct mlx5_priv *priv = dev->data->dev_private;
979 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
980 struct mlx5_rxq_ctrl *rxq_ctrl =
981 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
983 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
985 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
986 sm->state, strerror(errno));
991 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
992 struct mlx5_txq_ctrl *txq_ctrl =
993 container_of(txq, struct mlx5_txq_ctrl, txq);
995 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
996 MLX5_TXQ_MOD_ERR2RDY,
997 (uint8_t)priv->dev_port);
1005 * Modify a Verbs queue state.
1008 * Pointer to Ethernet device.
1010 * State modify request parameters.
1013 * 0 in case of success else non-zero value.
1016 mlx5_queue_state_modify(struct rte_eth_dev *dev,
1017 struct mlx5_mp_arg_queue_state_modify *sm)
1019 struct mlx5_priv *priv = dev->data->dev_private;
1022 switch (rte_eal_process_type()) {
1023 case RTE_PROC_PRIMARY:
1024 ret = mlx5_queue_state_modify_primary(dev, sm);
1026 case RTE_PROC_SECONDARY:
1027 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
1036 * Handle a Rx error.
1037 * The function inserts the RQ state to reset when the first error CQE is
1038 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
1039 * it moves the RQ state to ready and initializes the RQ.
1040 * Next CQE identification and error counting are in the caller responsibility.
1043 * Pointer to RX queue structure.
1045 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
1046 * 0 when called from non-vectorized Rx burst.
1049 * -1 in case of recovery error, otherwise the CQE status.
1052 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1054 const uint16_t cqe_n = 1 << rxq->cqe_n;
1055 const uint16_t cqe_mask = cqe_n - 1;
1056 const uint16_t wqe_n = 1 << rxq->elts_n;
1057 const uint16_t strd_n = 1 << rxq->strd_num_n;
1058 struct mlx5_rxq_ctrl *rxq_ctrl =
1059 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1061 volatile struct mlx5_cqe *cqe;
1062 volatile struct mlx5_err_cqe *err_cqe;
1064 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1066 struct mlx5_mp_arg_queue_state_modify sm;
1069 switch (rxq->err_state) {
1070 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1071 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1073 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1075 sm.queue_id = rxq->idx;
1076 sm.state = IBV_WQS_RESET;
1077 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1079 if (rxq_ctrl->dump_file_n <
1080 rxq_ctrl->priv->config.max_dump_files_num) {
1081 MKSTR(err_str, "Unexpected CQE error syndrome "
1082 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1083 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1084 rxq->cqn, rxq_ctrl->wqn,
1085 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1086 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1087 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1088 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1089 mlx5_dump_debug_information(name, NULL, err_str, 0);
1090 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1091 (const void *)((uintptr_t)
1093 sizeof(*u.cqe) * cqe_n);
1094 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1095 (const void *)((uintptr_t)
1098 rxq_ctrl->dump_file_n++;
1100 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1102 case MLX5_RXQ_ERR_STATE_NEED_READY:
1103 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1104 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1106 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1109 * The RQ consumer index must be zeroed while moving
1110 * from RESET state to RDY state.
1112 *rxq->rq_db = rte_cpu_to_be_32(0);
1115 sm.queue_id = rxq->idx;
1116 sm.state = IBV_WQS_RDY;
1117 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1121 const uint32_t elts_n =
1122 mlx5_rxq_mprq_enabled(rxq) ?
1123 wqe_n * strd_n : wqe_n;
1124 const uint32_t e_mask = elts_n - 1;
1126 mlx5_rxq_mprq_enabled(rxq) ?
1127 rxq->elts_ci : rxq->rq_ci;
1129 struct rte_mbuf **elt;
1131 unsigned int n = elts_n - (elts_ci -
1134 for (i = 0; i < (int)n; ++i) {
1135 elt_idx = (elts_ci + i) & e_mask;
1136 elt = &(*rxq->elts)[elt_idx];
1137 *elt = rte_mbuf_raw_alloc(rxq->mp);
1139 for (i--; i >= 0; --i) {
1140 elt_idx = (elts_ci +
1144 rte_pktmbuf_free_seg
1150 for (i = 0; i < (int)elts_n; ++i) {
1151 elt = &(*rxq->elts)[i];
1153 (uint16_t)((*elt)->buf_len -
1154 rte_pktmbuf_headroom(*elt));
1156 /* Padding with a fake mbuf for vec Rx. */
1157 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1158 (*rxq->elts)[elts_n + i] =
1161 mlx5_rxq_initialize(rxq);
1162 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1171 * Get size of the next packet for a given CQE. For compressed CQEs, the
1172 * consumer index is updated only once all packets of the current one have
1176 * Pointer to RX queue.
1180 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1184 * 0 in case of empty CQE, otherwise the packet size in bytes.
1187 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1188 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1190 struct rxq_zip *zip = &rxq->zip;
1191 uint16_t cqe_n = cqe_cnt + 1;
1197 /* Process compressed data in the CQE and mini arrays. */
1199 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1200 (volatile struct mlx5_mini_cqe8 (*)[8])
1201 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1203 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt &
1205 *mcqe = &(*mc)[zip->ai & 7];
1206 if ((++zip->ai & 7) == 0) {
1207 /* Invalidate consumed CQEs */
1210 while (idx != end) {
1211 (*rxq->cqes)[idx & cqe_cnt].op_own =
1212 MLX5_CQE_INVALIDATE;
1216 * Increment consumer index to skip the number
1217 * of CQEs consumed. Hardware leaves holes in
1218 * the CQ ring for software use.
1223 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1224 /* Invalidate the rest */
1228 while (idx != end) {
1229 (*rxq->cqes)[idx & cqe_cnt].op_own =
1230 MLX5_CQE_INVALIDATE;
1233 rxq->cq_ci = zip->cq_ci;
1237 * No compressed data, get next CQE and verify if it is
1245 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1246 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1247 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1249 ret = mlx5_rx_err_handle(rxq, 0);
1250 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1258 * Introduce the local variable to have queue cq_ci
1259 * index in queue structure always consistent with
1260 * actual CQE boundary (not pointing to the middle
1261 * of compressed CQE session).
1263 cq_ci = rxq->cq_ci + 1;
1264 op_own = cqe->op_own;
1265 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1266 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1267 (volatile struct mlx5_mini_cqe8 (*)[8])
1268 (uintptr_t)(&(*rxq->cqes)
1269 [cq_ci & cqe_cnt].pkt_info);
1271 /* Fix endianness. */
1272 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1274 * Current mini array position is the one
1275 * returned by check_cqe64().
1277 * If completion comprises several mini arrays,
1278 * as a special case the second one is located
1279 * 7 CQEs after the initial CQE instead of 8
1280 * for subsequent ones.
1283 zip->na = zip->ca + 7;
1284 /* Compute the next non compressed CQE. */
1285 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1286 /* Get packet size to return. */
1287 len = rte_be_to_cpu_32((*mc)[0].byte_cnt &
1291 /* Prefetch all to be invalidated */
1294 while (idx != end) {
1295 rte_prefetch0(&(*rxq->cqes)[(idx) &
1301 len = rte_be_to_cpu_32(cqe->byte_cnt);
1304 if (unlikely(rxq->err_state)) {
1305 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1306 ++rxq->stats.idropped;
1314 * Translate RX completion flags to offload flags.
1320 * Offload flags (ol_flags) for struct rte_mbuf.
1322 static inline uint32_t
1323 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1325 uint32_t ol_flags = 0;
1326 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1330 MLX5_CQE_RX_L3_HDR_VALID,
1331 PKT_RX_IP_CKSUM_GOOD) |
1333 MLX5_CQE_RX_L4_HDR_VALID,
1334 PKT_RX_L4_CKSUM_GOOD);
1339 * Fill in mbuf fields from RX completion flags.
1340 * Note that pkt->ol_flags should be initialized outside of this function.
1343 * Pointer to RX queue.
1348 * @param rss_hash_res
1349 * Packet RSS Hash result.
1352 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1353 volatile struct mlx5_cqe *cqe,
1354 volatile struct mlx5_mini_cqe8 *mcqe)
1356 /* Update packet information. */
1357 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);
1359 if (rxq->rss_hash) {
1360 uint32_t rss_hash_res = 0;
1362 /* If compressed, take hash result from mini-CQE. */
1364 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_HASH)
1365 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1367 rss_hash_res = rte_be_to_cpu_32(mcqe->rx_hash_result);
1369 pkt->hash.rss = rss_hash_res;
1370 pkt->ol_flags |= PKT_RX_RSS_HASH;
1376 /* If compressed, take flow tag from mini-CQE. */
1378 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1379 mark = cqe->sop_drop_qpn;
1381 mark = ((mcqe->byte_cnt_flow & 0xff) << 8) |
1382 (mcqe->flow_tag_high << 16);
1383 if (MLX5_FLOW_MARK_IS_VALID(mark)) {
1384 pkt->ol_flags |= PKT_RX_FDIR;
1385 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) {
1386 pkt->ol_flags |= PKT_RX_FDIR_ID;
1387 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1391 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1392 pkt->ol_flags |= rxq->flow_meta_mask;
1393 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1394 cqe->flow_table_metadata;
1397 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1398 if (rxq->vlan_strip) {
1402 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1403 vlan_strip = cqe->hdr_type_etc &
1404 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1406 vlan_strip = mcqe->hdr_type &
1407 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1409 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1410 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1413 if (rxq->hw_timestamp) {
1414 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1416 if (rxq->rt_timestamp)
1417 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1418 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1419 pkt->ol_flags |= rxq->timestamp_rx_flag;
1424 * DPDK callback for RX.
1427 * Generic pointer to RX queue structure.
1429 * Array to store received packets.
1431 * Maximum number of packets in array.
1434 * Number of packets successfully received (<= pkts_n).
1437 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1439 struct mlx5_rxq_data *rxq = dpdk_rxq;
1440 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1441 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1442 const unsigned int sges_n = rxq->sges_n;
1443 struct rte_mbuf *pkt = NULL;
1444 struct rte_mbuf *seg = NULL;
1445 volatile struct mlx5_cqe *cqe =
1446 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1448 unsigned int rq_ci = rxq->rq_ci << sges_n;
1449 int len = 0; /* keep its value across iterations. */
1452 unsigned int idx = rq_ci & wqe_cnt;
1453 volatile struct mlx5_wqe_data_seg *wqe =
1454 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1455 struct rte_mbuf *rep = (*rxq->elts)[idx];
1456 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1464 /* Allocate the buf from the same pool. */
1465 rep = rte_mbuf_raw_alloc(seg->pool);
1466 if (unlikely(rep == NULL)) {
1467 ++rxq->stats.rx_nombuf;
1470 * no buffers before we even started,
1471 * bail out silently.
1475 while (pkt != seg) {
1476 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1480 rte_mbuf_raw_free(pkt);
1486 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1487 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1489 rte_mbuf_raw_free(rep);
1493 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1494 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1495 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1496 if (rxq->crc_present)
1497 len -= RTE_ETHER_CRC_LEN;
1499 if (cqe->lro_num_seg > 1) {
1501 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1503 pkt->ol_flags |= PKT_RX_LRO;
1504 pkt->tso_segsz = len / cqe->lro_num_seg;
1507 DATA_LEN(rep) = DATA_LEN(seg);
1508 PKT_LEN(rep) = PKT_LEN(seg);
1509 SET_DATA_OFF(rep, DATA_OFF(seg));
1510 PORT(rep) = PORT(seg);
1511 (*rxq->elts)[idx] = rep;
1513 * Fill NIC descriptor with the new buffer. The lkey and size
1514 * of the buffers are already known, only the buffer address
1517 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1518 /* If there's only one MR, no need to replace LKey in WQE. */
1519 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1520 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1521 if (len > DATA_LEN(seg)) {
1522 len -= DATA_LEN(seg);
1527 DATA_LEN(seg) = len;
1528 #ifdef MLX5_PMD_SOFT_COUNTERS
1529 /* Increment bytes counter. */
1530 rxq->stats.ibytes += PKT_LEN(pkt);
1532 /* Return packet. */
1537 /* Align consumer index to the next stride. */
1542 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1544 /* Update the consumer index. */
1545 rxq->rq_ci = rq_ci >> sges_n;
1547 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1549 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1550 #ifdef MLX5_PMD_SOFT_COUNTERS
1551 /* Increment packets counter. */
1552 rxq->stats.ipackets += i;
1558 * Update LRO packet TCP header.
1559 * The HW LRO feature doesn't update the TCP header after coalescing the
1560 * TCP segments but supplies information in CQE to fill it by SW.
1563 * Pointer to the TCP header.
1565 * Pointer to the completion entry..
1567 * The L3 pseudo-header checksum.
1570 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1571 volatile struct mlx5_cqe *__rte_restrict cqe,
1572 uint32_t phcsum, uint8_t l4_type)
1575 * The HW calculates only the TCP payload checksum, need to complete
1576 * the TCP header checksum and the L3 pseudo-header checksum.
1578 uint32_t csum = phcsum + cqe->csum;
1580 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1581 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1582 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1583 tcp->recv_ack = cqe->lro_ack_seq_num;
1584 tcp->rx_win = cqe->lro_tcp_win;
1586 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1587 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1589 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1590 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1591 csum = (~csum) & 0xffff;
1598 * Update LRO packet headers.
1599 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1600 * TCP segments but supply information in CQE to fill it by SW.
1603 * The packet address.
1605 * Pointer to the completion entry..
1607 * The packet length.
1610 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1611 volatile struct mlx5_cqe *__rte_restrict cqe,
1612 volatile struct mlx5_mini_cqe8 *mcqe,
1613 struct mlx5_rxq_data *rxq, uint32_t len)
1616 struct rte_ether_hdr *eth;
1617 struct rte_vlan_hdr *vlan;
1618 struct rte_ipv4_hdr *ipv4;
1619 struct rte_ipv6_hdr *ipv6;
1620 struct rte_tcp_hdr *tcp;
1625 uint16_t proto = h.eth->ether_type;
1630 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1631 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1632 proto = h.vlan->eth_proto;
1635 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1636 h.ipv4->time_to_live = cqe->lro_min_ttl;
1637 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1638 h.ipv4->hdr_checksum = 0;
1639 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1640 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1643 h.ipv6->hop_limits = cqe->lro_min_ttl;
1644 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1646 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1650 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1651 l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1652 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1654 l4_type = (rte_be_to_cpu_16(mcqe->hdr_type) &
1655 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1656 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);
1660 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1662 struct mlx5_mprq_buf *buf = opaque;
1664 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1665 rte_mempool_put(buf->mp, buf);
1666 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1667 __ATOMIC_RELAXED) == 0)) {
1668 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1669 rte_mempool_put(buf->mp, buf);
1674 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1676 mlx5_mprq_buf_free_cb(NULL, buf);
1680 * DPDK callback for RX with Multi-Packet RQ support.
1683 * Generic pointer to RX queue structure.
1685 * Array to store received packets.
1687 * Maximum number of packets in array.
1690 * Number of packets successfully received (<= pkts_n).
1693 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1695 struct mlx5_rxq_data *rxq = dpdk_rxq;
1696 const uint32_t strd_n = 1 << rxq->strd_num_n;
1697 const uint32_t strd_sz = 1 << rxq->strd_sz_n;
1698 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1699 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1700 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1702 uint32_t rq_ci = rxq->rq_ci;
1703 uint16_t consumed_strd = rxq->consumed_strd;
1704 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1706 while (i < pkts_n) {
1707 struct rte_mbuf *pkt;
1713 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1714 enum mlx5_rqx_code rxq_code;
1716 if (consumed_strd == strd_n) {
1717 /* Replace WQE if the buffer is still in use. */
1718 mprq_buf_replace(rxq, rq_ci & wq_mask);
1719 /* Advance to the next WQE. */
1722 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1724 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1725 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1729 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1730 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1731 if (rxq->crc_present)
1732 len -= RTE_ETHER_CRC_LEN;
1734 rxq->mcqe_format == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1735 strd_cnt = (len / strd_sz) + !!(len % strd_sz);
1737 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1738 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1739 MLX5_ASSERT(strd_cnt);
1740 consumed_strd += strd_cnt;
1741 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1743 strd_idx = rte_be_to_cpu_16(mcqe == NULL ?
1746 MLX5_ASSERT(strd_idx < strd_n);
1747 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1749 pkt = rte_pktmbuf_alloc(rxq->mp);
1750 if (unlikely(pkt == NULL)) {
1751 ++rxq->stats.rx_nombuf;
1754 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1755 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1756 if (rxq->crc_present)
1757 len -= RTE_ETHER_CRC_LEN;
1758 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1759 strd_idx, strd_cnt);
1760 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1761 rte_pktmbuf_free_seg(pkt);
1762 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1763 ++rxq->stats.idropped;
1766 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1767 ++rxq->stats.rx_nombuf;
1771 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1772 if (cqe->lro_num_seg > 1) {
1773 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1774 cqe, mcqe, rxq, len);
1775 pkt->ol_flags |= PKT_RX_LRO;
1776 pkt->tso_segsz = len / cqe->lro_num_seg;
1779 PORT(pkt) = rxq->port_id;
1780 #ifdef MLX5_PMD_SOFT_COUNTERS
1781 /* Increment bytes counter. */
1782 rxq->stats.ibytes += PKT_LEN(pkt);
1784 /* Return packet. */
1788 /* Update the consumer indexes. */
1789 rxq->consumed_strd = consumed_strd;
1791 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1792 if (rq_ci != rxq->rq_ci) {
1795 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1797 #ifdef MLX5_PMD_SOFT_COUNTERS
1798 /* Increment packets counter. */
1799 rxq->stats.ipackets += i;
1805 * Dummy DPDK callback for TX.
1807 * This function is used to temporarily replace the real callback during
1808 * unsafe control operations on the queue, or in case of error.
1811 * Generic pointer to TX queue structure.
1813 * Packets to transmit.
1815 * Number of packets in array.
1818 * Number of packets successfully transmitted (<= pkts_n).
1821 removed_tx_burst(void *dpdk_txq __rte_unused,
1822 struct rte_mbuf **pkts __rte_unused,
1823 uint16_t pkts_n __rte_unused)
1830 * Dummy DPDK callback for RX.
1832 * This function is used to temporarily replace the real callback during
1833 * unsafe control operations on the queue, or in case of error.
1836 * Generic pointer to RX queue structure.
1838 * Array to store received packets.
1840 * Maximum number of packets in array.
1843 * Number of packets successfully received (<= pkts_n).
1846 removed_rx_burst(void *dpdk_txq __rte_unused,
1847 struct rte_mbuf **pkts __rte_unused,
1848 uint16_t pkts_n __rte_unused)
1855 * Vectorized Rx/Tx routines are not compiled in when required vector
1856 * instructions are not supported on a target architecture. The following null
1857 * stubs are needed for linkage when those are not included outside of this file
1858 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1862 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1863 struct rte_mbuf **pkts __rte_unused,
1864 uint16_t pkts_n __rte_unused)
1870 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1871 struct rte_mbuf **pkts __rte_unused,
1872 uint16_t pkts_n __rte_unused)
1878 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1884 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1890 * Free the mbufs from the linear array of pointers.
1893 * Pointer to array of packets to be free.
1895 * Number of packets to be freed.
1897 * Configured Tx offloads mask. It is fully defined at
1898 * compile time and may be used for optimization.
1900 static __rte_always_inline void
1901 mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
1902 unsigned int pkts_n,
1903 unsigned int olx __rte_unused)
1905 struct rte_mempool *pool = NULL;
1906 struct rte_mbuf **p_free = NULL;
1907 struct rte_mbuf *mbuf;
1908 unsigned int n_free = 0;
1911 * The implemented algorithm eliminates
1912 * copying pointers to temporary array
1913 * for rte_mempool_put_bulk() calls.
1916 MLX5_ASSERT(pkts_n);
1920 * Decrement mbuf reference counter, detach
1921 * indirect and external buffers if needed.
1923 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1924 if (likely(mbuf != NULL)) {
1925 MLX5_ASSERT(mbuf == *pkts);
1926 if (likely(n_free != 0)) {
1927 if (unlikely(pool != mbuf->pool))
1928 /* From different pool. */
1931 /* Start new scan array. */
1938 if (unlikely(pkts_n == 0)) {
1944 * This happens if mbuf is still referenced.
1945 * We can't put it back to the pool, skip.
1949 if (unlikely(n_free != 0))
1950 /* There is some array to free.*/
1952 if (unlikely(pkts_n == 0))
1953 /* Last mbuf, nothing to free. */
1959 * This loop is implemented to avoid multiple
1960 * inlining of rte_mempool_put_bulk().
1963 MLX5_ASSERT(p_free);
1964 MLX5_ASSERT(n_free);
1966 * Free the array of pre-freed mbufs
1967 * belonging to the same memory pool.
1969 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1970 if (unlikely(mbuf != NULL)) {
1971 /* There is the request to start new scan. */
1976 if (likely(pkts_n != 0))
1979 * This is the last mbuf to be freed.
1980 * Do one more loop iteration to complete.
1981 * This is rare case of the last unique mbuf.
1986 if (likely(pkts_n == 0))
1994 * No inline version to free buffers for optimal call
1995 * on the tx_burst completion.
1997 static __rte_noinline void
1998 __mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
1999 unsigned int pkts_n,
2000 unsigned int olx __rte_unused)
2002 mlx5_tx_free_mbuf(pkts, pkts_n, olx);
2006 * Free the mbuf from the elts ring buffer till new tail.
2009 * Pointer to Tx queue structure.
2011 * Index in elts to free up to, becomes new elts tail.
2013 * Configured Tx offloads mask. It is fully defined at
2014 * compile time and may be used for optimization.
2016 static __rte_always_inline void
2017 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
2019 unsigned int olx __rte_unused)
2021 uint16_t n_elts = tail - txq->elts_tail;
2023 MLX5_ASSERT(n_elts);
2024 MLX5_ASSERT(n_elts <= txq->elts_s);
2026 * Implement a loop to support ring buffer wraparound
2027 * with single inlining of mlx5_tx_free_mbuf().
2032 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
2033 part = RTE_MIN(part, n_elts);
2035 MLX5_ASSERT(part <= txq->elts_s);
2036 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
2038 txq->elts_tail += part;
2044 * Store the mbuf being sent into elts ring buffer.
2045 * On Tx completion these mbufs will be freed.
2048 * Pointer to Tx queue structure.
2050 * Pointer to array of packets to be stored.
2052 * Number of packets to be stored.
2054 * Configured Tx offloads mask. It is fully defined at
2055 * compile time and may be used for optimization.
2057 static __rte_always_inline void
2058 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
2059 struct rte_mbuf **__rte_restrict pkts,
2060 unsigned int pkts_n,
2061 unsigned int olx __rte_unused)
2064 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2067 MLX5_ASSERT(pkts_n);
2068 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2070 MLX5_ASSERT(part <= txq->elts_s);
2071 /* This code is a good candidate for vectorizing with SIMD. */
2072 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2074 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2075 txq->elts_head += pkts_n;
2076 if (unlikely(part < pkts_n))
2077 /* The copy is wrapping around the elts array. */
2078 rte_memcpy((void *)elts, (void *)(pkts + part),
2079 (pkts_n - part) * sizeof(struct rte_mbuf *));
2083 * Update completion queue consuming index via doorbell
2084 * and flush the completed data buffers.
2087 * Pointer to TX queue structure.
2088 * @param valid CQE pointer
2089 * if not NULL update txq->wqe_pi and flush the buffers
2091 * Configured Tx offloads mask. It is fully defined at
2092 * compile time and may be used for optimization.
2094 static __rte_always_inline void
2095 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2096 volatile struct mlx5_cqe *last_cqe,
2097 unsigned int olx __rte_unused)
2099 if (likely(last_cqe != NULL)) {
2102 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2103 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2104 if (likely(tail != txq->elts_tail)) {
2105 mlx5_tx_free_elts(txq, tail, olx);
2106 MLX5_ASSERT(tail == txq->elts_tail);
2112 * Manage TX completions. This routine checks the CQ for
2113 * arrived CQEs, deduces the last accomplished WQE in SQ,
2114 * updates SQ producing index and frees all completed mbufs.
2117 * Pointer to TX queue structure.
2119 * Configured Tx offloads mask. It is fully defined at
2120 * compile time and may be used for optimization.
2122 * NOTE: not inlined intentionally, it makes tx_burst
2123 * routine smaller, simple and faster - from experiments.
2126 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2127 unsigned int olx __rte_unused)
2129 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2130 volatile struct mlx5_cqe *last_cqe = NULL;
2131 bool ring_doorbell = false;
2135 volatile struct mlx5_cqe *cqe;
2137 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2138 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2139 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2140 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2141 /* No new CQEs in completion queue. */
2142 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2146 * Some error occurred, try to restart.
2147 * We have no barrier after WQE related Doorbell
2148 * written, make sure all writes are completed
2149 * here, before we might perform SQ reset.
2152 ret = mlx5_tx_error_cqe_handle
2153 (txq, (volatile struct mlx5_err_cqe *)cqe);
2154 if (unlikely(ret < 0)) {
2156 * Some error occurred on queue error
2157 * handling, we do not advance the index
2158 * here, allowing to retry on next call.
2163 * We are going to fetch all entries with
2164 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2165 * The send queue is supposed to be empty.
2167 ring_doorbell = true;
2169 txq->cq_pi = txq->cq_ci;
2173 /* Normal transmit completion. */
2174 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2175 #ifdef RTE_LIBRTE_MLX5_DEBUG
2176 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2179 ring_doorbell = true;
2183 * We have to restrict the amount of processed CQEs
2184 * in one tx_burst routine call. The CQ may be large
2185 * and many CQEs may be updated by the NIC in one
2186 * transaction. Buffers freeing is time consuming,
2187 * multiple iterations may introduce significant
2190 if (likely(--count == 0))
2193 if (likely(ring_doorbell)) {
2194 /* Ring doorbell to notify hardware. */
2195 rte_compiler_barrier();
2196 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2197 mlx5_tx_comp_flush(txq, last_cqe, olx);
2202 * Check if the completion request flag should be set in the last WQE.
2203 * Both pushed mbufs and WQEs are monitored and the completion request
2204 * flag is set if any of thresholds is reached.
2207 * Pointer to TX queue structure.
2209 * Pointer to burst routine local context.
2211 * Configured Tx offloads mask. It is fully defined at
2212 * compile time and may be used for optimization.
2214 static __rte_always_inline void
2215 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2216 struct mlx5_txq_local *__rte_restrict loc,
2219 uint16_t head = txq->elts_head;
2222 part = MLX5_TXOFF_CONFIG(INLINE) ?
2223 0 : loc->pkts_sent - loc->pkts_copy;
2225 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2226 (MLX5_TXOFF_CONFIG(INLINE) &&
2227 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2228 volatile struct mlx5_wqe *last = loc->wqe_last;
2231 txq->elts_comp = head;
2232 if (MLX5_TXOFF_CONFIG(INLINE))
2233 txq->wqe_comp = txq->wqe_ci;
2234 /* Request unconditional completion on last WQE. */
2235 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2236 MLX5_COMP_MODE_OFFSET);
2237 /* Save elts_head in dedicated free on completion queue. */
2238 #ifdef RTE_LIBRTE_MLX5_DEBUG
2239 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2240 (last->cseg.opcode >> 8) << 16;
2242 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2244 /* A CQE slot must always be available. */
2245 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2250 * DPDK callback to check the status of a tx descriptor.
2255 * The index of the descriptor in the ring.
2258 * The status of the tx descriptor.
2261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2263 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2266 mlx5_tx_handle_completion(txq, 0);
2267 used = txq->elts_head - txq->elts_tail;
2269 return RTE_ETH_TX_DESC_FULL;
2270 return RTE_ETH_TX_DESC_DONE;
2274 * Build the Control Segment with specified opcode:
2275 * - MLX5_OPCODE_SEND
2276 * - MLX5_OPCODE_ENHANCED_MPSW
2280 * Pointer to TX queue structure.
2282 * Pointer to burst routine local context.
2284 * Pointer to WQE to fill with built Control Segment.
2286 * Supposed length of WQE in segments.
2288 * SQ WQE opcode to put into Control Segment.
2290 * Configured Tx offloads mask. It is fully defined at
2291 * compile time and may be used for optimization.
2293 static __rte_always_inline void
2294 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2295 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2296 struct mlx5_wqe *__rte_restrict wqe,
2298 unsigned int opcode,
2299 unsigned int olx __rte_unused)
2301 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2303 /* For legacy MPW replace the EMPW by TSO with modifier. */
2304 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2305 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2306 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2307 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2308 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2309 MLX5_COMP_MODE_OFFSET);
2310 cs->misc = RTE_BE32(0);
2314 * Build the Synchronize Queue Segment with specified completion index.
2317 * Pointer to TX queue structure.
2319 * Pointer to burst routine local context.
2321 * Pointer to WQE to fill with built Control Segment.
2323 * Completion index in Clock Queue to wait.
2325 * Configured Tx offloads mask. It is fully defined at
2326 * compile time and may be used for optimization.
2328 static __rte_always_inline void
2329 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2330 struct mlx5_txq_local *restrict loc __rte_unused,
2331 struct mlx5_wqe *restrict wqe,
2333 unsigned int olx __rte_unused)
2335 struct mlx5_wqe_qseg *qs;
2337 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2338 qs->max_index = rte_cpu_to_be_32(wci);
2339 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq_obj.cq->id);
2340 qs->reserved0 = RTE_BE32(0);
2341 qs->reserved1 = RTE_BE32(0);
2345 * Build the Ethernet Segment without inlined data.
2346 * Supports Software Parser, Checksums and VLAN
2347 * insertion Tx offload features.
2350 * Pointer to TX queue structure.
2352 * Pointer to burst routine local context.
2354 * Pointer to WQE to fill with built Ethernet Segment.
2356 * Configured Tx offloads mask. It is fully defined at
2357 * compile time and may be used for optimization.
2359 static __rte_always_inline void
2360 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2361 struct mlx5_txq_local *__rte_restrict loc,
2362 struct mlx5_wqe *__rte_restrict wqe,
2365 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2369 * Calculate and set check sum flags first, dword field
2370 * in segment may be shared with Software Parser flags.
2372 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2373 es->flags = rte_cpu_to_le_32(csum);
2375 * Calculate and set Software Parser offsets and flags.
2376 * These flags a set for custom UDP and IP tunnel packets.
2378 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2379 /* Fill metadata field if needed. */
2380 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2381 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2382 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2383 /* Engage VLAN tag insertion feature if requested. */
2384 if (MLX5_TXOFF_CONFIG(VLAN) &&
2385 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2387 * We should get here only if device support
2388 * this feature correctly.
2390 MLX5_ASSERT(txq->vlan_en);
2391 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2392 loc->mbuf->vlan_tci);
2394 es->inline_hdr = RTE_BE32(0);
2399 * Build the Ethernet Segment with minimal inlined data
2400 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2401 * used to fill the gap in single WQEBB WQEs.
2402 * Supports Software Parser, Checksums and VLAN
2403 * insertion Tx offload features.
2406 * Pointer to TX queue structure.
2408 * Pointer to burst routine local context.
2410 * Pointer to WQE to fill with built Ethernet Segment.
2412 * Length of VLAN tag insertion if any.
2414 * Configured Tx offloads mask. It is fully defined at
2415 * compile time and may be used for optimization.
2417 static __rte_always_inline void
2418 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2419 struct mlx5_txq_local *__rte_restrict loc,
2420 struct mlx5_wqe *__rte_restrict wqe,
2424 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2426 uint8_t *psrc, *pdst;
2429 * Calculate and set check sum flags first, dword field
2430 * in segment may be shared with Software Parser flags.
2432 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2433 es->flags = rte_cpu_to_le_32(csum);
2435 * Calculate and set Software Parser offsets and flags.
2436 * These flags a set for custom UDP and IP tunnel packets.
2438 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2439 /* Fill metadata field if needed. */
2440 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2441 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2442 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2443 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2444 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2445 es->inline_data = *(unaligned_uint16_t *)psrc;
2446 psrc += sizeof(uint16_t);
2447 pdst = (uint8_t *)(es + 1);
2448 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2449 /* Implement VLAN tag insertion as part inline data. */
2450 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2451 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2452 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2453 /* Insert VLAN ethertype + VLAN tag. */
2454 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2455 ((RTE_ETHER_TYPE_VLAN << 16) |
2456 loc->mbuf->vlan_tci);
2457 pdst += sizeof(struct rte_vlan_hdr);
2458 /* Copy the rest two bytes from packet data. */
2459 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2460 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2462 /* Fill the gap in the title WQEBB with inline data. */
2463 rte_mov16(pdst, psrc);
2468 * Build the Ethernet Segment with entire packet
2469 * data inlining. Checks the boundary of WQEBB and
2470 * ring buffer wrapping, supports Software Parser,
2471 * Checksums and VLAN insertion Tx offload features.
2474 * Pointer to TX queue structure.
2476 * Pointer to burst routine local context.
2478 * Pointer to WQE to fill with built Ethernet Segment.
2480 * Length of VLAN tag insertion if any.
2482 * Length of data to inline (VLAN included, if any).
2484 * TSO flag, set mss field from the packet.
2486 * Configured Tx offloads mask. It is fully defined at
2487 * compile time and may be used for optimization.
2490 * Pointer to the next Data Segment (aligned and wrapped around).
2492 static __rte_always_inline struct mlx5_wqe_dseg *
2493 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2494 struct mlx5_txq_local *__rte_restrict loc,
2495 struct mlx5_wqe *__rte_restrict wqe,
2501 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2503 uint8_t *psrc, *pdst;
2507 * Calculate and set check sum flags first, dword field
2508 * in segment may be shared with Software Parser flags.
2510 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2513 csum |= loc->mbuf->tso_segsz;
2514 es->flags = rte_cpu_to_be_32(csum);
2516 es->flags = rte_cpu_to_le_32(csum);
2519 * Calculate and set Software Parser offsets and flags.
2520 * These flags a set for custom UDP and IP tunnel packets.
2522 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2523 /* Fill metadata field if needed. */
2524 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2525 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2526 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2527 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2528 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2529 es->inline_data = *(unaligned_uint16_t *)psrc;
2530 psrc += sizeof(uint16_t);
2531 pdst = (uint8_t *)(es + 1);
2532 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2533 /* Implement VLAN tag insertion as part inline data. */
2534 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2535 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2536 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2537 /* Insert VLAN ethertype + VLAN tag. */
2538 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2539 ((RTE_ETHER_TYPE_VLAN << 16) |
2540 loc->mbuf->vlan_tci);
2541 pdst += sizeof(struct rte_vlan_hdr);
2542 /* Copy the rest two bytes from packet data. */
2543 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2544 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2545 psrc += sizeof(uint16_t);
2547 /* Fill the gap in the title WQEBB with inline data. */
2548 rte_mov16(pdst, psrc);
2549 psrc += sizeof(rte_v128u32_t);
2551 pdst = (uint8_t *)(es + 2);
2552 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2553 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2554 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2556 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2557 return (struct mlx5_wqe_dseg *)pdst;
2560 * The WQEBB space availability is checked by caller.
2561 * Here we should be aware of WQE ring buffer wraparound only.
2563 part = (uint8_t *)txq->wqes_end - pdst;
2564 part = RTE_MIN(part, inlen);
2566 rte_memcpy(pdst, psrc, part);
2568 if (likely(!inlen)) {
2570 * If return value is not used by the caller
2571 * the code below will be optimized out.
2574 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2575 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2576 pdst = (uint8_t *)txq->wqes;
2577 return (struct mlx5_wqe_dseg *)pdst;
2579 pdst = (uint8_t *)txq->wqes;
2586 * Copy data from chain of mbuf to the specified linear buffer.
2587 * Checksums and VLAN insertion Tx offload features. If data
2588 * from some mbuf copied completely this mbuf is freed. Local
2589 * structure is used to keep the byte stream state.
2592 * Pointer to the destination linear buffer.
2594 * Pointer to burst routine local context.
2596 * Length of data to be copied.
2598 * Length of data to be copied ignoring no inline hint.
2600 * Configured Tx offloads mask. It is fully defined at
2601 * compile time and may be used for optimization.
2604 * Number of actual copied data bytes. This is always greater than or
2605 * equal to must parameter and might be lesser than len in no inline
2606 * hint flag is encountered.
2608 static __rte_always_inline unsigned int
2609 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2610 struct mlx5_txq_local *__rte_restrict loc,
2613 unsigned int olx __rte_unused)
2615 struct rte_mbuf *mbuf;
2616 unsigned int part, dlen, copy = 0;
2620 MLX5_ASSERT(must <= len);
2622 /* Allow zero length packets, must check first. */
2623 dlen = rte_pktmbuf_data_len(loc->mbuf);
2624 if (dlen <= loc->mbuf_off) {
2625 /* Exhausted packet, just free. */
2627 loc->mbuf = mbuf->next;
2628 rte_pktmbuf_free_seg(mbuf);
2630 MLX5_ASSERT(loc->mbuf_nseg > 1);
2631 MLX5_ASSERT(loc->mbuf);
2633 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2638 * We already copied the minimal
2639 * requested amount of data.
2644 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2646 * Copy only the minimal required
2647 * part of the data buffer.
2654 dlen -= loc->mbuf_off;
2655 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2657 part = RTE_MIN(len, dlen);
2658 rte_memcpy(pdst, psrc, part);
2660 loc->mbuf_off += part;
2663 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2665 /* Exhausted packet, just free. */
2667 loc->mbuf = mbuf->next;
2668 rte_pktmbuf_free_seg(mbuf);
2670 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2680 * Build the Ethernet Segment with inlined data from
2681 * multi-segment packet. Checks the boundary of WQEBB
2682 * and ring buffer wrapping, supports Software Parser,
2683 * Checksums and VLAN insertion Tx offload features.
2686 * Pointer to TX queue structure.
2688 * Pointer to burst routine local context.
2690 * Pointer to WQE to fill with built Ethernet Segment.
2692 * Length of VLAN tag insertion if any.
2694 * Length of data to inline (VLAN included, if any).
2696 * TSO flag, set mss field from the packet.
2698 * Configured Tx offloads mask. It is fully defined at
2699 * compile time and may be used for optimization.
2702 * Pointer to the next Data Segment (aligned and
2703 * possible NOT wrapped around - caller should do
2704 * wrapping check on its own).
2706 static __rte_always_inline struct mlx5_wqe_dseg *
2707 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2708 struct mlx5_txq_local *__rte_restrict loc,
2709 struct mlx5_wqe *__rte_restrict wqe,
2715 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2718 unsigned int part, tlen = 0;
2721 * Calculate and set check sum flags first, uint32_t field
2722 * in segment may be shared with Software Parser flags.
2724 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2727 csum |= loc->mbuf->tso_segsz;
2728 es->flags = rte_cpu_to_be_32(csum);
2730 es->flags = rte_cpu_to_le_32(csum);
2733 * Calculate and set Software Parser offsets and flags.
2734 * These flags a set for custom UDP and IP tunnel packets.
2736 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2737 /* Fill metadata field if needed. */
2738 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2739 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2740 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2741 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2742 pdst = (uint8_t *)&es->inline_data;
2743 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2744 /* Implement VLAN tag insertion as part inline data. */
2745 mlx5_tx_mseg_memcpy(pdst, loc,
2746 2 * RTE_ETHER_ADDR_LEN,
2747 2 * RTE_ETHER_ADDR_LEN, olx);
2748 pdst += 2 * RTE_ETHER_ADDR_LEN;
2749 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2750 ((RTE_ETHER_TYPE_VLAN << 16) |
2751 loc->mbuf->vlan_tci);
2752 pdst += sizeof(struct rte_vlan_hdr);
2753 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2755 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2757 * The WQEBB space availability is checked by caller.
2758 * Here we should be aware of WQE ring buffer wraparound only.
2760 part = (uint8_t *)txq->wqes_end - pdst;
2761 part = RTE_MIN(part, inlen - tlen);
2767 * Copying may be interrupted inside the routine
2768 * if run into no inline hint flag.
2770 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2771 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2773 if (likely(inlen <= tlen) || copy < part) {
2774 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2776 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2777 return (struct mlx5_wqe_dseg *)pdst;
2779 pdst = (uint8_t *)txq->wqes;
2780 part = inlen - tlen;
2785 * Build the Data Segment of pointer type.
2788 * Pointer to TX queue structure.
2790 * Pointer to burst routine local context.
2792 * Pointer to WQE to fill with built Data Segment.
2794 * Data buffer to point.
2796 * Data buffer length.
2798 * Configured Tx offloads mask. It is fully defined at
2799 * compile time and may be used for optimization.
2801 static __rte_always_inline void
2802 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2803 struct mlx5_txq_local *__rte_restrict loc,
2804 struct mlx5_wqe_dseg *__rte_restrict dseg,
2807 unsigned int olx __rte_unused)
2811 dseg->bcount = rte_cpu_to_be_32(len);
2812 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2813 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2817 * Build the Data Segment of pointer type or inline
2818 * if data length is less than buffer in minimal
2819 * Data Segment size.
2822 * Pointer to TX queue structure.
2824 * Pointer to burst routine local context.
2826 * Pointer to WQE to fill with built Data Segment.
2828 * Data buffer to point.
2830 * Data buffer length.
2832 * Configured Tx offloads mask. It is fully defined at
2833 * compile time and may be used for optimization.
2835 static __rte_always_inline void
2836 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2837 struct mlx5_txq_local *__rte_restrict loc,
2838 struct mlx5_wqe_dseg *__rte_restrict dseg,
2841 unsigned int olx __rte_unused)
2847 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2848 dseg->bcount = rte_cpu_to_be_32(len);
2849 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2850 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2854 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2855 /* Unrolled implementation of generic rte_memcpy. */
2856 dst = (uintptr_t)&dseg->inline_data[0];
2857 src = (uintptr_t)buf;
2859 #ifdef RTE_ARCH_STRICT_ALIGN
2860 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2861 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2862 dst += sizeof(uint32_t);
2863 src += sizeof(uint32_t);
2864 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2865 dst += sizeof(uint32_t);
2866 src += sizeof(uint32_t);
2868 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2869 dst += sizeof(uint64_t);
2870 src += sizeof(uint64_t);
2874 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2875 dst += sizeof(uint32_t);
2876 src += sizeof(uint32_t);
2879 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2880 dst += sizeof(uint16_t);
2881 src += sizeof(uint16_t);
2884 *(uint8_t *)dst = *(uint8_t *)src;
2888 * Build the Data Segment of inlined data from single
2889 * segment packet, no VLAN insertion.
2892 * Pointer to TX queue structure.
2894 * Pointer to burst routine local context.
2896 * Pointer to WQE to fill with built Data Segment.
2898 * Data buffer to point.
2900 * Data buffer length.
2902 * Configured Tx offloads mask. It is fully defined at
2903 * compile time and may be used for optimization.
2906 * Pointer to the next Data Segment after inlined data.
2907 * Ring buffer wraparound check is needed. We do not
2908 * do it here because it may not be needed for the
2909 * last packet in the eMPW session.
2911 static __rte_always_inline struct mlx5_wqe_dseg *
2912 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2913 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2914 struct mlx5_wqe_dseg *__rte_restrict dseg,
2917 unsigned int olx __rte_unused)
2922 if (!MLX5_TXOFF_CONFIG(MPW)) {
2923 /* Store the descriptor byte counter for eMPW sessions. */
2924 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2925 pdst = &dseg->inline_data[0];
2927 /* The entire legacy MPW session counter is stored on close. */
2928 pdst = (uint8_t *)dseg;
2931 * The WQEBB space availability is checked by caller.
2932 * Here we should be aware of WQE ring buffer wraparound only.
2934 part = (uint8_t *)txq->wqes_end - pdst;
2935 part = RTE_MIN(part, len);
2937 rte_memcpy(pdst, buf, part);
2941 if (!MLX5_TXOFF_CONFIG(MPW))
2942 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2943 /* Note: no final wraparound check here. */
2944 return (struct mlx5_wqe_dseg *)pdst;
2946 pdst = (uint8_t *)txq->wqes;
2953 * Build the Data Segment of inlined data from single
2954 * segment packet with VLAN insertion.
2957 * Pointer to TX queue structure.
2959 * Pointer to burst routine local context.
2961 * Pointer to the dseg fill with built Data Segment.
2963 * Data buffer to point.
2965 * Data buffer length.
2967 * Configured Tx offloads mask. It is fully defined at
2968 * compile time and may be used for optimization.
2971 * Pointer to the next Data Segment after inlined data.
2972 * Ring buffer wraparound check is needed.
2974 static __rte_always_inline struct mlx5_wqe_dseg *
2975 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
2976 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2977 struct mlx5_wqe_dseg *__rte_restrict dseg,
2980 unsigned int olx __rte_unused)
2986 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
2987 if (!MLX5_TXOFF_CONFIG(MPW)) {
2988 /* Store the descriptor byte counter for eMPW sessions. */
2989 dseg->bcount = rte_cpu_to_be_32
2990 ((len + sizeof(struct rte_vlan_hdr)) |
2991 MLX5_ETH_WQE_DATA_INLINE);
2992 pdst = &dseg->inline_data[0];
2994 /* The entire legacy MPW session counter is stored on close. */
2995 pdst = (uint8_t *)dseg;
2997 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2998 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2999 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
3000 len -= MLX5_DSEG_MIN_INLINE_SIZE;
3001 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
3002 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
3003 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
3004 pdst = (uint8_t *)txq->wqes;
3005 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
3006 loc->mbuf->vlan_tci);
3007 pdst += sizeof(struct rte_vlan_hdr);
3009 * The WQEBB space availability is checked by caller.
3010 * Here we should be aware of WQE ring buffer wraparound only.
3012 part = (uint8_t *)txq->wqes_end - pdst;
3013 part = RTE_MIN(part, len);
3015 rte_memcpy(pdst, buf, part);
3019 if (!MLX5_TXOFF_CONFIG(MPW))
3020 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
3021 /* Note: no final wraparound check here. */
3022 return (struct mlx5_wqe_dseg *)pdst;
3024 pdst = (uint8_t *)txq->wqes;
3031 * Build the Ethernet Segment with optionally inlined data with
3032 * VLAN insertion and following Data Segments (if any) from
3033 * multi-segment packet. Used by ordinary send and TSO.
3036 * Pointer to TX queue structure.
3038 * Pointer to burst routine local context.
3040 * Pointer to WQE to fill with built Ethernet/Data Segments.
3042 * Length of VLAN header to insert, 0 means no VLAN insertion.
3044 * Data length to inline. For TSO this parameter specifies
3045 * exact value, for ordinary send routine can be aligned by
3046 * caller to provide better WQE space saving and data buffer
3047 * start address alignment. This length includes VLAN header
3050 * Zero means ordinary send, inlined data can be extended,
3051 * otherwise this is TSO, inlined data length is fixed.
3053 * Configured Tx offloads mask. It is fully defined at
3054 * compile time and may be used for optimization.
3057 * Actual size of built WQE in segments.
3059 static __rte_always_inline unsigned int
3060 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3061 struct mlx5_txq_local *__rte_restrict loc,
3062 struct mlx5_wqe *__rte_restrict wqe,
3066 unsigned int olx __rte_unused)
3068 struct mlx5_wqe_dseg *__rte_restrict dseg;
3071 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3072 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3075 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3076 if (!loc->mbuf_nseg)
3079 * There are still some mbuf remaining, not inlined.
3080 * The first mbuf may be partially inlined and we
3081 * must process the possible non-zero data offset.
3083 if (loc->mbuf_off) {
3088 * Exhausted packets must be dropped before.
3089 * Non-zero offset means there are some data
3090 * remained in the packet.
3092 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3093 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3094 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3096 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3098 * Build the pointer/minimal data Data Segment.
3099 * Do ring buffer wrapping check in advance.
3101 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3102 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3103 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3104 /* Store the mbuf to be freed on completion. */
3105 MLX5_ASSERT(loc->elts_free);
3106 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3109 if (--loc->mbuf_nseg == 0)
3111 loc->mbuf = loc->mbuf->next;
3115 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3116 struct rte_mbuf *mbuf;
3118 /* Zero length segment found, just skip. */
3120 loc->mbuf = loc->mbuf->next;
3121 rte_pktmbuf_free_seg(mbuf);
3122 if (--loc->mbuf_nseg == 0)
3125 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3126 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3129 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3130 rte_pktmbuf_data_len(loc->mbuf), olx);
3131 MLX5_ASSERT(loc->elts_free);
3132 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3135 if (--loc->mbuf_nseg == 0)
3137 loc->mbuf = loc->mbuf->next;
3142 /* Calculate actual segments used from the dseg pointer. */
3143 if ((uintptr_t)wqe < (uintptr_t)dseg)
3144 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3146 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3147 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3152 * The routine checks timestamp flag in the current packet,
3153 * and push WAIT WQE into the queue if scheduling is required.
3156 * Pointer to TX queue structure.
3158 * Pointer to burst routine local context.
3160 * Configured Tx offloads mask. It is fully defined at
3161 * compile time and may be used for optimization.
3164 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3165 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3166 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3167 * Local context variables partially updated.
3169 static __rte_always_inline enum mlx5_txcmp_code
3170 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3171 struct mlx5_txq_local *restrict loc,
3174 if (MLX5_TXOFF_CONFIG(TXPP) &&
3175 loc->mbuf->ol_flags & txq->ts_mask) {
3176 struct mlx5_wqe *wqe;
3181 * Estimate the required space quickly and roughly.
3182 * We would like to ensure the packet can be pushed
3183 * to the queue and we won't get the orphan WAIT WQE.
3185 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3186 loc->elts_free < NB_SEGS(loc->mbuf))
3187 return MLX5_TXCMP_CODE_EXIT;
3188 /* Convert the timestamp into completion to wait. */
3189 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3190 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3191 if (unlikely(wci < 0))
3192 return MLX5_TXCMP_CODE_SINGLE;
3193 /* Build the WAIT WQE with specified completion. */
3194 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3195 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3196 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3199 return MLX5_TXCMP_CODE_MULTI;
3201 return MLX5_TXCMP_CODE_SINGLE;
3205 * Tx one packet function for multi-segment TSO. Supports all
3206 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3207 * sends one packet per WQE.
3209 * This routine is responsible for storing processed mbuf
3210 * into elts ring buffer and update elts_head.
3213 * Pointer to TX queue structure.
3215 * Pointer to burst routine local context.
3217 * Configured Tx offloads mask. It is fully defined at
3218 * compile time and may be used for optimization.
3221 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3222 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3223 * Local context variables partially updated.
3225 static __rte_always_inline enum mlx5_txcmp_code
3226 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3227 struct mlx5_txq_local *__rte_restrict loc,
3230 struct mlx5_wqe *__rte_restrict wqe;
3231 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3233 if (MLX5_TXOFF_CONFIG(TXPP)) {
3234 enum mlx5_txcmp_code wret;
3236 /* Generate WAIT for scheduling if requested. */
3237 wret = mlx5_tx_schedule_send(txq, loc, olx);
3238 if (wret == MLX5_TXCMP_CODE_EXIT)
3239 return MLX5_TXCMP_CODE_EXIT;
3240 if (wret == MLX5_TXCMP_CODE_ERROR)
3241 return MLX5_TXCMP_CODE_ERROR;
3244 * Calculate data length to be inlined to estimate
3245 * the required space in WQE ring buffer.
3247 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3248 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3249 vlan = sizeof(struct rte_vlan_hdr);
3250 inlen = loc->mbuf->l2_len + vlan +
3251 loc->mbuf->l3_len + loc->mbuf->l4_len;
3252 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3253 return MLX5_TXCMP_CODE_ERROR;
3254 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3255 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3256 /* Packet must contain all TSO headers. */
3257 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3258 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3259 inlen > (dlen + vlan)))
3260 return MLX5_TXCMP_CODE_ERROR;
3261 MLX5_ASSERT(inlen >= txq->inlen_mode);
3263 * Check whether there are enough free WQEBBs:
3265 * - Ethernet Segment
3266 * - First Segment of inlined Ethernet data
3267 * - ... data continued ...
3268 * - Data Segments of pointer/min inline type
3270 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3271 MLX5_ESEG_MIN_INLINE_SIZE +
3273 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3274 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3275 return MLX5_TXCMP_CODE_EXIT;
3276 /* Check for maximal WQE size. */
3277 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3278 return MLX5_TXCMP_CODE_ERROR;
3279 #ifdef MLX5_PMD_SOFT_COUNTERS
3280 /* Update sent data bytes/packets counters. */
3281 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3282 loc->mbuf->tso_segsz;
3284 * One will be added for mbuf itself
3285 * at the end of the mlx5_tx_burst from
3286 * loc->pkts_sent field.
3289 txq->stats.opackets += ntcp;
3290 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3292 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3293 loc->wqe_last = wqe;
3294 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3295 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3296 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3297 txq->wqe_ci += (ds + 3) / 4;
3298 loc->wqe_free -= (ds + 3) / 4;
3299 return MLX5_TXCMP_CODE_MULTI;
3303 * Tx one packet function for multi-segment SEND. Supports all
3304 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3305 * sends one packet per WQE, without any data inlining in
3308 * This routine is responsible for storing processed mbuf
3309 * into elts ring buffer and update elts_head.
3312 * Pointer to TX queue structure.
3314 * Pointer to burst routine local context.
3316 * Configured Tx offloads mask. It is fully defined at
3317 * compile time and may be used for optimization.
3320 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3321 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3322 * Local context variables partially updated.
3324 static __rte_always_inline enum mlx5_txcmp_code
3325 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3326 struct mlx5_txq_local *__rte_restrict loc,
3329 struct mlx5_wqe_dseg *__rte_restrict dseg;
3330 struct mlx5_wqe *__rte_restrict wqe;
3331 unsigned int ds, nseg;
3333 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3334 if (MLX5_TXOFF_CONFIG(TXPP)) {
3335 enum mlx5_txcmp_code wret;
3337 /* Generate WAIT for scheduling if requested. */
3338 wret = mlx5_tx_schedule_send(txq, loc, olx);
3339 if (wret == MLX5_TXCMP_CODE_EXIT)
3340 return MLX5_TXCMP_CODE_EXIT;
3341 if (wret == MLX5_TXCMP_CODE_ERROR)
3342 return MLX5_TXCMP_CODE_ERROR;
3345 * No inline at all, it means the CPU cycles saving
3346 * is prioritized at configuration, we should not
3347 * copy any packet data to WQE.
3349 nseg = NB_SEGS(loc->mbuf);
3351 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3352 return MLX5_TXCMP_CODE_EXIT;
3353 /* Check for maximal WQE size. */
3354 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3355 return MLX5_TXCMP_CODE_ERROR;
3357 * Some Tx offloads may cause an error if
3358 * packet is not long enough, check against
3359 * assumed minimal length.
3361 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3362 return MLX5_TXCMP_CODE_ERROR;
3363 #ifdef MLX5_PMD_SOFT_COUNTERS
3364 /* Update sent data bytes counter. */
3365 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3366 if (MLX5_TXOFF_CONFIG(VLAN) &&
3367 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3368 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3371 * SEND WQE, one WQEBB:
3372 * - Control Segment, SEND opcode
3373 * - Ethernet Segment, optional VLAN, no inline
3374 * - Data Segments, pointer only type
3376 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3377 loc->wqe_last = wqe;
3378 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3379 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3380 dseg = &wqe->dseg[0];
3382 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3383 struct rte_mbuf *mbuf;
3386 * Zero length segment found, have to
3387 * correct total size of WQE in segments.
3388 * It is supposed to be rare occasion, so
3389 * in normal case (no zero length segments)
3390 * we avoid extra writing to the Control
3394 wqe->cseg.sq_ds -= RTE_BE32(1);
3396 loc->mbuf = mbuf->next;
3397 rte_pktmbuf_free_seg(mbuf);
3403 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3404 rte_pktmbuf_data_len(loc->mbuf), olx);
3405 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3410 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3411 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3412 loc->mbuf = loc->mbuf->next;
3415 txq->wqe_ci += (ds + 3) / 4;
3416 loc->wqe_free -= (ds + 3) / 4;
3417 return MLX5_TXCMP_CODE_MULTI;
3421 * Tx one packet function for multi-segment SEND. Supports all
3422 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3423 * sends one packet per WQE, with data inlining in
3424 * Ethernet Segment and minimal Data Segments.
3426 * This routine is responsible for storing processed mbuf
3427 * into elts ring buffer and update elts_head.
3430 * Pointer to TX queue structure.
3432 * Pointer to burst routine local context.
3434 * Configured Tx offloads mask. It is fully defined at
3435 * compile time and may be used for optimization.
3438 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3439 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3440 * Local context variables partially updated.
3442 static __rte_always_inline enum mlx5_txcmp_code
3443 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3444 struct mlx5_txq_local *__rte_restrict loc,
3447 struct mlx5_wqe *__rte_restrict wqe;
3448 unsigned int ds, inlen, dlen, vlan = 0;
3450 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3451 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3452 if (MLX5_TXOFF_CONFIG(TXPP)) {
3453 enum mlx5_txcmp_code wret;
3455 /* Generate WAIT for scheduling if requested. */
3456 wret = mlx5_tx_schedule_send(txq, loc, olx);
3457 if (wret == MLX5_TXCMP_CODE_EXIT)
3458 return MLX5_TXCMP_CODE_EXIT;
3459 if (wret == MLX5_TXCMP_CODE_ERROR)
3460 return MLX5_TXCMP_CODE_ERROR;
3463 * First calculate data length to be inlined
3464 * to estimate the required space for WQE.
3466 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3467 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3468 vlan = sizeof(struct rte_vlan_hdr);
3469 inlen = dlen + vlan;
3470 /* Check against minimal length. */
3471 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3472 return MLX5_TXCMP_CODE_ERROR;
3473 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3474 if (inlen > txq->inlen_send ||
3475 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3476 struct rte_mbuf *mbuf;
3481 * Packet length exceeds the allowed inline
3482 * data length, check whether the minimal
3483 * inlining is required.
3485 if (txq->inlen_mode) {
3486 MLX5_ASSERT(txq->inlen_mode >=
3487 MLX5_ESEG_MIN_INLINE_SIZE);
3488 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3489 inlen = txq->inlen_mode;
3491 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3492 !vlan || txq->vlan_en) {
3494 * VLAN insertion will be done inside by HW.
3495 * It is not utmost effective - VLAN flag is
3496 * checked twice, but we should proceed the
3497 * inlining length correctly and take into
3498 * account the VLAN header being inserted.
3500 return mlx5_tx_packet_multi_send
3503 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3506 * Now we know the minimal amount of data is requested
3507 * to inline. Check whether we should inline the buffers
3508 * from the chain beginning to eliminate some mbufs.
3511 nxlen = rte_pktmbuf_data_len(mbuf);
3512 if (unlikely(nxlen <= txq->inlen_send)) {
3513 /* We can inline first mbuf at least. */
3514 if (nxlen < inlen) {
3517 /* Scan mbufs till inlen filled. */
3522 nxlen = rte_pktmbuf_data_len(mbuf);
3524 } while (unlikely(nxlen < inlen));
3525 if (unlikely(nxlen > txq->inlen_send)) {
3526 /* We cannot inline entire mbuf. */
3527 smlen = inlen - smlen;
3528 start = rte_pktmbuf_mtod_offset
3529 (mbuf, uintptr_t, smlen);
3536 /* There should be not end of packet. */
3538 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3539 } while (unlikely(nxlen < txq->inlen_send));
3541 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3543 * Check whether we can do inline to align start
3544 * address of data buffer to cacheline.
3547 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3548 if (unlikely(start)) {
3550 if (start <= txq->inlen_send)
3555 * Check whether there are enough free WQEBBs:
3557 * - Ethernet Segment
3558 * - First Segment of inlined Ethernet data
3559 * - ... data continued ...
3560 * - Data Segments of pointer/min inline type
3562 * Estimate the number of Data Segments conservatively,
3563 * supposing no any mbufs is being freed during inlining.
3565 MLX5_ASSERT(inlen <= txq->inlen_send);
3566 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3567 MLX5_ESEG_MIN_INLINE_SIZE +
3569 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3570 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3571 return MLX5_TXCMP_CODE_EXIT;
3572 /* Check for maximal WQE size. */
3573 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3574 return MLX5_TXCMP_CODE_ERROR;
3575 #ifdef MLX5_PMD_SOFT_COUNTERS
3576 /* Update sent data bytes/packets counters. */
3577 txq->stats.obytes += dlen + vlan;
3579 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3580 loc->wqe_last = wqe;
3581 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3582 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3583 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3584 txq->wqe_ci += (ds + 3) / 4;
3585 loc->wqe_free -= (ds + 3) / 4;
3586 return MLX5_TXCMP_CODE_MULTI;
3590 * Tx burst function for multi-segment packets. Supports all
3591 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3592 * sends one packet per WQE. Function stops sending if it
3593 * encounters the single-segment packet.
3595 * This routine is responsible for storing processed mbuf
3596 * into elts ring buffer and update elts_head.
3599 * Pointer to TX queue structure.
3601 * Packets to transmit.
3603 * Number of packets in array.
3605 * Pointer to burst routine local context.
3607 * Configured Tx offloads mask. It is fully defined at
3608 * compile time and may be used for optimization.
3611 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3612 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3613 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3614 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3615 * Local context variables updated.
3617 static __rte_always_inline enum mlx5_txcmp_code
3618 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3619 struct rte_mbuf **__rte_restrict pkts,
3620 unsigned int pkts_n,
3621 struct mlx5_txq_local *__rte_restrict loc,
3624 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3625 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3626 pkts += loc->pkts_sent + 1;
3627 pkts_n -= loc->pkts_sent;
3629 enum mlx5_txcmp_code ret;
3631 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3633 * Estimate the number of free elts quickly but
3634 * conservatively. Some segment may be fully inlined
3635 * and freed, ignore this here - precise estimation
3638 if (loc->elts_free < NB_SEGS(loc->mbuf))
3639 return MLX5_TXCMP_CODE_EXIT;
3640 if (MLX5_TXOFF_CONFIG(TSO) &&
3641 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3642 /* Proceed with multi-segment TSO. */
3643 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3644 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3645 /* Proceed with multi-segment SEND with inlining. */
3646 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3648 /* Proceed with multi-segment SEND w/o inlining. */
3649 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3651 if (ret == MLX5_TXCMP_CODE_EXIT)
3652 return MLX5_TXCMP_CODE_EXIT;
3653 if (ret == MLX5_TXCMP_CODE_ERROR)
3654 return MLX5_TXCMP_CODE_ERROR;
3655 /* WQE is built, go to the next packet. */
3658 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3659 return MLX5_TXCMP_CODE_EXIT;
3660 loc->mbuf = *pkts++;
3662 rte_prefetch0(*pkts);
3663 if (likely(NB_SEGS(loc->mbuf) > 1))
3665 /* Here ends the series of multi-segment packets. */
3666 if (MLX5_TXOFF_CONFIG(TSO) &&
3667 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3668 return MLX5_TXCMP_CODE_TSO;
3669 return MLX5_TXCMP_CODE_SINGLE;
3675 * Tx burst function for single-segment packets with TSO.
3676 * Supports all types of Tx offloads, except multi-packets.
3677 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3678 * Function stops sending if it encounters the multi-segment
3679 * packet or packet without TSO requested.
3681 * The routine is responsible for storing processed mbuf
3682 * into elts ring buffer and update elts_head if inline
3683 * offloads is requested due to possible early freeing
3684 * of the inlined mbufs (can not store pkts array in elts
3688 * Pointer to TX queue structure.
3690 * Packets to transmit.
3692 * Number of packets in array.
3694 * Pointer to burst routine local context.
3696 * Configured Tx offloads mask. It is fully defined at
3697 * compile time and may be used for optimization.
3700 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3701 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3702 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3703 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3704 * Local context variables updated.
3706 static __rte_always_inline enum mlx5_txcmp_code
3707 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3708 struct rte_mbuf **__rte_restrict pkts,
3709 unsigned int pkts_n,
3710 struct mlx5_txq_local *__rte_restrict loc,
3713 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3714 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3715 pkts += loc->pkts_sent + 1;
3716 pkts_n -= loc->pkts_sent;
3718 struct mlx5_wqe_dseg *__rte_restrict dseg;
3719 struct mlx5_wqe *__rte_restrict wqe;
3720 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3723 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3724 if (MLX5_TXOFF_CONFIG(TXPP)) {
3725 enum mlx5_txcmp_code wret;
3727 /* Generate WAIT for scheduling if requested. */
3728 wret = mlx5_tx_schedule_send(txq, loc, olx);
3729 if (wret == MLX5_TXCMP_CODE_EXIT)
3730 return MLX5_TXCMP_CODE_EXIT;
3731 if (wret == MLX5_TXCMP_CODE_ERROR)
3732 return MLX5_TXCMP_CODE_ERROR;
3734 dlen = rte_pktmbuf_data_len(loc->mbuf);
3735 if (MLX5_TXOFF_CONFIG(VLAN) &&
3736 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3737 vlan = sizeof(struct rte_vlan_hdr);
3740 * First calculate the WQE size to check
3741 * whether we have enough space in ring buffer.
3743 hlen = loc->mbuf->l2_len + vlan +
3744 loc->mbuf->l3_len + loc->mbuf->l4_len;
3745 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3746 return MLX5_TXCMP_CODE_ERROR;
3747 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3748 hlen += loc->mbuf->outer_l2_len +
3749 loc->mbuf->outer_l3_len;
3750 /* Segment must contain all TSO headers. */
3751 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3752 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3753 hlen > (dlen + vlan)))
3754 return MLX5_TXCMP_CODE_ERROR;
3756 * Check whether there are enough free WQEBBs:
3758 * - Ethernet Segment
3759 * - First Segment of inlined Ethernet data
3760 * - ... data continued ...
3761 * - Finishing Data Segment of pointer type
3763 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3764 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3765 if (loc->wqe_free < ((ds + 3) / 4))
3766 return MLX5_TXCMP_CODE_EXIT;
3767 #ifdef MLX5_PMD_SOFT_COUNTERS
3768 /* Update sent data bytes/packets counters. */
3769 ntcp = (dlen + vlan - hlen +
3770 loc->mbuf->tso_segsz - 1) /
3771 loc->mbuf->tso_segsz;
3773 * One will be added for mbuf itself at the end
3774 * of the mlx5_tx_burst from loc->pkts_sent field.
3777 txq->stats.opackets += ntcp;
3778 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3781 * Build the TSO WQE:
3783 * - Ethernet Segment with hlen bytes inlined
3784 * - Data Segment of pointer type
3786 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3787 loc->wqe_last = wqe;
3788 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3789 MLX5_OPCODE_TSO, olx);
3790 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3791 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3792 dlen -= hlen - vlan;
3793 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3795 * WQE is built, update the loop parameters
3796 * and go to the next packet.
3798 txq->wqe_ci += (ds + 3) / 4;
3799 loc->wqe_free -= (ds + 3) / 4;
3800 if (MLX5_TXOFF_CONFIG(INLINE))
3801 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3805 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3806 return MLX5_TXCMP_CODE_EXIT;
3807 loc->mbuf = *pkts++;
3809 rte_prefetch0(*pkts);
3810 if (MLX5_TXOFF_CONFIG(MULTI) &&
3811 unlikely(NB_SEGS(loc->mbuf) > 1))
3812 return MLX5_TXCMP_CODE_MULTI;
3813 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3814 return MLX5_TXCMP_CODE_SINGLE;
3815 /* Continue with the next TSO packet. */
3821 * Analyze the packet and select the best method to send.
3824 * Pointer to TX queue structure.
3826 * Pointer to burst routine local context.
3828 * Configured Tx offloads mask. It is fully defined at
3829 * compile time and may be used for optimization.
3831 * The predefined flag whether do complete check for
3832 * multi-segment packets and TSO.
3835 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3836 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3837 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3838 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3840 static __rte_always_inline enum mlx5_txcmp_code
3841 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3842 struct mlx5_txq_local *__rte_restrict loc,
3846 /* Check for multi-segment packet. */
3848 MLX5_TXOFF_CONFIG(MULTI) &&
3849 unlikely(NB_SEGS(loc->mbuf) > 1))
3850 return MLX5_TXCMP_CODE_MULTI;
3851 /* Check for TSO packet. */
3853 MLX5_TXOFF_CONFIG(TSO) &&
3854 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3855 return MLX5_TXCMP_CODE_TSO;
3856 /* Check if eMPW is enabled at all. */
3857 if (!MLX5_TXOFF_CONFIG(EMPW))
3858 return MLX5_TXCMP_CODE_SINGLE;
3859 /* Check if eMPW can be engaged. */
3860 if (MLX5_TXOFF_CONFIG(VLAN) &&
3861 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3862 (!MLX5_TXOFF_CONFIG(INLINE) ||
3863 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3864 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3866 * eMPW does not support VLAN insertion offload,
3867 * we have to inline the entire packet but
3868 * packet is too long for inlining.
3870 return MLX5_TXCMP_CODE_SINGLE;
3872 return MLX5_TXCMP_CODE_EMPW;
3876 * Check the next packet attributes to match with the eMPW batch ones.
3877 * In addition, for legacy MPW the packet length is checked either.
3880 * Pointer to TX queue structure.
3882 * Pointer to Ethernet Segment of eMPW batch.
3884 * Pointer to burst routine local context.
3886 * Length of previous packet in MPW descriptor.
3888 * Configured Tx offloads mask. It is fully defined at
3889 * compile time and may be used for optimization.
3892 * true - packet match with eMPW batch attributes.
3893 * false - no match, eMPW should be restarted.
3895 static __rte_always_inline bool
3896 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3897 struct mlx5_wqe_eseg *__rte_restrict es,
3898 struct mlx5_txq_local *__rte_restrict loc,
3902 uint8_t swp_flags = 0;
3904 /* Compare the checksum flags, if any. */
3905 if (MLX5_TXOFF_CONFIG(CSUM) &&
3906 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3908 /* Compare the Software Parser offsets and flags. */
3909 if (MLX5_TXOFF_CONFIG(SWP) &&
3910 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3911 es->swp_flags != swp_flags))
3913 /* Fill metadata field if needed. */
3914 if (MLX5_TXOFF_CONFIG(METADATA) &&
3915 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3916 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3918 /* Legacy MPW can send packets with the same lengt only. */
3919 if (MLX5_TXOFF_CONFIG(MPW) &&
3920 dlen != rte_pktmbuf_data_len(loc->mbuf))
3922 /* There must be no VLAN packets in eMPW loop. */
3923 if (MLX5_TXOFF_CONFIG(VLAN))
3924 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3925 /* Check if the scheduling is requested. */
3926 if (MLX5_TXOFF_CONFIG(TXPP) &&
3927 loc->mbuf->ol_flags & txq->ts_mask)
3933 * Update send loop variables and WQE for eMPW loop
3934 * without data inlining. Number of Data Segments is
3935 * equal to the number of sent packets.
3938 * Pointer to TX queue structure.
3940 * Pointer to burst routine local context.
3942 * Number of packets/Data Segments/Packets.
3944 * Accumulated statistics, bytes sent
3946 * Configured Tx offloads mask. It is fully defined at
3947 * compile time and may be used for optimization.
3950 * true - packet match with eMPW batch attributes.
3951 * false - no match, eMPW should be restarted.
3953 static __rte_always_inline void
3954 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3955 struct mlx5_txq_local *__rte_restrict loc,
3958 unsigned int olx __rte_unused)
3960 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3961 #ifdef MLX5_PMD_SOFT_COUNTERS
3962 /* Update sent data bytes counter. */
3963 txq->stats.obytes += slen;
3967 loc->elts_free -= ds;
3968 loc->pkts_sent += ds;
3970 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3971 txq->wqe_ci += (ds + 3) / 4;
3972 loc->wqe_free -= (ds + 3) / 4;
3976 * Update send loop variables and WQE for eMPW loop
3977 * with data inlining. Gets the size of pushed descriptors
3978 * and data to the WQE.
3981 * Pointer to TX queue structure.
3983 * Pointer to burst routine local context.
3985 * Total size of descriptor/data in bytes.
3987 * Accumulated statistics, data bytes sent.
3989 * The base WQE for the eMPW/MPW descriptor.
3991 * Configured Tx offloads mask. It is fully defined at
3992 * compile time and may be used for optimization.
3995 * true - packet match with eMPW batch attributes.
3996 * false - no match, eMPW should be restarted.
3998 static __rte_always_inline void
3999 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
4000 struct mlx5_txq_local *__rte_restrict loc,
4003 struct mlx5_wqe *__rte_restrict wqem,
4004 unsigned int olx __rte_unused)
4006 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
4008 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4009 #ifdef MLX5_PMD_SOFT_COUNTERS
4010 /* Update sent data bytes counter. */
4011 txq->stats.obytes += slen;
4015 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
4017 * If the legacy MPW session contains the inline packets
4018 * we should set the only inline data segment length
4019 * and align the total length to the segment size.
4021 MLX5_ASSERT(len > sizeof(dseg->bcount));
4022 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
4023 MLX5_ETH_WQE_DATA_INLINE);
4024 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
4027 * The session is not legacy MPW or contains the
4028 * data buffer pointer segments.
4030 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
4031 len = len / MLX5_WSEG_SIZE + 2;
4033 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
4034 txq->wqe_ci += (len + 3) / 4;
4035 loc->wqe_free -= (len + 3) / 4;
4036 loc->wqe_last = wqem;
4040 * The set of Tx burst functions for single-segment packets
4041 * without TSO and with Multi-Packet Writing feature support.
4042 * Supports all types of Tx offloads, except multi-packets
4045 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4046 * as many packet per WQE as it can. If eMPW is not configured
4047 * or packet can not be sent with eMPW (VLAN insertion) the
4048 * ordinary SEND opcode is used and only one packet placed
4051 * Functions stop sending if it encounters the multi-segment
4052 * packet or packet with TSO requested.
4054 * The routines are responsible for storing processed mbuf
4055 * into elts ring buffer and update elts_head if inlining
4056 * offload is requested. Otherwise the copying mbufs to elts
4057 * can be postponed and completed at the end of burst routine.
4060 * Pointer to TX queue structure.
4062 * Packets to transmit.
4064 * Number of packets in array.
4066 * Pointer to burst routine local context.
4068 * Configured Tx offloads mask. It is fully defined at
4069 * compile time and may be used for optimization.
4072 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4073 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4074 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4075 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4076 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4077 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4079 * Local context variables updated.
4082 * The routine sends packets with MLX5_OPCODE_EMPW
4083 * without inlining, this is dedicated optimized branch.
4084 * No VLAN insertion is supported.
4086 static __rte_always_inline enum mlx5_txcmp_code
4087 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4088 struct rte_mbuf **__rte_restrict pkts,
4089 unsigned int pkts_n,
4090 struct mlx5_txq_local *__rte_restrict loc,
4094 * Subroutine is the part of mlx5_tx_burst_single()
4095 * and sends single-segment packet with eMPW opcode
4096 * without data inlining.
4098 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4099 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4100 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4101 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4102 pkts += loc->pkts_sent + 1;
4103 pkts_n -= loc->pkts_sent;
4105 struct mlx5_wqe_dseg *__rte_restrict dseg;
4106 struct mlx5_wqe_eseg *__rte_restrict eseg;
4107 enum mlx5_txcmp_code ret;
4108 unsigned int part, loop;
4109 unsigned int slen = 0;
4112 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4113 if (MLX5_TXOFF_CONFIG(TXPP)) {
4114 enum mlx5_txcmp_code wret;
4116 /* Generate WAIT for scheduling if requested. */
4117 wret = mlx5_tx_schedule_send(txq, loc, olx);
4118 if (wret == MLX5_TXCMP_CODE_EXIT)
4119 return MLX5_TXCMP_CODE_EXIT;
4120 if (wret == MLX5_TXCMP_CODE_ERROR)
4121 return MLX5_TXCMP_CODE_ERROR;
4123 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4124 MLX5_MPW_MAX_PACKETS :
4125 MLX5_EMPW_MAX_PACKETS);
4126 if (unlikely(loc->elts_free < part)) {
4127 /* We have no enough elts to save all mbufs. */
4128 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4129 return MLX5_TXCMP_CODE_EXIT;
4130 /* But we still able to send at least minimal eMPW. */
4131 part = loc->elts_free;
4133 /* Check whether we have enough WQEs */
4134 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4135 if (unlikely(loc->wqe_free <
4136 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4137 return MLX5_TXCMP_CODE_EXIT;
4138 part = (loc->wqe_free * 4) - 2;
4140 if (likely(part > 1))
4141 rte_prefetch0(*pkts);
4142 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4144 * Build eMPW title WQEBB:
4145 * - Control Segment, eMPW opcode
4146 * - Ethernet Segment, no inline
4148 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4149 MLX5_OPCODE_ENHANCED_MPSW, olx);
4150 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4151 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4152 eseg = &loc->wqe_last->eseg;
4153 dseg = &loc->wqe_last->dseg[0];
4155 /* Store the packet length for legacy MPW. */
4156 if (MLX5_TXOFF_CONFIG(MPW))
4157 eseg->mss = rte_cpu_to_be_16
4158 (rte_pktmbuf_data_len(loc->mbuf));
4160 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4161 #ifdef MLX5_PMD_SOFT_COUNTERS
4162 /* Update sent data bytes counter. */
4167 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4169 if (unlikely(--loop == 0))
4171 loc->mbuf = *pkts++;
4172 if (likely(loop > 1))
4173 rte_prefetch0(*pkts);
4174 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4176 * Unroll the completion code to avoid
4177 * returning variable value - it results in
4178 * unoptimized sequent checking in caller.
4180 if (ret == MLX5_TXCMP_CODE_MULTI) {
4182 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4183 if (unlikely(!loc->elts_free ||
4185 return MLX5_TXCMP_CODE_EXIT;
4186 return MLX5_TXCMP_CODE_MULTI;
4188 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4189 if (ret == MLX5_TXCMP_CODE_TSO) {
4191 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4192 if (unlikely(!loc->elts_free ||
4194 return MLX5_TXCMP_CODE_EXIT;
4195 return MLX5_TXCMP_CODE_TSO;
4197 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4199 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4200 if (unlikely(!loc->elts_free ||
4202 return MLX5_TXCMP_CODE_EXIT;
4203 return MLX5_TXCMP_CODE_SINGLE;
4205 if (ret != MLX5_TXCMP_CODE_EMPW) {
4208 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4209 return MLX5_TXCMP_CODE_ERROR;
4212 * Check whether packet parameters coincide
4213 * within assumed eMPW batch:
4214 * - check sum settings
4216 * - software parser settings
4217 * - packets length (legacy MPW only)
4218 * - scheduling is not required
4220 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4223 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4224 if (unlikely(!loc->elts_free ||
4226 return MLX5_TXCMP_CODE_EXIT;
4230 /* Packet attributes match, continue the same eMPW. */
4232 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4233 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4235 /* eMPW is built successfully, update loop parameters. */
4237 MLX5_ASSERT(pkts_n >= part);
4238 #ifdef MLX5_PMD_SOFT_COUNTERS
4239 /* Update sent data bytes counter. */
4240 txq->stats.obytes += slen;
4242 loc->elts_free -= part;
4243 loc->pkts_sent += part;
4244 txq->wqe_ci += (2 + part + 3) / 4;
4245 loc->wqe_free -= (2 + part + 3) / 4;
4247 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4248 return MLX5_TXCMP_CODE_EXIT;
4249 loc->mbuf = *pkts++;
4250 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4251 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4253 /* Continue sending eMPW batches. */
4259 * The routine sends packets with MLX5_OPCODE_EMPW
4260 * with inlining, optionally supports VLAN insertion.
4262 static __rte_always_inline enum mlx5_txcmp_code
4263 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4264 struct rte_mbuf **__rte_restrict pkts,
4265 unsigned int pkts_n,
4266 struct mlx5_txq_local *__rte_restrict loc,
4270 * Subroutine is the part of mlx5_tx_burst_single()
4271 * and sends single-segment packet with eMPW opcode
4272 * with data inlining.
4274 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4275 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4276 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4277 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4278 pkts += loc->pkts_sent + 1;
4279 pkts_n -= loc->pkts_sent;
4281 struct mlx5_wqe_dseg *__rte_restrict dseg;
4282 struct mlx5_wqe *__rte_restrict wqem;
4283 enum mlx5_txcmp_code ret;
4284 unsigned int room, part, nlim;
4285 unsigned int slen = 0;
4287 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4288 if (MLX5_TXOFF_CONFIG(TXPP)) {
4289 enum mlx5_txcmp_code wret;
4291 /* Generate WAIT for scheduling if requested. */
4292 wret = mlx5_tx_schedule_send(txq, loc, olx);
4293 if (wret == MLX5_TXCMP_CODE_EXIT)
4294 return MLX5_TXCMP_CODE_EXIT;
4295 if (wret == MLX5_TXCMP_CODE_ERROR)
4296 return MLX5_TXCMP_CODE_ERROR;
4299 * Limits the amount of packets in one WQE
4300 * to improve CQE latency generation.
4302 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4303 MLX5_MPW_INLINE_MAX_PACKETS :
4304 MLX5_EMPW_MAX_PACKETS);
4305 /* Check whether we have minimal amount WQEs */
4306 if (unlikely(loc->wqe_free <
4307 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4308 return MLX5_TXCMP_CODE_EXIT;
4309 if (likely(pkts_n > 1))
4310 rte_prefetch0(*pkts);
4311 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4313 * Build eMPW title WQEBB:
4314 * - Control Segment, eMPW opcode, zero DS
4315 * - Ethernet Segment, no inline
4317 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4318 MLX5_OPCODE_ENHANCED_MPSW, olx);
4319 mlx5_tx_eseg_none(txq, loc, wqem,
4320 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4321 dseg = &wqem->dseg[0];
4322 /* Store the packet length for legacy MPW. */
4323 if (MLX5_TXOFF_CONFIG(MPW))
4324 wqem->eseg.mss = rte_cpu_to_be_16
4325 (rte_pktmbuf_data_len(loc->mbuf));
4326 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4327 loc->wqe_free) * MLX5_WQE_SIZE -
4328 MLX5_WQE_CSEG_SIZE -
4330 /* Limit the room for legacy MPW sessions for performance. */
4331 if (MLX5_TXOFF_CONFIG(MPW))
4332 room = RTE_MIN(room,
4333 RTE_MAX(txq->inlen_empw +
4334 sizeof(dseg->bcount) +
4335 (MLX5_TXOFF_CONFIG(VLAN) ?
4336 sizeof(struct rte_vlan_hdr) : 0),
4337 MLX5_MPW_INLINE_MAX_PACKETS *
4338 MLX5_WQE_DSEG_SIZE));
4339 /* Build WQE till we have space, packets and resources. */
4342 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4343 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4346 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4347 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4348 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4350 * Some Tx offloads may cause an error if
4351 * packet is not long enough, check against
4352 * assumed minimal length.
4354 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4356 if (unlikely(!part))
4357 return MLX5_TXCMP_CODE_ERROR;
4359 * We have some successfully built
4360 * packet Data Segments to send.
4362 mlx5_tx_idone_empw(txq, loc, part,
4364 return MLX5_TXCMP_CODE_ERROR;
4366 /* Inline or not inline - that's the Question. */
4367 if (dlen > txq->inlen_empw ||
4368 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4370 if (MLX5_TXOFF_CONFIG(MPW)) {
4371 if (dlen > txq->inlen_send)
4375 /* Open new inline MPW session. */
4376 tlen += sizeof(dseg->bcount);
4377 dseg->bcount = RTE_BE32(0);
4379 (dseg, sizeof(dseg->bcount));
4382 * No pointer and inline descriptor
4383 * intermix for legacy MPW sessions.
4385 if (wqem->dseg[0].bcount)
4389 tlen = sizeof(dseg->bcount) + dlen;
4391 /* Inline entire packet, optional VLAN insertion. */
4392 if (MLX5_TXOFF_CONFIG(VLAN) &&
4393 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4395 * The packet length must be checked in
4396 * mlx5_tx_able_to_empw() and packet
4397 * fits into inline length guaranteed.
4400 sizeof(struct rte_vlan_hdr)) <=
4402 tlen += sizeof(struct rte_vlan_hdr);
4405 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4407 #ifdef MLX5_PMD_SOFT_COUNTERS
4408 /* Update sent data bytes counter. */
4409 slen += sizeof(struct rte_vlan_hdr);
4414 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4417 if (!MLX5_TXOFF_CONFIG(MPW))
4418 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4419 MLX5_ASSERT(room >= tlen);
4422 * Packet data are completely inline,
4423 * we can try to free the packet.
4425 if (likely(loc->pkts_sent == loc->mbuf_free)) {
4427 * All the packets from the burst beginning
4428 * are inline, we can free mbufs directly
4429 * from the origin array on tx_burst exit().
4435 * In order no to call rte_pktmbuf_free_seg() here,
4436 * in the most inner loop (that might be very
4437 * expensive) we just save the mbuf in elts.
4439 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4444 * No pointer and inline descriptor
4445 * intermix for legacy MPW sessions.
4447 if (MLX5_TXOFF_CONFIG(MPW) &&
4449 wqem->dseg[0].bcount == RTE_BE32(0))
4452 * Not inlinable VLAN packets are
4453 * proceeded outside of this routine.
4455 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4456 if (MLX5_TXOFF_CONFIG(VLAN))
4457 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4459 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4460 /* We have to store mbuf in elts.*/
4461 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4463 room -= MLX5_WQE_DSEG_SIZE;
4464 /* Ring buffer wraparound is checked at the loop end.*/
4467 #ifdef MLX5_PMD_SOFT_COUNTERS
4468 /* Update sent data bytes counter. */
4473 if (unlikely(!pkts_n || !loc->elts_free)) {
4475 * We have no resources/packets to
4476 * continue build descriptors.
4479 mlx5_tx_idone_empw(txq, loc, part,
4481 return MLX5_TXCMP_CODE_EXIT;
4483 loc->mbuf = *pkts++;
4484 if (likely(pkts_n > 1))
4485 rte_prefetch0(*pkts);
4486 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4488 * Unroll the completion code to avoid
4489 * returning variable value - it results in
4490 * unoptimized sequent checking in caller.
4492 if (ret == MLX5_TXCMP_CODE_MULTI) {
4494 mlx5_tx_idone_empw(txq, loc, part,
4496 if (unlikely(!loc->elts_free ||
4498 return MLX5_TXCMP_CODE_EXIT;
4499 return MLX5_TXCMP_CODE_MULTI;
4501 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4502 if (ret == MLX5_TXCMP_CODE_TSO) {
4504 mlx5_tx_idone_empw(txq, loc, part,
4506 if (unlikely(!loc->elts_free ||
4508 return MLX5_TXCMP_CODE_EXIT;
4509 return MLX5_TXCMP_CODE_TSO;
4511 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4513 mlx5_tx_idone_empw(txq, loc, part,
4515 if (unlikely(!loc->elts_free ||
4517 return MLX5_TXCMP_CODE_EXIT;
4518 return MLX5_TXCMP_CODE_SINGLE;
4520 if (ret != MLX5_TXCMP_CODE_EMPW) {
4523 mlx5_tx_idone_empw(txq, loc, part,
4525 return MLX5_TXCMP_CODE_ERROR;
4527 /* Check if we have minimal room left. */
4529 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4532 * Check whether packet parameters coincide
4533 * within assumed eMPW batch:
4534 * - check sum settings
4536 * - software parser settings
4537 * - packets length (legacy MPW only)
4538 * - scheduling is not required
4540 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4543 /* Packet attributes match, continue the same eMPW. */
4544 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4545 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4548 * We get here to close an existing eMPW
4549 * session and start the new one.
4551 MLX5_ASSERT(pkts_n);
4553 if (unlikely(!part))
4554 return MLX5_TXCMP_CODE_EXIT;
4555 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4556 if (unlikely(!loc->elts_free ||
4558 return MLX5_TXCMP_CODE_EXIT;
4559 /* Continue the loop with new eMPW session. */
4565 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4566 * Data inlining and VLAN insertion are supported.
4568 static __rte_always_inline enum mlx5_txcmp_code
4569 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4570 struct rte_mbuf **__rte_restrict pkts,
4571 unsigned int pkts_n,
4572 struct mlx5_txq_local *__rte_restrict loc,
4576 * Subroutine is the part of mlx5_tx_burst_single()
4577 * and sends single-segment packet with SEND opcode.
4579 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4580 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4581 pkts += loc->pkts_sent + 1;
4582 pkts_n -= loc->pkts_sent;
4584 struct mlx5_wqe *__rte_restrict wqe;
4585 enum mlx5_txcmp_code ret;
4587 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4588 if (MLX5_TXOFF_CONFIG(TXPP)) {
4589 enum mlx5_txcmp_code wret;
4591 /* Generate WAIT for scheduling if requested. */
4592 wret = mlx5_tx_schedule_send(txq, loc, olx);
4593 if (wret == MLX5_TXCMP_CODE_EXIT)
4594 return MLX5_TXCMP_CODE_EXIT;
4595 if (wret == MLX5_TXCMP_CODE_ERROR)
4596 return MLX5_TXCMP_CODE_ERROR;
4598 if (MLX5_TXOFF_CONFIG(INLINE)) {
4599 unsigned int inlen, vlan = 0;
4601 inlen = rte_pktmbuf_data_len(loc->mbuf);
4602 if (MLX5_TXOFF_CONFIG(VLAN) &&
4603 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4604 vlan = sizeof(struct rte_vlan_hdr);
4608 * If inlining is enabled at configuration time
4609 * the limit must be not less than minimal size.
4610 * Otherwise we would do extra check for data
4611 * size to avoid crashes due to length overflow.
4613 MLX5_ASSERT(txq->inlen_send >=
4614 MLX5_ESEG_MIN_INLINE_SIZE);
4615 if (inlen <= txq->inlen_send) {
4616 unsigned int seg_n, wqe_n;
4618 rte_prefetch0(rte_pktmbuf_mtod
4619 (loc->mbuf, uint8_t *));
4620 /* Check against minimal length. */
4621 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4622 return MLX5_TXCMP_CODE_ERROR;
4623 if (loc->mbuf->ol_flags &
4624 PKT_TX_DYNF_NOINLINE) {
4626 * The hint flag not to inline packet
4627 * data is set. Check whether we can
4630 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4632 (MLX5_TXOFF_CONFIG(MPW) &&
4634 if (inlen <= txq->inlen_send)
4637 * The hardware requires the
4638 * minimal inline data header.
4640 goto single_min_inline;
4642 if (MLX5_TXOFF_CONFIG(VLAN) &&
4643 vlan && !txq->vlan_en) {
4645 * We must insert VLAN tag
4646 * by software means.
4648 goto single_part_inline;
4650 goto single_no_inline;
4654 * Completely inlined packet data WQE:
4655 * - Control Segment, SEND opcode
4656 * - Ethernet Segment, no VLAN insertion
4657 * - Data inlined, VLAN optionally inserted
4658 * - Alignment to MLX5_WSEG_SIZE
4659 * Have to estimate amount of WQEBBs
4661 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4662 MLX5_ESEG_MIN_INLINE_SIZE +
4663 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4664 /* Check if there are enough WQEBBs. */
4665 wqe_n = (seg_n + 3) / 4;
4666 if (wqe_n > loc->wqe_free)
4667 return MLX5_TXCMP_CODE_EXIT;
4668 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4669 loc->wqe_last = wqe;
4670 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4671 MLX5_OPCODE_SEND, olx);
4672 mlx5_tx_eseg_data(txq, loc, wqe,
4673 vlan, inlen, 0, olx);
4674 txq->wqe_ci += wqe_n;
4675 loc->wqe_free -= wqe_n;
4677 * Packet data are completely inlined,
4678 * free the packet immediately.
4680 rte_pktmbuf_free_seg(loc->mbuf);
4681 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4682 MLX5_TXOFF_CONFIG(MPW)) &&
4685 * If minimal inlining is requested the eMPW
4686 * feature should be disabled due to data is
4687 * inlined into Ethernet Segment, which can
4688 * not contain inlined data for eMPW due to
4689 * segment shared for all packets.
4691 struct mlx5_wqe_dseg *__rte_restrict dseg;
4696 * The inline-mode settings require
4697 * to inline the specified amount of
4698 * data bytes to the Ethernet Segment.
4699 * We should check the free space in
4700 * WQE ring buffer to inline partially.
4703 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4704 MLX5_ASSERT(inlen > txq->inlen_mode);
4705 MLX5_ASSERT(txq->inlen_mode >=
4706 MLX5_ESEG_MIN_INLINE_SIZE);
4708 * Check whether there are enough free WQEBBs:
4710 * - Ethernet Segment
4711 * - First Segment of inlined Ethernet data
4712 * - ... data continued ...
4713 * - Finishing Data Segment of pointer type
4715 ds = (MLX5_WQE_CSEG_SIZE +
4716 MLX5_WQE_ESEG_SIZE +
4717 MLX5_WQE_DSEG_SIZE +
4719 MLX5_ESEG_MIN_INLINE_SIZE +
4720 MLX5_WQE_DSEG_SIZE +
4721 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4722 if (loc->wqe_free < ((ds + 3) / 4))
4723 return MLX5_TXCMP_CODE_EXIT;
4725 * Build the ordinary SEND WQE:
4727 * - Ethernet Segment, inline inlen_mode bytes
4728 * - Data Segment of pointer type
4730 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4731 loc->wqe_last = wqe;
4732 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4733 MLX5_OPCODE_SEND, olx);
4734 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4737 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4738 txq->inlen_mode - vlan;
4739 inlen -= txq->inlen_mode;
4740 mlx5_tx_dseg_ptr(txq, loc, dseg,
4743 * WQE is built, update the loop parameters
4744 * and got to the next packet.
4746 txq->wqe_ci += (ds + 3) / 4;
4747 loc->wqe_free -= (ds + 3) / 4;
4748 /* We have to store mbuf in elts.*/
4749 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4750 txq->elts[txq->elts_head++ & txq->elts_m] =
4758 * Partially inlined packet data WQE, we have
4759 * some space in title WQEBB, we can fill it
4760 * with some packet data. It takes one WQEBB,
4761 * it is available, no extra space check:
4762 * - Control Segment, SEND opcode
4763 * - Ethernet Segment, no VLAN insertion
4764 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4765 * - Data Segment, pointer type
4767 * We also get here if VLAN insertion is not
4768 * supported by HW, the inline is enabled.
4771 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4772 loc->wqe_last = wqe;
4773 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4774 MLX5_OPCODE_SEND, olx);
4775 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4776 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4777 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4779 * The length check is performed above, by
4780 * comparing with txq->inlen_send. We should
4781 * not get overflow here.
4783 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4784 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4785 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4789 /* We have to store mbuf in elts.*/
4790 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4791 txq->elts[txq->elts_head++ & txq->elts_m] =
4795 #ifdef MLX5_PMD_SOFT_COUNTERS
4796 /* Update sent data bytes counter. */
4797 txq->stats.obytes += vlan +
4798 rte_pktmbuf_data_len(loc->mbuf);
4802 * No inline at all, it means the CPU cycles saving
4803 * is prioritized at configuration, we should not
4804 * copy any packet data to WQE.
4806 * SEND WQE, one WQEBB:
4807 * - Control Segment, SEND opcode
4808 * - Ethernet Segment, optional VLAN, no inline
4809 * - Data Segment, pointer type
4812 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4813 loc->wqe_last = wqe;
4814 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4815 MLX5_OPCODE_SEND, olx);
4816 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4818 (txq, loc, &wqe->dseg[0],
4819 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4820 rte_pktmbuf_data_len(loc->mbuf), olx);
4824 * We should not store mbuf pointer in elts
4825 * if no inlining is configured, this is done
4826 * by calling routine in a batch copy.
4828 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4830 #ifdef MLX5_PMD_SOFT_COUNTERS
4831 /* Update sent data bytes counter. */
4832 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4833 if (MLX5_TXOFF_CONFIG(VLAN) &&
4834 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4835 txq->stats.obytes +=
4836 sizeof(struct rte_vlan_hdr);
4841 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4842 return MLX5_TXCMP_CODE_EXIT;
4843 loc->mbuf = *pkts++;
4845 rte_prefetch0(*pkts);
4846 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4847 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4853 static __rte_always_inline enum mlx5_txcmp_code
4854 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4855 struct rte_mbuf **__rte_restrict pkts,
4856 unsigned int pkts_n,
4857 struct mlx5_txq_local *__rte_restrict loc,
4860 enum mlx5_txcmp_code ret;
4862 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4863 if (ret == MLX5_TXCMP_CODE_SINGLE)
4865 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4867 /* Optimize for inline/no inline eMPW send. */
4868 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4869 mlx5_tx_burst_empw_inline
4870 (txq, pkts, pkts_n, loc, olx) :
4871 mlx5_tx_burst_empw_simple
4872 (txq, pkts, pkts_n, loc, olx);
4873 if (ret != MLX5_TXCMP_CODE_SINGLE)
4875 /* The resources to send one packet should remain. */
4876 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4878 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4879 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4880 if (ret != MLX5_TXCMP_CODE_EMPW)
4882 /* The resources to send one packet should remain. */
4883 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4888 * DPDK Tx callback template. This is configured template
4889 * used to generate routines optimized for specified offload setup.
4890 * One of this generated functions is chosen at SQ configuration
4894 * Generic pointer to TX queue structure.
4896 * Packets to transmit.
4898 * Number of packets in array.
4900 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4901 * values. Should be static to take compile time static configuration
4905 * Number of packets successfully transmitted (<= pkts_n).
4907 static __rte_always_inline uint16_t
4908 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4909 struct rte_mbuf **__rte_restrict pkts,
4913 struct mlx5_txq_local loc;
4914 enum mlx5_txcmp_code ret;
4917 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4918 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4919 if (unlikely(!pkts_n))
4921 if (MLX5_TXOFF_CONFIG(INLINE))
4925 loc.wqe_last = NULL;
4928 loc.pkts_loop = loc.pkts_sent;
4930 * Check if there are some CQEs, if any:
4931 * - process an encountered errors
4932 * - process the completed WQEs
4933 * - free related mbufs
4934 * - doorbell the NIC about processed CQEs
4936 rte_prefetch0(*(pkts + loc.pkts_sent));
4937 mlx5_tx_handle_completion(txq, olx);
4939 * Calculate the number of available resources - elts and WQEs.
4940 * There are two possible different scenarios:
4941 * - no data inlining into WQEs, one WQEBB may contains up to
4942 * four packets, in this case elts become scarce resource
4943 * - data inlining into WQEs, one packet may require multiple
4944 * WQEBBs, the WQEs become the limiting factor.
4946 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4947 loc.elts_free = txq->elts_s -
4948 (uint16_t)(txq->elts_head - txq->elts_tail);
4949 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4950 loc.wqe_free = txq->wqe_s -
4951 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4952 if (unlikely(!loc.elts_free || !loc.wqe_free))
4956 * Fetch the packet from array. Usually this is
4957 * the first packet in series of multi/single
4960 loc.mbuf = *(pkts + loc.pkts_sent);
4961 /* Dedicated branch for multi-segment packets. */
4962 if (MLX5_TXOFF_CONFIG(MULTI) &&
4963 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4965 * Multi-segment packet encountered.
4966 * Hardware is able to process it only
4967 * with SEND/TSO opcodes, one packet
4968 * per WQE, do it in dedicated routine.
4971 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4972 part = loc.pkts_sent - loc.pkts_copy;
4973 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4975 * There are some single-segment mbufs not
4976 * stored in elts. The mbufs must be in the
4977 * same order as WQEs, so we must copy the
4978 * mbufs to elts here, before the coming
4979 * multi-segment packet mbufs is appended.
4981 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4983 loc.pkts_copy = loc.pkts_sent;
4985 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4986 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4987 if (!MLX5_TXOFF_CONFIG(INLINE))
4988 loc.pkts_copy = loc.pkts_sent;
4990 * These returned code checks are supposed
4991 * to be optimized out due to routine inlining.
4993 if (ret == MLX5_TXCMP_CODE_EXIT) {
4995 * The routine returns this code when
4996 * all packets are sent or there is no
4997 * enough resources to complete request.
5001 if (ret == MLX5_TXCMP_CODE_ERROR) {
5003 * The routine returns this code when
5004 * some error in the incoming packets
5007 txq->stats.oerrors++;
5010 if (ret == MLX5_TXCMP_CODE_SINGLE) {
5012 * The single-segment packet was encountered
5013 * in the array, try to send it with the
5014 * best optimized way, possible engaging eMPW.
5016 goto enter_send_single;
5018 if (MLX5_TXOFF_CONFIG(TSO) &&
5019 ret == MLX5_TXCMP_CODE_TSO) {
5021 * The single-segment TSO packet was
5022 * encountered in the array.
5024 goto enter_send_tso;
5026 /* We must not get here. Something is going wrong. */
5028 txq->stats.oerrors++;
5031 /* Dedicated branch for single-segment TSO packets. */
5032 if (MLX5_TXOFF_CONFIG(TSO) &&
5033 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
5035 * TSO might require special way for inlining
5036 * (dedicated parameters) and is sent with
5037 * MLX5_OPCODE_TSO opcode only, provide this
5038 * in dedicated branch.
5041 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
5042 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5043 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
5045 * These returned code checks are supposed
5046 * to be optimized out due to routine inlining.
5048 if (ret == MLX5_TXCMP_CODE_EXIT)
5050 if (ret == MLX5_TXCMP_CODE_ERROR) {
5051 txq->stats.oerrors++;
5054 if (ret == MLX5_TXCMP_CODE_SINGLE)
5055 goto enter_send_single;
5056 if (MLX5_TXOFF_CONFIG(MULTI) &&
5057 ret == MLX5_TXCMP_CODE_MULTI) {
5059 * The multi-segment packet was
5060 * encountered in the array.
5062 goto enter_send_multi;
5064 /* We must not get here. Something is going wrong. */
5066 txq->stats.oerrors++;
5070 * The dedicated branch for the single-segment packets
5071 * without TSO. Often these ones can be sent using
5072 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5073 * The routine builds the WQEs till it encounters
5074 * the TSO or multi-segment packet (in case if these
5075 * offloads are requested at SQ configuration time).
5078 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5079 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5081 * These returned code checks are supposed
5082 * to be optimized out due to routine inlining.
5084 if (ret == MLX5_TXCMP_CODE_EXIT)
5086 if (ret == MLX5_TXCMP_CODE_ERROR) {
5087 txq->stats.oerrors++;
5090 if (MLX5_TXOFF_CONFIG(MULTI) &&
5091 ret == MLX5_TXCMP_CODE_MULTI) {
5093 * The multi-segment packet was
5094 * encountered in the array.
5096 goto enter_send_multi;
5098 if (MLX5_TXOFF_CONFIG(TSO) &&
5099 ret == MLX5_TXCMP_CODE_TSO) {
5101 * The single-segment TSO packet was
5102 * encountered in the array.
5104 goto enter_send_tso;
5106 /* We must not get here. Something is going wrong. */
5108 txq->stats.oerrors++;
5112 * Main Tx loop is completed, do the rest:
5113 * - set completion request if thresholds are reached
5114 * - doorbell the hardware
5115 * - copy the rest of mbufs to elts (if any)
5117 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5118 loc.pkts_sent >= loc.pkts_copy);
5119 /* Take a shortcut if nothing is sent. */
5120 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5122 /* Request CQE generation if limits are reached. */
5123 mlx5_tx_request_completion(txq, &loc, olx);
5125 * Ring QP doorbell immediately after WQE building completion
5126 * to improve latencies. The pure software related data treatment
5127 * can be completed after doorbell. Tx CQEs for this SQ are
5128 * processed in this thread only by the polling.
5130 * The rdma core library can map doorbell register in two ways,
5131 * depending on the environment variable "MLX5_SHUT_UP_BF":
5133 * - as regular cached memory, the variable is either missing or
5134 * set to zero. This type of mapping may cause the significant
5135 * doorbell register writing latency and requires explicit
5136 * memory write barrier to mitigate this issue and prevent
5139 * - as non-cached memory, the variable is present and set to
5140 * not "0" value. This type of mapping may cause performance
5141 * impact under heavy loading conditions but the explicit write
5142 * memory barrier is not required and it may improve core
5145 * - the legacy behaviour (prior 19.08 release) was to use some
5146 * heuristics to decide whether write memory barrier should
5147 * be performed. This behavior is supported with specifying
5148 * tx_db_nc=2, write barrier is skipped if application
5149 * provides the full recommended burst of packets, it
5150 * supposes the next packets are coming and the write barrier
5151 * will be issued on the next burst (after descriptor writing,
5154 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5155 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5156 /* Not all of the mbufs may be stored into elts yet. */
5157 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5158 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5160 * There are some single-segment mbufs not stored in elts.
5161 * It can be only if the last packet was single-segment.
5162 * The copying is gathered into one place due to it is
5163 * a good opportunity to optimize that with SIMD.
5164 * Unfortunately if inlining is enabled the gaps in
5165 * pointer array may happen due to early freeing of the
5168 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5169 loc.pkts_copy = loc.pkts_sent;
5171 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5172 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5173 if (pkts_n > loc.pkts_sent) {
5175 * If burst size is large there might be no enough CQE
5176 * fetched from completion queue and no enough resources
5177 * freed to send all the packets.
5182 #ifdef MLX5_PMD_SOFT_COUNTERS
5183 /* Increment sent packets counter. */
5184 txq->stats.opackets += loc.pkts_sent;
5186 if (MLX5_TXOFF_CONFIG(INLINE) && loc.mbuf_free)
5187 __mlx5_tx_free_mbuf(pkts, loc.mbuf_free, olx);
5188 return loc.pkts_sent;
5191 /* Generate routines with Enhanced Multi-Packet Write support. */
5192 MLX5_TXOFF_DECL(full_empw,
5193 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5195 MLX5_TXOFF_DECL(none_empw,
5196 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5198 MLX5_TXOFF_DECL(md_empw,
5199 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5201 MLX5_TXOFF_DECL(mt_empw,
5202 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5203 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5205 MLX5_TXOFF_DECL(mtsc_empw,
5206 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5207 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5208 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5210 MLX5_TXOFF_DECL(mti_empw,
5211 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5212 MLX5_TXOFF_CONFIG_INLINE |
5213 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5215 MLX5_TXOFF_DECL(mtv_empw,
5216 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5217 MLX5_TXOFF_CONFIG_VLAN |
5218 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5220 MLX5_TXOFF_DECL(mtiv_empw,
5221 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5222 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5223 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5225 MLX5_TXOFF_DECL(sc_empw,
5226 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5227 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5229 MLX5_TXOFF_DECL(sci_empw,
5230 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5231 MLX5_TXOFF_CONFIG_INLINE |
5232 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5234 MLX5_TXOFF_DECL(scv_empw,
5235 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5236 MLX5_TXOFF_CONFIG_VLAN |
5237 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5239 MLX5_TXOFF_DECL(sciv_empw,
5240 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5241 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5242 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5244 MLX5_TXOFF_DECL(i_empw,
5245 MLX5_TXOFF_CONFIG_INLINE |
5246 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5248 MLX5_TXOFF_DECL(v_empw,
5249 MLX5_TXOFF_CONFIG_VLAN |
5250 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5252 MLX5_TXOFF_DECL(iv_empw,
5253 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5254 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5256 /* Generate routines without Enhanced Multi-Packet Write support. */
5257 MLX5_TXOFF_DECL(full,
5258 MLX5_TXOFF_CONFIG_FULL)
5260 MLX5_TXOFF_DECL(none,
5261 MLX5_TXOFF_CONFIG_NONE)
5264 MLX5_TXOFF_CONFIG_METADATA)
5267 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5268 MLX5_TXOFF_CONFIG_METADATA)
5270 MLX5_TXOFF_DECL(mtsc,
5271 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5272 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5273 MLX5_TXOFF_CONFIG_METADATA)
5275 MLX5_TXOFF_DECL(mti,
5276 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5277 MLX5_TXOFF_CONFIG_INLINE |
5278 MLX5_TXOFF_CONFIG_METADATA)
5281 MLX5_TXOFF_DECL(mtv,
5282 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5283 MLX5_TXOFF_CONFIG_VLAN |
5284 MLX5_TXOFF_CONFIG_METADATA)
5287 MLX5_TXOFF_DECL(mtiv,
5288 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5289 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5290 MLX5_TXOFF_CONFIG_METADATA)
5293 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5294 MLX5_TXOFF_CONFIG_METADATA)
5296 MLX5_TXOFF_DECL(sci,
5297 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5298 MLX5_TXOFF_CONFIG_INLINE |
5299 MLX5_TXOFF_CONFIG_METADATA)
5302 MLX5_TXOFF_DECL(scv,
5303 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5304 MLX5_TXOFF_CONFIG_VLAN |
5305 MLX5_TXOFF_CONFIG_METADATA)
5308 MLX5_TXOFF_DECL(sciv,
5309 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5310 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5311 MLX5_TXOFF_CONFIG_METADATA)
5314 MLX5_TXOFF_CONFIG_INLINE |
5315 MLX5_TXOFF_CONFIG_METADATA)
5318 MLX5_TXOFF_CONFIG_VLAN |
5319 MLX5_TXOFF_CONFIG_METADATA)
5322 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5323 MLX5_TXOFF_CONFIG_METADATA)
5325 /* Generate routines with timestamp scheduling. */
5326 MLX5_TXOFF_DECL(full_ts_nompw,
5327 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5329 MLX5_TXOFF_DECL(full_ts_nompwi,
5330 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5331 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5332 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5333 MLX5_TXOFF_CONFIG_TXPP)
5335 MLX5_TXOFF_DECL(full_ts,
5336 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5337 MLX5_TXOFF_CONFIG_EMPW)
5339 MLX5_TXOFF_DECL(full_ts_noi,
5340 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5341 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5342 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5343 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5345 MLX5_TXOFF_DECL(none_ts,
5346 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5347 MLX5_TXOFF_CONFIG_EMPW)
5349 MLX5_TXOFF_DECL(mdi_ts,
5350 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5351 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5353 MLX5_TXOFF_DECL(mti_ts,
5354 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5355 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5356 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5358 MLX5_TXOFF_DECL(mtiv_ts,
5359 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5360 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5361 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5362 MLX5_TXOFF_CONFIG_EMPW)
5365 * Generate routines with Legacy Multi-Packet Write support.
5366 * This mode is supported by ConnectX-4 Lx only and imposes
5367 * offload limitations, not supported:
5368 * - ACL/Flows (metadata are becoming meaningless)
5369 * - WQE Inline headers
5370 * - SRIOV (E-Switch offloads)
5372 * - tunnel encapsulation/decapsulation
5375 MLX5_TXOFF_DECL(none_mpw,
5376 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5377 MLX5_TXOFF_CONFIG_MPW)
5379 MLX5_TXOFF_DECL(mci_mpw,
5380 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5381 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5382 MLX5_TXOFF_CONFIG_MPW)
5384 MLX5_TXOFF_DECL(mc_mpw,
5385 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5386 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5388 MLX5_TXOFF_DECL(i_mpw,
5389 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5390 MLX5_TXOFF_CONFIG_MPW)
5393 * Array of declared and compiled Tx burst function and corresponding
5394 * supported offloads set. The array is used to select the Tx burst
5395 * function for specified offloads set at Tx queue configuration time.
5398 eth_tx_burst_t func;
5401 MLX5_TXOFF_INFO(full_empw,
5402 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5403 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5404 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5405 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5407 MLX5_TXOFF_INFO(none_empw,
5408 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5410 MLX5_TXOFF_INFO(md_empw,
5411 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5413 MLX5_TXOFF_INFO(mt_empw,
5414 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5415 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5417 MLX5_TXOFF_INFO(mtsc_empw,
5418 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5419 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5420 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5422 MLX5_TXOFF_INFO(mti_empw,
5423 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5424 MLX5_TXOFF_CONFIG_INLINE |
5425 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5427 MLX5_TXOFF_INFO(mtv_empw,
5428 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5429 MLX5_TXOFF_CONFIG_VLAN |
5430 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5432 MLX5_TXOFF_INFO(mtiv_empw,
5433 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5434 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5435 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5437 MLX5_TXOFF_INFO(sc_empw,
5438 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5439 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5441 MLX5_TXOFF_INFO(sci_empw,
5442 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5443 MLX5_TXOFF_CONFIG_INLINE |
5444 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5446 MLX5_TXOFF_INFO(scv_empw,
5447 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5448 MLX5_TXOFF_CONFIG_VLAN |
5449 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5451 MLX5_TXOFF_INFO(sciv_empw,
5452 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5453 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5454 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5456 MLX5_TXOFF_INFO(i_empw,
5457 MLX5_TXOFF_CONFIG_INLINE |
5458 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5460 MLX5_TXOFF_INFO(v_empw,
5461 MLX5_TXOFF_CONFIG_VLAN |
5462 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5464 MLX5_TXOFF_INFO(iv_empw,
5465 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5466 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5468 MLX5_TXOFF_INFO(full_ts_nompw,
5469 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5471 MLX5_TXOFF_INFO(full_ts_nompwi,
5472 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5473 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5474 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5475 MLX5_TXOFF_CONFIG_TXPP)
5477 MLX5_TXOFF_INFO(full_ts,
5478 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5479 MLX5_TXOFF_CONFIG_EMPW)
5481 MLX5_TXOFF_INFO(full_ts_noi,
5482 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5483 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5484 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5485 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5487 MLX5_TXOFF_INFO(none_ts,
5488 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5489 MLX5_TXOFF_CONFIG_EMPW)
5491 MLX5_TXOFF_INFO(mdi_ts,
5492 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5493 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5495 MLX5_TXOFF_INFO(mti_ts,
5496 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5497 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5498 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5500 MLX5_TXOFF_INFO(mtiv_ts,
5501 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5502 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5503 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5504 MLX5_TXOFF_CONFIG_EMPW)
5506 MLX5_TXOFF_INFO(full,
5507 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5508 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5509 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5510 MLX5_TXOFF_CONFIG_METADATA)
5512 MLX5_TXOFF_INFO(none,
5513 MLX5_TXOFF_CONFIG_NONE)
5516 MLX5_TXOFF_CONFIG_METADATA)
5519 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5520 MLX5_TXOFF_CONFIG_METADATA)
5522 MLX5_TXOFF_INFO(mtsc,
5523 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5524 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5525 MLX5_TXOFF_CONFIG_METADATA)
5527 MLX5_TXOFF_INFO(mti,
5528 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5529 MLX5_TXOFF_CONFIG_INLINE |
5530 MLX5_TXOFF_CONFIG_METADATA)
5532 MLX5_TXOFF_INFO(mtv,
5533 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5534 MLX5_TXOFF_CONFIG_VLAN |
5535 MLX5_TXOFF_CONFIG_METADATA)
5537 MLX5_TXOFF_INFO(mtiv,
5538 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5539 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5540 MLX5_TXOFF_CONFIG_METADATA)
5543 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5544 MLX5_TXOFF_CONFIG_METADATA)
5546 MLX5_TXOFF_INFO(sci,
5547 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5548 MLX5_TXOFF_CONFIG_INLINE |
5549 MLX5_TXOFF_CONFIG_METADATA)
5551 MLX5_TXOFF_INFO(scv,
5552 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5553 MLX5_TXOFF_CONFIG_VLAN |
5554 MLX5_TXOFF_CONFIG_METADATA)
5556 MLX5_TXOFF_INFO(sciv,
5557 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5558 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5559 MLX5_TXOFF_CONFIG_METADATA)
5562 MLX5_TXOFF_CONFIG_INLINE |
5563 MLX5_TXOFF_CONFIG_METADATA)
5566 MLX5_TXOFF_CONFIG_VLAN |
5567 MLX5_TXOFF_CONFIG_METADATA)
5570 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5571 MLX5_TXOFF_CONFIG_METADATA)
5573 MLX5_TXOFF_INFO(none_mpw,
5574 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5575 MLX5_TXOFF_CONFIG_MPW)
5577 MLX5_TXOFF_INFO(mci_mpw,
5578 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5579 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5580 MLX5_TXOFF_CONFIG_MPW)
5582 MLX5_TXOFF_INFO(mc_mpw,
5583 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5584 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5586 MLX5_TXOFF_INFO(i_mpw,
5587 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5588 MLX5_TXOFF_CONFIG_MPW)
5592 * Configure the Tx function to use. The routine checks configured
5593 * Tx offloads for the device and selects appropriate Tx burst
5594 * routine. There are multiple Tx burst routines compiled from
5595 * the same template in the most optimal way for the dedicated
5599 * Pointer to private data structure.
5602 * Pointer to selected Tx burst function.
5605 mlx5_select_tx_function(struct rte_eth_dev *dev)
5607 struct mlx5_priv *priv = dev->data->dev_private;
5608 struct mlx5_dev_config *config = &priv->config;
5609 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5610 unsigned int diff = 0, olx = 0, i, m;
5613 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5614 /* We should support Multi-Segment Packets. */
5615 olx |= MLX5_TXOFF_CONFIG_MULTI;
5617 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5618 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5619 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5620 DEV_TX_OFFLOAD_IP_TNL_TSO |
5621 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5622 /* We should support TCP Send Offload. */
5623 olx |= MLX5_TXOFF_CONFIG_TSO;
5625 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5626 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5627 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5628 /* We should support Software Parser for Tunnels. */
5629 olx |= MLX5_TXOFF_CONFIG_SWP;
5631 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5632 DEV_TX_OFFLOAD_UDP_CKSUM |
5633 DEV_TX_OFFLOAD_TCP_CKSUM |
5634 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5635 /* We should support IP/TCP/UDP Checksums. */
5636 olx |= MLX5_TXOFF_CONFIG_CSUM;
5638 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5639 /* We should support VLAN insertion. */
5640 olx |= MLX5_TXOFF_CONFIG_VLAN;
5642 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5643 rte_mbuf_dynflag_lookup
5644 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5645 rte_mbuf_dynfield_lookup
5646 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5647 /* Offload configured, dynamic entities registered. */
5648 olx |= MLX5_TXOFF_CONFIG_TXPP;
5650 if (priv->txqs_n && (*priv->txqs)[0]) {
5651 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5653 if (txd->inlen_send) {
5655 * Check the data inline requirements. Data inline
5656 * is enabled on per device basis, we can check
5657 * the first Tx queue only.
5659 * If device does not support VLAN insertion in WQE
5660 * and some queues are requested to perform VLAN
5661 * insertion offload than inline must be enabled.
5663 olx |= MLX5_TXOFF_CONFIG_INLINE;
5666 if (config->mps == MLX5_MPW_ENHANCED &&
5667 config->txq_inline_min <= 0) {
5669 * The NIC supports Enhanced Multi-Packet Write
5670 * and does not require minimal inline data.
5672 olx |= MLX5_TXOFF_CONFIG_EMPW;
5674 if (rte_flow_dynf_metadata_avail()) {
5675 /* We should support Flow metadata. */
5676 olx |= MLX5_TXOFF_CONFIG_METADATA;
5678 if (config->mps == MLX5_MPW) {
5680 * The NIC supports Legacy Multi-Packet Write.
5681 * The MLX5_TXOFF_CONFIG_MPW controls the
5682 * descriptor building method in combination
5683 * with MLX5_TXOFF_CONFIG_EMPW.
5685 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5686 MLX5_TXOFF_CONFIG_SWP |
5687 MLX5_TXOFF_CONFIG_VLAN |
5688 MLX5_TXOFF_CONFIG_METADATA)))
5689 olx |= MLX5_TXOFF_CONFIG_EMPW |
5690 MLX5_TXOFF_CONFIG_MPW;
5693 * Scan the routines table to find the minimal
5694 * satisfying routine with requested offloads.
5696 m = RTE_DIM(txoff_func);
5697 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5700 tmp = txoff_func[i].olx;
5702 /* Meets requested offloads exactly.*/
5706 if ((tmp & olx) != olx) {
5707 /* Does not meet requested offloads at all. */
5710 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5711 /* Do not enable legacy MPW if not configured. */
5713 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5714 /* Do not enable eMPW if not configured. */
5716 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5717 /* Do not enable inlining if not configured. */
5719 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5720 /* Do not enable scheduling if not configured. */
5723 * Some routine meets the requirements.
5724 * Check whether it has minimal amount
5725 * of not requested offloads.
5727 tmp = __builtin_popcountl(tmp & ~olx);
5728 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5729 /* First or better match, save and continue. */
5735 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5736 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5737 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5738 /* Lighter not requested offload. */
5743 if (m >= RTE_DIM(txoff_func)) {
5744 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5745 " for requested offloads %04X",
5746 dev->data->port_id, olx);
5749 DRV_LOG(DEBUG, "port %u has selected Tx function"
5750 " supporting offloads %04X/%04X",
5751 dev->data->port_id, olx, txoff_func[m].olx);
5752 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5753 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5754 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5755 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5756 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5757 DRV_LOG(DEBUG, "\tSWP (software parser)");
5758 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5759 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5760 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5761 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5762 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5763 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5764 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5765 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5766 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5767 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5768 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5769 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5770 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5772 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5774 return txoff_func[m].func;
5778 * DPDK callback to get the TX queue information
5781 * Pointer to the device structure.
5783 * @param tx_queue_id
5784 * Tx queue identificator.
5787 * Pointer to the TX queue information structure.
5794 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5795 struct rte_eth_txq_info *qinfo)
5797 struct mlx5_priv *priv = dev->data->dev_private;
5798 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5799 struct mlx5_txq_ctrl *txq_ctrl =
5800 container_of(txq, struct mlx5_txq_ctrl, txq);
5804 qinfo->nb_desc = txq->elts_s;
5805 qinfo->conf.tx_thresh.pthresh = 0;
5806 qinfo->conf.tx_thresh.hthresh = 0;
5807 qinfo->conf.tx_thresh.wthresh = 0;
5808 qinfo->conf.tx_rs_thresh = 0;
5809 qinfo->conf.tx_free_thresh = 0;
5810 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5811 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5815 * DPDK callback to get the TX packet burst mode information
5818 * Pointer to the device structure.
5820 * @param tx_queue_id
5821 * Tx queue identificatior.
5824 * Pointer to the burts mode information.
5827 * 0 as success, -EINVAL as failure.
5831 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5832 uint16_t tx_queue_id __rte_unused,
5833 struct rte_eth_burst_mode *mode)
5835 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5836 unsigned int i, olx;
5838 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5839 if (pkt_burst == txoff_func[i].func) {
5840 olx = txoff_func[i].olx;
5841 snprintf(mode->info, sizeof(mode->info),
5842 "%s%s%s%s%s%s%s%s%s",
5843 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5844 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5845 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5846 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5848 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5850 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5852 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5854 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5856 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5858 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5860 (olx & MLX5_TXOFF_CONFIG_TXPP) ?