4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
73 check_cqe(volatile struct mlx5_cqe *cqe,
74 unsigned int cqes_n, const uint16_t ci)
75 __attribute__((always_inline));
78 txq_complete(struct txq *txq) __attribute__((always_inline));
80 static inline uint32_t
81 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
82 __attribute__((always_inline));
85 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
86 __attribute__((always_inline));
88 static inline uint32_t
89 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
90 __attribute__((always_inline));
93 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
94 uint16_t cqe_cnt, uint32_t *rss_hash)
95 __attribute__((always_inline));
97 static inline uint32_t
98 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
99 __attribute__((always_inline));
104 * Verify or set magic value in CQE.
113 check_cqe_seen(volatile struct mlx5_cqe *cqe)
115 static const uint8_t magic[] = "seen";
116 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
120 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
121 if (!ret || (*buf)[i] != magic[i]) {
123 (*buf)[i] = magic[i];
131 * Check whether CQE is valid.
136 * Size of completion queue.
141 * 0 on success, 1 on failure.
144 check_cqe(volatile struct mlx5_cqe *cqe,
145 unsigned int cqes_n, const uint16_t ci)
147 uint16_t idx = ci & cqes_n;
148 uint8_t op_own = cqe->op_own;
149 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
150 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
152 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
153 return 1; /* No CQE. */
155 if ((op_code == MLX5_CQE_RESP_ERR) ||
156 (op_code == MLX5_CQE_REQ_ERR)) {
157 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
158 uint8_t syndrome = err_cqe->syndrome;
160 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
161 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
163 if (!check_cqe_seen(cqe))
164 ERROR("unexpected CQE error %u (0x%02x)"
166 op_code, op_code, syndrome);
168 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
169 (op_code != MLX5_CQE_REQ)) {
170 if (!check_cqe_seen(cqe))
171 ERROR("unexpected CQE opcode %u (0x%02x)",
180 * Return the address of the WQE.
183 * Pointer to TX queue structure.
185 * WQE consumer index.
190 static inline uintptr_t *
191 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
193 ci &= ((1 << txq->wqe_n) - 1);
194 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
198 * Manage TX completions.
200 * When sending a burst, mlx5_tx_burst() posts several WRs.
203 * Pointer to TX queue structure.
206 txq_complete(struct txq *txq)
208 const unsigned int elts_n = 1 << txq->elts_n;
209 const unsigned int cqe_n = 1 << txq->cqe_n;
210 const unsigned int cqe_cnt = cqe_n - 1;
211 uint16_t elts_free = txq->elts_tail;
213 uint16_t cq_ci = txq->cq_ci;
214 volatile struct mlx5_cqe *cqe = NULL;
215 volatile struct mlx5_wqe_ctrl *ctrl;
218 volatile struct mlx5_cqe *tmp;
220 tmp = &(*txq->cqes)[cq_ci & cqe_cnt];
221 if (check_cqe(tmp, cqe_n, cq_ci))
225 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
226 if (!check_cqe_seen(cqe))
227 ERROR("unexpected compressed CQE, TX stopped");
230 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
231 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
232 if (!check_cqe_seen(cqe))
233 ERROR("unexpected error CQE, TX stopped");
239 if (unlikely(cqe == NULL))
241 txq->wqe_pi = ntohs(cqe->wqe_counter);
242 ctrl = (volatile struct mlx5_wqe_ctrl *)
243 tx_mlx5_wqe(txq, txq->wqe_pi);
244 elts_tail = ctrl->ctrl3;
245 assert(elts_tail < (1 << txq->wqe_n));
247 while (elts_free != elts_tail) {
248 struct rte_mbuf *elt = (*txq->elts)[elts_free];
249 unsigned int elts_free_next =
250 (elts_free + 1) & (elts_n - 1);
251 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
255 memset(&(*txq->elts)[elts_free],
257 sizeof((*txq->elts)[elts_free]));
259 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
260 /* Only one segment needs to be freed. */
261 rte_pktmbuf_free_seg(elt);
262 elts_free = elts_free_next;
265 txq->elts_tail = elts_tail;
266 /* Update the consumer index. */
268 *txq->cq_db = htonl(cq_ci);
272 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
273 * the cloned mbuf is allocated is returned instead.
279 * Memory pool where data is located for given mbuf.
281 static struct rte_mempool *
282 txq_mb2mp(struct rte_mbuf *buf)
284 if (unlikely(RTE_MBUF_INDIRECT(buf)))
285 return rte_mbuf_from_indirect(buf)->pool;
290 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
291 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
292 * remove an entry first.
295 * Pointer to TX queue structure.
297 * Memory Pool for which a Memory Region lkey must be returned.
300 * mr->lkey on success, (uint32_t)-1 on failure.
302 static inline uint32_t
303 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
306 uint32_t lkey = (uint32_t)-1;
308 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
309 if (unlikely(txq->mp2mr[i].mp == NULL)) {
310 /* Unknown MP, add a new MR for it. */
313 if (txq->mp2mr[i].mp == mp) {
314 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
315 assert(htonl(txq->mp2mr[i].mr->lkey) ==
317 lkey = txq->mp2mr[i].lkey;
321 if (unlikely(lkey == (uint32_t)-1))
322 lkey = txq_mp2mr_reg(txq, mp, i);
327 * Ring TX queue doorbell.
330 * Pointer to TX queue structure.
332 * Pointer to the last WQE posted in the NIC.
335 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
337 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
338 volatile uint64_t *src = ((volatile uint64_t *)wqe);
341 *txq->qp_db = htonl(txq->wqe_ci);
342 /* Ensure ordering between DB record and BF copy. */
348 * DPDK callback for TX.
351 * Generic pointer to TX queue structure.
353 * Packets to transmit.
355 * Number of packets in array.
358 * Number of packets successfully transmitted (<= pkts_n).
361 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
363 struct txq *txq = (struct txq *)dpdk_txq;
364 uint16_t elts_head = txq->elts_head;
365 const unsigned int elts_n = 1 << txq->elts_n;
371 volatile struct mlx5_wqe_v *wqe = NULL;
372 unsigned int segs_n = 0;
373 struct rte_mbuf *buf = NULL;
376 if (unlikely(!pkts_n))
378 /* Prefetch first packet cacheline. */
379 rte_prefetch0(*pkts);
380 /* Start processing. */
382 max = (elts_n - (elts_head - txq->elts_tail));
385 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
386 if (unlikely(!max_wqe))
389 volatile rte_v128u32_t *dseg = NULL;
394 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
396 uint8_t cs_flags = 0;
397 #ifdef MLX5_PMD_SOFT_COUNTERS
398 uint32_t total_length = 0;
403 segs_n = buf->nb_segs;
405 * Make sure there is enough room to store this packet and
406 * that one ring entry remains unused.
409 if (max < segs_n + 1)
415 if (unlikely(--max_wqe == 0))
417 wqe = (volatile struct mlx5_wqe_v *)
418 tx_mlx5_wqe(txq, txq->wqe_ci);
419 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
421 rte_prefetch0(*pkts);
422 addr = rte_pktmbuf_mtod(buf, uintptr_t);
423 length = DATA_LEN(buf);
424 ehdr = (((uint8_t *)addr)[1] << 8) |
425 ((uint8_t *)addr)[0];
426 #ifdef MLX5_PMD_SOFT_COUNTERS
427 total_length = length;
429 assert(length >= MLX5_WQE_DWORD_SIZE);
430 /* Update element. */
431 (*txq->elts)[elts_head] = buf;
432 elts_head = (elts_head + 1) & (elts_n - 1);
433 /* Prefetch next buffer data. */
435 volatile void *pkt_addr;
437 pkt_addr = rte_pktmbuf_mtod(*pkts, volatile void *);
438 rte_prefetch0(pkt_addr);
440 /* Should we enable HW CKSUM offload */
442 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
443 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
445 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
446 /* Replace the Ethernet type by the VLAN if necessary. */
447 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
448 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
449 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
453 /* Copy Destination and source mac address. */
454 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
456 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
457 /* Copy missing two bytes to end the DSeg. */
458 memcpy((uint8_t *)raw + len + sizeof(vlan),
459 ((uint8_t *)addr) + len, 2);
463 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
464 MLX5_WQE_DWORD_SIZE);
465 length -= pkt_inline_sz;
466 addr += pkt_inline_sz;
468 /* Inline if enough room. */
469 if (txq->max_inline != 0) {
470 uintptr_t end = (uintptr_t)
471 (((uintptr_t)txq->wqes) +
472 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
473 uint16_t max_inline =
474 txq->max_inline * RTE_CACHE_LINE_SIZE;
478 * raw starts two bytes before the boundary to
479 * continue the above copy of packet data.
481 raw += MLX5_WQE_DWORD_SIZE;
482 room = end - (uintptr_t)raw;
483 if (room > max_inline) {
484 uintptr_t addr_end = (addr + max_inline) &
485 ~(RTE_CACHE_LINE_SIZE - 1);
486 unsigned int copy_b =
487 RTE_MIN((addr_end - addr), length);
491 * One Dseg remains in the current WQE. To
492 * keep the computation positive, it is
493 * removed after the bytes to Dseg conversion.
495 n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
496 if (unlikely(max_wqe < n))
499 rte_memcpy((void *)raw, (void *)addr, copy_b);
502 pkt_inline_sz += copy_b;
504 assert(addr <= addr_end);
507 * 2 DWORDs consumed by the WQE header + ETH segment +
508 * the size of the inline part of the packet.
510 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
512 if (ds % (MLX5_WQE_SIZE /
513 MLX5_WQE_DWORD_SIZE) == 0) {
514 if (unlikely(--max_wqe == 0))
516 dseg = (volatile rte_v128u32_t *)
517 tx_mlx5_wqe(txq, txq->wqe_ci +
520 dseg = (volatile rte_v128u32_t *)
522 (ds * MLX5_WQE_DWORD_SIZE));
525 } else if (!segs_n) {
528 /* dseg will be advance as part of next_seg */
529 dseg = (volatile rte_v128u32_t *)
531 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
536 * No inline has been done in the packet, only the
537 * Ethernet Header as been stored.
539 dseg = (volatile rte_v128u32_t *)
540 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
543 /* Add the remaining packet as a simple ds. */
544 naddr = htonll(addr);
545 *dseg = (rte_v128u32_t){
547 txq_mp2mr(txq, txq_mb2mp(buf)),
560 * Spill on next WQE when the current one does not have
561 * enough room left. Size of WQE must a be a multiple
562 * of data segment size.
564 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
565 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
566 if (unlikely(--max_wqe == 0))
568 dseg = (volatile rte_v128u32_t *)
569 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
570 rte_prefetch0(tx_mlx5_wqe(txq,
571 txq->wqe_ci + ds / 4 + 1));
578 length = DATA_LEN(buf);
579 #ifdef MLX5_PMD_SOFT_COUNTERS
580 total_length += length;
582 /* Store segment information. */
583 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
584 *dseg = (rte_v128u32_t){
586 txq_mp2mr(txq, txq_mb2mp(buf)),
590 (*txq->elts)[elts_head] = buf;
591 elts_head = (elts_head + 1) & (elts_n - 1);
600 /* Initialize known and common part of the WQE structure. */
601 wqe->ctrl = (rte_v128u32_t){
602 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
603 htonl(txq->qp_num_8s | ds),
607 wqe->eseg = (rte_v128u32_t){
611 (ehdr << 16) | htons(pkt_inline_sz),
613 txq->wqe_ci += (ds + 3) / 4;
614 #ifdef MLX5_PMD_SOFT_COUNTERS
615 /* Increment sent bytes counter. */
616 txq->stats.obytes += total_length;
619 /* Take a shortcut if nothing must be sent. */
620 if (unlikely(i == 0))
622 /* Check whether completion threshold has been reached. */
623 comp = txq->elts_comp + i + j;
624 if (comp >= MLX5_TX_COMP_THRESH) {
625 volatile struct mlx5_wqe_ctrl *w =
626 (volatile struct mlx5_wqe_ctrl *)wqe;
628 /* Request completion on last WQE. */
630 /* Save elts_head in unused "immediate" field of WQE. */
631 w->ctrl3 = elts_head;
634 txq->elts_comp = comp;
636 #ifdef MLX5_PMD_SOFT_COUNTERS
637 /* Increment sent packets counter. */
638 txq->stats.opackets += i;
640 /* Ring QP doorbell. */
641 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)wqe);
642 txq->elts_head = elts_head;
647 * Open a MPW session.
650 * Pointer to TX queue structure.
652 * Pointer to MPW session structure.
657 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
659 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
660 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
661 (volatile struct mlx5_wqe_data_seg (*)[])
662 tx_mlx5_wqe(txq, idx + 1);
664 mpw->state = MLX5_MPW_STATE_OPENED;
668 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
669 mpw->wqe->eseg.mss = htons(length);
670 mpw->wqe->eseg.inline_hdr_sz = 0;
671 mpw->wqe->eseg.rsvd0 = 0;
672 mpw->wqe->eseg.rsvd1 = 0;
673 mpw->wqe->eseg.rsvd2 = 0;
674 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
675 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
676 mpw->wqe->ctrl[2] = 0;
677 mpw->wqe->ctrl[3] = 0;
678 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
679 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
680 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
681 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
682 mpw->data.dseg[2] = &(*dseg)[0];
683 mpw->data.dseg[3] = &(*dseg)[1];
684 mpw->data.dseg[4] = &(*dseg)[2];
688 * Close a MPW session.
691 * Pointer to TX queue structure.
693 * Pointer to MPW session structure.
696 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
698 unsigned int num = mpw->pkts_n;
701 * Store size in multiple of 16 bytes. Control and Ethernet segments
704 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
705 mpw->state = MLX5_MPW_STATE_CLOSED;
710 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
711 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
715 * DPDK callback for TX with MPW support.
718 * Generic pointer to TX queue structure.
720 * Packets to transmit.
722 * Number of packets in array.
725 * Number of packets successfully transmitted (<= pkts_n).
728 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
730 struct txq *txq = (struct txq *)dpdk_txq;
731 uint16_t elts_head = txq->elts_head;
732 const unsigned int elts_n = 1 << txq->elts_n;
738 struct mlx5_mpw mpw = {
739 .state = MLX5_MPW_STATE_CLOSED,
742 if (unlikely(!pkts_n))
744 /* Prefetch first packet cacheline. */
745 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
746 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
747 /* Start processing. */
749 max = (elts_n - (elts_head - txq->elts_tail));
752 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
753 if (unlikely(!max_wqe))
756 struct rte_mbuf *buf = *(pkts++);
757 unsigned int elts_head_next;
759 unsigned int segs_n = buf->nb_segs;
760 uint32_t cs_flags = 0;
763 * Make sure there is enough room to store this packet and
764 * that one ring entry remains unused.
767 if (max < segs_n + 1)
769 /* Do not bother with large packets MPW cannot handle. */
770 if (segs_n > MLX5_MPW_DSEG_MAX)
774 /* Should we enable HW CKSUM offload */
776 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
777 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
778 /* Retrieve packet information. */
779 length = PKT_LEN(buf);
781 /* Start new session if packet differs. */
782 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
783 ((mpw.len != length) ||
785 (mpw.wqe->eseg.cs_flags != cs_flags)))
786 mlx5_mpw_close(txq, &mpw);
787 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
789 * Multi-Packet WQE consumes at most two WQE.
790 * mlx5_mpw_new() expects to be able to use such
793 if (unlikely(max_wqe < 2))
796 mlx5_mpw_new(txq, &mpw, length);
797 mpw.wqe->eseg.cs_flags = cs_flags;
799 /* Multi-segment packets must be alone in their MPW. */
800 assert((segs_n == 1) || (mpw.pkts_n == 0));
801 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
805 volatile struct mlx5_wqe_data_seg *dseg;
808 elts_head_next = (elts_head + 1) & (elts_n - 1);
810 (*txq->elts)[elts_head] = buf;
811 dseg = mpw.data.dseg[mpw.pkts_n];
812 addr = rte_pktmbuf_mtod(buf, uintptr_t);
813 *dseg = (struct mlx5_wqe_data_seg){
814 .byte_count = htonl(DATA_LEN(buf)),
815 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
816 .addr = htonll(addr),
818 elts_head = elts_head_next;
819 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
820 length += DATA_LEN(buf);
826 assert(length == mpw.len);
827 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
828 mlx5_mpw_close(txq, &mpw);
829 elts_head = elts_head_next;
830 #ifdef MLX5_PMD_SOFT_COUNTERS
831 /* Increment sent bytes counter. */
832 txq->stats.obytes += length;
836 /* Take a shortcut if nothing must be sent. */
837 if (unlikely(i == 0))
839 /* Check whether completion threshold has been reached. */
840 /* "j" includes both packets and segments. */
841 comp = txq->elts_comp + j;
842 if (comp >= MLX5_TX_COMP_THRESH) {
843 volatile struct mlx5_wqe *wqe = mpw.wqe;
845 /* Request completion on last WQE. */
846 wqe->ctrl[2] = htonl(8);
847 /* Save elts_head in unused "immediate" field of WQE. */
848 wqe->ctrl[3] = elts_head;
851 txq->elts_comp = comp;
853 #ifdef MLX5_PMD_SOFT_COUNTERS
854 /* Increment sent packets counter. */
855 txq->stats.opackets += i;
857 /* Ring QP doorbell. */
858 if (mpw.state == MLX5_MPW_STATE_OPENED)
859 mlx5_mpw_close(txq, &mpw);
860 mlx5_tx_dbrec(txq, mpw.wqe);
861 txq->elts_head = elts_head;
866 * Open a MPW inline session.
869 * Pointer to TX queue structure.
871 * Pointer to MPW session structure.
876 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
878 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
879 struct mlx5_wqe_inl_small *inl;
881 mpw->state = MLX5_MPW_INL_STATE_OPENED;
885 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
886 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
889 mpw->wqe->ctrl[2] = 0;
890 mpw->wqe->ctrl[3] = 0;
891 mpw->wqe->eseg.mss = htons(length);
892 mpw->wqe->eseg.inline_hdr_sz = 0;
893 mpw->wqe->eseg.cs_flags = 0;
894 mpw->wqe->eseg.rsvd0 = 0;
895 mpw->wqe->eseg.rsvd1 = 0;
896 mpw->wqe->eseg.rsvd2 = 0;
897 inl = (struct mlx5_wqe_inl_small *)
898 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
899 mpw->data.raw = (uint8_t *)&inl->raw;
903 * Close a MPW inline session.
906 * Pointer to TX queue structure.
908 * Pointer to MPW session structure.
911 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
914 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
915 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
917 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
919 * Store size in multiple of 16 bytes. Control and Ethernet segments
922 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
923 mpw->state = MLX5_MPW_STATE_CLOSED;
924 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
925 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
929 * DPDK callback for TX with MPW inline support.
932 * Generic pointer to TX queue structure.
934 * Packets to transmit.
936 * Number of packets in array.
939 * Number of packets successfully transmitted (<= pkts_n).
942 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
945 struct txq *txq = (struct txq *)dpdk_txq;
946 uint16_t elts_head = txq->elts_head;
947 const unsigned int elts_n = 1 << txq->elts_n;
953 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
954 struct mlx5_mpw mpw = {
955 .state = MLX5_MPW_STATE_CLOSED,
958 * Compute the maximum number of WQE which can be consumed by inline
961 * - 1 control segment,
962 * - 1 Ethernet segment,
963 * - N Dseg from the inline request.
965 const unsigned int wqe_inl_n =
966 ((2 * MLX5_WQE_DWORD_SIZE +
967 txq->max_inline * RTE_CACHE_LINE_SIZE) +
968 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
970 if (unlikely(!pkts_n))
972 /* Prefetch first packet cacheline. */
973 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
974 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
975 /* Start processing. */
977 max = (elts_n - (elts_head - txq->elts_tail));
981 struct rte_mbuf *buf = *(pkts++);
982 unsigned int elts_head_next;
985 unsigned int segs_n = buf->nb_segs;
986 uint32_t cs_flags = 0;
989 * Make sure there is enough room to store this packet and
990 * that one ring entry remains unused.
993 if (max < segs_n + 1)
995 /* Do not bother with large packets MPW cannot handle. */
996 if (segs_n > MLX5_MPW_DSEG_MAX)
1001 * Compute max_wqe in case less WQE were consumed in previous
1004 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1005 /* Should we enable HW CKSUM offload */
1007 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1008 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1009 /* Retrieve packet information. */
1010 length = PKT_LEN(buf);
1011 /* Start new session if packet differs. */
1012 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1013 if ((mpw.len != length) ||
1015 (mpw.wqe->eseg.cs_flags != cs_flags))
1016 mlx5_mpw_close(txq, &mpw);
1017 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1018 if ((mpw.len != length) ||
1020 (length > inline_room) ||
1021 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1022 mlx5_mpw_inline_close(txq, &mpw);
1024 txq->max_inline * RTE_CACHE_LINE_SIZE;
1027 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1028 if ((segs_n != 1) ||
1029 (length > inline_room)) {
1031 * Multi-Packet WQE consumes at most two WQE.
1032 * mlx5_mpw_new() expects to be able to use
1035 if (unlikely(max_wqe < 2))
1038 mlx5_mpw_new(txq, &mpw, length);
1039 mpw.wqe->eseg.cs_flags = cs_flags;
1041 if (unlikely(max_wqe < wqe_inl_n))
1043 max_wqe -= wqe_inl_n;
1044 mlx5_mpw_inline_new(txq, &mpw, length);
1045 mpw.wqe->eseg.cs_flags = cs_flags;
1048 /* Multi-segment packets must be alone in their MPW. */
1049 assert((segs_n == 1) || (mpw.pkts_n == 0));
1050 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1051 assert(inline_room ==
1052 txq->max_inline * RTE_CACHE_LINE_SIZE);
1053 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1057 volatile struct mlx5_wqe_data_seg *dseg;
1060 (elts_head + 1) & (elts_n - 1);
1062 (*txq->elts)[elts_head] = buf;
1063 dseg = mpw.data.dseg[mpw.pkts_n];
1064 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1065 *dseg = (struct mlx5_wqe_data_seg){
1066 .byte_count = htonl(DATA_LEN(buf)),
1067 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1068 .addr = htonll(addr),
1070 elts_head = elts_head_next;
1071 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1072 length += DATA_LEN(buf);
1078 assert(length == mpw.len);
1079 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1080 mlx5_mpw_close(txq, &mpw);
1084 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1085 assert(length <= inline_room);
1086 assert(length == DATA_LEN(buf));
1087 elts_head_next = (elts_head + 1) & (elts_n - 1);
1088 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1089 (*txq->elts)[elts_head] = buf;
1090 /* Maximum number of bytes before wrapping. */
1091 max = ((((uintptr_t)(txq->wqes)) +
1094 (uintptr_t)mpw.data.raw);
1096 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1099 mpw.data.raw = (volatile void *)txq->wqes;
1100 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1101 (void *)(addr + max),
1103 mpw.data.raw += length - max;
1105 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1111 (volatile void *)txq->wqes;
1113 mpw.data.raw += length;
1117 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1118 mlx5_mpw_inline_close(txq, &mpw);
1120 txq->max_inline * RTE_CACHE_LINE_SIZE;
1122 inline_room -= length;
1125 mpw.total_len += length;
1126 elts_head = elts_head_next;
1127 #ifdef MLX5_PMD_SOFT_COUNTERS
1128 /* Increment sent bytes counter. */
1129 txq->stats.obytes += length;
1133 /* Take a shortcut if nothing must be sent. */
1134 if (unlikely(i == 0))
1136 /* Check whether completion threshold has been reached. */
1137 /* "j" includes both packets and segments. */
1138 comp = txq->elts_comp + j;
1139 if (comp >= MLX5_TX_COMP_THRESH) {
1140 volatile struct mlx5_wqe *wqe = mpw.wqe;
1142 /* Request completion on last WQE. */
1143 wqe->ctrl[2] = htonl(8);
1144 /* Save elts_head in unused "immediate" field of WQE. */
1145 wqe->ctrl[3] = elts_head;
1148 txq->elts_comp = comp;
1150 #ifdef MLX5_PMD_SOFT_COUNTERS
1151 /* Increment sent packets counter. */
1152 txq->stats.opackets += i;
1154 /* Ring QP doorbell. */
1155 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1156 mlx5_mpw_inline_close(txq, &mpw);
1157 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1158 mlx5_mpw_close(txq, &mpw);
1159 mlx5_tx_dbrec(txq, mpw.wqe);
1160 txq->elts_head = elts_head;
1165 * Translate RX completion flags to packet type.
1170 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1173 * Packet type for struct rte_mbuf.
1175 static inline uint32_t
1176 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1179 uint16_t flags = ntohs(cqe->hdr_type_etc);
1181 if (cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) {
1184 MLX5_CQE_RX_IPV4_PACKET,
1185 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN) |
1187 MLX5_CQE_RX_IPV6_PACKET,
1188 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN);
1189 pkt_type |= ((cqe->pkt_info & MLX5_CQE_RX_OUTER_PACKET) ?
1190 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
1191 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1195 MLX5_CQE_L3_HDR_TYPE_IPV6,
1196 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN) |
1198 MLX5_CQE_L3_HDR_TYPE_IPV4,
1199 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN);
1205 * Get size of the next packet for a given CQE. For compressed CQEs, the
1206 * consumer index is updated only once all packets of the current one have
1210 * Pointer to RX queue.
1213 * @param[out] rss_hash
1214 * Packet RSS Hash result.
1217 * Packet size in bytes (0 if there is none), -1 in case of completion
1221 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1222 uint16_t cqe_cnt, uint32_t *rss_hash)
1224 struct rxq_zip *zip = &rxq->zip;
1225 uint16_t cqe_n = cqe_cnt + 1;
1229 /* Process compressed data in the CQE and mini arrays. */
1231 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1232 (volatile struct mlx5_mini_cqe8 (*)[8])
1233 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt]);
1235 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1236 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1237 if ((++zip->ai & 7) == 0) {
1238 /* Invalidate consumed CQEs */
1241 while (idx != end) {
1242 (*rxq->cqes)[idx & cqe_cnt].op_own =
1243 MLX5_CQE_INVALIDATE;
1247 * Increment consumer index to skip the number of
1248 * CQEs consumed. Hardware leaves holes in the CQ
1249 * ring for software use.
1254 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1255 /* Invalidate the rest */
1259 while (idx != end) {
1260 (*rxq->cqes)[idx & cqe_cnt].op_own =
1261 MLX5_CQE_INVALIDATE;
1264 rxq->cq_ci = zip->cq_ci;
1267 /* No compressed data, get next CQE and verify if it is compressed. */
1272 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1273 if (unlikely(ret == 1))
1276 op_own = cqe->op_own;
1277 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1278 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1279 (volatile struct mlx5_mini_cqe8 (*)[8])
1280 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1283 /* Fix endianness. */
1284 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1286 * Current mini array position is the one returned by
1289 * If completion comprises several mini arrays, as a
1290 * special case the second one is located 7 CQEs after
1291 * the initial CQE instead of 8 for subsequent ones.
1293 zip->ca = rxq->cq_ci;
1294 zip->na = zip->ca + 7;
1295 /* Compute the next non compressed CQE. */
1297 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1298 /* Get packet size to return. */
1299 len = ntohl((*mc)[0].byte_cnt);
1300 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1302 /* Prefetch all the entries to be invalidated */
1305 while (idx != end) {
1306 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1310 len = ntohl(cqe->byte_cnt);
1311 *rss_hash = ntohl(cqe->rx_hash_res);
1313 /* Error while receiving packet. */
1314 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1321 * Translate RX completion flags to offload flags.
1324 * Pointer to RX queue structure.
1329 * Offload flags (ol_flags) for struct rte_mbuf.
1331 static inline uint32_t
1332 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1334 uint32_t ol_flags = 0;
1335 uint16_t flags = ntohs(cqe->hdr_type_etc);
1339 MLX5_CQE_RX_L3_HDR_VALID,
1340 PKT_RX_IP_CKSUM_GOOD) |
1342 MLX5_CQE_RX_L4_HDR_VALID,
1343 PKT_RX_L4_CKSUM_GOOD);
1344 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1347 MLX5_CQE_RX_L3_HDR_VALID,
1348 PKT_RX_IP_CKSUM_GOOD) |
1350 MLX5_CQE_RX_L4_HDR_VALID,
1351 PKT_RX_L4_CKSUM_GOOD);
1356 * DPDK callback for RX.
1359 * Generic pointer to RX queue structure.
1361 * Array to store received packets.
1363 * Maximum number of packets in array.
1366 * Number of packets successfully received (<= pkts_n).
1369 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1371 struct rxq *rxq = dpdk_rxq;
1372 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1373 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1374 const unsigned int sges_n = rxq->sges_n;
1375 struct rte_mbuf *pkt = NULL;
1376 struct rte_mbuf *seg = NULL;
1377 volatile struct mlx5_cqe *cqe =
1378 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1380 unsigned int rq_ci = rxq->rq_ci << sges_n;
1381 int len; /* keep its value across iterations. */
1384 unsigned int idx = rq_ci & wqe_cnt;
1385 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1386 struct rte_mbuf *rep = (*rxq->elts)[idx];
1387 uint32_t rss_hash_res = 0;
1395 rep = rte_mbuf_raw_alloc(rxq->mp);
1396 if (unlikely(rep == NULL)) {
1397 ++rxq->stats.rx_nombuf;
1400 * no buffers before we even started,
1401 * bail out silently.
1405 while (pkt != seg) {
1406 assert(pkt != (*rxq->elts)[idx]);
1408 rte_mbuf_refcnt_set(pkt, 0);
1409 __rte_mbuf_raw_free(pkt);
1415 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1416 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1419 rte_mbuf_refcnt_set(rep, 0);
1420 __rte_mbuf_raw_free(rep);
1423 if (unlikely(len == -1)) {
1424 /* RX error, packet is likely too large. */
1425 rte_mbuf_refcnt_set(rep, 0);
1426 __rte_mbuf_raw_free(rep);
1427 ++rxq->stats.idropped;
1431 assert(len >= (rxq->crc_present << 2));
1432 /* Update packet information. */
1433 pkt->packet_type = 0;
1435 if (rss_hash_res && rxq->rss_hash) {
1436 pkt->hash.rss = rss_hash_res;
1437 pkt->ol_flags = PKT_RX_RSS_HASH;
1440 ((cqe->sop_drop_qpn !=
1441 htonl(MLX5_FLOW_MARK_INVALID)) ||
1442 (cqe->sop_drop_qpn !=
1443 htonl(MLX5_FLOW_MARK_DEFAULT)))) {
1445 mlx5_flow_mark_get(cqe->sop_drop_qpn);
1446 pkt->ol_flags &= ~PKT_RX_RSS_HASH;
1447 pkt->ol_flags |= PKT_RX_FDIR | PKT_RX_FDIR_ID;
1449 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1453 rxq_cq_to_pkt_type(cqe);
1455 rxq_cq_to_ol_flags(rxq, cqe);
1457 if (cqe->hdr_type_etc &
1458 MLX5_CQE_VLAN_STRIPPED) {
1459 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1460 PKT_RX_VLAN_STRIPPED;
1461 pkt->vlan_tci = ntohs(cqe->vlan_info);
1463 if (rxq->crc_present)
1464 len -= ETHER_CRC_LEN;
1468 DATA_LEN(rep) = DATA_LEN(seg);
1469 PKT_LEN(rep) = PKT_LEN(seg);
1470 SET_DATA_OFF(rep, DATA_OFF(seg));
1471 NB_SEGS(rep) = NB_SEGS(seg);
1472 PORT(rep) = PORT(seg);
1474 (*rxq->elts)[idx] = rep;
1476 * Fill NIC descriptor with the new buffer. The lkey and size
1477 * of the buffers are already known, only the buffer address
1480 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1481 if (len > DATA_LEN(seg)) {
1482 len -= DATA_LEN(seg);
1487 DATA_LEN(seg) = len;
1488 #ifdef MLX5_PMD_SOFT_COUNTERS
1489 /* Increment bytes counter. */
1490 rxq->stats.ibytes += PKT_LEN(pkt);
1492 /* Return packet. */
1498 /* Align consumer index to the next stride. */
1503 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1505 /* Update the consumer index. */
1506 rxq->rq_ci = rq_ci >> sges_n;
1508 *rxq->cq_db = htonl(rxq->cq_ci);
1510 *rxq->rq_db = htonl(rxq->rq_ci);
1511 #ifdef MLX5_PMD_SOFT_COUNTERS
1512 /* Increment packets counter. */
1513 rxq->stats.ipackets += i;
1519 * Dummy DPDK callback for TX.
1521 * This function is used to temporarily replace the real callback during
1522 * unsafe control operations on the queue, or in case of error.
1525 * Generic pointer to TX queue structure.
1527 * Packets to transmit.
1529 * Number of packets in array.
1532 * Number of packets successfully transmitted (<= pkts_n).
1535 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1544 * Dummy DPDK callback for RX.
1546 * This function is used to temporarily replace the real callback during
1547 * unsafe control operations on the queue, or in case of error.
1550 * Generic pointer to RX queue structure.
1552 * Array to store received packets.
1554 * Maximum number of packets in array.
1557 * Number of packets successfully received (<= pkts_n).
1560 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)