1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 #include <rte_mempool.h>
12 #include <rte_prefetch.h>
13 #include <rte_common.h>
14 #include <rte_branch_prediction.h>
15 #include <rte_ether.h>
16 #include <rte_cycles.h>
20 #include <mlx5_common.h>
22 #include "mlx5_autoconf.h"
23 #include "mlx5_defs.h"
26 #include "mlx5_utils.h"
27 #include "mlx5_rxtx.h"
29 /* TX burst subroutines return codes. */
30 enum mlx5_txcmp_code {
31 MLX5_TXCMP_CODE_EXIT = 0,
32 MLX5_TXCMP_CODE_ERROR,
33 MLX5_TXCMP_CODE_SINGLE,
34 MLX5_TXCMP_CODE_MULTI,
40 * These defines are used to configure Tx burst routine option set
41 * supported at compile time. The not specified options are optimized out
42 * out due to if conditions can be explicitly calculated at compile time.
43 * The offloads with bigger runtime check (require more CPU cycles to
44 * skip) overhead should have the bigger index - this is needed to
45 * select the better matching routine function if no exact match and
46 * some offloads are not actually requested.
48 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
49 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
50 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
51 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
52 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
53 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
54 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
55 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
56 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
57 #define MLX5_TXOFF_CONFIG_TXPP (1u << 10) /* Scheduling on timestamp.*/
59 /* The most common offloads groups. */
60 #define MLX5_TXOFF_CONFIG_NONE 0
61 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
62 MLX5_TXOFF_CONFIG_TSO | \
63 MLX5_TXOFF_CONFIG_SWP | \
64 MLX5_TXOFF_CONFIG_CSUM | \
65 MLX5_TXOFF_CONFIG_INLINE | \
66 MLX5_TXOFF_CONFIG_VLAN | \
67 MLX5_TXOFF_CONFIG_METADATA)
69 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
71 #define MLX5_TXOFF_DECL(func, olx) \
72 static uint16_t mlx5_tx_burst_##func(void *txq, \
73 struct rte_mbuf **pkts, \
76 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
77 pkts, pkts_n, (olx)); \
80 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
82 static __rte_always_inline uint32_t
83 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
84 volatile struct mlx5_mini_cqe8 *mcqe);
86 static __rte_always_inline int
87 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
88 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
90 static __rte_always_inline uint32_t
91 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
93 static __rte_always_inline void
94 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
95 volatile struct mlx5_cqe *cqe,
96 volatile struct mlx5_mini_cqe8 *mcqe);
99 mlx5_queue_state_modify(struct rte_eth_dev *dev,
100 struct mlx5_mp_arg_queue_state_modify *sm);
103 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
104 volatile struct mlx5_cqe *__rte_restrict cqe,
105 uint32_t phcsum, uint8_t l4_type);
108 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
109 volatile struct mlx5_cqe *__rte_restrict cqe,
110 volatile struct mlx5_mini_cqe8 *mcqe,
111 struct mlx5_rxq_data *rxq, uint32_t len);
113 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
114 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
117 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
118 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
120 uint64_t rte_net_mlx5_dynf_inline_mask;
121 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
124 * Build a table to translate Rx completion flags to packet type.
126 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
129 mlx5_set_ptype_table(void)
132 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
134 /* Last entry must not be overwritten, reserved for errored packet. */
135 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
136 (*p)[i] = RTE_PTYPE_UNKNOWN;
138 * The index to the array should have:
139 * bit[1:0] = l3_hdr_type
140 * bit[4:2] = l4_hdr_type
143 * bit[7] = outer_l3_type
146 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
148 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_L4_NONFRAG;
150 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_L4_NONFRAG;
153 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
155 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 /* Repeat with outer_l3_type being set. Just in case. */
176 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_L4_NONFRAG;
178 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_L4_NONFRAG;
180 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
184 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
202 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L4_NONFRAG;
205 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
206 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L4_NONFRAG;
208 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
209 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_NONFRAG;
215 /* Tunneled - Fragmented */
216 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
222 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_FRAG;
225 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_FRAG;
229 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
262 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
272 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_UDP;
275 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_UDP;
281 * Build a table to translate packet to checksum type of Verbs.
284 mlx5_set_cksum_table(void)
290 * The index should have:
291 * bit[0] = PKT_TX_TCP_SEG
292 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
293 * bit[4] = PKT_TX_IP_CKSUM
294 * bit[8] = PKT_TX_OUTER_IP_CKSUM
297 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
300 /* Tunneled packet. */
301 if (i & (1 << 8)) /* Outer IP. */
302 v |= MLX5_ETH_WQE_L3_CSUM;
303 if (i & (1 << 4)) /* Inner IP. */
304 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
305 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
306 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
309 if (i & (1 << 4)) /* IP. */
310 v |= MLX5_ETH_WQE_L3_CSUM;
311 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
312 v |= MLX5_ETH_WQE_L4_CSUM;
314 mlx5_cksum_table[i] = v;
319 * Build a table to translate packet type of mbuf to SWP type of Verbs.
322 mlx5_set_swp_types_table(void)
328 * The index should have:
329 * bit[0:1] = PKT_TX_L4_MASK
330 * bit[4] = PKT_TX_IPV6
331 * bit[8] = PKT_TX_OUTER_IPV6
332 * bit[9] = PKT_TX_OUTER_UDP
334 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
337 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
339 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
341 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
342 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
343 v |= MLX5_ETH_WQE_L4_INNER_UDP;
344 mlx5_swp_types_table[i] = v;
349 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
350 * Flags must be preliminary initialized to zero.
353 * Pointer to burst routine local context.
355 * Pointer to store Software Parser flags
357 * Configured Tx offloads mask. It is fully defined at
358 * compile time and may be used for optimization.
361 * Software Parser offsets packed in dword.
362 * Software Parser flags are set by pointer.
364 static __rte_always_inline uint32_t
365 txq_mbuf_to_swp(struct mlx5_txq_local *__rte_restrict loc,
370 unsigned int idx, off;
373 if (!MLX5_TXOFF_CONFIG(SWP))
375 ol = loc->mbuf->ol_flags;
376 tunnel = ol & PKT_TX_TUNNEL_MASK;
378 * Check whether Software Parser is required.
379 * Only customized tunnels may ask for.
381 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
384 * The index should have:
385 * bit[0:1] = PKT_TX_L4_MASK
386 * bit[4] = PKT_TX_IPV6
387 * bit[8] = PKT_TX_OUTER_IPV6
388 * bit[9] = PKT_TX_OUTER_UDP
390 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
391 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
392 *swp_flags = mlx5_swp_types_table[idx];
394 * Set offsets for SW parser. Since ConnectX-5, SW parser just
395 * complements HW parser. SW parser starts to engage only if HW parser
396 * can't reach a header. For the older devices, HW parser will not kick
397 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
398 * should be set regardless of HW offload.
400 off = loc->mbuf->outer_l2_len;
401 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
402 off += sizeof(struct rte_vlan_hdr);
403 set = (off >> 1) << 8; /* Outer L3 offset. */
404 off += loc->mbuf->outer_l3_len;
405 if (tunnel == PKT_TX_TUNNEL_UDP)
406 set |= off >> 1; /* Outer L4 offset. */
407 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
408 const uint64_t csum = ol & PKT_TX_L4_MASK;
409 off += loc->mbuf->l2_len;
410 set |= (off >> 1) << 24; /* Inner L3 offset. */
411 if (csum == PKT_TX_TCP_CKSUM ||
412 csum == PKT_TX_UDP_CKSUM ||
413 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
414 off += loc->mbuf->l3_len;
415 set |= (off >> 1) << 16; /* Inner L4 offset. */
418 set = rte_cpu_to_le_32(set);
423 * Convert the Checksum offloads to Verbs.
426 * Pointer to the mbuf.
429 * Converted checksum flags.
431 static __rte_always_inline uint8_t
432 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
435 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
436 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
437 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
440 * The index should have:
441 * bit[0] = PKT_TX_TCP_SEG
442 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
443 * bit[4] = PKT_TX_IP_CKSUM
444 * bit[8] = PKT_TX_OUTER_IP_CKSUM
447 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
448 return mlx5_cksum_table[idx];
452 * Internal function to compute the number of used descriptors in an RX queue
458 * The number of used rx descriptor.
461 rx_queue_count(struct mlx5_rxq_data *rxq)
463 struct rxq_zip *zip = &rxq->zip;
464 volatile struct mlx5_cqe *cqe;
465 unsigned int cq_ci = rxq->cq_ci;
466 const unsigned int cqe_n = (1 << rxq->cqe_n);
467 const unsigned int cqe_cnt = cqe_n - 1;
468 unsigned int used = 0;
470 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
471 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
475 op_own = cqe->op_own;
476 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
477 if (unlikely(zip->ai))
478 n = zip->cqe_cnt - zip->ai;
480 n = rte_be_to_cpu_32(cqe->byte_cnt);
485 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
487 used = RTE_MIN(used, cqe_n);
492 * DPDK callback to check the status of a rx descriptor.
497 * The index of the descriptor in the ring.
500 * The status of the tx descriptor.
503 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
505 struct mlx5_rxq_data *rxq = rx_queue;
506 struct mlx5_rxq_ctrl *rxq_ctrl =
507 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
508 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
510 if (dev->rx_pkt_burst == NULL ||
511 dev->rx_pkt_burst == removed_rx_burst) {
515 if (offset >= (1 << rxq->cqe_n)) {
519 if (offset < rx_queue_count(rxq))
520 return RTE_ETH_RX_DESC_DONE;
521 return RTE_ETH_RX_DESC_AVAIL;
525 * DPDK callback to get the RX queue information
528 * Pointer to the device structure.
531 * Rx queue identificator.
534 * Pointer to the RX queue information structure.
541 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
542 struct rte_eth_rxq_info *qinfo)
544 struct mlx5_priv *priv = dev->data->dev_private;
545 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
546 struct mlx5_rxq_ctrl *rxq_ctrl =
547 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
551 qinfo->mp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
552 rxq->mprq_mp : rxq->mp;
553 qinfo->conf.rx_thresh.pthresh = 0;
554 qinfo->conf.rx_thresh.hthresh = 0;
555 qinfo->conf.rx_thresh.wthresh = 0;
556 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
557 qinfo->conf.rx_drop_en = 1;
558 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
559 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
560 qinfo->scattered_rx = dev->data->scattered_rx;
561 qinfo->nb_desc = 1 << rxq->elts_n;
565 * DPDK callback to get the RX packet burst mode information
568 * Pointer to the device structure.
571 * Rx queue identificatior.
574 * Pointer to the burts mode information.
577 * 0 as success, -EINVAL as failure.
581 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
582 uint16_t rx_queue_id __rte_unused,
583 struct rte_eth_burst_mode *mode)
585 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
586 struct mlx5_priv *priv = dev->data->dev_private;
587 struct mlx5_rxq_data *rxq;
589 rxq = (*priv->rxqs)[rx_queue_id];
594 if (pkt_burst == mlx5_rx_burst) {
595 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
596 } else if (pkt_burst == mlx5_rx_burst_mprq) {
597 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
598 } else if (pkt_burst == mlx5_rx_burst_vec) {
599 #if defined RTE_ARCH_X86_64
600 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
601 #elif defined RTE_ARCH_ARM64
602 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
603 #elif defined RTE_ARCH_PPC_64
604 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
608 } else if (pkt_burst == mlx5_rx_burst_mprq_vec) {
609 #if defined RTE_ARCH_X86_64
610 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector SSE");
611 #elif defined RTE_ARCH_ARM64
612 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector Neon");
613 #elif defined RTE_ARCH_PPC_64
614 snprintf(mode->info, sizeof(mode->info), "%s", "MPRQ Vector AltiVec");
625 * DPDK callback to get the number of used descriptors in a RX queue
628 * Pointer to the device structure.
634 * The number of used rx descriptor.
635 * -EINVAL if the queue is invalid
638 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
640 struct mlx5_priv *priv = dev->data->dev_private;
641 struct mlx5_rxq_data *rxq;
643 if (dev->rx_pkt_burst == NULL ||
644 dev->rx_pkt_burst == removed_rx_burst) {
648 rxq = (*priv->rxqs)[rx_queue_id];
653 return rx_queue_count(rxq);
656 #define MLX5_SYSTEM_LOG_DIR "/var/log"
658 * Dump debug information to log file.
663 * If not NULL this string is printed as a header to the output
664 * and the output will be in hexadecimal view.
666 * This is the buffer address to print out.
668 * The number of bytes to dump out.
671 mlx5_dump_debug_information(const char *fname, const char *hex_title,
672 const void *buf, unsigned int hex_len)
676 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
677 fd = fopen(path, "a+");
679 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
680 MKSTR(path2, "./%s", fname);
681 fd = fopen(path2, "a+");
683 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
686 DRV_LOG(INFO, "New debug dump in file %s", path2);
688 DRV_LOG(INFO, "New debug dump in file %s", path);
691 rte_hexdump(fd, hex_title, buf, hex_len);
693 fprintf(fd, "%s", (const char *)buf);
694 fprintf(fd, "\n\n\n");
699 * Move QP from error state to running state and initialize indexes.
702 * Pointer to TX queue control structure.
705 * 0 on success, else -1.
708 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
710 struct mlx5_mp_arg_queue_state_modify sm = {
712 .queue_id = txq_ctrl->txq.idx,
715 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
717 txq_ctrl->txq.wqe_ci = 0;
718 txq_ctrl->txq.wqe_pi = 0;
719 txq_ctrl->txq.elts_comp = 0;
723 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
725 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
727 static const uint8_t magic[] = "seen";
731 for (i = 0; i < sizeof(magic); ++i)
732 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
734 err_cqe->rsvd1[i] = magic[i];
743 * Pointer to TX queue structure.
745 * Pointer to the error CQE.
748 * Negative value if queue recovery failed, otherwise
749 * the error completion entry is handled successfully.
752 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *__rte_restrict txq,
753 volatile struct mlx5_err_cqe *err_cqe)
755 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
756 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
757 struct mlx5_txq_ctrl *txq_ctrl =
758 container_of(txq, struct mlx5_txq_ctrl, txq);
759 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
760 int seen = check_err_cqe_seen(err_cqe);
762 if (!seen && txq_ctrl->dump_file_n <
763 txq_ctrl->priv->config.max_dump_files_num) {
764 MKSTR(err_str, "Unexpected CQE error syndrome "
765 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
766 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
767 txq->cqe_s, txq->qp_num_8s >> 8,
768 rte_be_to_cpu_16(err_cqe->wqe_counter),
769 txq->wqe_ci, txq->cq_ci);
770 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
771 PORT_ID(txq_ctrl->priv), txq->idx,
772 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
773 mlx5_dump_debug_information(name, NULL, err_str, 0);
774 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
775 (const void *)((uintptr_t)
779 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
780 (const void *)((uintptr_t)
784 txq_ctrl->dump_file_n++;
788 * Count errors in WQEs units.
789 * Later it can be improved to count error packets,
790 * for example, by SQ parsing to find how much packets
791 * should be counted for each WQE.
793 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
795 if (tx_recover_qp(txq_ctrl)) {
796 /* Recovering failed - retry later on the same WQE. */
799 /* Release all the remaining buffers. */
800 txq_free_elts(txq_ctrl);
806 * Translate RX completion flags to packet type.
809 * Pointer to RX queue structure.
813 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
816 * Packet type for struct rte_mbuf.
818 static inline uint32_t
819 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
820 volatile struct mlx5_mini_cqe8 *mcqe)
824 uint8_t pinfo = (cqe->pkt_info & 0x3) << 6;
826 /* Get l3/l4 header from mini-CQE in case L3/L4 format*/
828 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
829 ptype = (cqe->hdr_type_etc & 0xfc00) >> 10;
831 ptype = mcqe->hdr_type >> 2;
833 * The index to the array should have:
834 * bit[1:0] = l3_hdr_type
835 * bit[4:2] = l4_hdr_type
838 * bit[7] = outer_l3_type
841 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
845 * Initialize Rx WQ and indexes.
848 * Pointer to RX queue structure.
851 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
853 const unsigned int wqe_n = 1 << rxq->elts_n;
856 for (i = 0; (i != wqe_n); ++i) {
857 volatile struct mlx5_wqe_data_seg *scat;
861 if (mlx5_rxq_mprq_enabled(rxq)) {
862 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
864 scat = &((volatile struct mlx5_wqe_mprq *)
866 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
867 1 << rxq->strd_num_n);
868 byte_count = (1 << rxq->strd_sz_n) *
869 (1 << rxq->strd_num_n);
871 struct rte_mbuf *buf = (*rxq->elts)[i];
873 scat = &((volatile struct mlx5_wqe_data_seg *)
875 addr = rte_pktmbuf_mtod(buf, uintptr_t);
876 byte_count = DATA_LEN(buf);
878 /* scat->addr must be able to store a pointer. */
879 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
880 *scat = (struct mlx5_wqe_data_seg){
881 .addr = rte_cpu_to_be_64(addr),
882 .byte_count = rte_cpu_to_be_32(byte_count),
883 .lkey = mlx5_rx_addr2mr(rxq, addr),
886 rxq->consumed_strd = 0;
887 rxq->decompressed = 0;
889 rxq->zip = (struct rxq_zip){
892 rxq->elts_ci = mlx5_rxq_mprq_enabled(rxq) ?
893 (wqe_n >> rxq->sges_n) * (1 << rxq->strd_num_n) : 0;
894 /* Update doorbell counter. */
895 rxq->rq_ci = wqe_n >> rxq->sges_n;
897 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
901 * Modify a Verbs/DevX queue state.
902 * This must be called from the primary process.
905 * Pointer to Ethernet device.
907 * State modify request parameters.
910 * 0 in case of success else non-zero value and rte_errno is set.
913 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
914 const struct mlx5_mp_arg_queue_state_modify *sm)
917 struct mlx5_priv *priv = dev->data->dev_private;
920 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
921 struct mlx5_rxq_ctrl *rxq_ctrl =
922 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
924 ret = priv->obj_ops.rxq_obj_modify(rxq_ctrl->obj, sm->state);
926 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
927 sm->state, strerror(errno));
932 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
933 struct mlx5_txq_ctrl *txq_ctrl =
934 container_of(txq, struct mlx5_txq_ctrl, txq);
936 ret = priv->obj_ops.txq_obj_modify(txq_ctrl->obj,
937 MLX5_TXQ_MOD_ERR2RDY,
938 (uint8_t)priv->dev_port);
946 * Modify a Verbs queue state.
949 * Pointer to Ethernet device.
951 * State modify request parameters.
954 * 0 in case of success else non-zero value.
957 mlx5_queue_state_modify(struct rte_eth_dev *dev,
958 struct mlx5_mp_arg_queue_state_modify *sm)
960 struct mlx5_priv *priv = dev->data->dev_private;
963 switch (rte_eal_process_type()) {
964 case RTE_PROC_PRIMARY:
965 ret = mlx5_queue_state_modify_primary(dev, sm);
967 case RTE_PROC_SECONDARY:
968 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
978 * The function inserts the RQ state to reset when the first error CQE is
979 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
980 * it moves the RQ state to ready and initializes the RQ.
981 * Next CQE identification and error counting are in the caller responsibility.
984 * Pointer to RX queue structure.
986 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
987 * 0 when called from non-vectorized Rx burst.
990 * -1 in case of recovery error, otherwise the CQE status.
993 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
995 const uint16_t cqe_n = 1 << rxq->cqe_n;
996 const uint16_t cqe_mask = cqe_n - 1;
997 const uint16_t wqe_n = 1 << rxq->elts_n;
998 const uint16_t strd_n = 1 << rxq->strd_num_n;
999 struct mlx5_rxq_ctrl *rxq_ctrl =
1000 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1002 volatile struct mlx5_cqe *cqe;
1003 volatile struct mlx5_err_cqe *err_cqe;
1005 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1007 struct mlx5_mp_arg_queue_state_modify sm;
1010 switch (rxq->err_state) {
1011 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1012 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1014 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1016 sm.queue_id = rxq->idx;
1017 sm.state = IBV_WQS_RESET;
1018 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1020 if (rxq_ctrl->dump_file_n <
1021 rxq_ctrl->priv->config.max_dump_files_num) {
1022 MKSTR(err_str, "Unexpected CQE error syndrome "
1023 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1024 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1025 rxq->cqn, rxq_ctrl->wqn,
1026 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1027 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1028 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1029 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1030 mlx5_dump_debug_information(name, NULL, err_str, 0);
1031 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1032 (const void *)((uintptr_t)
1034 sizeof(*u.cqe) * cqe_n);
1035 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1036 (const void *)((uintptr_t)
1039 rxq_ctrl->dump_file_n++;
1041 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1043 case MLX5_RXQ_ERR_STATE_NEED_READY:
1044 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1045 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1047 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1050 * The RQ consumer index must be zeroed while moving
1051 * from RESET state to RDY state.
1053 *rxq->rq_db = rte_cpu_to_be_32(0);
1056 sm.queue_id = rxq->idx;
1057 sm.state = IBV_WQS_RDY;
1058 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1062 const uint32_t elts_n =
1063 mlx5_rxq_mprq_enabled(rxq) ?
1064 wqe_n * strd_n : wqe_n;
1065 const uint32_t e_mask = elts_n - 1;
1067 mlx5_rxq_mprq_enabled(rxq) ?
1068 rxq->elts_ci : rxq->rq_ci;
1070 struct rte_mbuf **elt;
1072 unsigned int n = elts_n - (elts_ci -
1075 for (i = 0; i < (int)n; ++i) {
1076 elt_idx = (elts_ci + i) & e_mask;
1077 elt = &(*rxq->elts)[elt_idx];
1078 *elt = rte_mbuf_raw_alloc(rxq->mp);
1080 for (i--; i >= 0; --i) {
1081 elt_idx = (elts_ci +
1085 rte_pktmbuf_free_seg
1091 for (i = 0; i < (int)elts_n; ++i) {
1092 elt = &(*rxq->elts)[i];
1094 (uint16_t)((*elt)->buf_len -
1095 rte_pktmbuf_headroom(*elt));
1097 /* Padding with a fake mbuf for vec Rx. */
1098 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1099 (*rxq->elts)[elts_n + i] =
1102 mlx5_rxq_initialize(rxq);
1103 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1112 * Get size of the next packet for a given CQE. For compressed CQEs, the
1113 * consumer index is updated only once all packets of the current one have
1117 * Pointer to RX queue.
1121 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1125 * 0 in case of empty CQE, otherwise the packet size in bytes.
1128 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1129 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1131 struct rxq_zip *zip = &rxq->zip;
1132 uint16_t cqe_n = cqe_cnt + 1;
1138 /* Process compressed data in the CQE and mini arrays. */
1140 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1141 (volatile struct mlx5_mini_cqe8 (*)[8])
1142 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1144 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt &
1146 *mcqe = &(*mc)[zip->ai & 7];
1147 if ((++zip->ai & 7) == 0) {
1148 /* Invalidate consumed CQEs */
1151 while (idx != end) {
1152 (*rxq->cqes)[idx & cqe_cnt].op_own =
1153 MLX5_CQE_INVALIDATE;
1157 * Increment consumer index to skip the number
1158 * of CQEs consumed. Hardware leaves holes in
1159 * the CQ ring for software use.
1164 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1165 /* Invalidate the rest */
1169 while (idx != end) {
1170 (*rxq->cqes)[idx & cqe_cnt].op_own =
1171 MLX5_CQE_INVALIDATE;
1174 rxq->cq_ci = zip->cq_ci;
1178 * No compressed data, get next CQE and verify if it is
1186 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1187 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1188 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1190 ret = mlx5_rx_err_handle(rxq, 0);
1191 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1199 * Introduce the local variable to have queue cq_ci
1200 * index in queue structure always consistent with
1201 * actual CQE boundary (not pointing to the middle
1202 * of compressed CQE session).
1204 cq_ci = rxq->cq_ci + 1;
1205 op_own = cqe->op_own;
1206 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1207 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1208 (volatile struct mlx5_mini_cqe8 (*)[8])
1209 (uintptr_t)(&(*rxq->cqes)
1210 [cq_ci & cqe_cnt].pkt_info);
1212 /* Fix endianness. */
1213 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1215 * Current mini array position is the one
1216 * returned by check_cqe64().
1218 * If completion comprises several mini arrays,
1219 * as a special case the second one is located
1220 * 7 CQEs after the initial CQE instead of 8
1221 * for subsequent ones.
1224 zip->na = zip->ca + 7;
1225 /* Compute the next non compressed CQE. */
1226 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1227 /* Get packet size to return. */
1228 len = rte_be_to_cpu_32((*mc)[0].byte_cnt &
1232 /* Prefetch all to be invalidated */
1235 while (idx != end) {
1236 rte_prefetch0(&(*rxq->cqes)[(idx) &
1242 len = rte_be_to_cpu_32(cqe->byte_cnt);
1245 if (unlikely(rxq->err_state)) {
1246 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1247 ++rxq->stats.idropped;
1255 * Translate RX completion flags to offload flags.
1261 * Offload flags (ol_flags) for struct rte_mbuf.
1263 static inline uint32_t
1264 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1266 uint32_t ol_flags = 0;
1267 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1271 MLX5_CQE_RX_L3_HDR_VALID,
1272 PKT_RX_IP_CKSUM_GOOD) |
1274 MLX5_CQE_RX_L4_HDR_VALID,
1275 PKT_RX_L4_CKSUM_GOOD);
1280 * Fill in mbuf fields from RX completion flags.
1281 * Note that pkt->ol_flags should be initialized outside of this function.
1284 * Pointer to RX queue.
1289 * @param rss_hash_res
1290 * Packet RSS Hash result.
1293 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1294 volatile struct mlx5_cqe *cqe,
1295 volatile struct mlx5_mini_cqe8 *mcqe)
1297 /* Update packet information. */
1298 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe, mcqe);
1300 if (rxq->rss_hash) {
1301 uint32_t rss_hash_res = 0;
1303 /* If compressed, take hash result from mini-CQE. */
1305 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_HASH)
1306 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1308 rss_hash_res = rte_be_to_cpu_32(mcqe->rx_hash_result);
1310 pkt->hash.rss = rss_hash_res;
1311 pkt->ol_flags |= PKT_RX_RSS_HASH;
1317 /* If compressed, take flow tag from mini-CQE. */
1319 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1320 mark = cqe->sop_drop_qpn;
1322 mark = ((mcqe->byte_cnt_flow & 0xff) << 8) |
1323 (mcqe->flow_tag_high << 16);
1324 if (MLX5_FLOW_MARK_IS_VALID(mark)) {
1325 pkt->ol_flags |= PKT_RX_FDIR;
1326 if (mark != RTE_BE32(MLX5_FLOW_MARK_DEFAULT)) {
1327 pkt->ol_flags |= PKT_RX_FDIR_ID;
1328 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1332 if (rxq->dynf_meta && cqe->flow_table_metadata) {
1333 pkt->ol_flags |= rxq->flow_meta_mask;
1334 *RTE_MBUF_DYNFIELD(pkt, rxq->flow_meta_offset, uint32_t *) =
1335 cqe->flow_table_metadata;
1338 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1339 if (rxq->vlan_strip) {
1343 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1344 vlan_strip = cqe->hdr_type_etc &
1345 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1347 vlan_strip = mcqe->hdr_type &
1348 RTE_BE16(MLX5_CQE_VLAN_STRIPPED);
1350 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1351 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1354 if (rxq->hw_timestamp) {
1355 uint64_t ts = rte_be_to_cpu_64(cqe->timestamp);
1357 if (rxq->rt_timestamp)
1358 ts = mlx5_txpp_convert_rx_ts(rxq->sh, ts);
1359 mlx5_timestamp_set(pkt, rxq->timestamp_offset, ts);
1360 pkt->ol_flags |= rxq->timestamp_rx_flag;
1365 * DPDK callback for RX.
1368 * Generic pointer to RX queue structure.
1370 * Array to store received packets.
1372 * Maximum number of packets in array.
1375 * Number of packets successfully received (<= pkts_n).
1378 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1380 struct mlx5_rxq_data *rxq = dpdk_rxq;
1381 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1382 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1383 const unsigned int sges_n = rxq->sges_n;
1384 struct rte_mbuf *pkt = NULL;
1385 struct rte_mbuf *seg = NULL;
1386 volatile struct mlx5_cqe *cqe =
1387 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1389 unsigned int rq_ci = rxq->rq_ci << sges_n;
1390 int len = 0; /* keep its value across iterations. */
1393 unsigned int idx = rq_ci & wqe_cnt;
1394 volatile struct mlx5_wqe_data_seg *wqe =
1395 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1396 struct rte_mbuf *rep = (*rxq->elts)[idx];
1397 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1405 /* Allocate the buf from the same pool. */
1406 rep = rte_mbuf_raw_alloc(seg->pool);
1407 if (unlikely(rep == NULL)) {
1408 ++rxq->stats.rx_nombuf;
1411 * no buffers before we even started,
1412 * bail out silently.
1416 while (pkt != seg) {
1417 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1421 rte_mbuf_raw_free(pkt);
1427 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1428 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1430 rte_mbuf_raw_free(rep);
1434 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1435 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1436 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1437 if (rxq->crc_present)
1438 len -= RTE_ETHER_CRC_LEN;
1440 if (cqe->lro_num_seg > 1) {
1442 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1444 pkt->ol_flags |= PKT_RX_LRO;
1445 pkt->tso_segsz = len / cqe->lro_num_seg;
1448 DATA_LEN(rep) = DATA_LEN(seg);
1449 PKT_LEN(rep) = PKT_LEN(seg);
1450 SET_DATA_OFF(rep, DATA_OFF(seg));
1451 PORT(rep) = PORT(seg);
1452 (*rxq->elts)[idx] = rep;
1454 * Fill NIC descriptor with the new buffer. The lkey and size
1455 * of the buffers are already known, only the buffer address
1458 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1459 /* If there's only one MR, no need to replace LKey in WQE. */
1460 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1461 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1462 if (len > DATA_LEN(seg)) {
1463 len -= DATA_LEN(seg);
1468 DATA_LEN(seg) = len;
1469 #ifdef MLX5_PMD_SOFT_COUNTERS
1470 /* Increment bytes counter. */
1471 rxq->stats.ibytes += PKT_LEN(pkt);
1473 /* Return packet. */
1478 /* Align consumer index to the next stride. */
1483 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1485 /* Update the consumer index. */
1486 rxq->rq_ci = rq_ci >> sges_n;
1488 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1490 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1491 #ifdef MLX5_PMD_SOFT_COUNTERS
1492 /* Increment packets counter. */
1493 rxq->stats.ipackets += i;
1499 * Update LRO packet TCP header.
1500 * The HW LRO feature doesn't update the TCP header after coalescing the
1501 * TCP segments but supplies information in CQE to fill it by SW.
1504 * Pointer to the TCP header.
1506 * Pointer to the completion entry..
1508 * The L3 pseudo-header checksum.
1511 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *__rte_restrict tcp,
1512 volatile struct mlx5_cqe *__rte_restrict cqe,
1513 uint32_t phcsum, uint8_t l4_type)
1516 * The HW calculates only the TCP payload checksum, need to complete
1517 * the TCP header checksum and the L3 pseudo-header checksum.
1519 uint32_t csum = phcsum + cqe->csum;
1521 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1522 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1523 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1524 tcp->recv_ack = cqe->lro_ack_seq_num;
1525 tcp->rx_win = cqe->lro_tcp_win;
1527 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1528 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1530 csum += rte_raw_cksum(tcp, (tcp->data_off >> 4) * 4);
1531 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1532 csum = (~csum) & 0xffff;
1539 * Update LRO packet headers.
1540 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1541 * TCP segments but supply information in CQE to fill it by SW.
1544 * The packet address.
1546 * Pointer to the completion entry..
1548 * The packet length.
1551 mlx5_lro_update_hdr(uint8_t *__rte_restrict padd,
1552 volatile struct mlx5_cqe *__rte_restrict cqe,
1553 volatile struct mlx5_mini_cqe8 *mcqe,
1554 struct mlx5_rxq_data *rxq, uint32_t len)
1557 struct rte_ether_hdr *eth;
1558 struct rte_vlan_hdr *vlan;
1559 struct rte_ipv4_hdr *ipv4;
1560 struct rte_ipv6_hdr *ipv6;
1561 struct rte_tcp_hdr *tcp;
1566 uint16_t proto = h.eth->ether_type;
1571 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1572 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1573 proto = h.vlan->eth_proto;
1576 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1577 h.ipv4->time_to_live = cqe->lro_min_ttl;
1578 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1579 h.ipv4->hdr_checksum = 0;
1580 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1581 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1584 h.ipv6->hop_limits = cqe->lro_min_ttl;
1585 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1587 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1591 rxq->mcqe_format != MLX5_CQE_RESP_FORMAT_L34H_STRIDX)
1592 l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1593 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1595 l4_type = (rte_be_to_cpu_16(mcqe->hdr_type) &
1596 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1597 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum, l4_type);
1601 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1603 struct mlx5_mprq_buf *buf = opaque;
1605 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) == 1) {
1606 rte_mempool_put(buf->mp, buf);
1607 } else if (unlikely(__atomic_sub_fetch(&buf->refcnt, 1,
1608 __ATOMIC_RELAXED) == 0)) {
1609 __atomic_store_n(&buf->refcnt, 1, __ATOMIC_RELAXED);
1610 rte_mempool_put(buf->mp, buf);
1615 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1617 mlx5_mprq_buf_free_cb(NULL, buf);
1621 * DPDK callback for RX with Multi-Packet RQ support.
1624 * Generic pointer to RX queue structure.
1626 * Array to store received packets.
1628 * Maximum number of packets in array.
1631 * Number of packets successfully received (<= pkts_n).
1634 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1636 struct mlx5_rxq_data *rxq = dpdk_rxq;
1637 const uint32_t strd_n = 1 << rxq->strd_num_n;
1638 const uint32_t strd_sz = 1 << rxq->strd_sz_n;
1639 const uint32_t cq_mask = (1 << rxq->cqe_n) - 1;
1640 const uint32_t wq_mask = (1 << rxq->elts_n) - 1;
1641 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1643 uint32_t rq_ci = rxq->rq_ci;
1644 uint16_t consumed_strd = rxq->consumed_strd;
1645 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1647 while (i < pkts_n) {
1648 struct rte_mbuf *pkt;
1654 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1655 enum mlx5_rqx_code rxq_code;
1657 if (consumed_strd == strd_n) {
1658 /* Replace WQE if the buffer is still in use. */
1659 mprq_buf_replace(rxq, rq_ci & wq_mask);
1660 /* Advance to the next WQE. */
1663 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1665 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1666 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1670 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1671 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1672 if (rxq->crc_present)
1673 len -= RTE_ETHER_CRC_LEN;
1675 rxq->mcqe_format == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX)
1676 strd_cnt = (len / strd_sz) + !!(len % strd_sz);
1678 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1679 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1680 MLX5_ASSERT(strd_cnt);
1681 consumed_strd += strd_cnt;
1682 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1684 strd_idx = rte_be_to_cpu_16(mcqe == NULL ?
1687 MLX5_ASSERT(strd_idx < strd_n);
1688 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1690 pkt = rte_pktmbuf_alloc(rxq->mp);
1691 if (unlikely(pkt == NULL)) {
1692 ++rxq->stats.rx_nombuf;
1695 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1696 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1697 if (rxq->crc_present)
1698 len -= RTE_ETHER_CRC_LEN;
1699 rxq_code = mprq_buf_to_pkt(rxq, pkt, len, buf,
1700 strd_idx, strd_cnt);
1701 if (unlikely(rxq_code != MLX5_RXQ_CODE_EXIT)) {
1702 rte_pktmbuf_free_seg(pkt);
1703 if (rxq_code == MLX5_RXQ_CODE_DROPPED) {
1704 ++rxq->stats.idropped;
1707 if (rxq_code == MLX5_RXQ_CODE_NOMBUF) {
1708 ++rxq->stats.rx_nombuf;
1712 rxq_cq_to_mbuf(rxq, pkt, cqe, mcqe);
1713 if (cqe->lro_num_seg > 1) {
1714 mlx5_lro_update_hdr(rte_pktmbuf_mtod(pkt, uint8_t *),
1715 cqe, mcqe, rxq, len);
1716 pkt->ol_flags |= PKT_RX_LRO;
1717 pkt->tso_segsz = len / cqe->lro_num_seg;
1720 PORT(pkt) = rxq->port_id;
1721 #ifdef MLX5_PMD_SOFT_COUNTERS
1722 /* Increment bytes counter. */
1723 rxq->stats.ibytes += PKT_LEN(pkt);
1725 /* Return packet. */
1729 /* Update the consumer indexes. */
1730 rxq->consumed_strd = consumed_strd;
1732 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1733 if (rq_ci != rxq->rq_ci) {
1736 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1738 #ifdef MLX5_PMD_SOFT_COUNTERS
1739 /* Increment packets counter. */
1740 rxq->stats.ipackets += i;
1746 * Dummy DPDK callback for TX.
1748 * This function is used to temporarily replace the real callback during
1749 * unsafe control operations on the queue, or in case of error.
1752 * Generic pointer to TX queue structure.
1754 * Packets to transmit.
1756 * Number of packets in array.
1759 * Number of packets successfully transmitted (<= pkts_n).
1762 removed_tx_burst(void *dpdk_txq __rte_unused,
1763 struct rte_mbuf **pkts __rte_unused,
1764 uint16_t pkts_n __rte_unused)
1771 * Dummy DPDK callback for RX.
1773 * This function is used to temporarily replace the real callback during
1774 * unsafe control operations on the queue, or in case of error.
1777 * Generic pointer to RX queue structure.
1779 * Array to store received packets.
1781 * Maximum number of packets in array.
1784 * Number of packets successfully received (<= pkts_n).
1787 removed_rx_burst(void *dpdk_txq __rte_unused,
1788 struct rte_mbuf **pkts __rte_unused,
1789 uint16_t pkts_n __rte_unused)
1796 * Vectorized Rx/Tx routines are not compiled in when required vector
1797 * instructions are not supported on a target architecture. The following null
1798 * stubs are needed for linkage when those are not included outside of this file
1799 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1803 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1804 struct rte_mbuf **pkts __rte_unused,
1805 uint16_t pkts_n __rte_unused)
1811 mlx5_rx_burst_mprq_vec(void *dpdk_txq __rte_unused,
1812 struct rte_mbuf **pkts __rte_unused,
1813 uint16_t pkts_n __rte_unused)
1819 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1825 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1831 * Free the mbufs from the linear array of pointers.
1834 * Pointer to array of packets to be free.
1836 * Number of packets to be freed.
1838 * Configured Tx offloads mask. It is fully defined at
1839 * compile time and may be used for optimization.
1841 static __rte_always_inline void
1842 mlx5_tx_free_mbuf(struct rte_mbuf **__rte_restrict pkts,
1843 unsigned int pkts_n,
1844 unsigned int olx __rte_unused)
1846 struct rte_mempool *pool = NULL;
1847 struct rte_mbuf **p_free = NULL;
1848 struct rte_mbuf *mbuf;
1849 unsigned int n_free = 0;
1852 * The implemented algorithm eliminates
1853 * copying pointers to temporary array
1854 * for rte_mempool_put_bulk() calls.
1857 MLX5_ASSERT(pkts_n);
1861 * Decrement mbuf reference counter, detach
1862 * indirect and external buffers if needed.
1864 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1865 if (likely(mbuf != NULL)) {
1866 MLX5_ASSERT(mbuf == *pkts);
1867 if (likely(n_free != 0)) {
1868 if (unlikely(pool != mbuf->pool))
1869 /* From different pool. */
1872 /* Start new scan array. */
1879 if (unlikely(pkts_n == 0)) {
1885 * This happens if mbuf is still referenced.
1886 * We can't put it back to the pool, skip.
1890 if (unlikely(n_free != 0))
1891 /* There is some array to free.*/
1893 if (unlikely(pkts_n == 0))
1894 /* Last mbuf, nothing to free. */
1900 * This loop is implemented to avoid multiple
1901 * inlining of rte_mempool_put_bulk().
1904 MLX5_ASSERT(p_free);
1905 MLX5_ASSERT(n_free);
1907 * Free the array of pre-freed mbufs
1908 * belonging to the same memory pool.
1910 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1911 if (unlikely(mbuf != NULL)) {
1912 /* There is the request to start new scan. */
1917 if (likely(pkts_n != 0))
1920 * This is the last mbuf to be freed.
1921 * Do one more loop iteration to complete.
1922 * This is rare case of the last unique mbuf.
1927 if (likely(pkts_n == 0))
1936 * Free the mbuf from the elts ring buffer till new tail.
1939 * Pointer to Tx queue structure.
1941 * Index in elts to free up to, becomes new elts tail.
1943 * Configured Tx offloads mask. It is fully defined at
1944 * compile time and may be used for optimization.
1946 static __rte_always_inline void
1947 mlx5_tx_free_elts(struct mlx5_txq_data *__rte_restrict txq,
1949 unsigned int olx __rte_unused)
1951 uint16_t n_elts = tail - txq->elts_tail;
1953 MLX5_ASSERT(n_elts);
1954 MLX5_ASSERT(n_elts <= txq->elts_s);
1956 * Implement a loop to support ring buffer wraparound
1957 * with single inlining of mlx5_tx_free_mbuf().
1962 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1963 part = RTE_MIN(part, n_elts);
1965 MLX5_ASSERT(part <= txq->elts_s);
1966 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1968 txq->elts_tail += part;
1974 * Store the mbuf being sent into elts ring buffer.
1975 * On Tx completion these mbufs will be freed.
1978 * Pointer to Tx queue structure.
1980 * Pointer to array of packets to be stored.
1982 * Number of packets to be stored.
1984 * Configured Tx offloads mask. It is fully defined at
1985 * compile time and may be used for optimization.
1987 static __rte_always_inline void
1988 mlx5_tx_copy_elts(struct mlx5_txq_data *__rte_restrict txq,
1989 struct rte_mbuf **__rte_restrict pkts,
1990 unsigned int pkts_n,
1991 unsigned int olx __rte_unused)
1994 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
1997 MLX5_ASSERT(pkts_n);
1998 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2000 MLX5_ASSERT(part <= txq->elts_s);
2001 /* This code is a good candidate for vectorizing with SIMD. */
2002 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2004 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2005 txq->elts_head += pkts_n;
2006 if (unlikely(part < pkts_n))
2007 /* The copy is wrapping around the elts array. */
2008 rte_memcpy((void *)elts, (void *)(pkts + part),
2009 (pkts_n - part) * sizeof(struct rte_mbuf *));
2013 * Update completion queue consuming index via doorbell
2014 * and flush the completed data buffers.
2017 * Pointer to TX queue structure.
2018 * @param valid CQE pointer
2019 * if not NULL update txq->wqe_pi and flush the buffers
2021 * Configured Tx offloads mask. It is fully defined at
2022 * compile time and may be used for optimization.
2024 static __rte_always_inline void
2025 mlx5_tx_comp_flush(struct mlx5_txq_data *__rte_restrict txq,
2026 volatile struct mlx5_cqe *last_cqe,
2027 unsigned int olx __rte_unused)
2029 if (likely(last_cqe != NULL)) {
2032 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2033 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2034 if (likely(tail != txq->elts_tail)) {
2035 mlx5_tx_free_elts(txq, tail, olx);
2036 MLX5_ASSERT(tail == txq->elts_tail);
2042 * Manage TX completions. This routine checks the CQ for
2043 * arrived CQEs, deduces the last accomplished WQE in SQ,
2044 * updates SQ producing index and frees all completed mbufs.
2047 * Pointer to TX queue structure.
2049 * Configured Tx offloads mask. It is fully defined at
2050 * compile time and may be used for optimization.
2052 * NOTE: not inlined intentionally, it makes tx_burst
2053 * routine smaller, simple and faster - from experiments.
2056 mlx5_tx_handle_completion(struct mlx5_txq_data *__rte_restrict txq,
2057 unsigned int olx __rte_unused)
2059 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2060 volatile struct mlx5_cqe *last_cqe = NULL;
2061 bool ring_doorbell = false;
2064 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2065 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2067 volatile struct mlx5_cqe *cqe;
2069 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2070 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2071 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2072 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2073 /* No new CQEs in completion queue. */
2074 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2078 * Some error occurred, try to restart.
2079 * We have no barrier after WQE related Doorbell
2080 * written, make sure all writes are completed
2081 * here, before we might perform SQ reset.
2084 ret = mlx5_tx_error_cqe_handle
2085 (txq, (volatile struct mlx5_err_cqe *)cqe);
2086 if (unlikely(ret < 0)) {
2088 * Some error occurred on queue error
2089 * handling, we do not advance the index
2090 * here, allowing to retry on next call.
2095 * We are going to fetch all entries with
2096 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2097 * The send queue is supposed to be empty.
2099 ring_doorbell = true;
2101 txq->cq_pi = txq->cq_ci;
2105 /* Normal transmit completion. */
2106 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2107 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2109 ring_doorbell = true;
2113 * We have to restrict the amount of processed CQEs
2114 * in one tx_burst routine call. The CQ may be large
2115 * and many CQEs may be updated by the NIC in one
2116 * transaction. Buffers freeing is time consuming,
2117 * multiple iterations may introduce significant
2120 if (likely(--count == 0))
2123 if (likely(ring_doorbell)) {
2124 /* Ring doorbell to notify hardware. */
2125 rte_compiler_barrier();
2126 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2127 mlx5_tx_comp_flush(txq, last_cqe, olx);
2132 * Check if the completion request flag should be set in the last WQE.
2133 * Both pushed mbufs and WQEs are monitored and the completion request
2134 * flag is set if any of thresholds is reached.
2137 * Pointer to TX queue structure.
2139 * Pointer to burst routine local context.
2141 * Configured Tx offloads mask. It is fully defined at
2142 * compile time and may be used for optimization.
2144 static __rte_always_inline void
2145 mlx5_tx_request_completion(struct mlx5_txq_data *__rte_restrict txq,
2146 struct mlx5_txq_local *__rte_restrict loc,
2149 uint16_t head = txq->elts_head;
2152 part = MLX5_TXOFF_CONFIG(INLINE) ?
2153 0 : loc->pkts_sent - loc->pkts_copy;
2155 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2156 (MLX5_TXOFF_CONFIG(INLINE) &&
2157 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2158 volatile struct mlx5_wqe *last = loc->wqe_last;
2161 txq->elts_comp = head;
2162 if (MLX5_TXOFF_CONFIG(INLINE))
2163 txq->wqe_comp = txq->wqe_ci;
2164 /* Request unconditional completion on last WQE. */
2165 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2166 MLX5_COMP_MODE_OFFSET);
2167 /* Save elts_head in dedicated free on completion queue. */
2168 #ifdef RTE_LIBRTE_MLX5_DEBUG
2169 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2170 (last->cseg.opcode >> 8) << 16;
2172 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2174 /* A CQE slot must always be available. */
2175 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2180 * DPDK callback to check the status of a tx descriptor.
2185 * The index of the descriptor in the ring.
2188 * The status of the tx descriptor.
2191 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2193 struct mlx5_txq_data *__rte_restrict txq = tx_queue;
2196 mlx5_tx_handle_completion(txq, 0);
2197 used = txq->elts_head - txq->elts_tail;
2199 return RTE_ETH_TX_DESC_FULL;
2200 return RTE_ETH_TX_DESC_DONE;
2204 * Build the Control Segment with specified opcode:
2205 * - MLX5_OPCODE_SEND
2206 * - MLX5_OPCODE_ENHANCED_MPSW
2210 * Pointer to TX queue structure.
2212 * Pointer to burst routine local context.
2214 * Pointer to WQE to fill with built Control Segment.
2216 * Supposed length of WQE in segments.
2218 * SQ WQE opcode to put into Control Segment.
2220 * Configured Tx offloads mask. It is fully defined at
2221 * compile time and may be used for optimization.
2223 static __rte_always_inline void
2224 mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq,
2225 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2226 struct mlx5_wqe *__rte_restrict wqe,
2228 unsigned int opcode,
2229 unsigned int olx __rte_unused)
2231 struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg;
2233 /* For legacy MPW replace the EMPW by TSO with modifier. */
2234 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2235 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2236 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2237 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2238 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2239 MLX5_COMP_MODE_OFFSET);
2240 cs->misc = RTE_BE32(0);
2244 * Build the Synchronize Queue Segment with specified completion index.
2247 * Pointer to TX queue structure.
2249 * Pointer to burst routine local context.
2251 * Pointer to WQE to fill with built Control Segment.
2253 * Completion index in Clock Queue to wait.
2255 * Configured Tx offloads mask. It is fully defined at
2256 * compile time and may be used for optimization.
2258 static __rte_always_inline void
2259 mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
2260 struct mlx5_txq_local *restrict loc __rte_unused,
2261 struct mlx5_wqe *restrict wqe,
2263 unsigned int olx __rte_unused)
2265 struct mlx5_wqe_qseg *qs;
2267 qs = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
2268 qs->max_index = rte_cpu_to_be_32(wci);
2269 qs->qpn_cqn = rte_cpu_to_be_32(txq->sh->txpp.clock_queue.cq->id);
2270 qs->reserved0 = RTE_BE32(0);
2271 qs->reserved1 = RTE_BE32(0);
2275 * Build the Ethernet Segment without inlined data.
2276 * Supports Software Parser, Checksums and VLAN
2277 * insertion Tx offload features.
2280 * Pointer to TX queue structure.
2282 * Pointer to burst routine local context.
2284 * Pointer to WQE to fill with built Ethernet Segment.
2286 * Configured Tx offloads mask. It is fully defined at
2287 * compile time and may be used for optimization.
2289 static __rte_always_inline void
2290 mlx5_tx_eseg_none(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2291 struct mlx5_txq_local *__rte_restrict loc,
2292 struct mlx5_wqe *__rte_restrict wqe,
2295 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2299 * Calculate and set check sum flags first, dword field
2300 * in segment may be shared with Software Parser flags.
2302 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2303 es->flags = rte_cpu_to_le_32(csum);
2305 * Calculate and set Software Parser offsets and flags.
2306 * These flags a set for custom UDP and IP tunnel packets.
2308 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2309 /* Fill metadata field if needed. */
2310 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2311 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2312 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2313 /* Engage VLAN tag insertion feature if requested. */
2314 if (MLX5_TXOFF_CONFIG(VLAN) &&
2315 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2317 * We should get here only if device support
2318 * this feature correctly.
2320 MLX5_ASSERT(txq->vlan_en);
2321 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2322 loc->mbuf->vlan_tci);
2324 es->inline_hdr = RTE_BE32(0);
2329 * Build the Ethernet Segment with minimal inlined data
2330 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2331 * used to fill the gap in single WQEBB WQEs.
2332 * Supports Software Parser, Checksums and VLAN
2333 * insertion Tx offload features.
2336 * Pointer to TX queue structure.
2338 * Pointer to burst routine local context.
2340 * Pointer to WQE to fill with built Ethernet Segment.
2342 * Length of VLAN tag insertion if any.
2344 * Configured Tx offloads mask. It is fully defined at
2345 * compile time and may be used for optimization.
2347 static __rte_always_inline void
2348 mlx5_tx_eseg_dmin(struct mlx5_txq_data *__rte_restrict txq __rte_unused,
2349 struct mlx5_txq_local *__rte_restrict loc,
2350 struct mlx5_wqe *__rte_restrict wqe,
2354 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2356 uint8_t *psrc, *pdst;
2359 * Calculate and set check sum flags first, dword field
2360 * in segment may be shared with Software Parser flags.
2362 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2363 es->flags = rte_cpu_to_le_32(csum);
2365 * Calculate and set Software Parser offsets and flags.
2366 * These flags a set for custom UDP and IP tunnel packets.
2368 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2369 /* Fill metadata field if needed. */
2370 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2371 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2372 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2373 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2375 sizeof(rte_v128u32_t)),
2376 "invalid Ethernet Segment data size");
2377 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2379 sizeof(struct rte_vlan_hdr) +
2380 2 * RTE_ETHER_ADDR_LEN),
2381 "invalid Ethernet Segment data size");
2382 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2383 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2384 es->inline_data = *(unaligned_uint16_t *)psrc;
2385 psrc += sizeof(uint16_t);
2386 pdst = (uint8_t *)(es + 1);
2387 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2388 /* Implement VLAN tag insertion as part inline data. */
2389 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2390 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2391 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2392 /* Insert VLAN ethertype + VLAN tag. */
2393 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2394 ((RTE_ETHER_TYPE_VLAN << 16) |
2395 loc->mbuf->vlan_tci);
2396 pdst += sizeof(struct rte_vlan_hdr);
2397 /* Copy the rest two bytes from packet data. */
2398 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2399 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2401 /* Fill the gap in the title WQEBB with inline data. */
2402 rte_mov16(pdst, psrc);
2407 * Build the Ethernet Segment with entire packet
2408 * data inlining. Checks the boundary of WQEBB and
2409 * ring buffer wrapping, supports Software Parser,
2410 * Checksums and VLAN insertion Tx offload features.
2413 * Pointer to TX queue structure.
2415 * Pointer to burst routine local context.
2417 * Pointer to WQE to fill with built Ethernet Segment.
2419 * Length of VLAN tag insertion if any.
2421 * Length of data to inline (VLAN included, if any).
2423 * TSO flag, set mss field from the packet.
2425 * Configured Tx offloads mask. It is fully defined at
2426 * compile time and may be used for optimization.
2429 * Pointer to the next Data Segment (aligned and wrapped around).
2431 static __rte_always_inline struct mlx5_wqe_dseg *
2432 mlx5_tx_eseg_data(struct mlx5_txq_data *__rte_restrict txq,
2433 struct mlx5_txq_local *__rte_restrict loc,
2434 struct mlx5_wqe *__rte_restrict wqe,
2440 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2442 uint8_t *psrc, *pdst;
2446 * Calculate and set check sum flags first, dword field
2447 * in segment may be shared with Software Parser flags.
2449 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2452 csum |= loc->mbuf->tso_segsz;
2453 es->flags = rte_cpu_to_be_32(csum);
2455 es->flags = rte_cpu_to_le_32(csum);
2458 * Calculate and set Software Parser offsets and flags.
2459 * These flags a set for custom UDP and IP tunnel packets.
2461 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2462 /* Fill metadata field if needed. */
2463 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2464 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2465 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2466 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2468 sizeof(rte_v128u32_t)),
2469 "invalid Ethernet Segment data size");
2470 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2472 sizeof(struct rte_vlan_hdr) +
2473 2 * RTE_ETHER_ADDR_LEN),
2474 "invalid Ethernet Segment data size");
2475 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2476 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2477 es->inline_data = *(unaligned_uint16_t *)psrc;
2478 psrc += sizeof(uint16_t);
2479 pdst = (uint8_t *)(es + 1);
2480 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2481 /* Implement VLAN tag insertion as part inline data. */
2482 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2483 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2484 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2485 /* Insert VLAN ethertype + VLAN tag. */
2486 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2487 ((RTE_ETHER_TYPE_VLAN << 16) |
2488 loc->mbuf->vlan_tci);
2489 pdst += sizeof(struct rte_vlan_hdr);
2490 /* Copy the rest two bytes from packet data. */
2491 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2492 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2493 psrc += sizeof(uint16_t);
2495 /* Fill the gap in the title WQEBB with inline data. */
2496 rte_mov16(pdst, psrc);
2497 psrc += sizeof(rte_v128u32_t);
2499 pdst = (uint8_t *)(es + 2);
2500 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2501 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2502 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2504 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2505 return (struct mlx5_wqe_dseg *)pdst;
2508 * The WQEBB space availability is checked by caller.
2509 * Here we should be aware of WQE ring buffer wraparound only.
2511 part = (uint8_t *)txq->wqes_end - pdst;
2512 part = RTE_MIN(part, inlen);
2514 rte_memcpy(pdst, psrc, part);
2516 if (likely(!inlen)) {
2518 * If return value is not used by the caller
2519 * the code below will be optimized out.
2522 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2523 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2524 pdst = (uint8_t *)txq->wqes;
2525 return (struct mlx5_wqe_dseg *)pdst;
2527 pdst = (uint8_t *)txq->wqes;
2534 * Copy data from chain of mbuf to the specified linear buffer.
2535 * Checksums and VLAN insertion Tx offload features. If data
2536 * from some mbuf copied completely this mbuf is freed. Local
2537 * structure is used to keep the byte stream state.
2540 * Pointer to the destination linear buffer.
2542 * Pointer to burst routine local context.
2544 * Length of data to be copied.
2546 * Length of data to be copied ignoring no inline hint.
2548 * Configured Tx offloads mask. It is fully defined at
2549 * compile time and may be used for optimization.
2552 * Number of actual copied data bytes. This is always greater than or
2553 * equal to must parameter and might be lesser than len in no inline
2554 * hint flag is encountered.
2556 static __rte_always_inline unsigned int
2557 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2558 struct mlx5_txq_local *__rte_restrict loc,
2561 unsigned int olx __rte_unused)
2563 struct rte_mbuf *mbuf;
2564 unsigned int part, dlen, copy = 0;
2568 MLX5_ASSERT(must <= len);
2570 /* Allow zero length packets, must check first. */
2571 dlen = rte_pktmbuf_data_len(loc->mbuf);
2572 if (dlen <= loc->mbuf_off) {
2573 /* Exhausted packet, just free. */
2575 loc->mbuf = mbuf->next;
2576 rte_pktmbuf_free_seg(mbuf);
2578 MLX5_ASSERT(loc->mbuf_nseg > 1);
2579 MLX5_ASSERT(loc->mbuf);
2581 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2586 * We already copied the minimal
2587 * requested amount of data.
2592 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2594 * Copy only the minimal required
2595 * part of the data buffer.
2602 dlen -= loc->mbuf_off;
2603 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2605 part = RTE_MIN(len, dlen);
2606 rte_memcpy(pdst, psrc, part);
2608 loc->mbuf_off += part;
2611 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2613 /* Exhausted packet, just free. */
2615 loc->mbuf = mbuf->next;
2616 rte_pktmbuf_free_seg(mbuf);
2618 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2628 * Build the Ethernet Segment with inlined data from
2629 * multi-segment packet. Checks the boundary of WQEBB
2630 * and ring buffer wrapping, supports Software Parser,
2631 * Checksums and VLAN insertion Tx offload features.
2634 * Pointer to TX queue structure.
2636 * Pointer to burst routine local context.
2638 * Pointer to WQE to fill with built Ethernet Segment.
2640 * Length of VLAN tag insertion if any.
2642 * Length of data to inline (VLAN included, if any).
2644 * TSO flag, set mss field from the packet.
2646 * Configured Tx offloads mask. It is fully defined at
2647 * compile time and may be used for optimization.
2650 * Pointer to the next Data Segment (aligned and
2651 * possible NOT wrapped around - caller should do
2652 * wrapping check on its own).
2654 static __rte_always_inline struct mlx5_wqe_dseg *
2655 mlx5_tx_eseg_mdat(struct mlx5_txq_data *__rte_restrict txq,
2656 struct mlx5_txq_local *__rte_restrict loc,
2657 struct mlx5_wqe *__rte_restrict wqe,
2663 struct mlx5_wqe_eseg *__rte_restrict es = &wqe->eseg;
2666 unsigned int part, tlen = 0;
2669 * Calculate and set check sum flags first, uint32_t field
2670 * in segment may be shared with Software Parser flags.
2672 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2675 csum |= loc->mbuf->tso_segsz;
2676 es->flags = rte_cpu_to_be_32(csum);
2678 es->flags = rte_cpu_to_le_32(csum);
2681 * Calculate and set Software Parser offsets and flags.
2682 * These flags a set for custom UDP and IP tunnel packets.
2684 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2685 /* Fill metadata field if needed. */
2686 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2687 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2688 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2689 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2691 sizeof(rte_v128u32_t)),
2692 "invalid Ethernet Segment data size");
2693 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2695 sizeof(struct rte_vlan_hdr) +
2696 2 * RTE_ETHER_ADDR_LEN),
2697 "invalid Ethernet Segment data size");
2698 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2699 pdst = (uint8_t *)&es->inline_data;
2700 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2701 /* Implement VLAN tag insertion as part inline data. */
2702 mlx5_tx_mseg_memcpy(pdst, loc,
2703 2 * RTE_ETHER_ADDR_LEN,
2704 2 * RTE_ETHER_ADDR_LEN, olx);
2705 pdst += 2 * RTE_ETHER_ADDR_LEN;
2706 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2707 ((RTE_ETHER_TYPE_VLAN << 16) |
2708 loc->mbuf->vlan_tci);
2709 pdst += sizeof(struct rte_vlan_hdr);
2710 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2712 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2714 * The WQEBB space availability is checked by caller.
2715 * Here we should be aware of WQE ring buffer wraparound only.
2717 part = (uint8_t *)txq->wqes_end - pdst;
2718 part = RTE_MIN(part, inlen - tlen);
2724 * Copying may be interrupted inside the routine
2725 * if run into no inline hint flag.
2727 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2728 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2730 if (likely(inlen <= tlen) || copy < part) {
2731 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2733 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2734 return (struct mlx5_wqe_dseg *)pdst;
2736 pdst = (uint8_t *)txq->wqes;
2737 part = inlen - tlen;
2742 * Build the Data Segment of pointer type.
2745 * Pointer to TX queue structure.
2747 * Pointer to burst routine local context.
2749 * Pointer to WQE to fill with built Data Segment.
2751 * Data buffer to point.
2753 * Data buffer length.
2755 * Configured Tx offloads mask. It is fully defined at
2756 * compile time and may be used for optimization.
2758 static __rte_always_inline void
2759 mlx5_tx_dseg_ptr(struct mlx5_txq_data *__rte_restrict txq,
2760 struct mlx5_txq_local *__rte_restrict loc,
2761 struct mlx5_wqe_dseg *__rte_restrict dseg,
2764 unsigned int olx __rte_unused)
2768 dseg->bcount = rte_cpu_to_be_32(len);
2769 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2770 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2774 * Build the Data Segment of pointer type or inline
2775 * if data length is less than buffer in minimal
2776 * Data Segment size.
2779 * Pointer to TX queue structure.
2781 * Pointer to burst routine local context.
2783 * Pointer to WQE to fill with built Data Segment.
2785 * Data buffer to point.
2787 * Data buffer length.
2789 * Configured Tx offloads mask. It is fully defined at
2790 * compile time and may be used for optimization.
2792 static __rte_always_inline void
2793 mlx5_tx_dseg_iptr(struct mlx5_txq_data *__rte_restrict txq,
2794 struct mlx5_txq_local *__rte_restrict loc,
2795 struct mlx5_wqe_dseg *__rte_restrict dseg,
2798 unsigned int olx __rte_unused)
2804 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2805 dseg->bcount = rte_cpu_to_be_32(len);
2806 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2807 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2811 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2812 /* Unrolled implementation of generic rte_memcpy. */
2813 dst = (uintptr_t)&dseg->inline_data[0];
2814 src = (uintptr_t)buf;
2816 #ifdef RTE_ARCH_STRICT_ALIGN
2817 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2818 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2819 dst += sizeof(uint32_t);
2820 src += sizeof(uint32_t);
2821 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2822 dst += sizeof(uint32_t);
2823 src += sizeof(uint32_t);
2825 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2826 dst += sizeof(uint64_t);
2827 src += sizeof(uint64_t);
2831 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2832 dst += sizeof(uint32_t);
2833 src += sizeof(uint32_t);
2836 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2837 dst += sizeof(uint16_t);
2838 src += sizeof(uint16_t);
2841 *(uint8_t *)dst = *(uint8_t *)src;
2845 * Build the Data Segment of inlined data from single
2846 * segment packet, no VLAN insertion.
2849 * Pointer to TX queue structure.
2851 * Pointer to burst routine local context.
2853 * Pointer to WQE to fill with built Data Segment.
2855 * Data buffer to point.
2857 * Data buffer length.
2859 * Configured Tx offloads mask. It is fully defined at
2860 * compile time and may be used for optimization.
2863 * Pointer to the next Data Segment after inlined data.
2864 * Ring buffer wraparound check is needed. We do not
2865 * do it here because it may not be needed for the
2866 * last packet in the eMPW session.
2868 static __rte_always_inline struct mlx5_wqe_dseg *
2869 mlx5_tx_dseg_empw(struct mlx5_txq_data *__rte_restrict txq,
2870 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2871 struct mlx5_wqe_dseg *__rte_restrict dseg,
2874 unsigned int olx __rte_unused)
2879 if (!MLX5_TXOFF_CONFIG(MPW)) {
2880 /* Store the descriptor byte counter for eMPW sessions. */
2881 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2882 pdst = &dseg->inline_data[0];
2884 /* The entire legacy MPW session counter is stored on close. */
2885 pdst = (uint8_t *)dseg;
2888 * The WQEBB space availability is checked by caller.
2889 * Here we should be aware of WQE ring buffer wraparound only.
2891 part = (uint8_t *)txq->wqes_end - pdst;
2892 part = RTE_MIN(part, len);
2894 rte_memcpy(pdst, buf, part);
2898 if (!MLX5_TXOFF_CONFIG(MPW))
2899 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2900 /* Note: no final wraparound check here. */
2901 return (struct mlx5_wqe_dseg *)pdst;
2903 pdst = (uint8_t *)txq->wqes;
2910 * Build the Data Segment of inlined data from single
2911 * segment packet with VLAN insertion.
2914 * Pointer to TX queue structure.
2916 * Pointer to burst routine local context.
2918 * Pointer to the dseg fill with built Data Segment.
2920 * Data buffer to point.
2922 * Data buffer length.
2924 * Configured Tx offloads mask. It is fully defined at
2925 * compile time and may be used for optimization.
2928 * Pointer to the next Data Segment after inlined data.
2929 * Ring buffer wraparound check is needed.
2931 static __rte_always_inline struct mlx5_wqe_dseg *
2932 mlx5_tx_dseg_vlan(struct mlx5_txq_data *__rte_restrict txq,
2933 struct mlx5_txq_local *__rte_restrict loc __rte_unused,
2934 struct mlx5_wqe_dseg *__rte_restrict dseg,
2937 unsigned int olx __rte_unused)
2943 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
2944 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2945 (2 * RTE_ETHER_ADDR_LEN),
2946 "invalid Data Segment data size");
2947 if (!MLX5_TXOFF_CONFIG(MPW)) {
2948 /* Store the descriptor byte counter for eMPW sessions. */
2949 dseg->bcount = rte_cpu_to_be_32
2950 ((len + sizeof(struct rte_vlan_hdr)) |
2951 MLX5_ETH_WQE_DATA_INLINE);
2952 pdst = &dseg->inline_data[0];
2954 /* The entire legacy MPW session counter is stored on close. */
2955 pdst = (uint8_t *)dseg;
2957 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2958 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2959 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2960 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2961 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2962 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2963 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2964 pdst = (uint8_t *)txq->wqes;
2965 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2966 loc->mbuf->vlan_tci);
2967 pdst += sizeof(struct rte_vlan_hdr);
2969 * The WQEBB space availability is checked by caller.
2970 * Here we should be aware of WQE ring buffer wraparound only.
2972 part = (uint8_t *)txq->wqes_end - pdst;
2973 part = RTE_MIN(part, len);
2975 rte_memcpy(pdst, buf, part);
2979 if (!MLX5_TXOFF_CONFIG(MPW))
2980 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2981 /* Note: no final wraparound check here. */
2982 return (struct mlx5_wqe_dseg *)pdst;
2984 pdst = (uint8_t *)txq->wqes;
2991 * Build the Ethernet Segment with optionally inlined data with
2992 * VLAN insertion and following Data Segments (if any) from
2993 * multi-segment packet. Used by ordinary send and TSO.
2996 * Pointer to TX queue structure.
2998 * Pointer to burst routine local context.
3000 * Pointer to WQE to fill with built Ethernet/Data Segments.
3002 * Length of VLAN header to insert, 0 means no VLAN insertion.
3004 * Data length to inline. For TSO this parameter specifies
3005 * exact value, for ordinary send routine can be aligned by
3006 * caller to provide better WQE space saving and data buffer
3007 * start address alignment. This length includes VLAN header
3010 * Zero means ordinary send, inlined data can be extended,
3011 * otherwise this is TSO, inlined data length is fixed.
3013 * Configured Tx offloads mask. It is fully defined at
3014 * compile time and may be used for optimization.
3017 * Actual size of built WQE in segments.
3019 static __rte_always_inline unsigned int
3020 mlx5_tx_mseg_build(struct mlx5_txq_data *__rte_restrict txq,
3021 struct mlx5_txq_local *__rte_restrict loc,
3022 struct mlx5_wqe *__rte_restrict wqe,
3026 unsigned int olx __rte_unused)
3028 struct mlx5_wqe_dseg *__rte_restrict dseg;
3031 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3032 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3035 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3036 if (!loc->mbuf_nseg)
3039 * There are still some mbuf remaining, not inlined.
3040 * The first mbuf may be partially inlined and we
3041 * must process the possible non-zero data offset.
3043 if (loc->mbuf_off) {
3048 * Exhausted packets must be dropped before.
3049 * Non-zero offset means there are some data
3050 * remained in the packet.
3052 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3053 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3054 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3056 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3058 * Build the pointer/minimal data Data Segment.
3059 * Do ring buffer wrapping check in advance.
3061 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3062 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3063 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3064 /* Store the mbuf to be freed on completion. */
3065 MLX5_ASSERT(loc->elts_free);
3066 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3069 if (--loc->mbuf_nseg == 0)
3071 loc->mbuf = loc->mbuf->next;
3075 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3076 struct rte_mbuf *mbuf;
3078 /* Zero length segment found, just skip. */
3080 loc->mbuf = loc->mbuf->next;
3081 rte_pktmbuf_free_seg(mbuf);
3082 if (--loc->mbuf_nseg == 0)
3085 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3086 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3089 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3090 rte_pktmbuf_data_len(loc->mbuf), olx);
3091 MLX5_ASSERT(loc->elts_free);
3092 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3095 if (--loc->mbuf_nseg == 0)
3097 loc->mbuf = loc->mbuf->next;
3102 /* Calculate actual segments used from the dseg pointer. */
3103 if ((uintptr_t)wqe < (uintptr_t)dseg)
3104 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3106 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3107 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3112 * The routine checks timestamp flag in the current packet,
3113 * and push WAIT WQE into the queue if scheduling is required.
3116 * Pointer to TX queue structure.
3118 * Pointer to burst routine local context.
3120 * Configured Tx offloads mask. It is fully defined at
3121 * compile time and may be used for optimization.
3124 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3125 * MLX5_TXCMP_CODE_SINGLE - continue processing with the packet.
3126 * MLX5_TXCMP_CODE_MULTI - the WAIT inserted, continue processing.
3127 * Local context variables partially updated.
3129 static __rte_always_inline enum mlx5_txcmp_code
3130 mlx5_tx_schedule_send(struct mlx5_txq_data *restrict txq,
3131 struct mlx5_txq_local *restrict loc,
3134 if (MLX5_TXOFF_CONFIG(TXPP) &&
3135 loc->mbuf->ol_flags & txq->ts_mask) {
3136 struct mlx5_wqe *wqe;
3141 * Estimate the required space quickly and roughly.
3142 * We would like to ensure the packet can be pushed
3143 * to the queue and we won't get the orphan WAIT WQE.
3145 if (loc->wqe_free <= MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE ||
3146 loc->elts_free < NB_SEGS(loc->mbuf))
3147 return MLX5_TXCMP_CODE_EXIT;
3148 /* Convert the timestamp into completion to wait. */
3149 ts = *RTE_MBUF_DYNFIELD(loc->mbuf, txq->ts_offset, uint64_t *);
3150 wci = mlx5_txpp_convert_tx_ts(txq->sh, ts);
3151 if (unlikely(wci < 0))
3152 return MLX5_TXCMP_CODE_SINGLE;
3153 /* Build the WAIT WQE with specified completion. */
3154 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3155 mlx5_tx_cseg_init(txq, loc, wqe, 2, MLX5_OPCODE_WAIT, olx);
3156 mlx5_tx_wseg_init(txq, loc, wqe, wci, olx);
3159 return MLX5_TXCMP_CODE_MULTI;
3161 return MLX5_TXCMP_CODE_SINGLE;
3165 * Tx one packet function for multi-segment TSO. Supports all
3166 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3167 * sends one packet per WQE.
3169 * This routine is responsible for storing processed mbuf
3170 * into elts ring buffer and update elts_head.
3173 * Pointer to TX queue structure.
3175 * Pointer to burst routine local context.
3177 * Configured Tx offloads mask. It is fully defined at
3178 * compile time and may be used for optimization.
3181 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3182 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3183 * Local context variables partially updated.
3185 static __rte_always_inline enum mlx5_txcmp_code
3186 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *__rte_restrict txq,
3187 struct mlx5_txq_local *__rte_restrict loc,
3190 struct mlx5_wqe *__rte_restrict wqe;
3191 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3193 if (MLX5_TXOFF_CONFIG(TXPP)) {
3194 enum mlx5_txcmp_code wret;
3196 /* Generate WAIT for scheduling if requested. */
3197 wret = mlx5_tx_schedule_send(txq, loc, olx);
3198 if (wret == MLX5_TXCMP_CODE_EXIT)
3199 return MLX5_TXCMP_CODE_EXIT;
3200 if (wret == MLX5_TXCMP_CODE_ERROR)
3201 return MLX5_TXCMP_CODE_ERROR;
3204 * Calculate data length to be inlined to estimate
3205 * the required space in WQE ring buffer.
3207 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3208 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3209 vlan = sizeof(struct rte_vlan_hdr);
3210 inlen = loc->mbuf->l2_len + vlan +
3211 loc->mbuf->l3_len + loc->mbuf->l4_len;
3212 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3213 return MLX5_TXCMP_CODE_ERROR;
3214 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3215 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3216 /* Packet must contain all TSO headers. */
3217 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3218 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3219 inlen > (dlen + vlan)))
3220 return MLX5_TXCMP_CODE_ERROR;
3221 MLX5_ASSERT(inlen >= txq->inlen_mode);
3223 * Check whether there are enough free WQEBBs:
3225 * - Ethernet Segment
3226 * - First Segment of inlined Ethernet data
3227 * - ... data continued ...
3228 * - Data Segments of pointer/min inline type
3230 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3231 MLX5_ESEG_MIN_INLINE_SIZE +
3233 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3234 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3235 return MLX5_TXCMP_CODE_EXIT;
3236 /* Check for maximal WQE size. */
3237 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3238 return MLX5_TXCMP_CODE_ERROR;
3239 #ifdef MLX5_PMD_SOFT_COUNTERS
3240 /* Update sent data bytes/packets counters. */
3241 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3242 loc->mbuf->tso_segsz;
3244 * One will be added for mbuf itself
3245 * at the end of the mlx5_tx_burst from
3246 * loc->pkts_sent field.
3249 txq->stats.opackets += ntcp;
3250 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3252 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3253 loc->wqe_last = wqe;
3254 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3255 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3256 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3257 txq->wqe_ci += (ds + 3) / 4;
3258 loc->wqe_free -= (ds + 3) / 4;
3259 return MLX5_TXCMP_CODE_MULTI;
3263 * Tx one packet function for multi-segment SEND. Supports all
3264 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3265 * sends one packet per WQE, without any data inlining in
3268 * This routine is responsible for storing processed mbuf
3269 * into elts ring buffer and update elts_head.
3272 * Pointer to TX queue structure.
3274 * Pointer to burst routine local context.
3276 * Configured Tx offloads mask. It is fully defined at
3277 * compile time and may be used for optimization.
3280 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3281 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3282 * Local context variables partially updated.
3284 static __rte_always_inline enum mlx5_txcmp_code
3285 mlx5_tx_packet_multi_send(struct mlx5_txq_data *__rte_restrict txq,
3286 struct mlx5_txq_local *__rte_restrict loc,
3289 struct mlx5_wqe_dseg *__rte_restrict dseg;
3290 struct mlx5_wqe *__rte_restrict wqe;
3291 unsigned int ds, nseg;
3293 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3294 if (MLX5_TXOFF_CONFIG(TXPP)) {
3295 enum mlx5_txcmp_code wret;
3297 /* Generate WAIT for scheduling if requested. */
3298 wret = mlx5_tx_schedule_send(txq, loc, olx);
3299 if (wret == MLX5_TXCMP_CODE_EXIT)
3300 return MLX5_TXCMP_CODE_EXIT;
3301 if (wret == MLX5_TXCMP_CODE_ERROR)
3302 return MLX5_TXCMP_CODE_ERROR;
3305 * No inline at all, it means the CPU cycles saving
3306 * is prioritized at configuration, we should not
3307 * copy any packet data to WQE.
3309 nseg = NB_SEGS(loc->mbuf);
3311 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3312 return MLX5_TXCMP_CODE_EXIT;
3313 /* Check for maximal WQE size. */
3314 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3315 return MLX5_TXCMP_CODE_ERROR;
3317 * Some Tx offloads may cause an error if
3318 * packet is not long enough, check against
3319 * assumed minimal length.
3321 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3322 return MLX5_TXCMP_CODE_ERROR;
3323 #ifdef MLX5_PMD_SOFT_COUNTERS
3324 /* Update sent data bytes counter. */
3325 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3326 if (MLX5_TXOFF_CONFIG(VLAN) &&
3327 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3328 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3331 * SEND WQE, one WQEBB:
3332 * - Control Segment, SEND opcode
3333 * - Ethernet Segment, optional VLAN, no inline
3334 * - Data Segments, pointer only type
3336 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3337 loc->wqe_last = wqe;
3338 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3339 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3340 dseg = &wqe->dseg[0];
3342 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3343 struct rte_mbuf *mbuf;
3346 * Zero length segment found, have to
3347 * correct total size of WQE in segments.
3348 * It is supposed to be rare occasion, so
3349 * in normal case (no zero length segments)
3350 * we avoid extra writing to the Control
3354 wqe->cseg.sq_ds -= RTE_BE32(1);
3356 loc->mbuf = mbuf->next;
3357 rte_pktmbuf_free_seg(mbuf);
3363 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3364 rte_pktmbuf_data_len(loc->mbuf), olx);
3365 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3370 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3371 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3372 loc->mbuf = loc->mbuf->next;
3375 txq->wqe_ci += (ds + 3) / 4;
3376 loc->wqe_free -= (ds + 3) / 4;
3377 return MLX5_TXCMP_CODE_MULTI;
3381 * Tx one packet function for multi-segment SEND. Supports all
3382 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3383 * sends one packet per WQE, with data inlining in
3384 * Ethernet Segment and minimal Data Segments.
3386 * This routine is responsible for storing processed mbuf
3387 * into elts ring buffer and update elts_head.
3390 * Pointer to TX queue structure.
3392 * Pointer to burst routine local context.
3394 * Configured Tx offloads mask. It is fully defined at
3395 * compile time and may be used for optimization.
3398 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3399 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3400 * Local context variables partially updated.
3402 static __rte_always_inline enum mlx5_txcmp_code
3403 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *__rte_restrict txq,
3404 struct mlx5_txq_local *__rte_restrict loc,
3407 struct mlx5_wqe *__rte_restrict wqe;
3408 unsigned int ds, inlen, dlen, vlan = 0;
3410 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3411 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3412 if (MLX5_TXOFF_CONFIG(TXPP)) {
3413 enum mlx5_txcmp_code wret;
3415 /* Generate WAIT for scheduling if requested. */
3416 wret = mlx5_tx_schedule_send(txq, loc, olx);
3417 if (wret == MLX5_TXCMP_CODE_EXIT)
3418 return MLX5_TXCMP_CODE_EXIT;
3419 if (wret == MLX5_TXCMP_CODE_ERROR)
3420 return MLX5_TXCMP_CODE_ERROR;
3423 * First calculate data length to be inlined
3424 * to estimate the required space for WQE.
3426 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3427 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3428 vlan = sizeof(struct rte_vlan_hdr);
3429 inlen = dlen + vlan;
3430 /* Check against minimal length. */
3431 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3432 return MLX5_TXCMP_CODE_ERROR;
3433 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3434 if (inlen > txq->inlen_send ||
3435 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3436 struct rte_mbuf *mbuf;
3441 * Packet length exceeds the allowed inline
3442 * data length, check whether the minimal
3443 * inlining is required.
3445 if (txq->inlen_mode) {
3446 MLX5_ASSERT(txq->inlen_mode >=
3447 MLX5_ESEG_MIN_INLINE_SIZE);
3448 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3449 inlen = txq->inlen_mode;
3451 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3452 !vlan || txq->vlan_en) {
3454 * VLAN insertion will be done inside by HW.
3455 * It is not utmost effective - VLAN flag is
3456 * checked twice, but we should proceed the
3457 * inlining length correctly and take into
3458 * account the VLAN header being inserted.
3460 return mlx5_tx_packet_multi_send
3463 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3466 * Now we know the minimal amount of data is requested
3467 * to inline. Check whether we should inline the buffers
3468 * from the chain beginning to eliminate some mbufs.
3471 nxlen = rte_pktmbuf_data_len(mbuf);
3472 if (unlikely(nxlen <= txq->inlen_send)) {
3473 /* We can inline first mbuf at least. */
3474 if (nxlen < inlen) {
3477 /* Scan mbufs till inlen filled. */
3482 nxlen = rte_pktmbuf_data_len(mbuf);
3484 } while (unlikely(nxlen < inlen));
3485 if (unlikely(nxlen > txq->inlen_send)) {
3486 /* We cannot inline entire mbuf. */
3487 smlen = inlen - smlen;
3488 start = rte_pktmbuf_mtod_offset
3489 (mbuf, uintptr_t, smlen);
3496 /* There should be not end of packet. */
3498 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3499 } while (unlikely(nxlen < txq->inlen_send));
3501 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3503 * Check whether we can do inline to align start
3504 * address of data buffer to cacheline.
3507 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3508 if (unlikely(start)) {
3510 if (start <= txq->inlen_send)
3515 * Check whether there are enough free WQEBBs:
3517 * - Ethernet Segment
3518 * - First Segment of inlined Ethernet data
3519 * - ... data continued ...
3520 * - Data Segments of pointer/min inline type
3522 * Estimate the number of Data Segments conservatively,
3523 * supposing no any mbufs is being freed during inlining.
3525 MLX5_ASSERT(inlen <= txq->inlen_send);
3526 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3527 MLX5_ESEG_MIN_INLINE_SIZE +
3529 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3530 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3531 return MLX5_TXCMP_CODE_EXIT;
3532 /* Check for maximal WQE size. */
3533 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3534 return MLX5_TXCMP_CODE_ERROR;
3535 #ifdef MLX5_PMD_SOFT_COUNTERS
3536 /* Update sent data bytes/packets counters. */
3537 txq->stats.obytes += dlen + vlan;
3539 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3540 loc->wqe_last = wqe;
3541 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3542 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3543 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3544 txq->wqe_ci += (ds + 3) / 4;
3545 loc->wqe_free -= (ds + 3) / 4;
3546 return MLX5_TXCMP_CODE_MULTI;
3550 * Tx burst function for multi-segment packets. Supports all
3551 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3552 * sends one packet per WQE. Function stops sending if it
3553 * encounters the single-segment packet.
3555 * This routine is responsible for storing processed mbuf
3556 * into elts ring buffer and update elts_head.
3559 * Pointer to TX queue structure.
3561 * Packets to transmit.
3563 * Number of packets in array.
3565 * Pointer to burst routine local context.
3567 * Configured Tx offloads mask. It is fully defined at
3568 * compile time and may be used for optimization.
3571 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3572 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3573 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3574 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3575 * Local context variables updated.
3577 static __rte_always_inline enum mlx5_txcmp_code
3578 mlx5_tx_burst_mseg(struct mlx5_txq_data *__rte_restrict txq,
3579 struct rte_mbuf **__rte_restrict pkts,
3580 unsigned int pkts_n,
3581 struct mlx5_txq_local *__rte_restrict loc,
3584 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3585 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3586 pkts += loc->pkts_sent + 1;
3587 pkts_n -= loc->pkts_sent;
3589 enum mlx5_txcmp_code ret;
3591 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3593 * Estimate the number of free elts quickly but
3594 * conservatively. Some segment may be fully inlined
3595 * and freed, ignore this here - precise estimation
3598 if (loc->elts_free < NB_SEGS(loc->mbuf))
3599 return MLX5_TXCMP_CODE_EXIT;
3600 if (MLX5_TXOFF_CONFIG(TSO) &&
3601 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3602 /* Proceed with multi-segment TSO. */
3603 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3604 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3605 /* Proceed with multi-segment SEND with inlining. */
3606 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3608 /* Proceed with multi-segment SEND w/o inlining. */
3609 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3611 if (ret == MLX5_TXCMP_CODE_EXIT)
3612 return MLX5_TXCMP_CODE_EXIT;
3613 if (ret == MLX5_TXCMP_CODE_ERROR)
3614 return MLX5_TXCMP_CODE_ERROR;
3615 /* WQE is built, go to the next packet. */
3618 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3619 return MLX5_TXCMP_CODE_EXIT;
3620 loc->mbuf = *pkts++;
3622 rte_prefetch0(*pkts);
3623 if (likely(NB_SEGS(loc->mbuf) > 1))
3625 /* Here ends the series of multi-segment packets. */
3626 if (MLX5_TXOFF_CONFIG(TSO) &&
3627 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3628 return MLX5_TXCMP_CODE_TSO;
3629 return MLX5_TXCMP_CODE_SINGLE;
3635 * Tx burst function for single-segment packets with TSO.
3636 * Supports all types of Tx offloads, except multi-packets.
3637 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3638 * Function stops sending if it encounters the multi-segment
3639 * packet or packet without TSO requested.
3641 * The routine is responsible for storing processed mbuf
3642 * into elts ring buffer and update elts_head if inline
3643 * offloads is requested due to possible early freeing
3644 * of the inlined mbufs (can not store pkts array in elts
3648 * Pointer to TX queue structure.
3650 * Packets to transmit.
3652 * Number of packets in array.
3654 * Pointer to burst routine local context.
3656 * Configured Tx offloads mask. It is fully defined at
3657 * compile time and may be used for optimization.
3660 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3661 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3662 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3663 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3664 * Local context variables updated.
3666 static __rte_always_inline enum mlx5_txcmp_code
3667 mlx5_tx_burst_tso(struct mlx5_txq_data *__rte_restrict txq,
3668 struct rte_mbuf **__rte_restrict pkts,
3669 unsigned int pkts_n,
3670 struct mlx5_txq_local *__rte_restrict loc,
3673 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3674 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3675 pkts += loc->pkts_sent + 1;
3676 pkts_n -= loc->pkts_sent;
3678 struct mlx5_wqe_dseg *__rte_restrict dseg;
3679 struct mlx5_wqe *__rte_restrict wqe;
3680 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3683 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3684 if (MLX5_TXOFF_CONFIG(TXPP)) {
3685 enum mlx5_txcmp_code wret;
3687 /* Generate WAIT for scheduling if requested. */
3688 wret = mlx5_tx_schedule_send(txq, loc, olx);
3689 if (wret == MLX5_TXCMP_CODE_EXIT)
3690 return MLX5_TXCMP_CODE_EXIT;
3691 if (wret == MLX5_TXCMP_CODE_ERROR)
3692 return MLX5_TXCMP_CODE_ERROR;
3694 dlen = rte_pktmbuf_data_len(loc->mbuf);
3695 if (MLX5_TXOFF_CONFIG(VLAN) &&
3696 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3697 vlan = sizeof(struct rte_vlan_hdr);
3700 * First calculate the WQE size to check
3701 * whether we have enough space in ring buffer.
3703 hlen = loc->mbuf->l2_len + vlan +
3704 loc->mbuf->l3_len + loc->mbuf->l4_len;
3705 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3706 return MLX5_TXCMP_CODE_ERROR;
3707 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3708 hlen += loc->mbuf->outer_l2_len +
3709 loc->mbuf->outer_l3_len;
3710 /* Segment must contain all TSO headers. */
3711 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3712 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3713 hlen > (dlen + vlan)))
3714 return MLX5_TXCMP_CODE_ERROR;
3716 * Check whether there are enough free WQEBBs:
3718 * - Ethernet Segment
3719 * - First Segment of inlined Ethernet data
3720 * - ... data continued ...
3721 * - Finishing Data Segment of pointer type
3723 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3724 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3725 if (loc->wqe_free < ((ds + 3) / 4))
3726 return MLX5_TXCMP_CODE_EXIT;
3727 #ifdef MLX5_PMD_SOFT_COUNTERS
3728 /* Update sent data bytes/packets counters. */
3729 ntcp = (dlen + vlan - hlen +
3730 loc->mbuf->tso_segsz - 1) /
3731 loc->mbuf->tso_segsz;
3733 * One will be added for mbuf itself at the end
3734 * of the mlx5_tx_burst from loc->pkts_sent field.
3737 txq->stats.opackets += ntcp;
3738 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3741 * Build the TSO WQE:
3743 * - Ethernet Segment with hlen bytes inlined
3744 * - Data Segment of pointer type
3746 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3747 loc->wqe_last = wqe;
3748 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3749 MLX5_OPCODE_TSO, olx);
3750 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3751 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3752 dlen -= hlen - vlan;
3753 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3755 * WQE is built, update the loop parameters
3756 * and go to the next packet.
3758 txq->wqe_ci += (ds + 3) / 4;
3759 loc->wqe_free -= (ds + 3) / 4;
3760 if (MLX5_TXOFF_CONFIG(INLINE))
3761 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3765 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3766 return MLX5_TXCMP_CODE_EXIT;
3767 loc->mbuf = *pkts++;
3769 rte_prefetch0(*pkts);
3770 if (MLX5_TXOFF_CONFIG(MULTI) &&
3771 unlikely(NB_SEGS(loc->mbuf) > 1))
3772 return MLX5_TXCMP_CODE_MULTI;
3773 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3774 return MLX5_TXCMP_CODE_SINGLE;
3775 /* Continue with the next TSO packet. */
3781 * Analyze the packet and select the best method to send.
3784 * Pointer to TX queue structure.
3786 * Pointer to burst routine local context.
3788 * Configured Tx offloads mask. It is fully defined at
3789 * compile time and may be used for optimization.
3791 * The predefined flag whether do complete check for
3792 * multi-segment packets and TSO.
3795 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3796 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3797 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3798 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3800 static __rte_always_inline enum mlx5_txcmp_code
3801 mlx5_tx_able_to_empw(struct mlx5_txq_data *__rte_restrict txq,
3802 struct mlx5_txq_local *__rte_restrict loc,
3806 /* Check for multi-segment packet. */
3808 MLX5_TXOFF_CONFIG(MULTI) &&
3809 unlikely(NB_SEGS(loc->mbuf) > 1))
3810 return MLX5_TXCMP_CODE_MULTI;
3811 /* Check for TSO packet. */
3813 MLX5_TXOFF_CONFIG(TSO) &&
3814 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3815 return MLX5_TXCMP_CODE_TSO;
3816 /* Check if eMPW is enabled at all. */
3817 if (!MLX5_TXOFF_CONFIG(EMPW))
3818 return MLX5_TXCMP_CODE_SINGLE;
3819 /* Check if eMPW can be engaged. */
3820 if (MLX5_TXOFF_CONFIG(VLAN) &&
3821 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3822 (!MLX5_TXOFF_CONFIG(INLINE) ||
3823 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3824 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3826 * eMPW does not support VLAN insertion offload,
3827 * we have to inline the entire packet but
3828 * packet is too long for inlining.
3830 return MLX5_TXCMP_CODE_SINGLE;
3832 return MLX5_TXCMP_CODE_EMPW;
3836 * Check the next packet attributes to match with the eMPW batch ones.
3837 * In addition, for legacy MPW the packet length is checked either.
3840 * Pointer to TX queue structure.
3842 * Pointer to Ethernet Segment of eMPW batch.
3844 * Pointer to burst routine local context.
3846 * Length of previous packet in MPW descriptor.
3848 * Configured Tx offloads mask. It is fully defined at
3849 * compile time and may be used for optimization.
3852 * true - packet match with eMPW batch attributes.
3853 * false - no match, eMPW should be restarted.
3855 static __rte_always_inline bool
3856 mlx5_tx_match_empw(struct mlx5_txq_data *__rte_restrict txq,
3857 struct mlx5_wqe_eseg *__rte_restrict es,
3858 struct mlx5_txq_local *__rte_restrict loc,
3862 uint8_t swp_flags = 0;
3864 /* Compare the checksum flags, if any. */
3865 if (MLX5_TXOFF_CONFIG(CSUM) &&
3866 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3868 /* Compare the Software Parser offsets and flags. */
3869 if (MLX5_TXOFF_CONFIG(SWP) &&
3870 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3871 es->swp_flags != swp_flags))
3873 /* Fill metadata field if needed. */
3874 if (MLX5_TXOFF_CONFIG(METADATA) &&
3875 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3876 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3878 /* Legacy MPW can send packets with the same lengt only. */
3879 if (MLX5_TXOFF_CONFIG(MPW) &&
3880 dlen != rte_pktmbuf_data_len(loc->mbuf))
3882 /* There must be no VLAN packets in eMPW loop. */
3883 if (MLX5_TXOFF_CONFIG(VLAN))
3884 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3885 /* Check if the scheduling is requested. */
3886 if (MLX5_TXOFF_CONFIG(TXPP) &&
3887 loc->mbuf->ol_flags & txq->ts_mask)
3893 * Update send loop variables and WQE for eMPW loop
3894 * without data inlining. Number of Data Segments is
3895 * equal to the number of sent packets.
3898 * Pointer to TX queue structure.
3900 * Pointer to burst routine local context.
3902 * Number of packets/Data Segments/Packets.
3904 * Accumulated statistics, bytes sent
3906 * Configured Tx offloads mask. It is fully defined at
3907 * compile time and may be used for optimization.
3910 * true - packet match with eMPW batch attributes.
3911 * false - no match, eMPW should be restarted.
3913 static __rte_always_inline void
3914 mlx5_tx_sdone_empw(struct mlx5_txq_data *__rte_restrict txq,
3915 struct mlx5_txq_local *__rte_restrict loc,
3918 unsigned int olx __rte_unused)
3920 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3921 #ifdef MLX5_PMD_SOFT_COUNTERS
3922 /* Update sent data bytes counter. */
3923 txq->stats.obytes += slen;
3927 loc->elts_free -= ds;
3928 loc->pkts_sent += ds;
3930 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3931 txq->wqe_ci += (ds + 3) / 4;
3932 loc->wqe_free -= (ds + 3) / 4;
3936 * Update send loop variables and WQE for eMPW loop
3937 * with data inlining. Gets the size of pushed descriptors
3938 * and data to the WQE.
3941 * Pointer to TX queue structure.
3943 * Pointer to burst routine local context.
3945 * Total size of descriptor/data in bytes.
3947 * Accumulated statistics, data bytes sent.
3949 * The base WQE for the eMPW/MPW descriptor.
3951 * Configured Tx offloads mask. It is fully defined at
3952 * compile time and may be used for optimization.
3955 * true - packet match with eMPW batch attributes.
3956 * false - no match, eMPW should be restarted.
3958 static __rte_always_inline void
3959 mlx5_tx_idone_empw(struct mlx5_txq_data *__rte_restrict txq,
3960 struct mlx5_txq_local *__rte_restrict loc,
3963 struct mlx5_wqe *__rte_restrict wqem,
3964 unsigned int olx __rte_unused)
3966 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
3968 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3969 #ifdef MLX5_PMD_SOFT_COUNTERS
3970 /* Update sent data bytes counter. */
3971 txq->stats.obytes += slen;
3975 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
3977 * If the legacy MPW session contains the inline packets
3978 * we should set the only inline data segment length
3979 * and align the total length to the segment size.
3981 MLX5_ASSERT(len > sizeof(dseg->bcount));
3982 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
3983 MLX5_ETH_WQE_DATA_INLINE);
3984 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
3987 * The session is not legacy MPW or contains the
3988 * data buffer pointer segments.
3990 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
3991 len = len / MLX5_WSEG_SIZE + 2;
3993 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3994 txq->wqe_ci += (len + 3) / 4;
3995 loc->wqe_free -= (len + 3) / 4;
3996 loc->wqe_last = wqem;
4000 * The set of Tx burst functions for single-segment packets
4001 * without TSO and with Multi-Packet Writing feature support.
4002 * Supports all types of Tx offloads, except multi-packets
4005 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4006 * as many packet per WQE as it can. If eMPW is not configured
4007 * or packet can not be sent with eMPW (VLAN insertion) the
4008 * ordinary SEND opcode is used and only one packet placed
4011 * Functions stop sending if it encounters the multi-segment
4012 * packet or packet with TSO requested.
4014 * The routines are responsible for storing processed mbuf
4015 * into elts ring buffer and update elts_head if inlining
4016 * offload is requested. Otherwise the copying mbufs to elts
4017 * can be postponed and completed at the end of burst routine.
4020 * Pointer to TX queue structure.
4022 * Packets to transmit.
4024 * Number of packets in array.
4026 * Pointer to burst routine local context.
4028 * Configured Tx offloads mask. It is fully defined at
4029 * compile time and may be used for optimization.
4032 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4033 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4034 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4035 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4036 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4037 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4039 * Local context variables updated.
4042 * The routine sends packets with MLX5_OPCODE_EMPW
4043 * without inlining, this is dedicated optimized branch.
4044 * No VLAN insertion is supported.
4046 static __rte_always_inline enum mlx5_txcmp_code
4047 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *__rte_restrict txq,
4048 struct rte_mbuf **__rte_restrict pkts,
4049 unsigned int pkts_n,
4050 struct mlx5_txq_local *__rte_restrict loc,
4054 * Subroutine is the part of mlx5_tx_burst_single()
4055 * and sends single-segment packet with eMPW opcode
4056 * without data inlining.
4058 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4059 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4060 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4061 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4062 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4063 pkts += loc->pkts_sent + 1;
4064 pkts_n -= loc->pkts_sent;
4066 struct mlx5_wqe_dseg *__rte_restrict dseg;
4067 struct mlx5_wqe_eseg *__rte_restrict eseg;
4068 enum mlx5_txcmp_code ret;
4069 unsigned int part, loop;
4070 unsigned int slen = 0;
4073 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4074 if (MLX5_TXOFF_CONFIG(TXPP)) {
4075 enum mlx5_txcmp_code wret;
4077 /* Generate WAIT for scheduling if requested. */
4078 wret = mlx5_tx_schedule_send(txq, loc, olx);
4079 if (wret == MLX5_TXCMP_CODE_EXIT)
4080 return MLX5_TXCMP_CODE_EXIT;
4081 if (wret == MLX5_TXCMP_CODE_ERROR)
4082 return MLX5_TXCMP_CODE_ERROR;
4084 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4085 MLX5_MPW_MAX_PACKETS :
4086 MLX5_EMPW_MAX_PACKETS);
4087 if (unlikely(loc->elts_free < part)) {
4088 /* We have no enough elts to save all mbufs. */
4089 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4090 return MLX5_TXCMP_CODE_EXIT;
4091 /* But we still able to send at least minimal eMPW. */
4092 part = loc->elts_free;
4094 /* Check whether we have enough WQEs */
4095 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4096 if (unlikely(loc->wqe_free <
4097 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4098 return MLX5_TXCMP_CODE_EXIT;
4099 part = (loc->wqe_free * 4) - 2;
4101 if (likely(part > 1))
4102 rte_prefetch0(*pkts);
4103 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4105 * Build eMPW title WQEBB:
4106 * - Control Segment, eMPW opcode
4107 * - Ethernet Segment, no inline
4109 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4110 MLX5_OPCODE_ENHANCED_MPSW, olx);
4111 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4112 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4113 eseg = &loc->wqe_last->eseg;
4114 dseg = &loc->wqe_last->dseg[0];
4116 /* Store the packet length for legacy MPW. */
4117 if (MLX5_TXOFF_CONFIG(MPW))
4118 eseg->mss = rte_cpu_to_be_16
4119 (rte_pktmbuf_data_len(loc->mbuf));
4121 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4122 #ifdef MLX5_PMD_SOFT_COUNTERS
4123 /* Update sent data bytes counter. */
4128 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4130 if (unlikely(--loop == 0))
4132 loc->mbuf = *pkts++;
4133 if (likely(loop > 1))
4134 rte_prefetch0(*pkts);
4135 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4137 * Unroll the completion code to avoid
4138 * returning variable value - it results in
4139 * unoptimized sequent checking in caller.
4141 if (ret == MLX5_TXCMP_CODE_MULTI) {
4143 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4144 if (unlikely(!loc->elts_free ||
4146 return MLX5_TXCMP_CODE_EXIT;
4147 return MLX5_TXCMP_CODE_MULTI;
4149 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4150 if (ret == MLX5_TXCMP_CODE_TSO) {
4152 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4153 if (unlikely(!loc->elts_free ||
4155 return MLX5_TXCMP_CODE_EXIT;
4156 return MLX5_TXCMP_CODE_TSO;
4158 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4160 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4161 if (unlikely(!loc->elts_free ||
4163 return MLX5_TXCMP_CODE_EXIT;
4164 return MLX5_TXCMP_CODE_SINGLE;
4166 if (ret != MLX5_TXCMP_CODE_EMPW) {
4169 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4170 return MLX5_TXCMP_CODE_ERROR;
4173 * Check whether packet parameters coincide
4174 * within assumed eMPW batch:
4175 * - check sum settings
4177 * - software parser settings
4178 * - packets length (legacy MPW only)
4179 * - scheduling is not required
4181 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4184 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4185 if (unlikely(!loc->elts_free ||
4187 return MLX5_TXCMP_CODE_EXIT;
4191 /* Packet attributes match, continue the same eMPW. */
4193 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4194 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4196 /* eMPW is built successfully, update loop parameters. */
4198 MLX5_ASSERT(pkts_n >= part);
4199 #ifdef MLX5_PMD_SOFT_COUNTERS
4200 /* Update sent data bytes counter. */
4201 txq->stats.obytes += slen;
4203 loc->elts_free -= part;
4204 loc->pkts_sent += part;
4205 txq->wqe_ci += (2 + part + 3) / 4;
4206 loc->wqe_free -= (2 + part + 3) / 4;
4208 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4209 return MLX5_TXCMP_CODE_EXIT;
4210 loc->mbuf = *pkts++;
4211 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4212 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4214 /* Continue sending eMPW batches. */
4220 * The routine sends packets with MLX5_OPCODE_EMPW
4221 * with inlining, optionally supports VLAN insertion.
4223 static __rte_always_inline enum mlx5_txcmp_code
4224 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *__rte_restrict txq,
4225 struct rte_mbuf **__rte_restrict pkts,
4226 unsigned int pkts_n,
4227 struct mlx5_txq_local *__rte_restrict loc,
4231 * Subroutine is the part of mlx5_tx_burst_single()
4232 * and sends single-segment packet with eMPW opcode
4233 * with data inlining.
4235 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4236 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4237 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4238 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4239 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4240 pkts += loc->pkts_sent + 1;
4241 pkts_n -= loc->pkts_sent;
4243 struct mlx5_wqe_dseg *__rte_restrict dseg;
4244 struct mlx5_wqe *__rte_restrict wqem;
4245 enum mlx5_txcmp_code ret;
4246 unsigned int room, part, nlim;
4247 unsigned int slen = 0;
4249 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4250 if (MLX5_TXOFF_CONFIG(TXPP)) {
4251 enum mlx5_txcmp_code wret;
4253 /* Generate WAIT for scheduling if requested. */
4254 wret = mlx5_tx_schedule_send(txq, loc, olx);
4255 if (wret == MLX5_TXCMP_CODE_EXIT)
4256 return MLX5_TXCMP_CODE_EXIT;
4257 if (wret == MLX5_TXCMP_CODE_ERROR)
4258 return MLX5_TXCMP_CODE_ERROR;
4261 * Limits the amount of packets in one WQE
4262 * to improve CQE latency generation.
4264 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4265 MLX5_MPW_INLINE_MAX_PACKETS :
4266 MLX5_EMPW_MAX_PACKETS);
4267 /* Check whether we have minimal amount WQEs */
4268 if (unlikely(loc->wqe_free <
4269 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4270 return MLX5_TXCMP_CODE_EXIT;
4271 if (likely(pkts_n > 1))
4272 rte_prefetch0(*pkts);
4273 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4275 * Build eMPW title WQEBB:
4276 * - Control Segment, eMPW opcode, zero DS
4277 * - Ethernet Segment, no inline
4279 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4280 MLX5_OPCODE_ENHANCED_MPSW, olx);
4281 mlx5_tx_eseg_none(txq, loc, wqem,
4282 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4283 dseg = &wqem->dseg[0];
4284 /* Store the packet length for legacy MPW. */
4285 if (MLX5_TXOFF_CONFIG(MPW))
4286 wqem->eseg.mss = rte_cpu_to_be_16
4287 (rte_pktmbuf_data_len(loc->mbuf));
4288 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4289 loc->wqe_free) * MLX5_WQE_SIZE -
4290 MLX5_WQE_CSEG_SIZE -
4292 /* Limit the room for legacy MPW sessions for performance. */
4293 if (MLX5_TXOFF_CONFIG(MPW))
4294 room = RTE_MIN(room,
4295 RTE_MAX(txq->inlen_empw +
4296 sizeof(dseg->bcount) +
4297 (MLX5_TXOFF_CONFIG(VLAN) ?
4298 sizeof(struct rte_vlan_hdr) : 0),
4299 MLX5_MPW_INLINE_MAX_PACKETS *
4300 MLX5_WQE_DSEG_SIZE));
4301 /* Build WQE till we have space, packets and resources. */
4304 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4305 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4308 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4309 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4310 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4312 * Some Tx offloads may cause an error if
4313 * packet is not long enough, check against
4314 * assumed minimal length.
4316 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4318 if (unlikely(!part))
4319 return MLX5_TXCMP_CODE_ERROR;
4321 * We have some successfully built
4322 * packet Data Segments to send.
4324 mlx5_tx_idone_empw(txq, loc, part,
4326 return MLX5_TXCMP_CODE_ERROR;
4328 /* Inline or not inline - that's the Question. */
4329 if (dlen > txq->inlen_empw ||
4330 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4332 if (MLX5_TXOFF_CONFIG(MPW)) {
4333 if (dlen > txq->inlen_send)
4337 /* Open new inline MPW session. */
4338 tlen += sizeof(dseg->bcount);
4339 dseg->bcount = RTE_BE32(0);
4341 (dseg, sizeof(dseg->bcount));
4344 * No pointer and inline descriptor
4345 * intermix for legacy MPW sessions.
4347 if (wqem->dseg[0].bcount)
4351 tlen = sizeof(dseg->bcount) + dlen;
4353 /* Inline entire packet, optional VLAN insertion. */
4354 if (MLX5_TXOFF_CONFIG(VLAN) &&
4355 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4357 * The packet length must be checked in
4358 * mlx5_tx_able_to_empw() and packet
4359 * fits into inline length guaranteed.
4362 sizeof(struct rte_vlan_hdr)) <=
4364 tlen += sizeof(struct rte_vlan_hdr);
4367 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4369 #ifdef MLX5_PMD_SOFT_COUNTERS
4370 /* Update sent data bytes counter. */
4371 slen += sizeof(struct rte_vlan_hdr);
4376 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4379 if (!MLX5_TXOFF_CONFIG(MPW))
4380 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4381 MLX5_ASSERT(room >= tlen);
4384 * Packet data are completely inlined,
4385 * free the packet immediately.
4387 rte_pktmbuf_free_seg(loc->mbuf);
4391 * No pointer and inline descriptor
4392 * intermix for legacy MPW sessions.
4394 if (MLX5_TXOFF_CONFIG(MPW) &&
4396 wqem->dseg[0].bcount == RTE_BE32(0))
4399 * Not inlinable VLAN packets are
4400 * proceeded outside of this routine.
4402 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4403 if (MLX5_TXOFF_CONFIG(VLAN))
4404 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4406 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4407 /* We have to store mbuf in elts.*/
4408 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4409 room -= MLX5_WQE_DSEG_SIZE;
4410 /* Ring buffer wraparound is checked at the loop end.*/
4413 #ifdef MLX5_PMD_SOFT_COUNTERS
4414 /* Update sent data bytes counter. */
4420 if (unlikely(!pkts_n || !loc->elts_free)) {
4422 * We have no resources/packets to
4423 * continue build descriptors.
4426 mlx5_tx_idone_empw(txq, loc, part,
4428 return MLX5_TXCMP_CODE_EXIT;
4430 loc->mbuf = *pkts++;
4431 if (likely(pkts_n > 1))
4432 rte_prefetch0(*pkts);
4433 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4435 * Unroll the completion code to avoid
4436 * returning variable value - it results in
4437 * unoptimized sequent checking in caller.
4439 if (ret == MLX5_TXCMP_CODE_MULTI) {
4441 mlx5_tx_idone_empw(txq, loc, part,
4443 if (unlikely(!loc->elts_free ||
4445 return MLX5_TXCMP_CODE_EXIT;
4446 return MLX5_TXCMP_CODE_MULTI;
4448 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4449 if (ret == MLX5_TXCMP_CODE_TSO) {
4451 mlx5_tx_idone_empw(txq, loc, part,
4453 if (unlikely(!loc->elts_free ||
4455 return MLX5_TXCMP_CODE_EXIT;
4456 return MLX5_TXCMP_CODE_TSO;
4458 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4460 mlx5_tx_idone_empw(txq, loc, part,
4462 if (unlikely(!loc->elts_free ||
4464 return MLX5_TXCMP_CODE_EXIT;
4465 return MLX5_TXCMP_CODE_SINGLE;
4467 if (ret != MLX5_TXCMP_CODE_EMPW) {
4470 mlx5_tx_idone_empw(txq, loc, part,
4472 return MLX5_TXCMP_CODE_ERROR;
4474 /* Check if we have minimal room left. */
4476 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4479 * Check whether packet parameters coincide
4480 * within assumed eMPW batch:
4481 * - check sum settings
4483 * - software parser settings
4484 * - packets length (legacy MPW only)
4485 * - scheduling is not required
4487 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4490 /* Packet attributes match, continue the same eMPW. */
4491 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4492 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4495 * We get here to close an existing eMPW
4496 * session and start the new one.
4498 MLX5_ASSERT(pkts_n);
4500 if (unlikely(!part))
4501 return MLX5_TXCMP_CODE_EXIT;
4502 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4503 if (unlikely(!loc->elts_free ||
4505 return MLX5_TXCMP_CODE_EXIT;
4506 /* Continue the loop with new eMPW session. */
4512 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4513 * Data inlining and VLAN insertion are supported.
4515 static __rte_always_inline enum mlx5_txcmp_code
4516 mlx5_tx_burst_single_send(struct mlx5_txq_data *__rte_restrict txq,
4517 struct rte_mbuf **__rte_restrict pkts,
4518 unsigned int pkts_n,
4519 struct mlx5_txq_local *__rte_restrict loc,
4523 * Subroutine is the part of mlx5_tx_burst_single()
4524 * and sends single-segment packet with SEND opcode.
4526 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4527 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4528 pkts += loc->pkts_sent + 1;
4529 pkts_n -= loc->pkts_sent;
4531 struct mlx5_wqe *__rte_restrict wqe;
4532 enum mlx5_txcmp_code ret;
4534 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4535 if (MLX5_TXOFF_CONFIG(TXPP)) {
4536 enum mlx5_txcmp_code wret;
4538 /* Generate WAIT for scheduling if requested. */
4539 wret = mlx5_tx_schedule_send(txq, loc, olx);
4540 if (wret == MLX5_TXCMP_CODE_EXIT)
4541 return MLX5_TXCMP_CODE_EXIT;
4542 if (wret == MLX5_TXCMP_CODE_ERROR)
4543 return MLX5_TXCMP_CODE_ERROR;
4545 if (MLX5_TXOFF_CONFIG(INLINE)) {
4546 unsigned int inlen, vlan = 0;
4548 inlen = rte_pktmbuf_data_len(loc->mbuf);
4549 if (MLX5_TXOFF_CONFIG(VLAN) &&
4550 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4551 vlan = sizeof(struct rte_vlan_hdr);
4553 static_assert((sizeof(struct rte_vlan_hdr) +
4554 sizeof(struct rte_ether_hdr)) ==
4555 MLX5_ESEG_MIN_INLINE_SIZE,
4556 "invalid min inline data size");
4559 * If inlining is enabled at configuration time
4560 * the limit must be not less than minimal size.
4561 * Otherwise we would do extra check for data
4562 * size to avoid crashes due to length overflow.
4564 MLX5_ASSERT(txq->inlen_send >=
4565 MLX5_ESEG_MIN_INLINE_SIZE);
4566 if (inlen <= txq->inlen_send) {
4567 unsigned int seg_n, wqe_n;
4569 rte_prefetch0(rte_pktmbuf_mtod
4570 (loc->mbuf, uint8_t *));
4571 /* Check against minimal length. */
4572 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4573 return MLX5_TXCMP_CODE_ERROR;
4574 if (loc->mbuf->ol_flags &
4575 PKT_TX_DYNF_NOINLINE) {
4577 * The hint flag not to inline packet
4578 * data is set. Check whether we can
4581 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4583 (MLX5_TXOFF_CONFIG(MPW) &&
4585 if (inlen <= txq->inlen_send)
4588 * The hardware requires the
4589 * minimal inline data header.
4591 goto single_min_inline;
4593 if (MLX5_TXOFF_CONFIG(VLAN) &&
4594 vlan && !txq->vlan_en) {
4596 * We must insert VLAN tag
4597 * by software means.
4599 goto single_part_inline;
4601 goto single_no_inline;
4605 * Completely inlined packet data WQE:
4606 * - Control Segment, SEND opcode
4607 * - Ethernet Segment, no VLAN insertion
4608 * - Data inlined, VLAN optionally inserted
4609 * - Alignment to MLX5_WSEG_SIZE
4610 * Have to estimate amount of WQEBBs
4612 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4613 MLX5_ESEG_MIN_INLINE_SIZE +
4614 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4615 /* Check if there are enough WQEBBs. */
4616 wqe_n = (seg_n + 3) / 4;
4617 if (wqe_n > loc->wqe_free)
4618 return MLX5_TXCMP_CODE_EXIT;
4619 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4620 loc->wqe_last = wqe;
4621 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4622 MLX5_OPCODE_SEND, olx);
4623 mlx5_tx_eseg_data(txq, loc, wqe,
4624 vlan, inlen, 0, olx);
4625 txq->wqe_ci += wqe_n;
4626 loc->wqe_free -= wqe_n;
4628 * Packet data are completely inlined,
4629 * free the packet immediately.
4631 rte_pktmbuf_free_seg(loc->mbuf);
4632 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4633 MLX5_TXOFF_CONFIG(MPW)) &&
4636 * If minimal inlining is requested the eMPW
4637 * feature should be disabled due to data is
4638 * inlined into Ethernet Segment, which can
4639 * not contain inlined data for eMPW due to
4640 * segment shared for all packets.
4642 struct mlx5_wqe_dseg *__rte_restrict dseg;
4647 * The inline-mode settings require
4648 * to inline the specified amount of
4649 * data bytes to the Ethernet Segment.
4650 * We should check the free space in
4651 * WQE ring buffer to inline partially.
4654 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4655 MLX5_ASSERT(inlen > txq->inlen_mode);
4656 MLX5_ASSERT(txq->inlen_mode >=
4657 MLX5_ESEG_MIN_INLINE_SIZE);
4659 * Check whether there are enough free WQEBBs:
4661 * - Ethernet Segment
4662 * - First Segment of inlined Ethernet data
4663 * - ... data continued ...
4664 * - Finishing Data Segment of pointer type
4666 ds = (MLX5_WQE_CSEG_SIZE +
4667 MLX5_WQE_ESEG_SIZE +
4668 MLX5_WQE_DSEG_SIZE +
4670 MLX5_ESEG_MIN_INLINE_SIZE +
4671 MLX5_WQE_DSEG_SIZE +
4672 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4673 if (loc->wqe_free < ((ds + 3) / 4))
4674 return MLX5_TXCMP_CODE_EXIT;
4676 * Build the ordinary SEND WQE:
4678 * - Ethernet Segment, inline inlen_mode bytes
4679 * - Data Segment of pointer type
4681 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4682 loc->wqe_last = wqe;
4683 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4684 MLX5_OPCODE_SEND, olx);
4685 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4688 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4689 txq->inlen_mode - vlan;
4690 inlen -= txq->inlen_mode;
4691 mlx5_tx_dseg_ptr(txq, loc, dseg,
4694 * WQE is built, update the loop parameters
4695 * and got to the next packet.
4697 txq->wqe_ci += (ds + 3) / 4;
4698 loc->wqe_free -= (ds + 3) / 4;
4699 /* We have to store mbuf in elts.*/
4700 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4701 txq->elts[txq->elts_head++ & txq->elts_m] =
4709 * Partially inlined packet data WQE, we have
4710 * some space in title WQEBB, we can fill it
4711 * with some packet data. It takes one WQEBB,
4712 * it is available, no extra space check:
4713 * - Control Segment, SEND opcode
4714 * - Ethernet Segment, no VLAN insertion
4715 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4716 * - Data Segment, pointer type
4718 * We also get here if VLAN insertion is not
4719 * supported by HW, the inline is enabled.
4722 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4723 loc->wqe_last = wqe;
4724 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4725 MLX5_OPCODE_SEND, olx);
4726 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4727 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4728 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4730 * The length check is performed above, by
4731 * comparing with txq->inlen_send. We should
4732 * not get overflow here.
4734 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4735 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4736 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4740 /* We have to store mbuf in elts.*/
4741 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4742 txq->elts[txq->elts_head++ & txq->elts_m] =
4746 #ifdef MLX5_PMD_SOFT_COUNTERS
4747 /* Update sent data bytes counter. */
4748 txq->stats.obytes += vlan +
4749 rte_pktmbuf_data_len(loc->mbuf);
4753 * No inline at all, it means the CPU cycles saving
4754 * is prioritized at configuration, we should not
4755 * copy any packet data to WQE.
4757 * SEND WQE, one WQEBB:
4758 * - Control Segment, SEND opcode
4759 * - Ethernet Segment, optional VLAN, no inline
4760 * - Data Segment, pointer type
4763 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4764 loc->wqe_last = wqe;
4765 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4766 MLX5_OPCODE_SEND, olx);
4767 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4769 (txq, loc, &wqe->dseg[0],
4770 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4771 rte_pktmbuf_data_len(loc->mbuf), olx);
4775 * We should not store mbuf pointer in elts
4776 * if no inlining is configured, this is done
4777 * by calling routine in a batch copy.
4779 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4781 #ifdef MLX5_PMD_SOFT_COUNTERS
4782 /* Update sent data bytes counter. */
4783 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4784 if (MLX5_TXOFF_CONFIG(VLAN) &&
4785 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4786 txq->stats.obytes +=
4787 sizeof(struct rte_vlan_hdr);
4792 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4793 return MLX5_TXCMP_CODE_EXIT;
4794 loc->mbuf = *pkts++;
4796 rte_prefetch0(*pkts);
4797 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4798 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4804 static __rte_always_inline enum mlx5_txcmp_code
4805 mlx5_tx_burst_single(struct mlx5_txq_data *__rte_restrict txq,
4806 struct rte_mbuf **__rte_restrict pkts,
4807 unsigned int pkts_n,
4808 struct mlx5_txq_local *__rte_restrict loc,
4811 enum mlx5_txcmp_code ret;
4813 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4814 if (ret == MLX5_TXCMP_CODE_SINGLE)
4816 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4818 /* Optimize for inline/no inline eMPW send. */
4819 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4820 mlx5_tx_burst_empw_inline
4821 (txq, pkts, pkts_n, loc, olx) :
4822 mlx5_tx_burst_empw_simple
4823 (txq, pkts, pkts_n, loc, olx);
4824 if (ret != MLX5_TXCMP_CODE_SINGLE)
4826 /* The resources to send one packet should remain. */
4827 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4829 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4830 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4831 if (ret != MLX5_TXCMP_CODE_EMPW)
4833 /* The resources to send one packet should remain. */
4834 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4839 * DPDK Tx callback template. This is configured template
4840 * used to generate routines optimized for specified offload setup.
4841 * One of this generated functions is chosen at SQ configuration
4845 * Generic pointer to TX queue structure.
4847 * Packets to transmit.
4849 * Number of packets in array.
4851 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4852 * values. Should be static to take compile time static configuration
4856 * Number of packets successfully transmitted (<= pkts_n).
4858 static __rte_always_inline uint16_t
4859 mlx5_tx_burst_tmpl(struct mlx5_txq_data *__rte_restrict txq,
4860 struct rte_mbuf **__rte_restrict pkts,
4864 struct mlx5_txq_local loc;
4865 enum mlx5_txcmp_code ret;
4868 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4869 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4870 if (unlikely(!pkts_n))
4874 loc.wqe_last = NULL;
4877 loc.pkts_loop = loc.pkts_sent;
4879 * Check if there are some CQEs, if any:
4880 * - process an encountered errors
4881 * - process the completed WQEs
4882 * - free related mbufs
4883 * - doorbell the NIC about processed CQEs
4885 rte_prefetch0(*(pkts + loc.pkts_sent));
4886 mlx5_tx_handle_completion(txq, olx);
4888 * Calculate the number of available resources - elts and WQEs.
4889 * There are two possible different scenarios:
4890 * - no data inlining into WQEs, one WQEBB may contains up to
4891 * four packets, in this case elts become scarce resource
4892 * - data inlining into WQEs, one packet may require multiple
4893 * WQEBBs, the WQEs become the limiting factor.
4895 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4896 loc.elts_free = txq->elts_s -
4897 (uint16_t)(txq->elts_head - txq->elts_tail);
4898 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4899 loc.wqe_free = txq->wqe_s -
4900 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4901 if (unlikely(!loc.elts_free || !loc.wqe_free))
4905 * Fetch the packet from array. Usually this is
4906 * the first packet in series of multi/single
4909 loc.mbuf = *(pkts + loc.pkts_sent);
4910 /* Dedicated branch for multi-segment packets. */
4911 if (MLX5_TXOFF_CONFIG(MULTI) &&
4912 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4914 * Multi-segment packet encountered.
4915 * Hardware is able to process it only
4916 * with SEND/TSO opcodes, one packet
4917 * per WQE, do it in dedicated routine.
4920 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4921 part = loc.pkts_sent - loc.pkts_copy;
4922 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4924 * There are some single-segment mbufs not
4925 * stored in elts. The mbufs must be in the
4926 * same order as WQEs, so we must copy the
4927 * mbufs to elts here, before the coming
4928 * multi-segment packet mbufs is appended.
4930 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4932 loc.pkts_copy = loc.pkts_sent;
4934 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4935 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4936 if (!MLX5_TXOFF_CONFIG(INLINE))
4937 loc.pkts_copy = loc.pkts_sent;
4939 * These returned code checks are supposed
4940 * to be optimized out due to routine inlining.
4942 if (ret == MLX5_TXCMP_CODE_EXIT) {
4944 * The routine returns this code when
4945 * all packets are sent or there is no
4946 * enough resources to complete request.
4950 if (ret == MLX5_TXCMP_CODE_ERROR) {
4952 * The routine returns this code when
4953 * some error in the incoming packets
4956 txq->stats.oerrors++;
4959 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4961 * The single-segment packet was encountered
4962 * in the array, try to send it with the
4963 * best optimized way, possible engaging eMPW.
4965 goto enter_send_single;
4967 if (MLX5_TXOFF_CONFIG(TSO) &&
4968 ret == MLX5_TXCMP_CODE_TSO) {
4970 * The single-segment TSO packet was
4971 * encountered in the array.
4973 goto enter_send_tso;
4975 /* We must not get here. Something is going wrong. */
4977 txq->stats.oerrors++;
4980 /* Dedicated branch for single-segment TSO packets. */
4981 if (MLX5_TXOFF_CONFIG(TSO) &&
4982 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4984 * TSO might require special way for inlining
4985 * (dedicated parameters) and is sent with
4986 * MLX5_OPCODE_TSO opcode only, provide this
4987 * in dedicated branch.
4990 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
4991 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4992 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4994 * These returned code checks are supposed
4995 * to be optimized out due to routine inlining.
4997 if (ret == MLX5_TXCMP_CODE_EXIT)
4999 if (ret == MLX5_TXCMP_CODE_ERROR) {
5000 txq->stats.oerrors++;
5003 if (ret == MLX5_TXCMP_CODE_SINGLE)
5004 goto enter_send_single;
5005 if (MLX5_TXOFF_CONFIG(MULTI) &&
5006 ret == MLX5_TXCMP_CODE_MULTI) {
5008 * The multi-segment packet was
5009 * encountered in the array.
5011 goto enter_send_multi;
5013 /* We must not get here. Something is going wrong. */
5015 txq->stats.oerrors++;
5019 * The dedicated branch for the single-segment packets
5020 * without TSO. Often these ones can be sent using
5021 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
5022 * The routine builds the WQEs till it encounters
5023 * the TSO or multi-segment packet (in case if these
5024 * offloads are requested at SQ configuration time).
5027 MLX5_ASSERT(pkts_n > loc.pkts_sent);
5028 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
5030 * These returned code checks are supposed
5031 * to be optimized out due to routine inlining.
5033 if (ret == MLX5_TXCMP_CODE_EXIT)
5035 if (ret == MLX5_TXCMP_CODE_ERROR) {
5036 txq->stats.oerrors++;
5039 if (MLX5_TXOFF_CONFIG(MULTI) &&
5040 ret == MLX5_TXCMP_CODE_MULTI) {
5042 * The multi-segment packet was
5043 * encountered in the array.
5045 goto enter_send_multi;
5047 if (MLX5_TXOFF_CONFIG(TSO) &&
5048 ret == MLX5_TXCMP_CODE_TSO) {
5050 * The single-segment TSO packet was
5051 * encountered in the array.
5053 goto enter_send_tso;
5055 /* We must not get here. Something is going wrong. */
5057 txq->stats.oerrors++;
5061 * Main Tx loop is completed, do the rest:
5062 * - set completion request if thresholds are reached
5063 * - doorbell the hardware
5064 * - copy the rest of mbufs to elts (if any)
5066 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5067 loc.pkts_sent >= loc.pkts_copy);
5068 /* Take a shortcut if nothing is sent. */
5069 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5071 /* Request CQE generation if limits are reached. */
5072 mlx5_tx_request_completion(txq, &loc, olx);
5074 * Ring QP doorbell immediately after WQE building completion
5075 * to improve latencies. The pure software related data treatment
5076 * can be completed after doorbell. Tx CQEs for this SQ are
5077 * processed in this thread only by the polling.
5079 * The rdma core library can map doorbell register in two ways,
5080 * depending on the environment variable "MLX5_SHUT_UP_BF":
5082 * - as regular cached memory, the variable is either missing or
5083 * set to zero. This type of mapping may cause the significant
5084 * doorbell register writing latency and requires explicit
5085 * memory write barrier to mitigate this issue and prevent
5088 * - as non-cached memory, the variable is present and set to
5089 * not "0" value. This type of mapping may cause performance
5090 * impact under heavy loading conditions but the explicit write
5091 * memory barrier is not required and it may improve core
5094 * - the legacy behaviour (prior 19.08 release) was to use some
5095 * heuristics to decide whether write memory barrier should
5096 * be performed. This behavior is supported with specifying
5097 * tx_db_nc=2, write barrier is skipped if application
5098 * provides the full recommended burst of packets, it
5099 * supposes the next packets are coming and the write barrier
5100 * will be issued on the next burst (after descriptor writing,
5103 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5104 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5105 /* Not all of the mbufs may be stored into elts yet. */
5106 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5107 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5109 * There are some single-segment mbufs not stored in elts.
5110 * It can be only if the last packet was single-segment.
5111 * The copying is gathered into one place due to it is
5112 * a good opportunity to optimize that with SIMD.
5113 * Unfortunately if inlining is enabled the gaps in
5114 * pointer array may happen due to early freeing of the
5117 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5118 loc.pkts_copy = loc.pkts_sent;
5120 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5121 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5122 if (pkts_n > loc.pkts_sent) {
5124 * If burst size is large there might be no enough CQE
5125 * fetched from completion queue and no enough resources
5126 * freed to send all the packets.
5131 #ifdef MLX5_PMD_SOFT_COUNTERS
5132 /* Increment sent packets counter. */
5133 txq->stats.opackets += loc.pkts_sent;
5135 return loc.pkts_sent;
5138 /* Generate routines with Enhanced Multi-Packet Write support. */
5139 MLX5_TXOFF_DECL(full_empw,
5140 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5142 MLX5_TXOFF_DECL(none_empw,
5143 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5145 MLX5_TXOFF_DECL(md_empw,
5146 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5148 MLX5_TXOFF_DECL(mt_empw,
5149 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5150 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5152 MLX5_TXOFF_DECL(mtsc_empw,
5153 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5154 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5155 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5157 MLX5_TXOFF_DECL(mti_empw,
5158 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5159 MLX5_TXOFF_CONFIG_INLINE |
5160 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5162 MLX5_TXOFF_DECL(mtv_empw,
5163 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5164 MLX5_TXOFF_CONFIG_VLAN |
5165 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5167 MLX5_TXOFF_DECL(mtiv_empw,
5168 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5169 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5170 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5172 MLX5_TXOFF_DECL(sc_empw,
5173 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5174 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5176 MLX5_TXOFF_DECL(sci_empw,
5177 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5178 MLX5_TXOFF_CONFIG_INLINE |
5179 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5181 MLX5_TXOFF_DECL(scv_empw,
5182 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5183 MLX5_TXOFF_CONFIG_VLAN |
5184 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5186 MLX5_TXOFF_DECL(sciv_empw,
5187 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5188 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5189 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5191 MLX5_TXOFF_DECL(i_empw,
5192 MLX5_TXOFF_CONFIG_INLINE |
5193 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5195 MLX5_TXOFF_DECL(v_empw,
5196 MLX5_TXOFF_CONFIG_VLAN |
5197 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5199 MLX5_TXOFF_DECL(iv_empw,
5200 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5201 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5203 /* Generate routines without Enhanced Multi-Packet Write support. */
5204 MLX5_TXOFF_DECL(full,
5205 MLX5_TXOFF_CONFIG_FULL)
5207 MLX5_TXOFF_DECL(none,
5208 MLX5_TXOFF_CONFIG_NONE)
5211 MLX5_TXOFF_CONFIG_METADATA)
5214 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5215 MLX5_TXOFF_CONFIG_METADATA)
5217 MLX5_TXOFF_DECL(mtsc,
5218 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5219 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5220 MLX5_TXOFF_CONFIG_METADATA)
5222 MLX5_TXOFF_DECL(mti,
5223 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5224 MLX5_TXOFF_CONFIG_INLINE |
5225 MLX5_TXOFF_CONFIG_METADATA)
5228 MLX5_TXOFF_DECL(mtv,
5229 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5230 MLX5_TXOFF_CONFIG_VLAN |
5231 MLX5_TXOFF_CONFIG_METADATA)
5234 MLX5_TXOFF_DECL(mtiv,
5235 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5236 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5237 MLX5_TXOFF_CONFIG_METADATA)
5240 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5241 MLX5_TXOFF_CONFIG_METADATA)
5243 MLX5_TXOFF_DECL(sci,
5244 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5245 MLX5_TXOFF_CONFIG_INLINE |
5246 MLX5_TXOFF_CONFIG_METADATA)
5249 MLX5_TXOFF_DECL(scv,
5250 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5251 MLX5_TXOFF_CONFIG_VLAN |
5252 MLX5_TXOFF_CONFIG_METADATA)
5255 MLX5_TXOFF_DECL(sciv,
5256 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5257 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5258 MLX5_TXOFF_CONFIG_METADATA)
5261 MLX5_TXOFF_CONFIG_INLINE |
5262 MLX5_TXOFF_CONFIG_METADATA)
5265 MLX5_TXOFF_CONFIG_VLAN |
5266 MLX5_TXOFF_CONFIG_METADATA)
5269 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5270 MLX5_TXOFF_CONFIG_METADATA)
5272 /* Generate routines with timestamp scheduling. */
5273 MLX5_TXOFF_DECL(full_ts_nompw,
5274 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5276 MLX5_TXOFF_DECL(full_ts_nompwi,
5277 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5278 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5279 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5280 MLX5_TXOFF_CONFIG_TXPP)
5282 MLX5_TXOFF_DECL(full_ts,
5283 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5284 MLX5_TXOFF_CONFIG_EMPW)
5286 MLX5_TXOFF_DECL(full_ts_noi,
5287 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5288 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5289 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5290 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5292 MLX5_TXOFF_DECL(none_ts,
5293 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5294 MLX5_TXOFF_CONFIG_EMPW)
5296 MLX5_TXOFF_DECL(mdi_ts,
5297 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5298 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5300 MLX5_TXOFF_DECL(mti_ts,
5301 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5302 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5303 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5305 MLX5_TXOFF_DECL(mtiv_ts,
5306 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5307 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5308 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5309 MLX5_TXOFF_CONFIG_EMPW)
5312 * Generate routines with Legacy Multi-Packet Write support.
5313 * This mode is supported by ConnectX-4 Lx only and imposes
5314 * offload limitations, not supported:
5315 * - ACL/Flows (metadata are becoming meaningless)
5316 * - WQE Inline headers
5317 * - SRIOV (E-Switch offloads)
5319 * - tunnel encapsulation/decapsulation
5322 MLX5_TXOFF_DECL(none_mpw,
5323 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5324 MLX5_TXOFF_CONFIG_MPW)
5326 MLX5_TXOFF_DECL(mci_mpw,
5327 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5328 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5329 MLX5_TXOFF_CONFIG_MPW)
5331 MLX5_TXOFF_DECL(mc_mpw,
5332 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5333 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5335 MLX5_TXOFF_DECL(i_mpw,
5336 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5337 MLX5_TXOFF_CONFIG_MPW)
5340 * Array of declared and compiled Tx burst function and corresponding
5341 * supported offloads set. The array is used to select the Tx burst
5342 * function for specified offloads set at Tx queue configuration time.
5345 eth_tx_burst_t func;
5348 MLX5_TXOFF_INFO(full_empw,
5349 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5350 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5351 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5352 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5354 MLX5_TXOFF_INFO(none_empw,
5355 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5357 MLX5_TXOFF_INFO(md_empw,
5358 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5360 MLX5_TXOFF_INFO(mt_empw,
5361 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5362 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5364 MLX5_TXOFF_INFO(mtsc_empw,
5365 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5366 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5367 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5369 MLX5_TXOFF_INFO(mti_empw,
5370 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5371 MLX5_TXOFF_CONFIG_INLINE |
5372 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5374 MLX5_TXOFF_INFO(mtv_empw,
5375 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5376 MLX5_TXOFF_CONFIG_VLAN |
5377 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5379 MLX5_TXOFF_INFO(mtiv_empw,
5380 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5381 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5382 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5384 MLX5_TXOFF_INFO(sc_empw,
5385 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5386 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5388 MLX5_TXOFF_INFO(sci_empw,
5389 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5390 MLX5_TXOFF_CONFIG_INLINE |
5391 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5393 MLX5_TXOFF_INFO(scv_empw,
5394 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5395 MLX5_TXOFF_CONFIG_VLAN |
5396 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5398 MLX5_TXOFF_INFO(sciv_empw,
5399 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5400 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5401 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5403 MLX5_TXOFF_INFO(i_empw,
5404 MLX5_TXOFF_CONFIG_INLINE |
5405 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5407 MLX5_TXOFF_INFO(v_empw,
5408 MLX5_TXOFF_CONFIG_VLAN |
5409 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5411 MLX5_TXOFF_INFO(iv_empw,
5412 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5413 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5415 MLX5_TXOFF_INFO(full_ts_nompw,
5416 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP)
5418 MLX5_TXOFF_INFO(full_ts_nompwi,
5419 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5420 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5421 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5422 MLX5_TXOFF_CONFIG_TXPP)
5424 MLX5_TXOFF_INFO(full_ts,
5425 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_TXPP |
5426 MLX5_TXOFF_CONFIG_EMPW)
5428 MLX5_TXOFF_INFO(full_ts_noi,
5429 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5430 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5431 MLX5_TXOFF_CONFIG_VLAN | MLX5_TXOFF_CONFIG_METADATA |
5432 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5434 MLX5_TXOFF_INFO(none_ts,
5435 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_TXPP |
5436 MLX5_TXOFF_CONFIG_EMPW)
5438 MLX5_TXOFF_INFO(mdi_ts,
5439 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5440 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5442 MLX5_TXOFF_INFO(mti_ts,
5443 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5444 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_METADATA |
5445 MLX5_TXOFF_CONFIG_TXPP | MLX5_TXOFF_CONFIG_EMPW)
5447 MLX5_TXOFF_INFO(mtiv_ts,
5448 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5449 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5450 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_TXPP |
5451 MLX5_TXOFF_CONFIG_EMPW)
5453 MLX5_TXOFF_INFO(full,
5454 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5455 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5456 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5457 MLX5_TXOFF_CONFIG_METADATA)
5459 MLX5_TXOFF_INFO(none,
5460 MLX5_TXOFF_CONFIG_NONE)
5463 MLX5_TXOFF_CONFIG_METADATA)
5466 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5467 MLX5_TXOFF_CONFIG_METADATA)
5469 MLX5_TXOFF_INFO(mtsc,
5470 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5471 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5472 MLX5_TXOFF_CONFIG_METADATA)
5474 MLX5_TXOFF_INFO(mti,
5475 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5476 MLX5_TXOFF_CONFIG_INLINE |
5477 MLX5_TXOFF_CONFIG_METADATA)
5479 MLX5_TXOFF_INFO(mtv,
5480 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5481 MLX5_TXOFF_CONFIG_VLAN |
5482 MLX5_TXOFF_CONFIG_METADATA)
5484 MLX5_TXOFF_INFO(mtiv,
5485 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5486 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5487 MLX5_TXOFF_CONFIG_METADATA)
5490 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5491 MLX5_TXOFF_CONFIG_METADATA)
5493 MLX5_TXOFF_INFO(sci,
5494 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5495 MLX5_TXOFF_CONFIG_INLINE |
5496 MLX5_TXOFF_CONFIG_METADATA)
5498 MLX5_TXOFF_INFO(scv,
5499 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5500 MLX5_TXOFF_CONFIG_VLAN |
5501 MLX5_TXOFF_CONFIG_METADATA)
5503 MLX5_TXOFF_INFO(sciv,
5504 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5505 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5506 MLX5_TXOFF_CONFIG_METADATA)
5509 MLX5_TXOFF_CONFIG_INLINE |
5510 MLX5_TXOFF_CONFIG_METADATA)
5513 MLX5_TXOFF_CONFIG_VLAN |
5514 MLX5_TXOFF_CONFIG_METADATA)
5517 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5518 MLX5_TXOFF_CONFIG_METADATA)
5520 MLX5_TXOFF_INFO(none_mpw,
5521 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5522 MLX5_TXOFF_CONFIG_MPW)
5524 MLX5_TXOFF_INFO(mci_mpw,
5525 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5526 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5527 MLX5_TXOFF_CONFIG_MPW)
5529 MLX5_TXOFF_INFO(mc_mpw,
5530 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5531 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5533 MLX5_TXOFF_INFO(i_mpw,
5534 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5535 MLX5_TXOFF_CONFIG_MPW)
5539 * Configure the Tx function to use. The routine checks configured
5540 * Tx offloads for the device and selects appropriate Tx burst
5541 * routine. There are multiple Tx burst routines compiled from
5542 * the same template in the most optimal way for the dedicated
5546 * Pointer to private data structure.
5549 * Pointer to selected Tx burst function.
5552 mlx5_select_tx_function(struct rte_eth_dev *dev)
5554 struct mlx5_priv *priv = dev->data->dev_private;
5555 struct mlx5_dev_config *config = &priv->config;
5556 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5557 unsigned int diff = 0, olx = 0, i, m;
5559 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5560 MLX5_DSEG_MAX, "invalid WQE max size");
5561 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5562 "invalid WQE Control Segment size");
5563 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5564 "invalid WQE Ethernet Segment size");
5565 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5566 "invalid WQE Data Segment size");
5567 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5568 "invalid WQE size");
5570 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5571 /* We should support Multi-Segment Packets. */
5572 olx |= MLX5_TXOFF_CONFIG_MULTI;
5574 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5575 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5576 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5577 DEV_TX_OFFLOAD_IP_TNL_TSO |
5578 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5579 /* We should support TCP Send Offload. */
5580 olx |= MLX5_TXOFF_CONFIG_TSO;
5582 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5583 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5584 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5585 /* We should support Software Parser for Tunnels. */
5586 olx |= MLX5_TXOFF_CONFIG_SWP;
5588 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5589 DEV_TX_OFFLOAD_UDP_CKSUM |
5590 DEV_TX_OFFLOAD_TCP_CKSUM |
5591 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5592 /* We should support IP/TCP/UDP Checksums. */
5593 olx |= MLX5_TXOFF_CONFIG_CSUM;
5595 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5596 /* We should support VLAN insertion. */
5597 olx |= MLX5_TXOFF_CONFIG_VLAN;
5599 if (tx_offloads & DEV_TX_OFFLOAD_SEND_ON_TIMESTAMP &&
5600 rte_mbuf_dynflag_lookup
5601 (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL) >= 0 &&
5602 rte_mbuf_dynfield_lookup
5603 (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL) >= 0) {
5604 /* Offload configured, dynamic entities registered. */
5605 olx |= MLX5_TXOFF_CONFIG_TXPP;
5607 if (priv->txqs_n && (*priv->txqs)[0]) {
5608 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5610 if (txd->inlen_send) {
5612 * Check the data inline requirements. Data inline
5613 * is enabled on per device basis, we can check
5614 * the first Tx queue only.
5616 * If device does not support VLAN insertion in WQE
5617 * and some queues are requested to perform VLAN
5618 * insertion offload than inline must be enabled.
5620 olx |= MLX5_TXOFF_CONFIG_INLINE;
5623 if (config->mps == MLX5_MPW_ENHANCED &&
5624 config->txq_inline_min <= 0) {
5626 * The NIC supports Enhanced Multi-Packet Write
5627 * and does not require minimal inline data.
5629 olx |= MLX5_TXOFF_CONFIG_EMPW;
5631 if (rte_flow_dynf_metadata_avail()) {
5632 /* We should support Flow metadata. */
5633 olx |= MLX5_TXOFF_CONFIG_METADATA;
5635 if (config->mps == MLX5_MPW) {
5637 * The NIC supports Legacy Multi-Packet Write.
5638 * The MLX5_TXOFF_CONFIG_MPW controls the
5639 * descriptor building method in combination
5640 * with MLX5_TXOFF_CONFIG_EMPW.
5642 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5643 MLX5_TXOFF_CONFIG_SWP |
5644 MLX5_TXOFF_CONFIG_VLAN |
5645 MLX5_TXOFF_CONFIG_METADATA)))
5646 olx |= MLX5_TXOFF_CONFIG_EMPW |
5647 MLX5_TXOFF_CONFIG_MPW;
5650 * Scan the routines table to find the minimal
5651 * satisfying routine with requested offloads.
5653 m = RTE_DIM(txoff_func);
5654 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5657 tmp = txoff_func[i].olx;
5659 /* Meets requested offloads exactly.*/
5663 if ((tmp & olx) != olx) {
5664 /* Does not meet requested offloads at all. */
5667 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_MPW)
5668 /* Do not enable legacy MPW if not configured. */
5670 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5671 /* Do not enable eMPW if not configured. */
5673 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5674 /* Do not enable inlining if not configured. */
5676 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_TXPP)
5677 /* Do not enable scheduling if not configured. */
5680 * Some routine meets the requirements.
5681 * Check whether it has minimal amount
5682 * of not requested offloads.
5684 tmp = __builtin_popcountl(tmp & ~olx);
5685 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5686 /* First or better match, save and continue. */
5692 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5693 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5694 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5695 /* Lighter not requested offload. */
5700 if (m >= RTE_DIM(txoff_func)) {
5701 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5702 " for requested offloads %04X",
5703 dev->data->port_id, olx);
5706 DRV_LOG(DEBUG, "port %u has selected Tx function"
5707 " supporting offloads %04X/%04X",
5708 dev->data->port_id, olx, txoff_func[m].olx);
5709 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5710 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5711 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5712 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5713 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5714 DRV_LOG(DEBUG, "\tSWP (software parser)");
5715 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5716 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5717 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5718 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5719 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5720 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5721 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5722 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5723 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TXPP)
5724 DRV_LOG(DEBUG, "\tMETAD (tx Scheduling)");
5725 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5726 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5727 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5729 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5731 return txoff_func[m].func;
5735 * DPDK callback to get the TX queue information
5738 * Pointer to the device structure.
5740 * @param tx_queue_id
5741 * Tx queue identificator.
5744 * Pointer to the TX queue information structure.
5751 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5752 struct rte_eth_txq_info *qinfo)
5754 struct mlx5_priv *priv = dev->data->dev_private;
5755 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5756 struct mlx5_txq_ctrl *txq_ctrl =
5757 container_of(txq, struct mlx5_txq_ctrl, txq);
5761 qinfo->nb_desc = txq->elts_s;
5762 qinfo->conf.tx_thresh.pthresh = 0;
5763 qinfo->conf.tx_thresh.hthresh = 0;
5764 qinfo->conf.tx_thresh.wthresh = 0;
5765 qinfo->conf.tx_rs_thresh = 0;
5766 qinfo->conf.tx_free_thresh = 0;
5767 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5768 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5772 * DPDK callback to get the TX packet burst mode information
5775 * Pointer to the device structure.
5777 * @param tx_queue_id
5778 * Tx queue identificatior.
5781 * Pointer to the burts mode information.
5784 * 0 as success, -EINVAL as failure.
5788 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5789 uint16_t tx_queue_id __rte_unused,
5790 struct rte_eth_burst_mode *mode)
5792 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5793 unsigned int i, olx;
5795 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5796 if (pkt_burst == txoff_func[i].func) {
5797 olx = txoff_func[i].olx;
5798 snprintf(mode->info, sizeof(mode->info),
5799 "%s%s%s%s%s%s%s%s%s",
5800 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5801 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5802 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5803 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5805 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5807 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5809 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5811 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5813 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5815 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5817 (olx & MLX5_TXOFF_CONFIG_TXPP) ?