1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
46 static __rte_always_inline void
47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
48 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
50 static __rte_always_inline void
51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
54 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
61 * Build a table to translate Rx completion flags to packet type.
63 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
66 mlx5_set_ptype_table(void)
69 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
71 /* Last entry must not be overwritten, reserved for errored packet. */
72 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
73 (*p)[i] = RTE_PTYPE_UNKNOWN;
75 * The index to the array should have:
76 * bit[1:0] = l3_hdr_type
77 * bit[4:2] = l4_hdr_type
80 * bit[7] = outer_l3_type
83 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
85 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
90 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
92 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
95 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
97 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
99 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
101 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
103 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
105 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
108 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
112 /* Repeat with outer_l3_type being set. Just in case. */
113 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 RTE_PTYPE_L4_NONFRAG;
115 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
116 RTE_PTYPE_L4_NONFRAG;
117 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
119 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
121 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
131 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
133 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
138 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L4_NONFRAG;
145 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
190 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L4_TCP;
193 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L4_TCP;
196 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_TCP;
199 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_TCP;
203 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_UDP;
206 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_UDP;
209 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_UDP;
212 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_UDP;
218 * Build a table to translate packet to checksum type of Verbs.
221 mlx5_set_cksum_table(void)
227 * The index should have:
228 * bit[0] = PKT_TX_TCP_SEG
229 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
230 * bit[4] = PKT_TX_IP_CKSUM
231 * bit[8] = PKT_TX_OUTER_IP_CKSUM
234 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
237 /* Tunneled packet. */
238 if (i & (1 << 8)) /* Outer IP. */
239 v |= MLX5_ETH_WQE_L3_CSUM;
240 if (i & (1 << 4)) /* Inner IP. */
241 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
242 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
243 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
246 if (i & (1 << 4)) /* IP. */
247 v |= MLX5_ETH_WQE_L3_CSUM;
248 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
249 v |= MLX5_ETH_WQE_L4_CSUM;
251 mlx5_cksum_table[i] = v;
256 * Build a table to translate packet type of mbuf to SWP type of Verbs.
259 mlx5_set_swp_types_table(void)
265 * The index should have:
266 * bit[0:1] = PKT_TX_L4_MASK
267 * bit[4] = PKT_TX_IPV6
268 * bit[8] = PKT_TX_OUTER_IPV6
269 * bit[9] = PKT_TX_OUTER_UDP
271 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
274 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
276 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
278 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
279 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
280 v |= MLX5_ETH_WQE_L4_INNER_UDP;
281 mlx5_swp_types_table[i] = v;
286 * Return the size of tailroom of WQ.
289 * Pointer to TX queue structure.
291 * Pointer to tail of WQ.
297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
300 tailroom = (uintptr_t)(txq->wqes) +
301 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
307 * Copy data to tailroom of circular queue.
310 * Pointer to destination.
314 * Number of bytes to copy.
316 * Pointer to head of queue.
318 * Size of tailroom from dst.
321 * Pointer after copied data.
324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
325 void *base, size_t tailroom)
330 rte_memcpy(dst, src, tailroom);
331 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
333 ret = (uint8_t *)base + n - tailroom;
335 rte_memcpy(dst, src, n);
336 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
342 * Inline TSO headers into WQE.
345 * 0 on success, negative errno value on failure.
348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
351 uint16_t *pkt_inline_sz,
355 uint16_t *tso_header_sz)
357 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
358 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
360 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
361 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
365 *tso_segsz = buf->tso_segsz;
366 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
367 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
368 txq->stats.oerrors++;
372 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
373 /* First seg must contain all TSO headers. */
374 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
375 *tso_header_sz > DATA_LEN(buf)) {
376 txq->stats.oerrors++;
379 copy_b = *tso_header_sz - *pkt_inline_sz;
380 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
382 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
383 if (unlikely(*max_wqe < n_wqe))
386 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
389 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
390 *pkt_inline_sz += copy_b;
396 * DPDK callback to check the status of a tx descriptor.
401 * The index of the descriptor in the ring.
404 * The status of the tx descriptor.
407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
409 struct mlx5_txq_data *txq = tx_queue;
412 mlx5_tx_complete(txq);
413 used = txq->elts_head - txq->elts_tail;
415 return RTE_ETH_TX_DESC_FULL;
416 return RTE_ETH_TX_DESC_DONE;
420 * DPDK callback to check the status of a rx descriptor.
425 * The index of the descriptor in the ring.
428 * The status of the tx descriptor.
431 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
433 struct mlx5_rxq_data *rxq = rx_queue;
434 struct rxq_zip *zip = &rxq->zip;
435 volatile struct mlx5_cqe *cqe;
436 const unsigned int cqe_n = (1 << rxq->cqe_n);
437 const unsigned int cqe_cnt = cqe_n - 1;
441 /* if we are processing a compressed cqe */
443 used = zip->cqe_cnt - zip->ca;
449 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
450 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
454 op_own = cqe->op_own;
455 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
456 n = rte_be_to_cpu_32(cqe->byte_cnt);
461 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
463 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
465 return RTE_ETH_RX_DESC_DONE;
466 return RTE_ETH_RX_DESC_AVAIL;
470 * DPDK callback for TX.
473 * Generic pointer to TX queue structure.
475 * Packets to transmit.
477 * Number of packets in array.
480 * Number of packets successfully transmitted (<= pkts_n).
483 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
485 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
486 uint16_t elts_head = txq->elts_head;
487 const uint16_t elts_n = 1 << txq->elts_n;
488 const uint16_t elts_m = elts_n - 1;
495 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
496 unsigned int segs_n = 0;
497 const unsigned int max_inline = txq->max_inline;
499 if (unlikely(!pkts_n))
501 /* Prefetch first packet cacheline. */
502 rte_prefetch0(*pkts);
503 /* Start processing. */
504 mlx5_tx_complete(txq);
505 max_elts = (elts_n - (elts_head - txq->elts_tail));
506 /* A CQE slot must always be available. */
507 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
508 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
509 if (unlikely(!max_wqe))
512 struct rte_mbuf *buf = *pkts; /* First_seg. */
514 volatile struct mlx5_wqe_v *wqe = NULL;
515 volatile rte_v128u32_t *dseg = NULL;
518 unsigned int sg = 0; /* counter of additional segs attached. */
520 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
521 uint16_t tso_header_sz = 0;
524 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
525 uint32_t swp_offsets = 0;
526 uint8_t swp_types = 0;
527 uint16_t tso_segsz = 0;
528 #ifdef MLX5_PMD_SOFT_COUNTERS
529 uint32_t total_length = 0;
533 segs_n = buf->nb_segs;
535 * Make sure there is enough room to store this packet and
536 * that one ring entry remains unused.
539 if (max_elts < segs_n)
543 if (unlikely(--max_wqe == 0))
545 wqe = (volatile struct mlx5_wqe_v *)
546 tx_mlx5_wqe(txq, txq->wqe_ci);
547 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
549 rte_prefetch0(*(pkts + 1));
550 addr = rte_pktmbuf_mtod(buf, uintptr_t);
551 length = DATA_LEN(buf);
552 ehdr = (((uint8_t *)addr)[1] << 8) |
553 ((uint8_t *)addr)[0];
554 #ifdef MLX5_PMD_SOFT_COUNTERS
555 total_length = length;
557 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
558 txq->stats.oerrors++;
561 /* Update element. */
562 (*txq->elts)[elts_head & elts_m] = buf;
563 /* Prefetch next buffer data. */
566 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
567 cs_flags = txq_ol_cksum_to_cs(buf);
568 txq_mbuf_to_swp(txq, buf, (uint8_t *)&swp_offsets, &swp_types);
569 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
570 /* Replace the Ethernet type by the VLAN if necessary. */
571 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
572 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
574 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
578 /* Copy Destination and source mac address. */
579 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
581 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
582 /* Copy missing two bytes to end the DSeg. */
583 memcpy((uint8_t *)raw + len + sizeof(vlan),
584 ((uint8_t *)addr) + len, 2);
588 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
589 MLX5_WQE_DWORD_SIZE);
590 length -= pkt_inline_sz;
591 addr += pkt_inline_sz;
593 raw += MLX5_WQE_DWORD_SIZE;
595 ret = inline_tso(txq, buf, &length,
596 &addr, &pkt_inline_sz,
598 &tso_segsz, &tso_header_sz);
599 if (ret == -EINVAL) {
601 } else if (ret == -EAGAIN) {
603 wqe->ctrl = (rte_v128u32_t){
604 rte_cpu_to_be_32(txq->wqe_ci << 8),
605 rte_cpu_to_be_32(txq->qp_num_8s | 1),
610 #ifdef MLX5_PMD_SOFT_COUNTERS
617 /* Inline if enough room. */
618 if (max_inline || tso) {
620 uintptr_t end = (uintptr_t)
621 (((uintptr_t)txq->wqes) +
622 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
623 unsigned int inline_room = max_inline *
624 RTE_CACHE_LINE_SIZE -
625 (pkt_inline_sz - 2) -
631 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
632 RTE_CACHE_LINE_SIZE);
633 copy_b = (addr_end > addr) ?
634 RTE_MIN((addr_end - addr), length) : 0;
635 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
637 * One Dseg remains in the current WQE. To
638 * keep the computation positive, it is
639 * removed after the bytes to Dseg conversion.
641 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
643 if (unlikely(max_wqe < n))
648 inl = rte_cpu_to_be_32(copy_b |
650 rte_memcpy((void *)raw,
651 (void *)&inl, sizeof(inl));
653 pkt_inline_sz += sizeof(inl);
655 rte_memcpy((void *)raw, (void *)addr, copy_b);
658 pkt_inline_sz += copy_b;
661 * 2 DWORDs consumed by the WQE header + ETH segment +
662 * the size of the inline part of the packet.
664 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
666 if (ds % (MLX5_WQE_SIZE /
667 MLX5_WQE_DWORD_SIZE) == 0) {
668 if (unlikely(--max_wqe == 0))
670 dseg = (volatile rte_v128u32_t *)
671 tx_mlx5_wqe(txq, txq->wqe_ci +
674 dseg = (volatile rte_v128u32_t *)
676 (ds * MLX5_WQE_DWORD_SIZE));
679 } else if (!segs_n) {
683 * Further inline the next segment only for
688 inline_room -= copy_b;
692 /* Move to the next segment. */
696 addr = rte_pktmbuf_mtod(buf, uintptr_t);
697 length = DATA_LEN(buf);
698 #ifdef MLX5_PMD_SOFT_COUNTERS
699 total_length += length;
701 (*txq->elts)[++elts_head & elts_m] = buf;
706 * No inline has been done in the packet, only the
707 * Ethernet Header as been stored.
709 dseg = (volatile rte_v128u32_t *)
710 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
713 /* Add the remaining packet as a simple ds. */
714 addr = rte_cpu_to_be_64(addr);
715 *dseg = (rte_v128u32_t){
716 rte_cpu_to_be_32(length),
717 mlx5_tx_mb2mr(txq, buf),
730 * Spill on next WQE when the current one does not have
731 * enough room left. Size of WQE must a be a multiple
732 * of data segment size.
734 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
735 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
736 if (unlikely(--max_wqe == 0))
738 dseg = (volatile rte_v128u32_t *)
739 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
740 rte_prefetch0(tx_mlx5_wqe(txq,
741 txq->wqe_ci + ds / 4 + 1));
748 length = DATA_LEN(buf);
749 #ifdef MLX5_PMD_SOFT_COUNTERS
750 total_length += length;
752 /* Store segment information. */
753 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
754 *dseg = (rte_v128u32_t){
755 rte_cpu_to_be_32(length),
756 mlx5_tx_mb2mr(txq, buf),
760 (*txq->elts)[++elts_head & elts_m] = buf;
764 if (ds > MLX5_DSEG_MAX) {
765 txq->stats.oerrors++;
772 /* Initialize known and common part of the WQE structure. */
774 wqe->ctrl = (rte_v128u32_t){
775 rte_cpu_to_be_32((txq->wqe_ci << 8) |
777 rte_cpu_to_be_32(txq->qp_num_8s | ds),
781 wqe->eseg = (rte_v128u32_t){
783 cs_flags | (swp_types << 8) |
784 (rte_cpu_to_be_16(tso_segsz) << 16),
786 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
789 wqe->ctrl = (rte_v128u32_t){
790 rte_cpu_to_be_32((txq->wqe_ci << 8) |
792 rte_cpu_to_be_32(txq->qp_num_8s | ds),
796 wqe->eseg = (rte_v128u32_t){
798 cs_flags | (swp_types << 8),
800 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
804 txq->wqe_ci += (ds + 3) / 4;
805 /* Save the last successful WQE for completion request */
806 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
807 #ifdef MLX5_PMD_SOFT_COUNTERS
808 /* Increment sent bytes counter. */
809 txq->stats.obytes += total_length;
811 } while (i < pkts_n);
812 /* Take a shortcut if nothing must be sent. */
813 if (unlikely((i + k) == 0))
815 txq->elts_head += (i + j);
816 /* Check whether completion threshold has been reached. */
817 comp = txq->elts_comp + i + j + k;
818 if (comp >= MLX5_TX_COMP_THRESH) {
819 /* Request completion on last WQE. */
820 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
821 /* Save elts_head in unused "immediate" field of WQE. */
822 last_wqe->ctrl3 = txq->elts_head;
828 txq->elts_comp = comp;
830 #ifdef MLX5_PMD_SOFT_COUNTERS
831 /* Increment sent packets counter. */
832 txq->stats.opackets += i;
834 /* Ring QP doorbell. */
835 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
840 * Open a MPW session.
843 * Pointer to TX queue structure.
845 * Pointer to MPW session structure.
850 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
852 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
853 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
854 (volatile struct mlx5_wqe_data_seg (*)[])
855 tx_mlx5_wqe(txq, idx + 1);
857 mpw->state = MLX5_MPW_STATE_OPENED;
861 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
862 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
863 mpw->wqe->eseg.inline_hdr_sz = 0;
864 mpw->wqe->eseg.rsvd0 = 0;
865 mpw->wqe->eseg.rsvd1 = 0;
866 mpw->wqe->eseg.rsvd2 = 0;
867 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
870 mpw->wqe->ctrl[2] = 0;
871 mpw->wqe->ctrl[3] = 0;
872 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
873 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
874 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
875 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
876 mpw->data.dseg[2] = &(*dseg)[0];
877 mpw->data.dseg[3] = &(*dseg)[1];
878 mpw->data.dseg[4] = &(*dseg)[2];
882 * Close a MPW session.
885 * Pointer to TX queue structure.
887 * Pointer to MPW session structure.
890 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
892 unsigned int num = mpw->pkts_n;
895 * Store size in multiple of 16 bytes. Control and Ethernet segments
898 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
899 mpw->state = MLX5_MPW_STATE_CLOSED;
904 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
905 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
909 * DPDK callback for TX with MPW support.
912 * Generic pointer to TX queue structure.
914 * Packets to transmit.
916 * Number of packets in array.
919 * Number of packets successfully transmitted (<= pkts_n).
922 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
924 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
925 uint16_t elts_head = txq->elts_head;
926 const uint16_t elts_n = 1 << txq->elts_n;
927 const uint16_t elts_m = elts_n - 1;
933 struct mlx5_mpw mpw = {
934 .state = MLX5_MPW_STATE_CLOSED,
937 if (unlikely(!pkts_n))
939 /* Prefetch first packet cacheline. */
940 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
941 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
942 /* Start processing. */
943 mlx5_tx_complete(txq);
944 max_elts = (elts_n - (elts_head - txq->elts_tail));
945 /* A CQE slot must always be available. */
946 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
947 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
948 if (unlikely(!max_wqe))
951 struct rte_mbuf *buf = *(pkts++);
953 unsigned int segs_n = buf->nb_segs;
957 * Make sure there is enough room to store this packet and
958 * that one ring entry remains unused.
961 if (max_elts < segs_n)
963 /* Do not bother with large packets MPW cannot handle. */
964 if (segs_n > MLX5_MPW_DSEG_MAX) {
965 txq->stats.oerrors++;
970 cs_flags = txq_ol_cksum_to_cs(buf);
971 /* Retrieve packet information. */
972 length = PKT_LEN(buf);
974 /* Start new session if packet differs. */
975 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
976 ((mpw.len != length) ||
978 (mpw.wqe->eseg.cs_flags != cs_flags)))
979 mlx5_mpw_close(txq, &mpw);
980 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
982 * Multi-Packet WQE consumes at most two WQE.
983 * mlx5_mpw_new() expects to be able to use such
986 if (unlikely(max_wqe < 2))
989 mlx5_mpw_new(txq, &mpw, length);
990 mpw.wqe->eseg.cs_flags = cs_flags;
992 /* Multi-segment packets must be alone in their MPW. */
993 assert((segs_n == 1) || (mpw.pkts_n == 0));
994 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
998 volatile struct mlx5_wqe_data_seg *dseg;
1002 (*txq->elts)[elts_head++ & elts_m] = buf;
1003 dseg = mpw.data.dseg[mpw.pkts_n];
1004 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1005 *dseg = (struct mlx5_wqe_data_seg){
1006 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1007 .lkey = mlx5_tx_mb2mr(txq, buf),
1008 .addr = rte_cpu_to_be_64(addr),
1010 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1011 length += DATA_LEN(buf);
1017 assert(length == mpw.len);
1018 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1019 mlx5_mpw_close(txq, &mpw);
1020 #ifdef MLX5_PMD_SOFT_COUNTERS
1021 /* Increment sent bytes counter. */
1022 txq->stats.obytes += length;
1026 /* Take a shortcut if nothing must be sent. */
1027 if (unlikely(i == 0))
1029 /* Check whether completion threshold has been reached. */
1030 /* "j" includes both packets and segments. */
1031 comp = txq->elts_comp + j;
1032 if (comp >= MLX5_TX_COMP_THRESH) {
1033 volatile struct mlx5_wqe *wqe = mpw.wqe;
1035 /* Request completion on last WQE. */
1036 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1037 /* Save elts_head in unused "immediate" field of WQE. */
1038 wqe->ctrl[3] = elts_head;
1044 txq->elts_comp = comp;
1046 #ifdef MLX5_PMD_SOFT_COUNTERS
1047 /* Increment sent packets counter. */
1048 txq->stats.opackets += i;
1050 /* Ring QP doorbell. */
1051 if (mpw.state == MLX5_MPW_STATE_OPENED)
1052 mlx5_mpw_close(txq, &mpw);
1053 mlx5_tx_dbrec(txq, mpw.wqe);
1054 txq->elts_head = elts_head;
1059 * Open a MPW inline session.
1062 * Pointer to TX queue structure.
1064 * Pointer to MPW session structure.
1069 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1072 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1073 struct mlx5_wqe_inl_small *inl;
1075 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1079 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1080 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1081 (txq->wqe_ci << 8) |
1083 mpw->wqe->ctrl[2] = 0;
1084 mpw->wqe->ctrl[3] = 0;
1085 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1086 mpw->wqe->eseg.inline_hdr_sz = 0;
1087 mpw->wqe->eseg.cs_flags = 0;
1088 mpw->wqe->eseg.rsvd0 = 0;
1089 mpw->wqe->eseg.rsvd1 = 0;
1090 mpw->wqe->eseg.rsvd2 = 0;
1091 inl = (struct mlx5_wqe_inl_small *)
1092 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1093 mpw->data.raw = (uint8_t *)&inl->raw;
1097 * Close a MPW inline session.
1100 * Pointer to TX queue structure.
1102 * Pointer to MPW session structure.
1105 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1108 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1109 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1111 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1113 * Store size in multiple of 16 bytes. Control and Ethernet segments
1116 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1118 mpw->state = MLX5_MPW_STATE_CLOSED;
1119 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1120 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1124 * DPDK callback for TX with MPW inline support.
1127 * Generic pointer to TX queue structure.
1129 * Packets to transmit.
1131 * Number of packets in array.
1134 * Number of packets successfully transmitted (<= pkts_n).
1137 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1140 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1141 uint16_t elts_head = txq->elts_head;
1142 const uint16_t elts_n = 1 << txq->elts_n;
1143 const uint16_t elts_m = elts_n - 1;
1149 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1150 struct mlx5_mpw mpw = {
1151 .state = MLX5_MPW_STATE_CLOSED,
1154 * Compute the maximum number of WQE which can be consumed by inline
1157 * - 1 control segment,
1158 * - 1 Ethernet segment,
1159 * - N Dseg from the inline request.
1161 const unsigned int wqe_inl_n =
1162 ((2 * MLX5_WQE_DWORD_SIZE +
1163 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1164 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1166 if (unlikely(!pkts_n))
1168 /* Prefetch first packet cacheline. */
1169 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1170 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1171 /* Start processing. */
1172 mlx5_tx_complete(txq);
1173 max_elts = (elts_n - (elts_head - txq->elts_tail));
1174 /* A CQE slot must always be available. */
1175 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1177 struct rte_mbuf *buf = *(pkts++);
1180 unsigned int segs_n = buf->nb_segs;
1184 * Make sure there is enough room to store this packet and
1185 * that one ring entry remains unused.
1188 if (max_elts < segs_n)
1190 /* Do not bother with large packets MPW cannot handle. */
1191 if (segs_n > MLX5_MPW_DSEG_MAX) {
1192 txq->stats.oerrors++;
1198 * Compute max_wqe in case less WQE were consumed in previous
1201 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1202 cs_flags = txq_ol_cksum_to_cs(buf);
1203 /* Retrieve packet information. */
1204 length = PKT_LEN(buf);
1205 /* Start new session if packet differs. */
1206 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1207 if ((mpw.len != length) ||
1209 (mpw.wqe->eseg.cs_flags != cs_flags))
1210 mlx5_mpw_close(txq, &mpw);
1211 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1212 if ((mpw.len != length) ||
1214 (length > inline_room) ||
1215 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1216 mlx5_mpw_inline_close(txq, &mpw);
1218 txq->max_inline * RTE_CACHE_LINE_SIZE;
1221 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1222 if ((segs_n != 1) ||
1223 (length > inline_room)) {
1225 * Multi-Packet WQE consumes at most two WQE.
1226 * mlx5_mpw_new() expects to be able to use
1229 if (unlikely(max_wqe < 2))
1232 mlx5_mpw_new(txq, &mpw, length);
1233 mpw.wqe->eseg.cs_flags = cs_flags;
1235 if (unlikely(max_wqe < wqe_inl_n))
1237 max_wqe -= wqe_inl_n;
1238 mlx5_mpw_inline_new(txq, &mpw, length);
1239 mpw.wqe->eseg.cs_flags = cs_flags;
1242 /* Multi-segment packets must be alone in their MPW. */
1243 assert((segs_n == 1) || (mpw.pkts_n == 0));
1244 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1245 assert(inline_room ==
1246 txq->max_inline * RTE_CACHE_LINE_SIZE);
1247 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1251 volatile struct mlx5_wqe_data_seg *dseg;
1254 (*txq->elts)[elts_head++ & elts_m] = buf;
1255 dseg = mpw.data.dseg[mpw.pkts_n];
1256 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1257 *dseg = (struct mlx5_wqe_data_seg){
1259 rte_cpu_to_be_32(DATA_LEN(buf)),
1260 .lkey = mlx5_tx_mb2mr(txq, buf),
1261 .addr = rte_cpu_to_be_64(addr),
1263 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1264 length += DATA_LEN(buf);
1270 assert(length == mpw.len);
1271 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1272 mlx5_mpw_close(txq, &mpw);
1276 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1277 assert(length <= inline_room);
1278 assert(length == DATA_LEN(buf));
1279 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1280 (*txq->elts)[elts_head++ & elts_m] = buf;
1281 /* Maximum number of bytes before wrapping. */
1282 max = ((((uintptr_t)(txq->wqes)) +
1285 (uintptr_t)mpw.data.raw);
1287 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1290 mpw.data.raw = (volatile void *)txq->wqes;
1291 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1292 (void *)(addr + max),
1294 mpw.data.raw += length - max;
1296 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1302 (volatile void *)txq->wqes;
1304 mpw.data.raw += length;
1307 mpw.total_len += length;
1309 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1310 mlx5_mpw_inline_close(txq, &mpw);
1312 txq->max_inline * RTE_CACHE_LINE_SIZE;
1314 inline_room -= length;
1317 #ifdef MLX5_PMD_SOFT_COUNTERS
1318 /* Increment sent bytes counter. */
1319 txq->stats.obytes += length;
1323 /* Take a shortcut if nothing must be sent. */
1324 if (unlikely(i == 0))
1326 /* Check whether completion threshold has been reached. */
1327 /* "j" includes both packets and segments. */
1328 comp = txq->elts_comp + j;
1329 if (comp >= MLX5_TX_COMP_THRESH) {
1330 volatile struct mlx5_wqe *wqe = mpw.wqe;
1332 /* Request completion on last WQE. */
1333 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1334 /* Save elts_head in unused "immediate" field of WQE. */
1335 wqe->ctrl[3] = elts_head;
1341 txq->elts_comp = comp;
1343 #ifdef MLX5_PMD_SOFT_COUNTERS
1344 /* Increment sent packets counter. */
1345 txq->stats.opackets += i;
1347 /* Ring QP doorbell. */
1348 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1349 mlx5_mpw_inline_close(txq, &mpw);
1350 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1351 mlx5_mpw_close(txq, &mpw);
1352 mlx5_tx_dbrec(txq, mpw.wqe);
1353 txq->elts_head = elts_head;
1358 * Open an Enhanced MPW session.
1361 * Pointer to TX queue structure.
1363 * Pointer to MPW session structure.
1368 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1370 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1372 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1374 mpw->total_len = sizeof(struct mlx5_wqe);
1375 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1377 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1378 (txq->wqe_ci << 8) |
1379 MLX5_OPCODE_ENHANCED_MPSW);
1380 mpw->wqe->ctrl[2] = 0;
1381 mpw->wqe->ctrl[3] = 0;
1382 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1383 if (unlikely(padding)) {
1384 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1386 /* Pad the first 2 DWORDs with zero-length inline header. */
1387 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1388 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1389 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1390 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1391 /* Start from the next WQEBB. */
1392 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1394 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1399 * Close an Enhanced MPW session.
1402 * Pointer to TX queue structure.
1404 * Pointer to MPW session structure.
1407 * Number of consumed WQEs.
1409 static inline uint16_t
1410 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1414 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1417 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1418 MLX5_WQE_DS(mpw->total_len));
1419 mpw->state = MLX5_MPW_STATE_CLOSED;
1420 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1426 * TX with Enhanced MPW support.
1429 * Pointer to TX queue structure.
1431 * Packets to transmit.
1433 * Number of packets in array.
1436 * Number of packets successfully transmitted (<= pkts_n).
1438 static inline uint16_t
1439 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1442 uint16_t elts_head = txq->elts_head;
1443 const uint16_t elts_n = 1 << txq->elts_n;
1444 const uint16_t elts_m = elts_n - 1;
1449 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1450 unsigned int mpw_room = 0;
1451 unsigned int inl_pad = 0;
1453 struct mlx5_mpw mpw = {
1454 .state = MLX5_MPW_STATE_CLOSED,
1457 if (unlikely(!pkts_n))
1459 /* Start processing. */
1460 mlx5_tx_complete(txq);
1461 max_elts = (elts_n - (elts_head - txq->elts_tail));
1462 /* A CQE slot must always be available. */
1463 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1464 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1465 if (unlikely(!max_wqe))
1468 struct rte_mbuf *buf = *(pkts++);
1470 unsigned int do_inline = 0; /* Whether inline is possible. */
1474 /* Multi-segmented packet is handled in slow-path outside. */
1475 assert(NB_SEGS(buf) == 1);
1476 /* Make sure there is enough room to store this packet. */
1477 if (max_elts - j == 0)
1479 cs_flags = txq_ol_cksum_to_cs(buf);
1480 /* Retrieve packet information. */
1481 length = PKT_LEN(buf);
1482 /* Start new session if:
1483 * - multi-segment packet
1484 * - no space left even for a dseg
1485 * - next packet can be inlined with a new WQE
1488 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1489 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1491 (length <= txq->inline_max_packet_sz &&
1492 inl_pad + sizeof(inl_hdr) + length >
1494 (mpw.wqe->eseg.cs_flags != cs_flags))
1495 max_wqe -= mlx5_empw_close(txq, &mpw);
1497 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1498 /* In Enhanced MPW, inline as much as the budget is
1499 * allowed. The remaining space is to be filled with
1500 * dsegs. If the title WQEBB isn't padded, it will have
1503 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1504 (max_inline ? max_inline :
1505 pkts_n * MLX5_WQE_DWORD_SIZE) +
1507 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1509 /* Don't pad the title WQEBB to not waste WQ. */
1510 mlx5_empw_new(txq, &mpw, 0);
1511 mpw_room -= mpw.total_len;
1513 do_inline = length <= txq->inline_max_packet_sz &&
1514 sizeof(inl_hdr) + length <= mpw_room &&
1516 mpw.wqe->eseg.cs_flags = cs_flags;
1518 /* Evaluate whether the next packet can be inlined.
1519 * Inlininig is possible when:
1520 * - length is less than configured value
1521 * - length fits for remaining space
1522 * - not required to fill the title WQEBB with dsegs
1525 length <= txq->inline_max_packet_sz &&
1526 inl_pad + sizeof(inl_hdr) + length <=
1528 (!txq->mpw_hdr_dseg ||
1529 mpw.total_len >= MLX5_WQE_SIZE);
1531 if (max_inline && do_inline) {
1532 /* Inline packet into WQE. */
1535 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1536 assert(length == DATA_LEN(buf));
1537 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1538 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1539 mpw.data.raw = (volatile void *)
1540 ((uintptr_t)mpw.data.raw + inl_pad);
1541 max = tx_mlx5_wq_tailroom(txq,
1542 (void *)(uintptr_t)mpw.data.raw);
1543 /* Copy inline header. */
1544 mpw.data.raw = (volatile void *)
1546 (void *)(uintptr_t)mpw.data.raw,
1549 (void *)(uintptr_t)txq->wqes,
1551 max = tx_mlx5_wq_tailroom(txq,
1552 (void *)(uintptr_t)mpw.data.raw);
1553 /* Copy packet data. */
1554 mpw.data.raw = (volatile void *)
1556 (void *)(uintptr_t)mpw.data.raw,
1559 (void *)(uintptr_t)txq->wqes,
1562 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1563 /* No need to get completion as the entire packet is
1564 * copied to WQ. Free the buf right away.
1566 rte_pktmbuf_free_seg(buf);
1567 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1568 /* Add pad in the next packet if any. */
1569 inl_pad = (((uintptr_t)mpw.data.raw +
1570 (MLX5_WQE_DWORD_SIZE - 1)) &
1571 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1572 (uintptr_t)mpw.data.raw;
1574 /* No inline. Load a dseg of packet pointer. */
1575 volatile rte_v128u32_t *dseg;
1577 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1578 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1579 assert(length == DATA_LEN(buf));
1580 if (!tx_mlx5_wq_tailroom(txq,
1581 (void *)((uintptr_t)mpw.data.raw
1583 dseg = (volatile void *)txq->wqes;
1585 dseg = (volatile void *)
1586 ((uintptr_t)mpw.data.raw +
1588 (*txq->elts)[elts_head++ & elts_m] = buf;
1589 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1591 *dseg = (rte_v128u32_t) {
1592 rte_cpu_to_be_32(length),
1593 mlx5_tx_mb2mr(txq, buf),
1597 mpw.data.raw = (volatile void *)(dseg + 1);
1598 mpw.total_len += (inl_pad + sizeof(*dseg));
1601 mpw_room -= (inl_pad + sizeof(*dseg));
1604 #ifdef MLX5_PMD_SOFT_COUNTERS
1605 /* Increment sent bytes counter. */
1606 txq->stats.obytes += length;
1609 } while (i < pkts_n);
1610 /* Take a shortcut if nothing must be sent. */
1611 if (unlikely(i == 0))
1613 /* Check whether completion threshold has been reached. */
1614 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1615 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1616 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1617 volatile struct mlx5_wqe *wqe = mpw.wqe;
1619 /* Request completion on last WQE. */
1620 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1621 /* Save elts_head in unused "immediate" field of WQE. */
1622 wqe->ctrl[3] = elts_head;
1624 txq->mpw_comp = txq->wqe_ci;
1629 txq->elts_comp += j;
1631 #ifdef MLX5_PMD_SOFT_COUNTERS
1632 /* Increment sent packets counter. */
1633 txq->stats.opackets += i;
1635 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1636 mlx5_empw_close(txq, &mpw);
1637 /* Ring QP doorbell. */
1638 mlx5_tx_dbrec(txq, mpw.wqe);
1639 txq->elts_head = elts_head;
1644 * DPDK callback for TX with Enhanced MPW support.
1647 * Generic pointer to TX queue structure.
1649 * Packets to transmit.
1651 * Number of packets in array.
1654 * Number of packets successfully transmitted (<= pkts_n).
1657 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1659 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1662 while (pkts_n > nb_tx) {
1666 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1668 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1673 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1675 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1685 * Translate RX completion flags to packet type.
1688 * Pointer to RX queue structure.
1692 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1695 * Packet type for struct rte_mbuf.
1697 static inline uint32_t
1698 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1701 uint8_t pinfo = cqe->pkt_info;
1702 uint16_t ptype = cqe->hdr_type_etc;
1705 * The index to the array should have:
1706 * bit[1:0] = l3_hdr_type
1707 * bit[4:2] = l4_hdr_type
1710 * bit[7] = outer_l3_type
1712 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1713 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1717 * Get size of the next packet for a given CQE. For compressed CQEs, the
1718 * consumer index is updated only once all packets of the current one have
1722 * Pointer to RX queue.
1726 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1730 * Packet size in bytes (0 if there is none), -1 in case of completion
1734 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1735 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1737 struct rxq_zip *zip = &rxq->zip;
1738 uint16_t cqe_n = cqe_cnt + 1;
1742 /* Process compressed data in the CQE and mini arrays. */
1744 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1745 (volatile struct mlx5_mini_cqe8 (*)[8])
1746 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1748 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1749 *mcqe = &(*mc)[zip->ai & 7];
1750 if ((++zip->ai & 7) == 0) {
1751 /* Invalidate consumed CQEs */
1754 while (idx != end) {
1755 (*rxq->cqes)[idx & cqe_cnt].op_own =
1756 MLX5_CQE_INVALIDATE;
1760 * Increment consumer index to skip the number of
1761 * CQEs consumed. Hardware leaves holes in the CQ
1762 * ring for software use.
1767 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1768 /* Invalidate the rest */
1772 while (idx != end) {
1773 (*rxq->cqes)[idx & cqe_cnt].op_own =
1774 MLX5_CQE_INVALIDATE;
1777 rxq->cq_ci = zip->cq_ci;
1780 /* No compressed data, get next CQE and verify if it is compressed. */
1785 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1786 if (unlikely(ret == 1))
1789 op_own = cqe->op_own;
1791 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1792 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1793 (volatile struct mlx5_mini_cqe8 (*)[8])
1794 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1797 /* Fix endianness. */
1798 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1800 * Current mini array position is the one returned by
1803 * If completion comprises several mini arrays, as a
1804 * special case the second one is located 7 CQEs after
1805 * the initial CQE instead of 8 for subsequent ones.
1807 zip->ca = rxq->cq_ci;
1808 zip->na = zip->ca + 7;
1809 /* Compute the next non compressed CQE. */
1811 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1812 /* Get packet size to return. */
1813 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1816 /* Prefetch all the entries to be invalidated */
1819 while (idx != end) {
1820 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1824 len = rte_be_to_cpu_32(cqe->byte_cnt);
1826 /* Error while receiving packet. */
1827 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1834 * Translate RX completion flags to offload flags.
1840 * Offload flags (ol_flags) for struct rte_mbuf.
1842 static inline uint32_t
1843 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1845 uint32_t ol_flags = 0;
1846 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1850 MLX5_CQE_RX_L3_HDR_VALID,
1851 PKT_RX_IP_CKSUM_GOOD) |
1853 MLX5_CQE_RX_L4_HDR_VALID,
1854 PKT_RX_L4_CKSUM_GOOD);
1859 * Fill in mbuf fields from RX completion flags.
1860 * Note that pkt->ol_flags should be initialized outside of this function.
1863 * Pointer to RX queue.
1868 * @param rss_hash_res
1869 * Packet RSS Hash result.
1872 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1873 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1875 /* Update packet information. */
1876 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1877 if (rss_hash_res && rxq->rss_hash) {
1878 pkt->hash.rss = rss_hash_res;
1879 pkt->ol_flags |= PKT_RX_RSS_HASH;
1881 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1882 pkt->ol_flags |= PKT_RX_FDIR;
1883 if (cqe->sop_drop_qpn !=
1884 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1885 uint32_t mark = cqe->sop_drop_qpn;
1887 pkt->ol_flags |= PKT_RX_FDIR_ID;
1888 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1892 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1893 if (rxq->vlan_strip &&
1894 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1895 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1896 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1898 if (rxq->hw_timestamp) {
1899 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1900 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1905 * DPDK callback for RX.
1908 * Generic pointer to RX queue structure.
1910 * Array to store received packets.
1912 * Maximum number of packets in array.
1915 * Number of packets successfully received (<= pkts_n).
1918 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1920 struct mlx5_rxq_data *rxq = dpdk_rxq;
1921 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1922 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1923 const unsigned int sges_n = rxq->sges_n;
1924 struct rte_mbuf *pkt = NULL;
1925 struct rte_mbuf *seg = NULL;
1926 volatile struct mlx5_cqe *cqe =
1927 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1929 unsigned int rq_ci = rxq->rq_ci << sges_n;
1930 int len = 0; /* keep its value across iterations. */
1933 unsigned int idx = rq_ci & wqe_cnt;
1934 volatile struct mlx5_wqe_data_seg *wqe =
1935 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1936 struct rte_mbuf *rep = (*rxq->elts)[idx];
1937 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1938 uint32_t rss_hash_res;
1946 rep = rte_mbuf_raw_alloc(rxq->mp);
1947 if (unlikely(rep == NULL)) {
1948 ++rxq->stats.rx_nombuf;
1951 * no buffers before we even started,
1952 * bail out silently.
1956 while (pkt != seg) {
1957 assert(pkt != (*rxq->elts)[idx]);
1961 rte_mbuf_raw_free(pkt);
1967 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1968 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1970 rte_mbuf_raw_free(rep);
1973 if (unlikely(len == -1)) {
1974 /* RX error, packet is likely too large. */
1975 rte_mbuf_raw_free(rep);
1976 ++rxq->stats.idropped;
1980 assert(len >= (rxq->crc_present << 2));
1982 /* If compressed, take hash result from mini-CQE. */
1983 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1985 mcqe->rx_hash_result);
1986 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1987 if (rxq->crc_present)
1988 len -= ETHER_CRC_LEN;
1991 DATA_LEN(rep) = DATA_LEN(seg);
1992 PKT_LEN(rep) = PKT_LEN(seg);
1993 SET_DATA_OFF(rep, DATA_OFF(seg));
1994 PORT(rep) = PORT(seg);
1995 (*rxq->elts)[idx] = rep;
1997 * Fill NIC descriptor with the new buffer. The lkey and size
1998 * of the buffers are already known, only the buffer address
2001 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2002 /* If there's only one MR, no need to replace LKey in WQE. */
2003 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2004 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2005 if (len > DATA_LEN(seg)) {
2006 len -= DATA_LEN(seg);
2011 DATA_LEN(seg) = len;
2012 #ifdef MLX5_PMD_SOFT_COUNTERS
2013 /* Increment bytes counter. */
2014 rxq->stats.ibytes += PKT_LEN(pkt);
2016 /* Return packet. */
2022 /* Align consumer index to the next stride. */
2027 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2029 /* Update the consumer index. */
2030 rxq->rq_ci = rq_ci >> sges_n;
2032 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2034 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2035 #ifdef MLX5_PMD_SOFT_COUNTERS
2036 /* Increment packets counter. */
2037 rxq->stats.ipackets += i;
2043 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2045 struct mlx5_mprq_buf *buf = opaque;
2047 if (rte_atomic16_read(&buf->refcnt) == 1) {
2048 rte_mempool_put(buf->mp, buf);
2049 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2050 rte_atomic16_set(&buf->refcnt, 1);
2051 rte_mempool_put(buf->mp, buf);
2056 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2058 mlx5_mprq_buf_free_cb(NULL, buf);
2062 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2064 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2065 volatile struct mlx5_wqe_data_seg *wqe =
2066 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2069 assert(rep != NULL);
2070 /* Replace MPRQ buf. */
2071 (*rxq->mprq_bufs)[rq_idx] = rep;
2073 addr = mlx5_mprq_buf_addr(rep);
2074 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2075 /* If there's only one MR, no need to replace LKey in WQE. */
2076 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2077 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2078 /* Stash a mbuf for next replacement. */
2079 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2080 rxq->mprq_repl = rep;
2082 rxq->mprq_repl = NULL;
2086 * DPDK callback for RX with Multi-Packet RQ support.
2089 * Generic pointer to RX queue structure.
2091 * Array to store received packets.
2093 * Maximum number of packets in array.
2096 * Number of packets successfully received (<= pkts_n).
2099 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2101 struct mlx5_rxq_data *rxq = dpdk_rxq;
2102 const unsigned int strd_n = 1 << rxq->strd_num_n;
2103 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2104 const unsigned int strd_shift =
2105 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2106 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2107 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2108 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2110 uint16_t rq_ci = rxq->rq_ci;
2111 uint16_t consumed_strd = rxq->consumed_strd;
2112 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2114 while (i < pkts_n) {
2115 struct rte_mbuf *pkt;
2123 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
2124 uint32_t rss_hash_res = 0;
2126 if (consumed_strd == strd_n) {
2127 /* Replace WQE only if the buffer is still in use. */
2128 if (rte_atomic16_read(&buf->refcnt) > 1) {
2129 mprq_buf_replace(rxq, rq_ci & wq_mask);
2130 /* Release the old buffer. */
2131 mlx5_mprq_buf_free(buf);
2132 } else if (unlikely(rxq->mprq_repl == NULL)) {
2133 struct mlx5_mprq_buf *rep;
2136 * Currently, the MPRQ mempool is out of buffer
2137 * and doing memcpy regardless of the size of Rx
2138 * packet. Retry allocation to get back to
2141 if (!rte_mempool_get(rxq->mprq_mp,
2143 rxq->mprq_repl = rep;
2145 /* Advance to the next WQE. */
2148 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2150 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2151 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
2154 if (unlikely(ret == -1)) {
2155 /* RX error, packet is likely too large. */
2156 ++rxq->stats.idropped;
2160 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2161 MLX5_MPRQ_STRIDE_NUM_SHIFT;
2163 consumed_strd += strd_cnt;
2164 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2167 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
2168 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
2170 /* mini-CQE for MPRQ doesn't have hash result. */
2171 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
2173 assert(strd_idx < strd_n);
2174 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
2176 * Currently configured to receive a packet per a stride. But if
2177 * MTU is adjusted through kernel interface, device could
2178 * consume multiple strides without raising an error. In this
2179 * case, the packet should be dropped because it is bigger than
2180 * the max_rx_pkt_len.
2182 if (unlikely(strd_cnt > 1)) {
2183 ++rxq->stats.idropped;
2186 pkt = rte_pktmbuf_alloc(rxq->mp);
2187 if (unlikely(pkt == NULL)) {
2188 ++rxq->stats.rx_nombuf;
2191 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2192 assert((int)len >= (rxq->crc_present << 2));
2193 if (rxq->crc_present)
2194 len -= ETHER_CRC_LEN;
2195 offset = strd_idx * strd_sz + strd_shift;
2196 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2197 /* Initialize the offload flag. */
2200 * Memcpy packets to the target mbuf if:
2201 * - The size of packet is smaller than mprq_max_memcpy_len.
2202 * - Out of buffer in the Mempool for Multi-Packet RQ.
2204 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2206 * When memcpy'ing packet due to out-of-buffer, the
2207 * packet must be smaller than the target mbuf.
2209 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2210 rte_pktmbuf_free_seg(pkt);
2211 ++rxq->stats.idropped;
2214 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2216 rte_iova_t buf_iova;
2217 struct rte_mbuf_ext_shared_info *shinfo;
2218 uint16_t buf_len = strd_cnt * strd_sz;
2220 /* Increment the refcnt of the whole chunk. */
2221 rte_atomic16_add_return(&buf->refcnt, 1);
2222 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2224 addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2226 * MLX5 device doesn't use iova but it is necessary in a
2227 * case where the Rx packet is transmitted via a
2230 buf_iova = rte_mempool_virt2iova(buf) +
2231 RTE_PTR_DIFF(addr, buf);
2232 shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2233 &buf_len, mlx5_mprq_buf_free_cb, buf);
2235 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2236 * attaching the stride to mbuf and more offload flags
2237 * will be added below by calling rxq_cq_to_mbuf().
2238 * Other fields will be overwritten.
2240 rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2242 rte_pktmbuf_reset_headroom(pkt);
2243 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2245 * Prevent potential overflow due to MTU change through
2248 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2249 rte_pktmbuf_free_seg(pkt);
2250 ++rxq->stats.idropped;
2254 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2256 DATA_LEN(pkt) = len;
2257 PORT(pkt) = rxq->port_id;
2258 #ifdef MLX5_PMD_SOFT_COUNTERS
2259 /* Increment bytes counter. */
2260 rxq->stats.ibytes += PKT_LEN(pkt);
2262 /* Return packet. */
2266 /* Update the consumer indexes. */
2267 rxq->consumed_strd = consumed_strd;
2269 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2270 if (rq_ci != rxq->rq_ci) {
2273 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2275 #ifdef MLX5_PMD_SOFT_COUNTERS
2276 /* Increment packets counter. */
2277 rxq->stats.ipackets += i;
2283 * Dummy DPDK callback for TX.
2285 * This function is used to temporarily replace the real callback during
2286 * unsafe control operations on the queue, or in case of error.
2289 * Generic pointer to TX queue structure.
2291 * Packets to transmit.
2293 * Number of packets in array.
2296 * Number of packets successfully transmitted (<= pkts_n).
2299 removed_tx_burst(void *dpdk_txq __rte_unused,
2300 struct rte_mbuf **pkts __rte_unused,
2301 uint16_t pkts_n __rte_unused)
2307 * Dummy DPDK callback for RX.
2309 * This function is used to temporarily replace the real callback during
2310 * unsafe control operations on the queue, or in case of error.
2313 * Generic pointer to RX queue structure.
2315 * Array to store received packets.
2317 * Maximum number of packets in array.
2320 * Number of packets successfully received (<= pkts_n).
2323 removed_rx_burst(void *dpdk_txq __rte_unused,
2324 struct rte_mbuf **pkts __rte_unused,
2325 uint16_t pkts_n __rte_unused)
2331 * Vectorized Rx/Tx routines are not compiled in when required vector
2332 * instructions are not supported on a target architecture. The following null
2333 * stubs are needed for linkage when those are not included outside of this file
2334 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2337 uint16_t __attribute__((weak))
2338 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2339 struct rte_mbuf **pkts __rte_unused,
2340 uint16_t pkts_n __rte_unused)
2345 uint16_t __attribute__((weak))
2346 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2347 struct rte_mbuf **pkts __rte_unused,
2348 uint16_t pkts_n __rte_unused)
2353 uint16_t __attribute__((weak))
2354 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2355 struct rte_mbuf **pkts __rte_unused,
2356 uint16_t pkts_n __rte_unused)
2361 int __attribute__((weak))
2362 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2367 int __attribute__((weak))
2368 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2373 int __attribute__((weak))
2374 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2379 int __attribute__((weak))
2380 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)