4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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13 * * Redistributions in binary form must reproduce the above copyright
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15 * the documentation and/or other materials provided with the
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18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_mempool.h>
53 #include <rte_prefetch.h>
54 #include <rte_common.h>
55 #include <rte_branch_prediction.h>
56 #include <rte_ether.h>
59 #include "mlx5_utils.h"
60 #include "mlx5_rxtx.h"
61 #include "mlx5_autoconf.h"
62 #include "mlx5_defs.h"
65 static __rte_always_inline uint32_t
66 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
68 static __rte_always_inline int
69 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
70 uint16_t cqe_cnt, uint32_t *rss_hash);
72 static __rte_always_inline uint32_t
73 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
75 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
76 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
80 * Build a table to translate Rx completion flags to packet type.
82 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
85 mlx5_set_ptype_table(void)
88 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
90 /* Last entry must not be overwritten, reserved for errored packet. */
91 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
92 (*p)[i] = RTE_PTYPE_UNKNOWN;
94 * The index to the array should have:
95 * bit[1:0] = l3_hdr_type
96 * bit[4:2] = l4_hdr_type
99 * bit[7] = outer_l3_type
102 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
103 RTE_PTYPE_L4_NONFRAG;
104 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
105 RTE_PTYPE_L4_NONFRAG;
107 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
109 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
112 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
117 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
119 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
121 /* Repeat with outer_l3_type being set. Just in case. */
122 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 RTE_PTYPE_L4_NONFRAG;
124 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 RTE_PTYPE_L4_NONFRAG;
126 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
128 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
130 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
132 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
134 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
136 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L4_NONFRAG;
145 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
146 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L4_NONFRAG;
148 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L4_NONFRAG;
151 /* Tunneled - Fragmented */
152 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
153 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L4_FRAG;
155 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L4_FRAG;
158 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L4_FRAG;
161 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
162 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L4_FRAG;
165 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
172 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
175 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
178 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
193 * Return the size of tailroom of WQ.
196 * Pointer to TX queue structure.
198 * Pointer to tail of WQ.
204 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
207 tailroom = (uintptr_t)(txq->wqes) +
208 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
214 * Copy data to tailroom of circular queue.
217 * Pointer to destination.
221 * Number of bytes to copy.
223 * Pointer to head of queue.
225 * Size of tailroom from dst.
228 * Pointer after copied data.
231 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
232 void *base, size_t tailroom)
237 rte_memcpy(dst, src, tailroom);
238 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
240 ret = (uint8_t *)base + n - tailroom;
242 rte_memcpy(dst, src, n);
243 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
249 * DPDK callback to check the status of a tx descriptor.
254 * The index of the descriptor in the ring.
257 * The status of the tx descriptor.
260 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
262 struct txq *txq = tx_queue;
265 mlx5_tx_complete(txq);
266 used = txq->elts_head - txq->elts_tail;
268 return RTE_ETH_TX_DESC_FULL;
269 return RTE_ETH_TX_DESC_DONE;
273 * DPDK callback to check the status of a rx descriptor.
278 * The index of the descriptor in the ring.
281 * The status of the tx descriptor.
284 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
286 struct rxq *rxq = rx_queue;
287 struct rxq_zip *zip = &rxq->zip;
288 volatile struct mlx5_cqe *cqe;
289 const unsigned int cqe_n = (1 << rxq->cqe_n);
290 const unsigned int cqe_cnt = cqe_n - 1;
294 /* if we are processing a compressed cqe */
296 used = zip->cqe_cnt - zip->ca;
302 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
303 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
307 op_own = cqe->op_own;
308 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
309 n = ntohl(cqe->byte_cnt);
314 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
316 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
318 return RTE_ETH_RX_DESC_DONE;
319 return RTE_ETH_RX_DESC_AVAIL;
323 * DPDK callback for TX.
326 * Generic pointer to TX queue structure.
328 * Packets to transmit.
330 * Number of packets in array.
333 * Number of packets successfully transmitted (<= pkts_n).
336 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
338 struct txq *txq = (struct txq *)dpdk_txq;
339 uint16_t elts_head = txq->elts_head;
340 const uint16_t elts_n = 1 << txq->elts_n;
341 const uint16_t elts_m = elts_n - 1;
346 unsigned int max_inline = txq->max_inline;
347 const unsigned int inline_en = !!max_inline && txq->inline_en;
350 volatile struct mlx5_wqe_v *wqe = NULL;
351 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
352 unsigned int segs_n = 0;
353 struct rte_mbuf *buf = NULL;
356 if (unlikely(!pkts_n))
358 /* Prefetch first packet cacheline. */
359 rte_prefetch0(*pkts);
360 /* Start processing. */
361 mlx5_tx_complete(txq);
362 max_elts = (elts_n - (elts_head - txq->elts_tail));
363 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
364 if (unlikely(!max_wqe))
367 volatile rte_v128u32_t *dseg = NULL;
370 unsigned int sg = 0; /* counter of additional segs attached. */
373 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
374 uint16_t tso_header_sz = 0;
376 uint8_t cs_flags = 0;
378 uint16_t tso_segsz = 0;
379 #ifdef MLX5_PMD_SOFT_COUNTERS
380 uint32_t total_length = 0;
385 segs_n = buf->nb_segs;
387 * Make sure there is enough room to store this packet and
388 * that one ring entry remains unused.
391 if (max_elts < segs_n)
395 if (unlikely(--max_wqe == 0))
397 wqe = (volatile struct mlx5_wqe_v *)
398 tx_mlx5_wqe(txq, txq->wqe_ci);
399 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
401 rte_prefetch0(*(pkts + 1));
402 addr = rte_pktmbuf_mtod(buf, uintptr_t);
403 length = DATA_LEN(buf);
404 ehdr = (((uint8_t *)addr)[1] << 8) |
405 ((uint8_t *)addr)[0];
406 #ifdef MLX5_PMD_SOFT_COUNTERS
407 total_length = length;
409 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
410 txq->stats.oerrors++;
413 /* Update element. */
414 (*txq->elts)[elts_head & elts_m] = buf;
415 /* Prefetch next buffer data. */
418 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
419 /* Should we enable HW CKSUM offload */
421 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
422 const uint64_t is_tunneled = buf->ol_flags &
424 PKT_TX_TUNNEL_VXLAN);
426 if (is_tunneled && txq->tunnel_en) {
427 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
428 MLX5_ETH_WQE_L4_INNER_CSUM;
429 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
430 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
432 cs_flags = MLX5_ETH_WQE_L3_CSUM |
433 MLX5_ETH_WQE_L4_CSUM;
436 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
437 /* Replace the Ethernet type by the VLAN if necessary. */
438 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
439 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
440 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
444 /* Copy Destination and source mac address. */
445 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
447 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
448 /* Copy missing two bytes to end the DSeg. */
449 memcpy((uint8_t *)raw + len + sizeof(vlan),
450 ((uint8_t *)addr) + len, 2);
454 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
455 MLX5_WQE_DWORD_SIZE);
456 length -= pkt_inline_sz;
457 addr += pkt_inline_sz;
459 raw += MLX5_WQE_DWORD_SIZE;
461 tso = buf->ol_flags & PKT_TX_TCP_SEG;
463 uintptr_t end = (uintptr_t)
464 (((uintptr_t)txq->wqes) +
468 uint8_t vlan_sz = (buf->ol_flags &
469 PKT_TX_VLAN_PKT) ? 4 : 0;
470 const uint64_t is_tunneled =
473 PKT_TX_TUNNEL_VXLAN);
475 tso_header_sz = buf->l2_len + vlan_sz +
476 buf->l3_len + buf->l4_len;
477 tso_segsz = buf->tso_segsz;
479 if (is_tunneled && txq->tunnel_en) {
480 tso_header_sz += buf->outer_l2_len +
482 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
484 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
486 if (unlikely(tso_header_sz >
487 MLX5_MAX_TSO_HEADER)) {
488 txq->stats.oerrors++;
491 copy_b = tso_header_sz - pkt_inline_sz;
492 /* First seg must contain all headers. */
493 assert(copy_b <= length);
495 ((end - (uintptr_t)raw) > copy_b)) {
496 uint16_t n = (MLX5_WQE_DS(copy_b) -
499 if (unlikely(max_wqe < n))
502 rte_memcpy((void *)raw,
503 (void *)addr, copy_b);
506 /* Include padding for TSO header. */
507 copy_b = MLX5_WQE_DS(copy_b) *
509 pkt_inline_sz += copy_b;
513 wqe->ctrl = (rte_v128u32_t){
514 htonl(txq->wqe_ci << 8),
515 htonl(txq->qp_num_8s | 1),
526 /* Inline if enough room. */
527 if (inline_en || tso) {
529 uintptr_t end = (uintptr_t)
530 (((uintptr_t)txq->wqes) +
531 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
532 unsigned int inline_room = max_inline *
533 RTE_CACHE_LINE_SIZE -
534 (pkt_inline_sz - 2) -
536 uintptr_t addr_end = (addr + inline_room) &
537 ~(RTE_CACHE_LINE_SIZE - 1);
538 unsigned int copy_b = (addr_end > addr) ?
539 RTE_MIN((addr_end - addr), length) :
542 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
544 * One Dseg remains in the current WQE. To
545 * keep the computation positive, it is
546 * removed after the bytes to Dseg conversion.
548 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
550 if (unlikely(max_wqe < n))
554 inl = htonl(copy_b | MLX5_INLINE_SEG);
555 rte_memcpy((void *)raw,
556 (void *)&inl, sizeof(inl));
558 pkt_inline_sz += sizeof(inl);
560 rte_memcpy((void *)raw, (void *)addr, copy_b);
563 pkt_inline_sz += copy_b;
566 * 2 DWORDs consumed by the WQE header + ETH segment +
567 * the size of the inline part of the packet.
569 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
571 if (ds % (MLX5_WQE_SIZE /
572 MLX5_WQE_DWORD_SIZE) == 0) {
573 if (unlikely(--max_wqe == 0))
575 dseg = (volatile rte_v128u32_t *)
576 tx_mlx5_wqe(txq, txq->wqe_ci +
579 dseg = (volatile rte_v128u32_t *)
581 (ds * MLX5_WQE_DWORD_SIZE));
584 } else if (!segs_n) {
587 /* dseg will be advance as part of next_seg */
588 dseg = (volatile rte_v128u32_t *)
590 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
595 * No inline has been done in the packet, only the
596 * Ethernet Header as been stored.
598 dseg = (volatile rte_v128u32_t *)
599 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
602 /* Add the remaining packet as a simple ds. */
603 naddr = htonll(addr);
604 *dseg = (rte_v128u32_t){
606 mlx5_tx_mb2mr(txq, buf),
619 * Spill on next WQE when the current one does not have
620 * enough room left. Size of WQE must a be a multiple
621 * of data segment size.
623 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
624 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
625 if (unlikely(--max_wqe == 0))
627 dseg = (volatile rte_v128u32_t *)
628 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
629 rte_prefetch0(tx_mlx5_wqe(txq,
630 txq->wqe_ci + ds / 4 + 1));
637 length = DATA_LEN(buf);
638 #ifdef MLX5_PMD_SOFT_COUNTERS
639 total_length += length;
641 /* Store segment information. */
642 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
643 *dseg = (rte_v128u32_t){
645 mlx5_tx_mb2mr(txq, buf),
649 (*txq->elts)[++elts_head & elts_m] = buf;
651 /* Advance counter only if all segs are successfully posted. */
657 if (ds > MLX5_DSEG_MAX) {
658 txq->stats.oerrors++;
664 /* Initialize known and common part of the WQE structure. */
666 wqe->ctrl = (rte_v128u32_t){
667 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
668 htonl(txq->qp_num_8s | ds),
672 wqe->eseg = (rte_v128u32_t){
674 cs_flags | (htons(tso_segsz) << 16),
676 (ehdr << 16) | htons(tso_header_sz),
679 wqe->ctrl = (rte_v128u32_t){
680 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
681 htonl(txq->qp_num_8s | ds),
685 wqe->eseg = (rte_v128u32_t){
689 (ehdr << 16) | htons(pkt_inline_sz),
693 txq->wqe_ci += (ds + 3) / 4;
694 /* Save the last successful WQE for completion request */
695 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
696 #ifdef MLX5_PMD_SOFT_COUNTERS
697 /* Increment sent bytes counter. */
698 txq->stats.obytes += total_length;
700 } while (i < pkts_n);
701 /* Take a shortcut if nothing must be sent. */
702 if (unlikely((i + k) == 0))
704 txq->elts_head += (i + j);
705 /* Check whether completion threshold has been reached. */
706 comp = txq->elts_comp + i + j + k;
707 if (comp >= MLX5_TX_COMP_THRESH) {
708 /* Request completion on last WQE. */
709 last_wqe->ctrl2 = htonl(8);
710 /* Save elts_head in unused "immediate" field of WQE. */
711 last_wqe->ctrl3 = txq->elts_head;
714 txq->elts_comp = comp;
716 #ifdef MLX5_PMD_SOFT_COUNTERS
717 /* Increment sent packets counter. */
718 txq->stats.opackets += i;
720 /* Ring QP doorbell. */
721 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
726 * Open a MPW session.
729 * Pointer to TX queue structure.
731 * Pointer to MPW session structure.
736 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
738 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
739 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
740 (volatile struct mlx5_wqe_data_seg (*)[])
741 tx_mlx5_wqe(txq, idx + 1);
743 mpw->state = MLX5_MPW_STATE_OPENED;
747 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
748 mpw->wqe->eseg.mss = htons(length);
749 mpw->wqe->eseg.inline_hdr_sz = 0;
750 mpw->wqe->eseg.rsvd0 = 0;
751 mpw->wqe->eseg.rsvd1 = 0;
752 mpw->wqe->eseg.rsvd2 = 0;
753 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
754 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
755 mpw->wqe->ctrl[2] = 0;
756 mpw->wqe->ctrl[3] = 0;
757 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
758 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
759 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
760 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
761 mpw->data.dseg[2] = &(*dseg)[0];
762 mpw->data.dseg[3] = &(*dseg)[1];
763 mpw->data.dseg[4] = &(*dseg)[2];
767 * Close a MPW session.
770 * Pointer to TX queue structure.
772 * Pointer to MPW session structure.
775 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
777 unsigned int num = mpw->pkts_n;
780 * Store size in multiple of 16 bytes. Control and Ethernet segments
783 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
784 mpw->state = MLX5_MPW_STATE_CLOSED;
789 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
790 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
794 * DPDK callback for TX with MPW support.
797 * Generic pointer to TX queue structure.
799 * Packets to transmit.
801 * Number of packets in array.
804 * Number of packets successfully transmitted (<= pkts_n).
807 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
809 struct txq *txq = (struct txq *)dpdk_txq;
810 uint16_t elts_head = txq->elts_head;
811 const uint16_t elts_n = 1 << txq->elts_n;
812 const uint16_t elts_m = elts_n - 1;
818 struct mlx5_mpw mpw = {
819 .state = MLX5_MPW_STATE_CLOSED,
822 if (unlikely(!pkts_n))
824 /* Prefetch first packet cacheline. */
825 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
826 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
827 /* Start processing. */
828 mlx5_tx_complete(txq);
829 max_elts = (elts_n - (elts_head - txq->elts_tail));
830 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
831 if (unlikely(!max_wqe))
834 struct rte_mbuf *buf = *(pkts++);
836 unsigned int segs_n = buf->nb_segs;
837 uint32_t cs_flags = 0;
840 * Make sure there is enough room to store this packet and
841 * that one ring entry remains unused.
844 if (max_elts < segs_n)
846 /* Do not bother with large packets MPW cannot handle. */
847 if (segs_n > MLX5_MPW_DSEG_MAX) {
848 txq->stats.oerrors++;
853 /* Should we enable HW CKSUM offload */
855 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
856 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
857 /* Retrieve packet information. */
858 length = PKT_LEN(buf);
860 /* Start new session if packet differs. */
861 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
862 ((mpw.len != length) ||
864 (mpw.wqe->eseg.cs_flags != cs_flags)))
865 mlx5_mpw_close(txq, &mpw);
866 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
868 * Multi-Packet WQE consumes at most two WQE.
869 * mlx5_mpw_new() expects to be able to use such
872 if (unlikely(max_wqe < 2))
875 mlx5_mpw_new(txq, &mpw, length);
876 mpw.wqe->eseg.cs_flags = cs_flags;
878 /* Multi-segment packets must be alone in their MPW. */
879 assert((segs_n == 1) || (mpw.pkts_n == 0));
880 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
884 volatile struct mlx5_wqe_data_seg *dseg;
888 (*txq->elts)[elts_head++ & elts_m] = buf;
889 dseg = mpw.data.dseg[mpw.pkts_n];
890 addr = rte_pktmbuf_mtod(buf, uintptr_t);
891 *dseg = (struct mlx5_wqe_data_seg){
892 .byte_count = htonl(DATA_LEN(buf)),
893 .lkey = mlx5_tx_mb2mr(txq, buf),
894 .addr = htonll(addr),
896 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
897 length += DATA_LEN(buf);
903 assert(length == mpw.len);
904 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
905 mlx5_mpw_close(txq, &mpw);
906 #ifdef MLX5_PMD_SOFT_COUNTERS
907 /* Increment sent bytes counter. */
908 txq->stats.obytes += length;
912 /* Take a shortcut if nothing must be sent. */
913 if (unlikely(i == 0))
915 /* Check whether completion threshold has been reached. */
916 /* "j" includes both packets and segments. */
917 comp = txq->elts_comp + j;
918 if (comp >= MLX5_TX_COMP_THRESH) {
919 volatile struct mlx5_wqe *wqe = mpw.wqe;
921 /* Request completion on last WQE. */
922 wqe->ctrl[2] = htonl(8);
923 /* Save elts_head in unused "immediate" field of WQE. */
924 wqe->ctrl[3] = elts_head;
927 txq->elts_comp = comp;
929 #ifdef MLX5_PMD_SOFT_COUNTERS
930 /* Increment sent packets counter. */
931 txq->stats.opackets += i;
933 /* Ring QP doorbell. */
934 if (mpw.state == MLX5_MPW_STATE_OPENED)
935 mlx5_mpw_close(txq, &mpw);
936 mlx5_tx_dbrec(txq, mpw.wqe);
937 txq->elts_head = elts_head;
942 * Open a MPW inline session.
945 * Pointer to TX queue structure.
947 * Pointer to MPW session structure.
952 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
954 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
955 struct mlx5_wqe_inl_small *inl;
957 mpw->state = MLX5_MPW_INL_STATE_OPENED;
961 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
962 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
965 mpw->wqe->ctrl[2] = 0;
966 mpw->wqe->ctrl[3] = 0;
967 mpw->wqe->eseg.mss = htons(length);
968 mpw->wqe->eseg.inline_hdr_sz = 0;
969 mpw->wqe->eseg.cs_flags = 0;
970 mpw->wqe->eseg.rsvd0 = 0;
971 mpw->wqe->eseg.rsvd1 = 0;
972 mpw->wqe->eseg.rsvd2 = 0;
973 inl = (struct mlx5_wqe_inl_small *)
974 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
975 mpw->data.raw = (uint8_t *)&inl->raw;
979 * Close a MPW inline session.
982 * Pointer to TX queue structure.
984 * Pointer to MPW session structure.
987 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
990 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
991 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
993 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
995 * Store size in multiple of 16 bytes. Control and Ethernet segments
998 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
999 mpw->state = MLX5_MPW_STATE_CLOSED;
1000 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1001 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1005 * DPDK callback for TX with MPW inline support.
1008 * Generic pointer to TX queue structure.
1010 * Packets to transmit.
1012 * Number of packets in array.
1015 * Number of packets successfully transmitted (<= pkts_n).
1018 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1021 struct txq *txq = (struct txq *)dpdk_txq;
1022 uint16_t elts_head = txq->elts_head;
1023 const uint16_t elts_n = 1 << txq->elts_n;
1024 const uint16_t elts_m = elts_n - 1;
1030 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1031 struct mlx5_mpw mpw = {
1032 .state = MLX5_MPW_STATE_CLOSED,
1035 * Compute the maximum number of WQE which can be consumed by inline
1038 * - 1 control segment,
1039 * - 1 Ethernet segment,
1040 * - N Dseg from the inline request.
1042 const unsigned int wqe_inl_n =
1043 ((2 * MLX5_WQE_DWORD_SIZE +
1044 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1045 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1047 if (unlikely(!pkts_n))
1049 /* Prefetch first packet cacheline. */
1050 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1051 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1052 /* Start processing. */
1053 mlx5_tx_complete(txq);
1054 max_elts = (elts_n - (elts_head - txq->elts_tail));
1056 struct rte_mbuf *buf = *(pkts++);
1059 unsigned int segs_n = buf->nb_segs;
1060 uint32_t cs_flags = 0;
1063 * Make sure there is enough room to store this packet and
1064 * that one ring entry remains unused.
1067 if (max_elts < segs_n)
1069 /* Do not bother with large packets MPW cannot handle. */
1070 if (segs_n > MLX5_MPW_DSEG_MAX) {
1071 txq->stats.oerrors++;
1077 * Compute max_wqe in case less WQE were consumed in previous
1080 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1081 /* Should we enable HW CKSUM offload */
1083 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1084 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1085 /* Retrieve packet information. */
1086 length = PKT_LEN(buf);
1087 /* Start new session if packet differs. */
1088 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1089 if ((mpw.len != length) ||
1091 (mpw.wqe->eseg.cs_flags != cs_flags))
1092 mlx5_mpw_close(txq, &mpw);
1093 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1094 if ((mpw.len != length) ||
1096 (length > inline_room) ||
1097 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1098 mlx5_mpw_inline_close(txq, &mpw);
1100 txq->max_inline * RTE_CACHE_LINE_SIZE;
1103 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1104 if ((segs_n != 1) ||
1105 (length > inline_room)) {
1107 * Multi-Packet WQE consumes at most two WQE.
1108 * mlx5_mpw_new() expects to be able to use
1111 if (unlikely(max_wqe < 2))
1114 mlx5_mpw_new(txq, &mpw, length);
1115 mpw.wqe->eseg.cs_flags = cs_flags;
1117 if (unlikely(max_wqe < wqe_inl_n))
1119 max_wqe -= wqe_inl_n;
1120 mlx5_mpw_inline_new(txq, &mpw, length);
1121 mpw.wqe->eseg.cs_flags = cs_flags;
1124 /* Multi-segment packets must be alone in their MPW. */
1125 assert((segs_n == 1) || (mpw.pkts_n == 0));
1126 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1127 assert(inline_room ==
1128 txq->max_inline * RTE_CACHE_LINE_SIZE);
1129 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1133 volatile struct mlx5_wqe_data_seg *dseg;
1136 (*txq->elts)[elts_head++ & elts_m] = buf;
1137 dseg = mpw.data.dseg[mpw.pkts_n];
1138 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1139 *dseg = (struct mlx5_wqe_data_seg){
1140 .byte_count = htonl(DATA_LEN(buf)),
1141 .lkey = mlx5_tx_mb2mr(txq, buf),
1142 .addr = htonll(addr),
1144 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1145 length += DATA_LEN(buf);
1151 assert(length == mpw.len);
1152 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1153 mlx5_mpw_close(txq, &mpw);
1157 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1158 assert(length <= inline_room);
1159 assert(length == DATA_LEN(buf));
1160 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1161 (*txq->elts)[elts_head++ & elts_m] = buf;
1162 /* Maximum number of bytes before wrapping. */
1163 max = ((((uintptr_t)(txq->wqes)) +
1166 (uintptr_t)mpw.data.raw);
1168 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1171 mpw.data.raw = (volatile void *)txq->wqes;
1172 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1173 (void *)(addr + max),
1175 mpw.data.raw += length - max;
1177 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1183 (volatile void *)txq->wqes;
1185 mpw.data.raw += length;
1188 mpw.total_len += length;
1190 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1191 mlx5_mpw_inline_close(txq, &mpw);
1193 txq->max_inline * RTE_CACHE_LINE_SIZE;
1195 inline_room -= length;
1198 #ifdef MLX5_PMD_SOFT_COUNTERS
1199 /* Increment sent bytes counter. */
1200 txq->stats.obytes += length;
1204 /* Take a shortcut if nothing must be sent. */
1205 if (unlikely(i == 0))
1207 /* Check whether completion threshold has been reached. */
1208 /* "j" includes both packets and segments. */
1209 comp = txq->elts_comp + j;
1210 if (comp >= MLX5_TX_COMP_THRESH) {
1211 volatile struct mlx5_wqe *wqe = mpw.wqe;
1213 /* Request completion on last WQE. */
1214 wqe->ctrl[2] = htonl(8);
1215 /* Save elts_head in unused "immediate" field of WQE. */
1216 wqe->ctrl[3] = elts_head;
1219 txq->elts_comp = comp;
1221 #ifdef MLX5_PMD_SOFT_COUNTERS
1222 /* Increment sent packets counter. */
1223 txq->stats.opackets += i;
1225 /* Ring QP doorbell. */
1226 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1227 mlx5_mpw_inline_close(txq, &mpw);
1228 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1229 mlx5_mpw_close(txq, &mpw);
1230 mlx5_tx_dbrec(txq, mpw.wqe);
1231 txq->elts_head = elts_head;
1236 * Open an Enhanced MPW session.
1239 * Pointer to TX queue structure.
1241 * Pointer to MPW session structure.
1246 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1248 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1250 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1252 mpw->total_len = sizeof(struct mlx5_wqe);
1253 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1254 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1255 (txq->wqe_ci << 8) |
1256 MLX5_OPCODE_ENHANCED_MPSW);
1257 mpw->wqe->ctrl[2] = 0;
1258 mpw->wqe->ctrl[3] = 0;
1259 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1260 if (unlikely(padding)) {
1261 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1263 /* Pad the first 2 DWORDs with zero-length inline header. */
1264 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1265 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1266 htonl(MLX5_INLINE_SEG);
1267 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1268 /* Start from the next WQEBB. */
1269 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1271 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1276 * Close an Enhanced MPW session.
1279 * Pointer to TX queue structure.
1281 * Pointer to MPW session structure.
1284 * Number of consumed WQEs.
1286 static inline uint16_t
1287 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1291 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1294 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1295 mpw->state = MLX5_MPW_STATE_CLOSED;
1296 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1302 * DPDK callback for TX with Enhanced MPW support.
1305 * Generic pointer to TX queue structure.
1307 * Packets to transmit.
1309 * Number of packets in array.
1312 * Number of packets successfully transmitted (<= pkts_n).
1315 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1317 struct txq *txq = (struct txq *)dpdk_txq;
1318 uint16_t elts_head = txq->elts_head;
1319 const uint16_t elts_n = 1 << txq->elts_n;
1320 const uint16_t elts_m = elts_n - 1;
1325 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1326 unsigned int mpw_room = 0;
1327 unsigned int inl_pad = 0;
1329 struct mlx5_mpw mpw = {
1330 .state = MLX5_MPW_STATE_CLOSED,
1333 if (unlikely(!pkts_n))
1335 /* Start processing. */
1336 mlx5_tx_complete(txq);
1337 max_elts = (elts_n - (elts_head - txq->elts_tail));
1338 /* A CQE slot must always be available. */
1339 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1340 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1341 if (unlikely(!max_wqe))
1344 struct rte_mbuf *buf = *(pkts++);
1348 unsigned int do_inline = 0; /* Whether inline is possible. */
1350 unsigned int segs_n = buf->nb_segs;
1351 uint32_t cs_flags = 0;
1354 * Make sure there is enough room to store this packet and
1355 * that one ring entry remains unused.
1358 if (max_elts - j < segs_n)
1360 /* Do not bother with large packets MPW cannot handle. */
1361 if (segs_n > MLX5_MPW_DSEG_MAX) {
1362 txq->stats.oerrors++;
1365 /* Should we enable HW CKSUM offload. */
1367 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1368 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1369 /* Retrieve packet information. */
1370 length = PKT_LEN(buf);
1371 /* Start new session if:
1372 * - multi-segment packet
1373 * - no space left even for a dseg
1374 * - next packet can be inlined with a new WQE
1376 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1379 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1380 if ((segs_n != 1) ||
1381 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1383 (length <= txq->inline_max_packet_sz &&
1384 inl_pad + sizeof(inl_hdr) + length >
1386 (mpw.wqe->eseg.cs_flags != cs_flags))
1387 max_wqe -= mlx5_empw_close(txq, &mpw);
1389 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1390 if (unlikely(segs_n != 1)) {
1391 /* Fall back to legacy MPW.
1392 * A MPW session consumes 2 WQEs at most to
1393 * include MLX5_MPW_DSEG_MAX pointers.
1395 if (unlikely(max_wqe < 2))
1397 mlx5_mpw_new(txq, &mpw, length);
1399 /* In Enhanced MPW, inline as much as the budget
1400 * is allowed. The remaining space is to be
1401 * filled with dsegs. If the title WQEBB isn't
1402 * padded, it will have 2 dsegs there.
1404 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1405 (max_inline ? max_inline :
1406 pkts_n * MLX5_WQE_DWORD_SIZE) +
1408 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1411 /* Don't pad the title WQEBB to not waste WQ. */
1412 mlx5_empw_new(txq, &mpw, 0);
1413 mpw_room -= mpw.total_len;
1416 length <= txq->inline_max_packet_sz &&
1417 sizeof(inl_hdr) + length <= mpw_room &&
1420 mpw.wqe->eseg.cs_flags = cs_flags;
1422 /* Evaluate whether the next packet can be inlined.
1423 * Inlininig is possible when:
1424 * - length is less than configured value
1425 * - length fits for remaining space
1426 * - not required to fill the title WQEBB with dsegs
1429 length <= txq->inline_max_packet_sz &&
1430 inl_pad + sizeof(inl_hdr) + length <=
1432 (!txq->mpw_hdr_dseg ||
1433 mpw.total_len >= MLX5_WQE_SIZE);
1435 /* Multi-segment packets must be alone in their MPW. */
1436 assert((segs_n == 1) || (mpw.pkts_n == 0));
1437 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1438 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1442 volatile struct mlx5_wqe_data_seg *dseg;
1445 (*txq->elts)[elts_head++ & elts_m] = buf;
1446 dseg = mpw.data.dseg[mpw.pkts_n];
1447 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1448 *dseg = (struct mlx5_wqe_data_seg){
1449 .byte_count = htonl(DATA_LEN(buf)),
1450 .lkey = mlx5_tx_mb2mr(txq, buf),
1451 .addr = htonll(addr),
1453 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1454 length += DATA_LEN(buf);
1460 /* A multi-segmented packet takes one MPW session.
1461 * TODO: Pack more multi-segmented packets if possible.
1463 mlx5_mpw_close(txq, &mpw);
1468 } else if (do_inline) {
1469 /* Inline packet into WQE. */
1472 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1473 assert(length == DATA_LEN(buf));
1474 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1475 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1476 mpw.data.raw = (volatile void *)
1477 ((uintptr_t)mpw.data.raw + inl_pad);
1478 max = tx_mlx5_wq_tailroom(txq,
1479 (void *)(uintptr_t)mpw.data.raw);
1480 /* Copy inline header. */
1481 mpw.data.raw = (volatile void *)
1483 (void *)(uintptr_t)mpw.data.raw,
1486 (void *)(uintptr_t)txq->wqes,
1488 max = tx_mlx5_wq_tailroom(txq,
1489 (void *)(uintptr_t)mpw.data.raw);
1490 /* Copy packet data. */
1491 mpw.data.raw = (volatile void *)
1493 (void *)(uintptr_t)mpw.data.raw,
1496 (void *)(uintptr_t)txq->wqes,
1499 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1500 /* No need to get completion as the entire packet is
1501 * copied to WQ. Free the buf right away.
1503 rte_pktmbuf_free_seg(buf);
1504 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1505 /* Add pad in the next packet if any. */
1506 inl_pad = (((uintptr_t)mpw.data.raw +
1507 (MLX5_WQE_DWORD_SIZE - 1)) &
1508 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1509 (uintptr_t)mpw.data.raw;
1511 /* No inline. Load a dseg of packet pointer. */
1512 volatile rte_v128u32_t *dseg;
1514 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1515 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1516 assert(length == DATA_LEN(buf));
1517 if (!tx_mlx5_wq_tailroom(txq,
1518 (void *)((uintptr_t)mpw.data.raw
1520 dseg = (volatile void *)txq->wqes;
1522 dseg = (volatile void *)
1523 ((uintptr_t)mpw.data.raw +
1525 (*txq->elts)[elts_head++ & elts_m] = buf;
1526 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1527 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1528 rte_prefetch2((void *)(addr +
1529 n * RTE_CACHE_LINE_SIZE));
1530 naddr = htonll(addr);
1531 *dseg = (rte_v128u32_t) {
1533 mlx5_tx_mb2mr(txq, buf),
1537 mpw.data.raw = (volatile void *)(dseg + 1);
1538 mpw.total_len += (inl_pad + sizeof(*dseg));
1541 mpw_room -= (inl_pad + sizeof(*dseg));
1544 #ifdef MLX5_PMD_SOFT_COUNTERS
1545 /* Increment sent bytes counter. */
1546 txq->stats.obytes += length;
1549 } while (i < pkts_n);
1550 /* Take a shortcut if nothing must be sent. */
1551 if (unlikely(i == 0))
1553 /* Check whether completion threshold has been reached. */
1554 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1555 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1556 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1557 volatile struct mlx5_wqe *wqe = mpw.wqe;
1559 /* Request completion on last WQE. */
1560 wqe->ctrl[2] = htonl(8);
1561 /* Save elts_head in unused "immediate" field of WQE. */
1562 wqe->ctrl[3] = elts_head;
1564 txq->mpw_comp = txq->wqe_ci;
1567 txq->elts_comp += j;
1569 #ifdef MLX5_PMD_SOFT_COUNTERS
1570 /* Increment sent packets counter. */
1571 txq->stats.opackets += i;
1573 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1574 mlx5_empw_close(txq, &mpw);
1575 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1576 mlx5_mpw_close(txq, &mpw);
1577 /* Ring QP doorbell. */
1578 mlx5_tx_dbrec(txq, mpw.wqe);
1579 txq->elts_head = elts_head;
1584 * Translate RX completion flags to packet type.
1589 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1592 * Packet type for struct rte_mbuf.
1594 static inline uint32_t
1595 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1598 uint8_t pinfo = cqe->pkt_info;
1599 uint16_t ptype = cqe->hdr_type_etc;
1602 * The index to the array should have:
1603 * bit[1:0] = l3_hdr_type
1604 * bit[4:2] = l4_hdr_type
1607 * bit[7] = outer_l3_type
1609 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1610 return mlx5_ptype_table[idx];
1614 * Get size of the next packet for a given CQE. For compressed CQEs, the
1615 * consumer index is updated only once all packets of the current one have
1619 * Pointer to RX queue.
1622 * @param[out] rss_hash
1623 * Packet RSS Hash result.
1626 * Packet size in bytes (0 if there is none), -1 in case of completion
1630 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1631 uint16_t cqe_cnt, uint32_t *rss_hash)
1633 struct rxq_zip *zip = &rxq->zip;
1634 uint16_t cqe_n = cqe_cnt + 1;
1638 /* Process compressed data in the CQE and mini arrays. */
1640 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1641 (volatile struct mlx5_mini_cqe8 (*)[8])
1642 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1644 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1645 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1646 if ((++zip->ai & 7) == 0) {
1647 /* Invalidate consumed CQEs */
1650 while (idx != end) {
1651 (*rxq->cqes)[idx & cqe_cnt].op_own =
1652 MLX5_CQE_INVALIDATE;
1656 * Increment consumer index to skip the number of
1657 * CQEs consumed. Hardware leaves holes in the CQ
1658 * ring for software use.
1663 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1664 /* Invalidate the rest */
1668 while (idx != end) {
1669 (*rxq->cqes)[idx & cqe_cnt].op_own =
1670 MLX5_CQE_INVALIDATE;
1673 rxq->cq_ci = zip->cq_ci;
1676 /* No compressed data, get next CQE and verify if it is compressed. */
1681 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1682 if (unlikely(ret == 1))
1685 op_own = cqe->op_own;
1686 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1687 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1688 (volatile struct mlx5_mini_cqe8 (*)[8])
1689 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1692 /* Fix endianness. */
1693 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1695 * Current mini array position is the one returned by
1698 * If completion comprises several mini arrays, as a
1699 * special case the second one is located 7 CQEs after
1700 * the initial CQE instead of 8 for subsequent ones.
1702 zip->ca = rxq->cq_ci;
1703 zip->na = zip->ca + 7;
1704 /* Compute the next non compressed CQE. */
1706 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1707 /* Get packet size to return. */
1708 len = ntohl((*mc)[0].byte_cnt);
1709 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1711 /* Prefetch all the entries to be invalidated */
1714 while (idx != end) {
1715 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1719 len = ntohl(cqe->byte_cnt);
1720 *rss_hash = ntohl(cqe->rx_hash_res);
1722 /* Error while receiving packet. */
1723 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1730 * Translate RX completion flags to offload flags.
1733 * Pointer to RX queue structure.
1738 * Offload flags (ol_flags) for struct rte_mbuf.
1740 static inline uint32_t
1741 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1743 uint32_t ol_flags = 0;
1744 uint16_t flags = ntohs(cqe->hdr_type_etc);
1748 MLX5_CQE_RX_L3_HDR_VALID,
1749 PKT_RX_IP_CKSUM_GOOD) |
1751 MLX5_CQE_RX_L4_HDR_VALID,
1752 PKT_RX_L4_CKSUM_GOOD);
1753 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1756 MLX5_CQE_RX_L3_HDR_VALID,
1757 PKT_RX_IP_CKSUM_GOOD) |
1759 MLX5_CQE_RX_L4_HDR_VALID,
1760 PKT_RX_L4_CKSUM_GOOD);
1765 * DPDK callback for RX.
1768 * Generic pointer to RX queue structure.
1770 * Array to store received packets.
1772 * Maximum number of packets in array.
1775 * Number of packets successfully received (<= pkts_n).
1778 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1780 struct rxq *rxq = dpdk_rxq;
1781 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1782 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1783 const unsigned int sges_n = rxq->sges_n;
1784 struct rte_mbuf *pkt = NULL;
1785 struct rte_mbuf *seg = NULL;
1786 volatile struct mlx5_cqe *cqe =
1787 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1789 unsigned int rq_ci = rxq->rq_ci << sges_n;
1790 int len = 0; /* keep its value across iterations. */
1793 unsigned int idx = rq_ci & wqe_cnt;
1794 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1795 struct rte_mbuf *rep = (*rxq->elts)[idx];
1796 uint32_t rss_hash_res = 0;
1804 rep = rte_mbuf_raw_alloc(rxq->mp);
1805 if (unlikely(rep == NULL)) {
1806 ++rxq->stats.rx_nombuf;
1809 * no buffers before we even started,
1810 * bail out silently.
1814 while (pkt != seg) {
1815 assert(pkt != (*rxq->elts)[idx]);
1819 rte_mbuf_raw_free(pkt);
1825 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1826 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1829 rte_mbuf_raw_free(rep);
1832 if (unlikely(len == -1)) {
1833 /* RX error, packet is likely too large. */
1834 rte_mbuf_raw_free(rep);
1835 ++rxq->stats.idropped;
1839 assert(len >= (rxq->crc_present << 2));
1840 /* Update packet information. */
1841 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1843 if (rss_hash_res && rxq->rss_hash) {
1844 pkt->hash.rss = rss_hash_res;
1845 pkt->ol_flags = PKT_RX_RSS_HASH;
1848 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1849 pkt->ol_flags |= PKT_RX_FDIR;
1850 if (cqe->sop_drop_qpn !=
1851 htonl(MLX5_FLOW_MARK_DEFAULT)) {
1852 uint32_t mark = cqe->sop_drop_qpn;
1854 pkt->ol_flags |= PKT_RX_FDIR_ID;
1856 mlx5_flow_mark_get(mark);
1859 if (rxq->csum | rxq->csum_l2tun)
1860 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1861 if (rxq->vlan_strip &&
1862 (cqe->hdr_type_etc &
1863 htons(MLX5_CQE_VLAN_STRIPPED))) {
1864 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1865 PKT_RX_VLAN_STRIPPED;
1866 pkt->vlan_tci = ntohs(cqe->vlan_info);
1868 if (rxq->crc_present)
1869 len -= ETHER_CRC_LEN;
1872 DATA_LEN(rep) = DATA_LEN(seg);
1873 PKT_LEN(rep) = PKT_LEN(seg);
1874 SET_DATA_OFF(rep, DATA_OFF(seg));
1875 PORT(rep) = PORT(seg);
1876 (*rxq->elts)[idx] = rep;
1878 * Fill NIC descriptor with the new buffer. The lkey and size
1879 * of the buffers are already known, only the buffer address
1882 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1883 if (len > DATA_LEN(seg)) {
1884 len -= DATA_LEN(seg);
1889 DATA_LEN(seg) = len;
1890 #ifdef MLX5_PMD_SOFT_COUNTERS
1891 /* Increment bytes counter. */
1892 rxq->stats.ibytes += PKT_LEN(pkt);
1894 /* Return packet. */
1900 /* Align consumer index to the next stride. */
1905 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1907 /* Update the consumer index. */
1908 rxq->rq_ci = rq_ci >> sges_n;
1910 *rxq->cq_db = htonl(rxq->cq_ci);
1912 *rxq->rq_db = htonl(rxq->rq_ci);
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914 /* Increment packets counter. */
1915 rxq->stats.ipackets += i;
1921 * Dummy DPDK callback for TX.
1923 * This function is used to temporarily replace the real callback during
1924 * unsafe control operations on the queue, or in case of error.
1927 * Generic pointer to TX queue structure.
1929 * Packets to transmit.
1931 * Number of packets in array.
1934 * Number of packets successfully transmitted (<= pkts_n).
1937 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1946 * Dummy DPDK callback for RX.
1948 * This function is used to temporarily replace the real callback during
1949 * unsafe control operations on the queue, or in case of error.
1952 * Generic pointer to RX queue structure.
1954 * Array to store received packets.
1956 * Maximum number of packets in array.
1959 * Number of packets successfully received (<= pkts_n).
1962 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1971 * Vectorized Rx/Tx routines are not compiled in when required vector
1972 * instructions are not supported on a target architecture. The following null
1973 * stubs are needed for linkage when those are not included outside of this file
1974 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1977 uint16_t __attribute__((weak))
1978 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1986 uint16_t __attribute__((weak))
1987 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1995 uint16_t __attribute__((weak))
1996 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2004 int __attribute__((weak))
2005 priv_check_raw_vec_tx_support(struct priv *priv)
2011 int __attribute__((weak))
2012 priv_check_vec_tx_support(struct priv *priv)
2018 int __attribute__((weak))
2019 rxq_check_vec_support(struct rxq *rxq)
2025 int __attribute__((weak))
2026 priv_check_vec_rx_support(struct priv *priv)