4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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13 * * Redistributions in binary form must reproduce the above copyright
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17 * * Neither the name of 6WIND S.A. nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-pedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-pedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 * Manage TX completions.
158 * When sending a burst, mlx5_tx_burst() posts several WRs.
161 * Pointer to TX queue structure.
164 txq_complete(struct txq *txq)
166 const unsigned int elts_n = txq->elts_n;
167 const unsigned int cqe_n = txq->cqe_n;
168 const unsigned int cqe_cnt = cqe_n - 1;
169 uint16_t elts_free = txq->elts_tail;
171 uint16_t cq_ci = txq->cq_ci;
172 volatile struct mlx5_cqe64 *cqe = NULL;
173 volatile union mlx5_wqe *wqe;
176 volatile struct mlx5_cqe64 *tmp;
178 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
179 if (check_cqe64(tmp, cqe_n, cq_ci))
183 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
184 if (!check_cqe64_seen(cqe))
185 ERROR("unexpected compressed CQE, TX stopped");
188 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
189 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
190 if (!check_cqe64_seen(cqe))
191 ERROR("unexpected error CQE, TX stopped");
197 if (unlikely(cqe == NULL))
199 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)];
200 elts_tail = wqe->wqe.ctrl.data[3];
201 assert(elts_tail < txq->wqe_n);
203 while (elts_free != elts_tail) {
204 struct rte_mbuf *elt = (*txq->elts)[elts_free];
205 unsigned int elts_free_next =
206 (elts_free + 1) & (elts_n - 1);
207 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
211 memset(&(*txq->elts)[elts_free],
213 sizeof((*txq->elts)[elts_free]));
215 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
216 /* Only one segment needs to be freed. */
217 rte_pktmbuf_free_seg(elt);
218 elts_free = elts_free_next;
221 txq->elts_tail = elts_tail;
222 /* Update the consumer index. */
224 *txq->cq_db = htonl(cq_ci);
228 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
229 * the cloned mbuf is allocated is returned instead.
235 * Memory pool where data is located for given mbuf.
237 static struct rte_mempool *
238 txq_mb2mp(struct rte_mbuf *buf)
240 if (unlikely(RTE_MBUF_INDIRECT(buf)))
241 return rte_mbuf_from_indirect(buf)->pool;
245 static inline uint32_t
246 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
247 __attribute__((always_inline));
250 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
251 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
252 * remove an entry first.
255 * Pointer to TX queue structure.
257 * Memory Pool for which a Memory Region lkey must be returned.
260 * mr->lkey on success, (uint32_t)-1 on failure.
262 static inline uint32_t
263 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
266 uint32_t lkey = (uint32_t)-1;
268 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
269 if (unlikely(txq->mp2mr[i].mp == NULL)) {
270 /* Unknown MP, add a new MR for it. */
273 if (txq->mp2mr[i].mp == mp) {
274 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
275 assert(htonl(txq->mp2mr[i].mr->lkey) ==
277 lkey = txq->mp2mr[i].lkey;
281 if (unlikely(lkey == (uint32_t)-1))
282 lkey = txq_mp2mr_reg(txq, mp, i);
287 * Write a regular WQE.
290 * Pointer to TX queue structure.
292 * Pointer to the WQE to fill.
294 * Buffer data address.
298 * Memory region lkey.
301 mlx5_wqe_write(struct txq *txq, volatile union mlx5_wqe *wqe,
302 uintptr_t addr, uint32_t length, uint32_t lkey)
304 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
305 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
306 wqe->wqe.ctrl.data[2] = 0;
307 wqe->wqe.ctrl.data[3] = 0;
308 wqe->inl.eseg.rsvd0 = 0;
309 wqe->inl.eseg.rsvd1 = 0;
310 wqe->inl.eseg.mss = 0;
311 wqe->inl.eseg.rsvd2 = 0;
312 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
313 /* Copy the first 16 bytes into inline header. */
314 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
315 (uint8_t *)(uintptr_t)addr,
316 MLX5_ETH_INLINE_HEADER_SIZE);
317 addr += MLX5_ETH_INLINE_HEADER_SIZE;
318 length -= MLX5_ETH_INLINE_HEADER_SIZE;
319 /* Store remaining data in data segment. */
320 wqe->wqe.dseg.byte_count = htonl(length);
321 wqe->wqe.dseg.lkey = lkey;
322 wqe->wqe.dseg.addr = htonll(addr);
323 /* Increment consumer index. */
328 * Write a regular WQE with VLAN.
331 * Pointer to TX queue structure.
333 * Pointer to the WQE to fill.
335 * Buffer data address.
339 * Memory region lkey.
341 * VLAN field to insert in packet.
344 mlx5_wqe_write_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
345 uintptr_t addr, uint32_t length, uint32_t lkey,
348 uint32_t vlan = htonl(0x81000000 | vlan_tci);
350 wqe->wqe.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
351 wqe->wqe.ctrl.data[1] = htonl((txq->qp_num_8s) | 4);
352 wqe->wqe.ctrl.data[2] = 0;
353 wqe->wqe.ctrl.data[3] = 0;
354 wqe->inl.eseg.rsvd0 = 0;
355 wqe->inl.eseg.rsvd1 = 0;
356 wqe->inl.eseg.mss = 0;
357 wqe->inl.eseg.rsvd2 = 0;
358 wqe->wqe.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
360 * Copy 12 bytes of source & destination MAC address.
361 * Copy 4 bytes of VLAN.
362 * Copy 2 bytes of Ether type.
364 rte_memcpy((uint8_t *)(uintptr_t)wqe->wqe.eseg.inline_hdr_start,
365 (uint8_t *)(uintptr_t)addr, 12);
366 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 12),
367 &vlan, sizeof(vlan));
368 rte_memcpy((uint8_t *)((uintptr_t)wqe->wqe.eseg.inline_hdr_start + 16),
369 (uint8_t *)((uintptr_t)addr + 12), 2);
370 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
371 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
372 /* Store remaining data in data segment. */
373 wqe->wqe.dseg.byte_count = htonl(length);
374 wqe->wqe.dseg.lkey = lkey;
375 wqe->wqe.dseg.addr = htonll(addr);
376 /* Increment consumer index. */
381 * Write a inline WQE.
384 * Pointer to TX queue structure.
386 * Pointer to the WQE to fill.
388 * Buffer data address.
392 * Memory region lkey.
395 mlx5_wqe_write_inline(struct txq *txq, volatile union mlx5_wqe *wqe,
396 uintptr_t addr, uint32_t length)
399 uint16_t wqe_cnt = txq->wqe_n - 1;
400 uint16_t wqe_ci = txq->wqe_ci + 1;
402 /* Copy the first 16 bytes into inline header. */
403 rte_memcpy((void *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
404 (void *)(uintptr_t)addr,
405 MLX5_ETH_INLINE_HEADER_SIZE);
406 addr += MLX5_ETH_INLINE_HEADER_SIZE;
407 length -= MLX5_ETH_INLINE_HEADER_SIZE;
408 size = 3 + ((4 + length + 15) / 16);
409 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
410 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
411 (void *)addr, MLX5_WQE64_INL_DATA);
412 addr += MLX5_WQE64_INL_DATA;
413 length -= MLX5_WQE64_INL_DATA;
415 volatile union mlx5_wqe *wqe_next =
416 &(*txq->wqes)[wqe_ci & wqe_cnt];
417 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
421 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
424 length -= copy_bytes;
428 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
429 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
430 wqe->inl.ctrl.data[2] = 0;
431 wqe->inl.ctrl.data[3] = 0;
432 wqe->inl.eseg.rsvd0 = 0;
433 wqe->inl.eseg.rsvd1 = 0;
434 wqe->inl.eseg.mss = 0;
435 wqe->inl.eseg.rsvd2 = 0;
436 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_INLINE_HEADER_SIZE);
437 /* Increment consumer index. */
438 txq->wqe_ci = wqe_ci;
442 * Write a inline WQE with VLAN.
445 * Pointer to TX queue structure.
447 * Pointer to the WQE to fill.
449 * Buffer data address.
453 * Memory region lkey.
455 * VLAN field to insert in packet.
458 mlx5_wqe_write_inline_vlan(struct txq *txq, volatile union mlx5_wqe *wqe,
459 uintptr_t addr, uint32_t length, uint16_t vlan_tci)
462 uint32_t wqe_cnt = txq->wqe_n - 1;
463 uint16_t wqe_ci = txq->wqe_ci + 1;
464 uint32_t vlan = htonl(0x81000000 | vlan_tci);
467 * Copy 12 bytes of source & destination MAC address.
468 * Copy 4 bytes of VLAN.
469 * Copy 2 bytes of Ether type.
471 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start,
472 (uint8_t *)addr, 12);
473 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 12,
474 &vlan, sizeof(vlan));
475 rte_memcpy((uint8_t *)(uintptr_t)wqe->inl.eseg.inline_hdr_start + 16,
476 ((uint8_t *)addr + 12), 2);
477 addr += MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
478 length -= MLX5_ETH_VLAN_INLINE_HEADER_SIZE - sizeof(vlan);
479 size = (sizeof(wqe->inl.ctrl.ctrl) +
480 sizeof(wqe->inl.eseg) +
481 sizeof(wqe->inl.byte_cnt) +
483 wqe->inl.byte_cnt = htonl(length | MLX5_INLINE_SEG);
484 rte_memcpy((void *)(uintptr_t)&wqe->inl.data[0],
485 (void *)addr, MLX5_WQE64_INL_DATA);
486 addr += MLX5_WQE64_INL_DATA;
487 length -= MLX5_WQE64_INL_DATA;
489 volatile union mlx5_wqe *wqe_next =
490 &(*txq->wqes)[wqe_ci & wqe_cnt];
491 uint32_t copy_bytes = (length > sizeof(*wqe)) ?
495 rte_mov64((uint8_t *)(uintptr_t)&wqe_next->data[0],
498 length -= copy_bytes;
502 wqe->inl.ctrl.data[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
503 wqe->inl.ctrl.data[1] = htonl(txq->qp_num_8s | size);
504 wqe->inl.ctrl.data[2] = 0;
505 wqe->inl.ctrl.data[3] = 0;
506 wqe->inl.eseg.rsvd0 = 0;
507 wqe->inl.eseg.rsvd1 = 0;
508 wqe->inl.eseg.mss = 0;
509 wqe->inl.eseg.rsvd2 = 0;
510 wqe->inl.eseg.inline_hdr_sz = htons(MLX5_ETH_VLAN_INLINE_HEADER_SIZE);
511 /* Increment consumer index. */
512 txq->wqe_ci = wqe_ci;
516 * Ring TX queue doorbell.
519 * Pointer to TX queue structure.
522 mlx5_tx_dbrec(struct txq *txq)
524 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
526 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
527 htonl(txq->qp_num_8s),
532 *txq->qp_db = htonl(txq->wqe_ci);
533 /* Ensure ordering between DB record and BF copy. */
535 rte_mov16(dst, (uint8_t *)data);
536 txq->bf_offset ^= txq->bf_buf_size;
543 * Pointer to TX queue structure.
545 * CQE consumer index.
548 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
550 volatile struct mlx5_cqe64 *cqe;
552 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
560 * Pointer to TX queue structure.
562 * WQE consumer index.
565 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
567 volatile union mlx5_wqe *wqe;
569 wqe = &(*txq->wqes)[ci & (txq->wqe_n - 1)];
574 * DPDK callback for TX.
577 * Generic pointer to TX queue structure.
579 * Packets to transmit.
581 * Number of packets in array.
584 * Number of packets successfully transmitted (<= pkts_n).
587 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
589 struct txq *txq = (struct txq *)dpdk_txq;
590 uint16_t elts_head = txq->elts_head;
591 const unsigned int elts_n = txq->elts_n;
596 volatile union mlx5_wqe *wqe = NULL;
598 if (unlikely(!pkts_n))
600 /* Prefetch first packet cacheline. */
601 tx_prefetch_cqe(txq, txq->cq_ci);
602 tx_prefetch_cqe(txq, txq->cq_ci + 1);
603 rte_prefetch0(*pkts);
604 /* Start processing. */
606 max = (elts_n - (elts_head - txq->elts_tail));
610 struct rte_mbuf *buf = *(pkts++);
611 unsigned int elts_head_next;
615 unsigned int segs_n = buf->nb_segs;
616 volatile struct mlx5_wqe_data_seg *dseg;
617 unsigned int ds = sizeof(*wqe) / 16;
620 * Make sure there is enough room to store this packet and
621 * that one ring entry remains unused.
624 if (max < segs_n + 1)
628 elts_head_next = (elts_head + 1) & (elts_n - 1);
629 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
630 dseg = &wqe->wqe.dseg;
633 rte_prefetch0(*pkts);
634 /* Retrieve buffer information. */
635 addr = rte_pktmbuf_mtod(buf, uintptr_t);
636 length = DATA_LEN(buf);
637 /* Update element. */
638 (*txq->elts)[elts_head] = buf;
639 /* Prefetch next buffer data. */
641 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
643 /* Retrieve Memory Region key for this memory pool. */
644 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
645 if (buf->ol_flags & PKT_TX_VLAN_PKT)
646 mlx5_wqe_write_vlan(txq, wqe, addr, length, lkey,
649 mlx5_wqe_write(txq, wqe, addr, length, lkey);
650 /* Should we enable HW CKSUM offload */
652 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
653 wqe->wqe.eseg.cs_flags =
654 MLX5_ETH_WQE_L3_CSUM |
655 MLX5_ETH_WQE_L4_CSUM;
657 wqe->wqe.eseg.cs_flags = 0;
661 * Spill on next WQE when the current one does not have
662 * enough room left. Size of WQE must a be a multiple
663 * of data segment size.
665 assert(!(sizeof(*wqe) % sizeof(*dseg)));
666 if (!(ds % (sizeof(*wqe) / 16)))
667 dseg = (volatile void *)
668 &(*txq->wqes)[txq->wqe_ci++ &
675 /* Store segment information. */
676 dseg->byte_count = htonl(DATA_LEN(buf));
677 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
678 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
679 (*txq->elts)[elts_head_next] = buf;
680 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
681 #ifdef MLX5_PMD_SOFT_COUNTERS
682 length += DATA_LEN(buf);
686 /* Update DS field in WQE. */
687 wqe->wqe.ctrl.data[1] &= htonl(0xffffffc0);
688 wqe->wqe.ctrl.data[1] |= htonl(ds & 0x3f);
689 elts_head = elts_head_next;
690 #ifdef MLX5_PMD_SOFT_COUNTERS
691 /* Increment sent bytes counter. */
692 txq->stats.obytes += length;
694 elts_head = elts_head_next;
697 /* Take a shortcut if nothing must be sent. */
698 if (unlikely(i == 0))
700 /* Check whether completion threshold has been reached. */
701 comp = txq->elts_comp + i + j;
702 if (comp >= MLX5_TX_COMP_THRESH) {
703 /* Request completion on last WQE. */
704 wqe->wqe.ctrl.data[2] = htonl(8);
705 /* Save elts_head in unused "immediate" field of WQE. */
706 wqe->wqe.ctrl.data[3] = elts_head;
709 txq->elts_comp = comp;
711 #ifdef MLX5_PMD_SOFT_COUNTERS
712 /* Increment sent packets counter. */
713 txq->stats.opackets += i;
715 /* Ring QP doorbell. */
717 txq->elts_head = elts_head;
722 * DPDK callback for TX with inline support.
725 * Generic pointer to TX queue structure.
727 * Packets to transmit.
729 * Number of packets in array.
732 * Number of packets successfully transmitted (<= pkts_n).
735 mlx5_tx_burst_inline(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
737 struct txq *txq = (struct txq *)dpdk_txq;
738 uint16_t elts_head = txq->elts_head;
739 const unsigned int elts_n = txq->elts_n;
744 volatile union mlx5_wqe *wqe = NULL;
745 unsigned int max_inline = txq->max_inline;
747 if (unlikely(!pkts_n))
749 /* Prefetch first packet cacheline. */
750 tx_prefetch_cqe(txq, txq->cq_ci);
751 tx_prefetch_cqe(txq, txq->cq_ci + 1);
752 rte_prefetch0(*pkts);
753 /* Start processing. */
755 max = (elts_n - (elts_head - txq->elts_tail));
759 struct rte_mbuf *buf = *(pkts++);
760 unsigned int elts_head_next;
764 unsigned int segs_n = buf->nb_segs;
765 volatile struct mlx5_wqe_data_seg *dseg;
766 unsigned int ds = sizeof(*wqe) / 16;
769 * Make sure there is enough room to store this packet and
770 * that one ring entry remains unused.
773 if (max < segs_n + 1)
777 elts_head_next = (elts_head + 1) & (elts_n - 1);
778 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)];
779 dseg = &wqe->wqe.dseg;
780 tx_prefetch_wqe(txq, txq->wqe_ci);
781 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
783 rte_prefetch0(*pkts);
784 /* Should we enable HW CKSUM offload */
786 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
787 wqe->inl.eseg.cs_flags =
788 MLX5_ETH_WQE_L3_CSUM |
789 MLX5_ETH_WQE_L4_CSUM;
791 wqe->inl.eseg.cs_flags = 0;
793 /* Retrieve buffer information. */
794 addr = rte_pktmbuf_mtod(buf, uintptr_t);
795 length = DATA_LEN(buf);
796 /* Update element. */
797 (*txq->elts)[elts_head] = buf;
798 /* Prefetch next buffer data. */
800 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
802 if ((length <= max_inline) && (segs_n == 1)) {
803 if (buf->ol_flags & PKT_TX_VLAN_PKT)
804 mlx5_wqe_write_inline_vlan(txq, wqe,
808 mlx5_wqe_write_inline(txq, wqe, addr, length);
811 /* Retrieve Memory Region key for this memory pool. */
812 lkey = txq_mp2mr(txq, txq_mb2mp(buf));
813 if (buf->ol_flags & PKT_TX_VLAN_PKT)
814 mlx5_wqe_write_vlan(txq, wqe, addr, length,
815 lkey, buf->vlan_tci);
817 mlx5_wqe_write(txq, wqe, addr, length, lkey);
821 * Spill on next WQE when the current one does not have
822 * enough room left. Size of WQE must a be a multiple
823 * of data segment size.
825 assert(!(sizeof(*wqe) % sizeof(*dseg)));
826 if (!(ds % (sizeof(*wqe) / 16)))
827 dseg = (volatile void *)
828 &(*txq->wqes)[txq->wqe_ci++ &
835 /* Store segment information. */
836 dseg->byte_count = htonl(DATA_LEN(buf));
837 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
838 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
839 (*txq->elts)[elts_head_next] = buf;
840 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
841 #ifdef MLX5_PMD_SOFT_COUNTERS
842 length += DATA_LEN(buf);
846 /* Update DS field in WQE. */
847 wqe->inl.ctrl.data[1] &= htonl(0xffffffc0);
848 wqe->inl.ctrl.data[1] |= htonl(ds & 0x3f);
850 elts_head = elts_head_next;
851 #ifdef MLX5_PMD_SOFT_COUNTERS
852 /* Increment sent bytes counter. */
853 txq->stats.obytes += length;
857 /* Take a shortcut if nothing must be sent. */
858 if (unlikely(i == 0))
860 /* Check whether completion threshold has been reached. */
861 comp = txq->elts_comp + i + j;
862 if (comp >= MLX5_TX_COMP_THRESH) {
863 /* Request completion on last WQE. */
864 wqe->inl.ctrl.data[2] = htonl(8);
865 /* Save elts_head in unused "immediate" field of WQE. */
866 wqe->inl.ctrl.data[3] = elts_head;
869 txq->elts_comp = comp;
871 #ifdef MLX5_PMD_SOFT_COUNTERS
872 /* Increment sent packets counter. */
873 txq->stats.opackets += i;
875 /* Ring QP doorbell. */
877 txq->elts_head = elts_head;
882 * Open a MPW session.
885 * Pointer to TX queue structure.
887 * Pointer to MPW session structure.
892 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
894 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
895 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
896 (volatile struct mlx5_wqe_data_seg (*)[])
897 (uintptr_t)&(*txq->wqes)[(idx + 1) & (txq->wqe_n - 1)];
899 mpw->state = MLX5_MPW_STATE_OPENED;
903 mpw->wqe = &(*txq->wqes)[idx];
904 mpw->wqe->mpw.eseg.mss = htons(length);
905 mpw->wqe->mpw.eseg.inline_hdr_sz = 0;
906 mpw->wqe->mpw.eseg.rsvd0 = 0;
907 mpw->wqe->mpw.eseg.rsvd1 = 0;
908 mpw->wqe->mpw.eseg.rsvd2 = 0;
909 mpw->wqe->mpw.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
911 MLX5_OPCODE_LSO_MPW);
912 mpw->wqe->mpw.ctrl.data[2] = 0;
913 mpw->wqe->mpw.ctrl.data[3] = 0;
914 mpw->data.dseg[0] = &mpw->wqe->mpw.dseg[0];
915 mpw->data.dseg[1] = &mpw->wqe->mpw.dseg[1];
916 mpw->data.dseg[2] = &(*dseg)[0];
917 mpw->data.dseg[3] = &(*dseg)[1];
918 mpw->data.dseg[4] = &(*dseg)[2];
922 * Close a MPW session.
925 * Pointer to TX queue structure.
927 * Pointer to MPW session structure.
930 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
932 unsigned int num = mpw->pkts_n;
935 * Store size in multiple of 16 bytes. Control and Ethernet segments
938 mpw->wqe->mpw.ctrl.data[1] = htonl(txq->qp_num_8s | (2 + num));
939 mpw->state = MLX5_MPW_STATE_CLOSED;
944 tx_prefetch_wqe(txq, txq->wqe_ci);
945 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
949 * DPDK callback for TX with MPW support.
952 * Generic pointer to TX queue structure.
954 * Packets to transmit.
956 * Number of packets in array.
959 * Number of packets successfully transmitted (<= pkts_n).
962 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
964 struct txq *txq = (struct txq *)dpdk_txq;
965 uint16_t elts_head = txq->elts_head;
966 const unsigned int elts_n = txq->elts_n;
971 struct mlx5_mpw mpw = {
972 .state = MLX5_MPW_STATE_CLOSED,
975 if (unlikely(!pkts_n))
977 /* Prefetch first packet cacheline. */
978 tx_prefetch_cqe(txq, txq->cq_ci);
979 tx_prefetch_wqe(txq, txq->wqe_ci);
980 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
981 /* Start processing. */
983 max = (elts_n - (elts_head - txq->elts_tail));
987 struct rte_mbuf *buf = *(pkts++);
988 unsigned int elts_head_next;
990 unsigned int segs_n = buf->nb_segs;
991 uint32_t cs_flags = 0;
994 * Make sure there is enough room to store this packet and
995 * that one ring entry remains unused.
998 if (max < segs_n + 1)
1000 /* Do not bother with large packets MPW cannot handle. */
1001 if (segs_n > MLX5_MPW_DSEG_MAX)
1005 /* Should we enable HW CKSUM offload */
1007 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1008 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1009 /* Retrieve packet information. */
1010 length = PKT_LEN(buf);
1012 /* Start new session if packet differs. */
1013 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
1014 ((mpw.len != length) ||
1016 (mpw.wqe->mpw.eseg.cs_flags != cs_flags)))
1017 mlx5_mpw_close(txq, &mpw);
1018 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1019 mlx5_mpw_new(txq, &mpw, length);
1020 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
1022 /* Multi-segment packets must be alone in their MPW. */
1023 assert((segs_n == 1) || (mpw.pkts_n == 0));
1024 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1028 volatile struct mlx5_wqe_data_seg *dseg;
1031 elts_head_next = (elts_head + 1) & (elts_n - 1);
1033 (*txq->elts)[elts_head] = buf;
1034 dseg = mpw.data.dseg[mpw.pkts_n];
1035 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1036 *dseg = (struct mlx5_wqe_data_seg){
1037 .byte_count = htonl(DATA_LEN(buf)),
1038 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1039 .addr = htonll(addr),
1041 elts_head = elts_head_next;
1042 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1043 length += DATA_LEN(buf);
1049 assert(length == mpw.len);
1050 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1051 mlx5_mpw_close(txq, &mpw);
1052 elts_head = elts_head_next;
1053 #ifdef MLX5_PMD_SOFT_COUNTERS
1054 /* Increment sent bytes counter. */
1055 txq->stats.obytes += length;
1059 /* Take a shortcut if nothing must be sent. */
1060 if (unlikely(i == 0))
1062 /* Check whether completion threshold has been reached. */
1063 /* "j" includes both packets and segments. */
1064 comp = txq->elts_comp + j;
1065 if (comp >= MLX5_TX_COMP_THRESH) {
1066 volatile union mlx5_wqe *wqe = mpw.wqe;
1068 /* Request completion on last WQE. */
1069 wqe->mpw.ctrl.data[2] = htonl(8);
1070 /* Save elts_head in unused "immediate" field of WQE. */
1071 wqe->mpw.ctrl.data[3] = elts_head;
1074 txq->elts_comp = comp;
1076 #ifdef MLX5_PMD_SOFT_COUNTERS
1077 /* Increment sent packets counter. */
1078 txq->stats.opackets += i;
1080 /* Ring QP doorbell. */
1081 if (mpw.state == MLX5_MPW_STATE_OPENED)
1082 mlx5_mpw_close(txq, &mpw);
1084 txq->elts_head = elts_head;
1089 * Open a MPW inline session.
1092 * Pointer to TX queue structure.
1094 * Pointer to MPW session structure.
1099 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
1101 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
1103 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1107 mpw->wqe = &(*txq->wqes)[idx];
1108 mpw->wqe->mpw_inl.ctrl.data[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
1109 (txq->wqe_ci << 8) |
1110 MLX5_OPCODE_LSO_MPW);
1111 mpw->wqe->mpw_inl.ctrl.data[2] = 0;
1112 mpw->wqe->mpw_inl.ctrl.data[3] = 0;
1113 mpw->wqe->mpw_inl.eseg.mss = htons(length);
1114 mpw->wqe->mpw_inl.eseg.inline_hdr_sz = 0;
1115 mpw->wqe->mpw_inl.eseg.cs_flags = 0;
1116 mpw->wqe->mpw_inl.eseg.rsvd0 = 0;
1117 mpw->wqe->mpw_inl.eseg.rsvd1 = 0;
1118 mpw->wqe->mpw_inl.eseg.rsvd2 = 0;
1119 mpw->data.raw = &mpw->wqe->mpw_inl.data[0];
1123 * Close a MPW inline session.
1126 * Pointer to TX queue structure.
1128 * Pointer to MPW session structure.
1131 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
1135 size = sizeof(*mpw->wqe) - MLX5_MWQE64_INL_DATA + mpw->total_len;
1137 * Store size in multiple of 16 bytes. Control and Ethernet segments
1140 mpw->wqe->mpw_inl.ctrl.data[1] =
1141 htonl(txq->qp_num_8s | ((size + 15) / 16));
1142 mpw->state = MLX5_MPW_STATE_CLOSED;
1143 mpw->wqe->mpw_inl.byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
1144 txq->wqe_ci += (size + (sizeof(*mpw->wqe) - 1)) / sizeof(*mpw->wqe);
1148 * DPDK callback for TX with MPW inline support.
1151 * Generic pointer to TX queue structure.
1153 * Packets to transmit.
1155 * Number of packets in array.
1158 * Number of packets successfully transmitted (<= pkts_n).
1161 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1164 struct txq *txq = (struct txq *)dpdk_txq;
1165 uint16_t elts_head = txq->elts_head;
1166 const unsigned int elts_n = txq->elts_n;
1171 unsigned int inline_room = txq->max_inline;
1172 struct mlx5_mpw mpw = {
1173 .state = MLX5_MPW_STATE_CLOSED,
1176 if (unlikely(!pkts_n))
1178 /* Prefetch first packet cacheline. */
1179 tx_prefetch_cqe(txq, txq->cq_ci);
1180 tx_prefetch_wqe(txq, txq->wqe_ci);
1181 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
1182 /* Start processing. */
1184 max = (elts_n - (elts_head - txq->elts_tail));
1188 struct rte_mbuf *buf = *(pkts++);
1189 unsigned int elts_head_next;
1192 unsigned int segs_n = buf->nb_segs;
1193 uint32_t cs_flags = 0;
1196 * Make sure there is enough room to store this packet and
1197 * that one ring entry remains unused.
1200 if (max < segs_n + 1)
1202 /* Do not bother with large packets MPW cannot handle. */
1203 if (segs_n > MLX5_MPW_DSEG_MAX)
1207 /* Should we enable HW CKSUM offload */
1209 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1210 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1211 /* Retrieve packet information. */
1212 length = PKT_LEN(buf);
1213 /* Start new session if packet differs. */
1214 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1215 if ((mpw.len != length) ||
1217 (mpw.wqe->mpw.eseg.cs_flags != cs_flags))
1218 mlx5_mpw_close(txq, &mpw);
1219 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1220 if ((mpw.len != length) ||
1222 (length > inline_room) ||
1223 (mpw.wqe->mpw_inl.eseg.cs_flags != cs_flags)) {
1224 mlx5_mpw_inline_close(txq, &mpw);
1225 inline_room = txq->max_inline;
1228 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1229 if ((segs_n != 1) ||
1230 (length > inline_room)) {
1231 mlx5_mpw_new(txq, &mpw, length);
1232 mpw.wqe->mpw.eseg.cs_flags = cs_flags;
1234 mlx5_mpw_inline_new(txq, &mpw, length);
1235 mpw.wqe->mpw_inl.eseg.cs_flags = cs_flags;
1238 /* Multi-segment packets must be alone in their MPW. */
1239 assert((segs_n == 1) || (mpw.pkts_n == 0));
1240 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1241 assert(inline_room == txq->max_inline);
1242 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1246 volatile struct mlx5_wqe_data_seg *dseg;
1249 (elts_head + 1) & (elts_n - 1);
1251 (*txq->elts)[elts_head] = buf;
1252 dseg = mpw.data.dseg[mpw.pkts_n];
1253 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1254 *dseg = (struct mlx5_wqe_data_seg){
1255 .byte_count = htonl(DATA_LEN(buf)),
1256 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
1257 .addr = htonll(addr),
1259 elts_head = elts_head_next;
1260 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1261 length += DATA_LEN(buf);
1267 assert(length == mpw.len);
1268 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1269 mlx5_mpw_close(txq, &mpw);
1273 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1274 assert(length <= inline_room);
1275 assert(length == DATA_LEN(buf));
1276 elts_head_next = (elts_head + 1) & (elts_n - 1);
1277 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1278 (*txq->elts)[elts_head] = buf;
1279 /* Maximum number of bytes before wrapping. */
1280 max = ((uintptr_t)&(*txq->wqes)[txq->wqe_n] -
1281 (uintptr_t)mpw.data.raw);
1283 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1287 (volatile void *)&(*txq->wqes)[0];
1288 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1289 (void *)(addr + max),
1291 mpw.data.raw += length - max;
1293 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1296 mpw.data.raw += length;
1298 if ((uintptr_t)mpw.data.raw ==
1299 (uintptr_t)&(*txq->wqes)[txq->wqe_n])
1301 (volatile void *)&(*txq->wqes)[0];
1304 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1305 mlx5_mpw_inline_close(txq, &mpw);
1306 inline_room = txq->max_inline;
1308 inline_room -= length;
1311 mpw.total_len += length;
1312 elts_head = elts_head_next;
1313 #ifdef MLX5_PMD_SOFT_COUNTERS
1314 /* Increment sent bytes counter. */
1315 txq->stats.obytes += length;
1319 /* Take a shortcut if nothing must be sent. */
1320 if (unlikely(i == 0))
1322 /* Check whether completion threshold has been reached. */
1323 /* "j" includes both packets and segments. */
1324 comp = txq->elts_comp + j;
1325 if (comp >= MLX5_TX_COMP_THRESH) {
1326 volatile union mlx5_wqe *wqe = mpw.wqe;
1328 /* Request completion on last WQE. */
1329 wqe->mpw_inl.ctrl.data[2] = htonl(8);
1330 /* Save elts_head in unused "immediate" field of WQE. */
1331 wqe->mpw_inl.ctrl.data[3] = elts_head;
1334 txq->elts_comp = comp;
1336 #ifdef MLX5_PMD_SOFT_COUNTERS
1337 /* Increment sent packets counter. */
1338 txq->stats.opackets += i;
1340 /* Ring QP doorbell. */
1341 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1342 mlx5_mpw_inline_close(txq, &mpw);
1343 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1344 mlx5_mpw_close(txq, &mpw);
1346 txq->elts_head = elts_head;
1351 * Translate RX completion flags to packet type.
1356 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1359 * Packet type for struct rte_mbuf.
1361 static inline uint32_t
1362 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
1365 uint8_t flags = cqe->l4_hdr_type_etc;
1366 uint8_t info = cqe->rsvd0[0];
1368 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
1371 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
1372 RTE_PTYPE_L3_IPV4) |
1374 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
1375 RTE_PTYPE_L3_IPV6) |
1377 IBV_EXP_CQ_RX_IPV4_PACKET,
1378 RTE_PTYPE_INNER_L3_IPV4) |
1380 IBV_EXP_CQ_RX_IPV6_PACKET,
1381 RTE_PTYPE_INNER_L3_IPV6);
1385 MLX5_CQE_L3_HDR_TYPE_IPV6,
1386 RTE_PTYPE_L3_IPV6) |
1388 MLX5_CQE_L3_HDR_TYPE_IPV4,
1394 * Get size of the next packet for a given CQE. For compressed CQEs, the
1395 * consumer index is updated only once all packets of the current one have
1399 * Pointer to RX queue.
1404 * Packet size in bytes (0 if there is none), -1 in case of completion
1408 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
1411 struct rxq_zip *zip = &rxq->zip;
1412 uint16_t cqe_n = cqe_cnt + 1;
1415 /* Process compressed data in the CQE and mini arrays. */
1417 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1418 (volatile struct mlx5_mini_cqe8 (*)[8])
1419 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
1421 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1422 if ((++zip->ai & 7) == 0) {
1424 * Increment consumer index to skip the number of
1425 * CQEs consumed. Hardware leaves holes in the CQ
1426 * ring for software use.
1431 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1432 uint16_t idx = rxq->cq_ci;
1433 uint16_t end = zip->cq_ci;
1435 while (idx != end) {
1436 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
1437 MLX5_CQE_INVALIDATE;
1440 rxq->cq_ci = zip->cq_ci;
1443 /* No compressed data, get next CQE and verify if it is compressed. */
1448 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
1449 if (unlikely(ret == 1))
1452 op_own = cqe->op_own;
1453 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1454 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1455 (volatile struct mlx5_mini_cqe8 (*)[8])
1456 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1459 /* Fix endianness. */
1460 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1462 * Current mini array position is the one returned by
1465 * If completion comprises several mini arrays, as a
1466 * special case the second one is located 7 CQEs after
1467 * the initial CQE instead of 8 for subsequent ones.
1469 zip->ca = rxq->cq_ci & cqe_cnt;
1470 zip->na = zip->ca + 7;
1471 /* Compute the next non compressed CQE. */
1473 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1474 /* Get packet size to return. */
1475 len = ntohl((*mc)[0].byte_cnt);
1478 len = ntohl(cqe->byte_cnt);
1480 /* Error while receiving packet. */
1481 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1488 * Translate RX completion flags to offload flags.
1491 * Pointer to RX queue structure.
1496 * Offload flags (ol_flags) for struct rte_mbuf.
1498 static inline uint32_t
1499 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
1501 uint32_t ol_flags = 0;
1502 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1503 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1504 uint8_t info = cqe->rsvd0[0];
1506 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1507 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1509 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
1510 PKT_RX_IP_CKSUM_BAD);
1511 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1512 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1513 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1514 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1516 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
1517 PKT_RX_L4_CKSUM_BAD);
1519 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
1520 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
1523 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1525 TRANSPOSE(~cqe->l4_hdr_type_etc,
1526 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
1527 PKT_RX_IP_CKSUM_BAD) |
1528 TRANSPOSE(~cqe->l4_hdr_type_etc,
1529 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
1530 PKT_RX_L4_CKSUM_BAD);
1535 * DPDK callback for RX.
1538 * Generic pointer to RX queue structure.
1540 * Array to store received packets.
1542 * Maximum number of packets in array.
1545 * Number of packets successfully received (<= pkts_n).
1548 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1550 struct rxq *rxq = dpdk_rxq;
1551 unsigned int pkts_ret = 0;
1553 unsigned int rq_ci = rxq->rq_ci;
1554 const unsigned int elts_n = rxq->elts_n;
1555 const unsigned int wqe_cnt = elts_n - 1;
1556 const unsigned int cqe_cnt = rxq->cqe_n - 1;
1558 for (i = 0; (i != pkts_n); ++i) {
1559 unsigned int idx = rq_ci & wqe_cnt;
1561 struct rte_mbuf *rep;
1562 struct rte_mbuf *pkt;
1563 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1564 volatile struct mlx5_cqe64 *cqe =
1565 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1567 pkt = (*rxq->elts)[idx];
1569 rep = rte_mbuf_raw_alloc(rxq->mp);
1570 if (unlikely(rep == NULL)) {
1571 ++rxq->stats.rx_nombuf;
1574 SET_DATA_OFF(rep, RTE_PKTMBUF_HEADROOM);
1576 PORT(rep) = rxq->port_id;
1578 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1579 if (unlikely(len == 0)) {
1580 rte_mbuf_refcnt_set(rep, 0);
1581 __rte_mbuf_raw_free(rep);
1584 if (unlikely(len == -1)) {
1585 /* RX error, packet is likely too large. */
1586 rte_mbuf_refcnt_set(rep, 0);
1587 __rte_mbuf_raw_free(rep);
1588 ++rxq->stats.idropped;
1593 * Fill NIC descriptor with the new buffer. The lkey and size
1594 * of the buffers are already known, only the buffer address
1597 wqe->addr = htonll((uintptr_t)rep->buf_addr +
1598 RTE_PKTMBUF_HEADROOM);
1599 (*rxq->elts)[idx] = rep;
1600 /* Update pkt information. */
1601 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1604 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1605 pkt->ol_flags = rxq_cq_to_ol_flags(rxq, cqe);
1607 if (cqe->l4_hdr_type_etc & MLX5_CQE_VLAN_STRIPPED) {
1608 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1609 PKT_RX_VLAN_STRIPPED;
1610 pkt->vlan_tci = ntohs(cqe->vlan_info);
1612 if (rxq->crc_present)
1613 len -= ETHER_CRC_LEN;
1616 DATA_LEN(pkt) = len;
1617 #ifdef MLX5_PMD_SOFT_COUNTERS
1618 /* Increment bytes counter. */
1619 rxq->stats.ibytes += len;
1621 /* Return packet. */
1627 if (unlikely((i == 0) && (rq_ci == rxq->rq_ci)))
1631 DEBUG("%p: reposting %u WRs", (void *)rxq, i);
1633 /* Update the consumer index. */
1636 *rxq->cq_db = htonl(rxq->cq_ci);
1638 *rxq->rq_db = htonl(rxq->rq_ci);
1639 #ifdef MLX5_PMD_SOFT_COUNTERS
1640 /* Increment packets counter. */
1641 rxq->stats.ipackets += pkts_ret;
1647 * Dummy DPDK callback for TX.
1649 * This function is used to temporarily replace the real callback during
1650 * unsafe control operations on the queue, or in case of error.
1653 * Generic pointer to TX queue structure.
1655 * Packets to transmit.
1657 * Number of packets in array.
1660 * Number of packets successfully transmitted (<= pkts_n).
1663 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1672 * Dummy DPDK callback for RX.
1674 * This function is used to temporarily replace the real callback during
1675 * unsafe control operations on the queue, or in case of error.
1678 * Generic pointer to RX queue structure.
1680 * Array to store received packets.
1682 * Maximum number of packets in array.
1685 * Number of packets successfully received (<= pkts_n).
1688 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)