1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, uint32_t *rss_hash);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
46 static __rte_always_inline void
47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
48 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
50 static __rte_always_inline void
51 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx);
53 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
54 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
57 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
58 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
61 * Build a table to translate Rx completion flags to packet type.
63 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
66 mlx5_set_ptype_table(void)
69 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
71 /* Last entry must not be overwritten, reserved for errored packet. */
72 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
73 (*p)[i] = RTE_PTYPE_UNKNOWN;
75 * The index to the array should have:
76 * bit[1:0] = l3_hdr_type
77 * bit[4:2] = l4_hdr_type
80 * bit[7] = outer_l3_type
83 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
85 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
90 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
92 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
95 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
97 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
99 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
101 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
103 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
105 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
108 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
112 /* Repeat with outer_l3_type being set. Just in case. */
113 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 RTE_PTYPE_L4_NONFRAG;
115 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
116 RTE_PTYPE_L4_NONFRAG;
117 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
119 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
121 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
127 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
131 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
133 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
138 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L4_NONFRAG;
145 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
190 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L4_TCP;
193 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L4_TCP;
196 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_TCP;
199 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_TCP;
203 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_UDP;
206 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_UDP;
209 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_UDP;
212 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L4_UDP;
218 * Build a table to translate packet to checksum type of Verbs.
221 mlx5_set_cksum_table(void)
227 * The index should have:
228 * bit[0] = PKT_TX_TCP_SEG
229 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
230 * bit[4] = PKT_TX_IP_CKSUM
231 * bit[8] = PKT_TX_OUTER_IP_CKSUM
234 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
237 /* Tunneled packet. */
238 if (i & (1 << 8)) /* Outer IP. */
239 v |= MLX5_ETH_WQE_L3_CSUM;
240 if (i & (1 << 4)) /* Inner IP. */
241 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
242 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
243 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
246 if (i & (1 << 4)) /* IP. */
247 v |= MLX5_ETH_WQE_L3_CSUM;
248 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
249 v |= MLX5_ETH_WQE_L4_CSUM;
251 mlx5_cksum_table[i] = v;
256 * Build a table to translate packet type of mbuf to SWP type of Verbs.
259 mlx5_set_swp_types_table(void)
265 * The index should have:
266 * bit[0:1] = PKT_TX_L4_MASK
267 * bit[4] = PKT_TX_IPV6
268 * bit[8] = PKT_TX_OUTER_IPV6
269 * bit[9] = PKT_TX_OUTER_UDP
271 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
274 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
276 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
278 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
279 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
280 v |= MLX5_ETH_WQE_L4_INNER_UDP;
281 mlx5_swp_types_table[i] = v;
286 * Return the size of tailroom of WQ.
289 * Pointer to TX queue structure.
291 * Pointer to tail of WQ.
297 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
300 tailroom = (uintptr_t)(txq->wqes) +
301 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
307 * Copy data to tailroom of circular queue.
310 * Pointer to destination.
314 * Number of bytes to copy.
316 * Pointer to head of queue.
318 * Size of tailroom from dst.
321 * Pointer after copied data.
324 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
325 void *base, size_t tailroom)
330 rte_memcpy(dst, src, tailroom);
331 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
333 ret = (uint8_t *)base + n - tailroom;
335 rte_memcpy(dst, src, n);
336 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
342 * Inline TSO headers into WQE.
345 * 0 on success, negative errno value on failure.
348 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
351 uint16_t *pkt_inline_sz,
355 uint16_t *tso_header_sz)
357 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
358 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
360 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
361 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
365 *tso_segsz = buf->tso_segsz;
366 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
367 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
368 txq->stats.oerrors++;
372 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
373 /* First seg must contain all TSO headers. */
374 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
375 *tso_header_sz > DATA_LEN(buf)) {
376 txq->stats.oerrors++;
379 copy_b = *tso_header_sz - *pkt_inline_sz;
380 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
382 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
383 if (unlikely(*max_wqe < n_wqe))
386 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
389 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
390 *pkt_inline_sz += copy_b;
396 * DPDK callback to check the status of a tx descriptor.
401 * The index of the descriptor in the ring.
404 * The status of the tx descriptor.
407 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
409 struct mlx5_txq_data *txq = tx_queue;
412 mlx5_tx_complete(txq);
413 used = txq->elts_head - txq->elts_tail;
415 return RTE_ETH_TX_DESC_FULL;
416 return RTE_ETH_TX_DESC_DONE;
420 * DPDK callback to check the status of a rx descriptor.
425 * The index of the descriptor in the ring.
428 * The status of the tx descriptor.
431 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
433 struct mlx5_rxq_data *rxq = rx_queue;
434 struct rxq_zip *zip = &rxq->zip;
435 volatile struct mlx5_cqe *cqe;
436 const unsigned int cqe_n = (1 << rxq->cqe_n);
437 const unsigned int cqe_cnt = cqe_n - 1;
441 /* if we are processing a compressed cqe */
443 used = zip->cqe_cnt - zip->ca;
449 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
450 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
454 op_own = cqe->op_own;
455 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
456 n = rte_be_to_cpu_32(cqe->byte_cnt);
461 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
463 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
465 return RTE_ETH_RX_DESC_DONE;
466 return RTE_ETH_RX_DESC_AVAIL;
470 * DPDK callback for TX.
473 * Generic pointer to TX queue structure.
475 * Packets to transmit.
477 * Number of packets in array.
480 * Number of packets successfully transmitted (<= pkts_n).
483 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
485 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
486 uint16_t elts_head = txq->elts_head;
487 const uint16_t elts_n = 1 << txq->elts_n;
488 const uint16_t elts_m = elts_n - 1;
495 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
496 unsigned int segs_n = 0;
497 const unsigned int max_inline = txq->max_inline;
499 if (unlikely(!pkts_n))
501 /* Prefetch first packet cacheline. */
502 rte_prefetch0(*pkts);
503 /* Start processing. */
504 mlx5_tx_complete(txq);
505 max_elts = (elts_n - (elts_head - txq->elts_tail));
506 /* A CQE slot must always be available. */
507 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
508 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
509 if (unlikely(!max_wqe))
512 struct rte_mbuf *buf = *pkts; /* First_seg. */
514 volatile struct mlx5_wqe_v *wqe = NULL;
515 volatile rte_v128u32_t *dseg = NULL;
518 unsigned int sg = 0; /* counter of additional segs attached. */
520 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
521 uint16_t tso_header_sz = 0;
524 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
525 uint8_t is_vlan = !!(buf->ol_flags & PKT_TX_VLAN_PKT);
526 uint32_t swp_offsets = 0;
527 uint8_t swp_types = 0;
528 uint16_t tso_segsz = 0;
529 #ifdef MLX5_PMD_SOFT_COUNTERS
530 uint32_t total_length = 0;
534 segs_n = buf->nb_segs;
536 * Make sure there is enough room to store this packet and
537 * that one ring entry remains unused.
540 if (max_elts < segs_n)
544 if (unlikely(--max_wqe == 0))
546 wqe = (volatile struct mlx5_wqe_v *)
547 tx_mlx5_wqe(txq, txq->wqe_ci);
548 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
550 rte_prefetch0(*(pkts + 1));
551 addr = rte_pktmbuf_mtod(buf, uintptr_t);
552 length = DATA_LEN(buf);
553 ehdr = (((uint8_t *)addr)[1] << 8) |
554 ((uint8_t *)addr)[0];
555 #ifdef MLX5_PMD_SOFT_COUNTERS
556 total_length = length;
558 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
559 txq->stats.oerrors++;
562 /* Update element. */
563 (*txq->elts)[elts_head & elts_m] = buf;
564 /* Prefetch next buffer data. */
567 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
568 cs_flags = txq_ol_cksum_to_cs(buf);
569 txq_mbuf_to_swp(txq, buf, tso, is_vlan,
570 (uint8_t *)&swp_offsets, &swp_types);
571 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
572 /* Replace the Ethernet type by the VLAN if necessary. */
574 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
576 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
580 /* Copy Destination and source mac address. */
581 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
583 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
584 /* Copy missing two bytes to end the DSeg. */
585 memcpy((uint8_t *)raw + len + sizeof(vlan),
586 ((uint8_t *)addr) + len, 2);
590 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
591 MLX5_WQE_DWORD_SIZE);
592 length -= pkt_inline_sz;
593 addr += pkt_inline_sz;
595 raw += MLX5_WQE_DWORD_SIZE;
597 ret = inline_tso(txq, buf, &length,
598 &addr, &pkt_inline_sz,
600 &tso_segsz, &tso_header_sz);
601 if (ret == -EINVAL) {
603 } else if (ret == -EAGAIN) {
605 wqe->ctrl = (rte_v128u32_t){
606 rte_cpu_to_be_32(txq->wqe_ci << 8),
607 rte_cpu_to_be_32(txq->qp_num_8s | 1),
612 #ifdef MLX5_PMD_SOFT_COUNTERS
619 /* Inline if enough room. */
620 if (max_inline || tso) {
622 uintptr_t end = (uintptr_t)
623 (((uintptr_t)txq->wqes) +
624 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
625 unsigned int inline_room = max_inline *
626 RTE_CACHE_LINE_SIZE -
627 (pkt_inline_sz - 2) -
633 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
634 RTE_CACHE_LINE_SIZE);
635 copy_b = (addr_end > addr) ?
636 RTE_MIN((addr_end - addr), length) : 0;
637 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
639 * One Dseg remains in the current WQE. To
640 * keep the computation positive, it is
641 * removed after the bytes to Dseg conversion.
643 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
645 if (unlikely(max_wqe < n))
650 inl = rte_cpu_to_be_32(copy_b |
652 rte_memcpy((void *)raw,
653 (void *)&inl, sizeof(inl));
655 pkt_inline_sz += sizeof(inl);
657 rte_memcpy((void *)raw, (void *)addr, copy_b);
660 pkt_inline_sz += copy_b;
663 * 2 DWORDs consumed by the WQE header + ETH segment +
664 * the size of the inline part of the packet.
666 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
668 if (ds % (MLX5_WQE_SIZE /
669 MLX5_WQE_DWORD_SIZE) == 0) {
670 if (unlikely(--max_wqe == 0))
672 dseg = (volatile rte_v128u32_t *)
673 tx_mlx5_wqe(txq, txq->wqe_ci +
676 dseg = (volatile rte_v128u32_t *)
678 (ds * MLX5_WQE_DWORD_SIZE));
681 } else if (!segs_n) {
685 * Further inline the next segment only for
690 inline_room -= copy_b;
694 /* Move to the next segment. */
698 addr = rte_pktmbuf_mtod(buf, uintptr_t);
699 length = DATA_LEN(buf);
700 #ifdef MLX5_PMD_SOFT_COUNTERS
701 total_length += length;
703 (*txq->elts)[++elts_head & elts_m] = buf;
708 * No inline has been done in the packet, only the
709 * Ethernet Header as been stored.
711 dseg = (volatile rte_v128u32_t *)
712 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
715 /* Add the remaining packet as a simple ds. */
716 addr = rte_cpu_to_be_64(addr);
717 *dseg = (rte_v128u32_t){
718 rte_cpu_to_be_32(length),
719 mlx5_tx_mb2mr(txq, buf),
732 * Spill on next WQE when the current one does not have
733 * enough room left. Size of WQE must a be a multiple
734 * of data segment size.
736 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
737 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
738 if (unlikely(--max_wqe == 0))
740 dseg = (volatile rte_v128u32_t *)
741 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
742 rte_prefetch0(tx_mlx5_wqe(txq,
743 txq->wqe_ci + ds / 4 + 1));
750 length = DATA_LEN(buf);
751 #ifdef MLX5_PMD_SOFT_COUNTERS
752 total_length += length;
754 /* Store segment information. */
755 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
756 *dseg = (rte_v128u32_t){
757 rte_cpu_to_be_32(length),
758 mlx5_tx_mb2mr(txq, buf),
762 (*txq->elts)[++elts_head & elts_m] = buf;
766 if (ds > MLX5_DSEG_MAX) {
767 txq->stats.oerrors++;
774 /* Initialize known and common part of the WQE structure. */
776 wqe->ctrl = (rte_v128u32_t){
777 rte_cpu_to_be_32((txq->wqe_ci << 8) |
779 rte_cpu_to_be_32(txq->qp_num_8s | ds),
783 wqe->eseg = (rte_v128u32_t){
785 cs_flags | (swp_types << 8) |
786 (rte_cpu_to_be_16(tso_segsz) << 16),
788 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
791 wqe->ctrl = (rte_v128u32_t){
792 rte_cpu_to_be_32((txq->wqe_ci << 8) |
794 rte_cpu_to_be_32(txq->qp_num_8s | ds),
798 wqe->eseg = (rte_v128u32_t){
800 cs_flags | (swp_types << 8),
802 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
806 txq->wqe_ci += (ds + 3) / 4;
807 /* Save the last successful WQE for completion request */
808 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
809 #ifdef MLX5_PMD_SOFT_COUNTERS
810 /* Increment sent bytes counter. */
811 txq->stats.obytes += total_length;
813 } while (i < pkts_n);
814 /* Take a shortcut if nothing must be sent. */
815 if (unlikely((i + k) == 0))
817 txq->elts_head += (i + j);
818 /* Check whether completion threshold has been reached. */
819 comp = txq->elts_comp + i + j + k;
820 if (comp >= MLX5_TX_COMP_THRESH) {
821 /* Request completion on last WQE. */
822 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
823 /* Save elts_head in unused "immediate" field of WQE. */
824 last_wqe->ctrl3 = txq->elts_head;
830 txq->elts_comp = comp;
832 #ifdef MLX5_PMD_SOFT_COUNTERS
833 /* Increment sent packets counter. */
834 txq->stats.opackets += i;
836 /* Ring QP doorbell. */
837 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
842 * Open a MPW session.
845 * Pointer to TX queue structure.
847 * Pointer to MPW session structure.
852 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
854 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
855 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
856 (volatile struct mlx5_wqe_data_seg (*)[])
857 tx_mlx5_wqe(txq, idx + 1);
859 mpw->state = MLX5_MPW_STATE_OPENED;
863 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
864 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
865 mpw->wqe->eseg.inline_hdr_sz = 0;
866 mpw->wqe->eseg.rsvd0 = 0;
867 mpw->wqe->eseg.rsvd1 = 0;
868 mpw->wqe->eseg.rsvd2 = 0;
869 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
872 mpw->wqe->ctrl[2] = 0;
873 mpw->wqe->ctrl[3] = 0;
874 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
875 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
876 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
877 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
878 mpw->data.dseg[2] = &(*dseg)[0];
879 mpw->data.dseg[3] = &(*dseg)[1];
880 mpw->data.dseg[4] = &(*dseg)[2];
884 * Close a MPW session.
887 * Pointer to TX queue structure.
889 * Pointer to MPW session structure.
892 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
894 unsigned int num = mpw->pkts_n;
897 * Store size in multiple of 16 bytes. Control and Ethernet segments
900 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
901 mpw->state = MLX5_MPW_STATE_CLOSED;
906 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
907 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
911 * DPDK callback for TX with MPW support.
914 * Generic pointer to TX queue structure.
916 * Packets to transmit.
918 * Number of packets in array.
921 * Number of packets successfully transmitted (<= pkts_n).
924 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
926 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
927 uint16_t elts_head = txq->elts_head;
928 const uint16_t elts_n = 1 << txq->elts_n;
929 const uint16_t elts_m = elts_n - 1;
935 struct mlx5_mpw mpw = {
936 .state = MLX5_MPW_STATE_CLOSED,
939 if (unlikely(!pkts_n))
941 /* Prefetch first packet cacheline. */
942 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
943 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
944 /* Start processing. */
945 mlx5_tx_complete(txq);
946 max_elts = (elts_n - (elts_head - txq->elts_tail));
947 /* A CQE slot must always be available. */
948 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
949 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
950 if (unlikely(!max_wqe))
953 struct rte_mbuf *buf = *(pkts++);
955 unsigned int segs_n = buf->nb_segs;
959 * Make sure there is enough room to store this packet and
960 * that one ring entry remains unused.
963 if (max_elts < segs_n)
965 /* Do not bother with large packets MPW cannot handle. */
966 if (segs_n > MLX5_MPW_DSEG_MAX) {
967 txq->stats.oerrors++;
972 cs_flags = txq_ol_cksum_to_cs(buf);
973 /* Retrieve packet information. */
974 length = PKT_LEN(buf);
976 /* Start new session if packet differs. */
977 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
978 ((mpw.len != length) ||
980 (mpw.wqe->eseg.cs_flags != cs_flags)))
981 mlx5_mpw_close(txq, &mpw);
982 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
984 * Multi-Packet WQE consumes at most two WQE.
985 * mlx5_mpw_new() expects to be able to use such
988 if (unlikely(max_wqe < 2))
991 mlx5_mpw_new(txq, &mpw, length);
992 mpw.wqe->eseg.cs_flags = cs_flags;
994 /* Multi-segment packets must be alone in their MPW. */
995 assert((segs_n == 1) || (mpw.pkts_n == 0));
996 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1000 volatile struct mlx5_wqe_data_seg *dseg;
1004 (*txq->elts)[elts_head++ & elts_m] = buf;
1005 dseg = mpw.data.dseg[mpw.pkts_n];
1006 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1007 *dseg = (struct mlx5_wqe_data_seg){
1008 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
1009 .lkey = mlx5_tx_mb2mr(txq, buf),
1010 .addr = rte_cpu_to_be_64(addr),
1012 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1013 length += DATA_LEN(buf);
1019 assert(length == mpw.len);
1020 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1021 mlx5_mpw_close(txq, &mpw);
1022 #ifdef MLX5_PMD_SOFT_COUNTERS
1023 /* Increment sent bytes counter. */
1024 txq->stats.obytes += length;
1028 /* Take a shortcut if nothing must be sent. */
1029 if (unlikely(i == 0))
1031 /* Check whether completion threshold has been reached. */
1032 /* "j" includes both packets and segments. */
1033 comp = txq->elts_comp + j;
1034 if (comp >= MLX5_TX_COMP_THRESH) {
1035 volatile struct mlx5_wqe *wqe = mpw.wqe;
1037 /* Request completion on last WQE. */
1038 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1039 /* Save elts_head in unused "immediate" field of WQE. */
1040 wqe->ctrl[3] = elts_head;
1046 txq->elts_comp = comp;
1048 #ifdef MLX5_PMD_SOFT_COUNTERS
1049 /* Increment sent packets counter. */
1050 txq->stats.opackets += i;
1052 /* Ring QP doorbell. */
1053 if (mpw.state == MLX5_MPW_STATE_OPENED)
1054 mlx5_mpw_close(txq, &mpw);
1055 mlx5_tx_dbrec(txq, mpw.wqe);
1056 txq->elts_head = elts_head;
1061 * Open a MPW inline session.
1064 * Pointer to TX queue structure.
1066 * Pointer to MPW session structure.
1071 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1074 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1075 struct mlx5_wqe_inl_small *inl;
1077 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1081 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1082 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1083 (txq->wqe_ci << 8) |
1085 mpw->wqe->ctrl[2] = 0;
1086 mpw->wqe->ctrl[3] = 0;
1087 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1088 mpw->wqe->eseg.inline_hdr_sz = 0;
1089 mpw->wqe->eseg.cs_flags = 0;
1090 mpw->wqe->eseg.rsvd0 = 0;
1091 mpw->wqe->eseg.rsvd1 = 0;
1092 mpw->wqe->eseg.rsvd2 = 0;
1093 inl = (struct mlx5_wqe_inl_small *)
1094 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1095 mpw->data.raw = (uint8_t *)&inl->raw;
1099 * Close a MPW inline session.
1102 * Pointer to TX queue structure.
1104 * Pointer to MPW session structure.
1107 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1110 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1111 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1113 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1115 * Store size in multiple of 16 bytes. Control and Ethernet segments
1118 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1120 mpw->state = MLX5_MPW_STATE_CLOSED;
1121 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1122 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1126 * DPDK callback for TX with MPW inline support.
1129 * Generic pointer to TX queue structure.
1131 * Packets to transmit.
1133 * Number of packets in array.
1136 * Number of packets successfully transmitted (<= pkts_n).
1139 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1142 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1143 uint16_t elts_head = txq->elts_head;
1144 const uint16_t elts_n = 1 << txq->elts_n;
1145 const uint16_t elts_m = elts_n - 1;
1151 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1152 struct mlx5_mpw mpw = {
1153 .state = MLX5_MPW_STATE_CLOSED,
1156 * Compute the maximum number of WQE which can be consumed by inline
1159 * - 1 control segment,
1160 * - 1 Ethernet segment,
1161 * - N Dseg from the inline request.
1163 const unsigned int wqe_inl_n =
1164 ((2 * MLX5_WQE_DWORD_SIZE +
1165 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1166 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1168 if (unlikely(!pkts_n))
1170 /* Prefetch first packet cacheline. */
1171 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1172 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1173 /* Start processing. */
1174 mlx5_tx_complete(txq);
1175 max_elts = (elts_n - (elts_head - txq->elts_tail));
1176 /* A CQE slot must always be available. */
1177 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1179 struct rte_mbuf *buf = *(pkts++);
1182 unsigned int segs_n = buf->nb_segs;
1186 * Make sure there is enough room to store this packet and
1187 * that one ring entry remains unused.
1190 if (max_elts < segs_n)
1192 /* Do not bother with large packets MPW cannot handle. */
1193 if (segs_n > MLX5_MPW_DSEG_MAX) {
1194 txq->stats.oerrors++;
1200 * Compute max_wqe in case less WQE were consumed in previous
1203 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1204 cs_flags = txq_ol_cksum_to_cs(buf);
1205 /* Retrieve packet information. */
1206 length = PKT_LEN(buf);
1207 /* Start new session if packet differs. */
1208 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1209 if ((mpw.len != length) ||
1211 (mpw.wqe->eseg.cs_flags != cs_flags))
1212 mlx5_mpw_close(txq, &mpw);
1213 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1214 if ((mpw.len != length) ||
1216 (length > inline_room) ||
1217 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1218 mlx5_mpw_inline_close(txq, &mpw);
1220 txq->max_inline * RTE_CACHE_LINE_SIZE;
1223 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1224 if ((segs_n != 1) ||
1225 (length > inline_room)) {
1227 * Multi-Packet WQE consumes at most two WQE.
1228 * mlx5_mpw_new() expects to be able to use
1231 if (unlikely(max_wqe < 2))
1234 mlx5_mpw_new(txq, &mpw, length);
1235 mpw.wqe->eseg.cs_flags = cs_flags;
1237 if (unlikely(max_wqe < wqe_inl_n))
1239 max_wqe -= wqe_inl_n;
1240 mlx5_mpw_inline_new(txq, &mpw, length);
1241 mpw.wqe->eseg.cs_flags = cs_flags;
1244 /* Multi-segment packets must be alone in their MPW. */
1245 assert((segs_n == 1) || (mpw.pkts_n == 0));
1246 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1247 assert(inline_room ==
1248 txq->max_inline * RTE_CACHE_LINE_SIZE);
1249 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1253 volatile struct mlx5_wqe_data_seg *dseg;
1256 (*txq->elts)[elts_head++ & elts_m] = buf;
1257 dseg = mpw.data.dseg[mpw.pkts_n];
1258 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1259 *dseg = (struct mlx5_wqe_data_seg){
1261 rte_cpu_to_be_32(DATA_LEN(buf)),
1262 .lkey = mlx5_tx_mb2mr(txq, buf),
1263 .addr = rte_cpu_to_be_64(addr),
1265 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1266 length += DATA_LEN(buf);
1272 assert(length == mpw.len);
1273 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1274 mlx5_mpw_close(txq, &mpw);
1278 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1279 assert(length <= inline_room);
1280 assert(length == DATA_LEN(buf));
1281 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1282 (*txq->elts)[elts_head++ & elts_m] = buf;
1283 /* Maximum number of bytes before wrapping. */
1284 max = ((((uintptr_t)(txq->wqes)) +
1287 (uintptr_t)mpw.data.raw);
1289 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1292 mpw.data.raw = (volatile void *)txq->wqes;
1293 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1294 (void *)(addr + max),
1296 mpw.data.raw += length - max;
1298 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1304 (volatile void *)txq->wqes;
1306 mpw.data.raw += length;
1309 mpw.total_len += length;
1311 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1312 mlx5_mpw_inline_close(txq, &mpw);
1314 txq->max_inline * RTE_CACHE_LINE_SIZE;
1316 inline_room -= length;
1319 #ifdef MLX5_PMD_SOFT_COUNTERS
1320 /* Increment sent bytes counter. */
1321 txq->stats.obytes += length;
1325 /* Take a shortcut if nothing must be sent. */
1326 if (unlikely(i == 0))
1328 /* Check whether completion threshold has been reached. */
1329 /* "j" includes both packets and segments. */
1330 comp = txq->elts_comp + j;
1331 if (comp >= MLX5_TX_COMP_THRESH) {
1332 volatile struct mlx5_wqe *wqe = mpw.wqe;
1334 /* Request completion on last WQE. */
1335 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1336 /* Save elts_head in unused "immediate" field of WQE. */
1337 wqe->ctrl[3] = elts_head;
1343 txq->elts_comp = comp;
1345 #ifdef MLX5_PMD_SOFT_COUNTERS
1346 /* Increment sent packets counter. */
1347 txq->stats.opackets += i;
1349 /* Ring QP doorbell. */
1350 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1351 mlx5_mpw_inline_close(txq, &mpw);
1352 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1353 mlx5_mpw_close(txq, &mpw);
1354 mlx5_tx_dbrec(txq, mpw.wqe);
1355 txq->elts_head = elts_head;
1360 * Open an Enhanced MPW session.
1363 * Pointer to TX queue structure.
1365 * Pointer to MPW session structure.
1370 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1372 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1374 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1376 mpw->total_len = sizeof(struct mlx5_wqe);
1377 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1379 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1380 (txq->wqe_ci << 8) |
1381 MLX5_OPCODE_ENHANCED_MPSW);
1382 mpw->wqe->ctrl[2] = 0;
1383 mpw->wqe->ctrl[3] = 0;
1384 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1385 if (unlikely(padding)) {
1386 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1388 /* Pad the first 2 DWORDs with zero-length inline header. */
1389 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1390 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1391 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1392 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1393 /* Start from the next WQEBB. */
1394 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1396 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1401 * Close an Enhanced MPW session.
1404 * Pointer to TX queue structure.
1406 * Pointer to MPW session structure.
1409 * Number of consumed WQEs.
1411 static inline uint16_t
1412 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1416 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1419 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1420 MLX5_WQE_DS(mpw->total_len));
1421 mpw->state = MLX5_MPW_STATE_CLOSED;
1422 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1428 * TX with Enhanced MPW support.
1431 * Pointer to TX queue structure.
1433 * Packets to transmit.
1435 * Number of packets in array.
1438 * Number of packets successfully transmitted (<= pkts_n).
1440 static inline uint16_t
1441 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1444 uint16_t elts_head = txq->elts_head;
1445 const uint16_t elts_n = 1 << txq->elts_n;
1446 const uint16_t elts_m = elts_n - 1;
1451 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1452 unsigned int mpw_room = 0;
1453 unsigned int inl_pad = 0;
1455 struct mlx5_mpw mpw = {
1456 .state = MLX5_MPW_STATE_CLOSED,
1459 if (unlikely(!pkts_n))
1461 /* Start processing. */
1462 mlx5_tx_complete(txq);
1463 max_elts = (elts_n - (elts_head - txq->elts_tail));
1464 /* A CQE slot must always be available. */
1465 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1466 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1467 if (unlikely(!max_wqe))
1470 struct rte_mbuf *buf = *(pkts++);
1472 unsigned int do_inline = 0; /* Whether inline is possible. */
1476 /* Multi-segmented packet is handled in slow-path outside. */
1477 assert(NB_SEGS(buf) == 1);
1478 /* Make sure there is enough room to store this packet. */
1479 if (max_elts - j == 0)
1481 cs_flags = txq_ol_cksum_to_cs(buf);
1482 /* Retrieve packet information. */
1483 length = PKT_LEN(buf);
1484 /* Start new session if:
1485 * - multi-segment packet
1486 * - no space left even for a dseg
1487 * - next packet can be inlined with a new WQE
1490 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1491 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1493 (length <= txq->inline_max_packet_sz &&
1494 inl_pad + sizeof(inl_hdr) + length >
1496 (mpw.wqe->eseg.cs_flags != cs_flags))
1497 max_wqe -= mlx5_empw_close(txq, &mpw);
1499 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1500 /* In Enhanced MPW, inline as much as the budget is
1501 * allowed. The remaining space is to be filled with
1502 * dsegs. If the title WQEBB isn't padded, it will have
1505 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1506 (max_inline ? max_inline :
1507 pkts_n * MLX5_WQE_DWORD_SIZE) +
1509 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1511 /* Don't pad the title WQEBB to not waste WQ. */
1512 mlx5_empw_new(txq, &mpw, 0);
1513 mpw_room -= mpw.total_len;
1515 do_inline = length <= txq->inline_max_packet_sz &&
1516 sizeof(inl_hdr) + length <= mpw_room &&
1518 mpw.wqe->eseg.cs_flags = cs_flags;
1520 /* Evaluate whether the next packet can be inlined.
1521 * Inlininig is possible when:
1522 * - length is less than configured value
1523 * - length fits for remaining space
1524 * - not required to fill the title WQEBB with dsegs
1527 length <= txq->inline_max_packet_sz &&
1528 inl_pad + sizeof(inl_hdr) + length <=
1530 (!txq->mpw_hdr_dseg ||
1531 mpw.total_len >= MLX5_WQE_SIZE);
1533 if (max_inline && do_inline) {
1534 /* Inline packet into WQE. */
1537 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1538 assert(length == DATA_LEN(buf));
1539 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1540 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1541 mpw.data.raw = (volatile void *)
1542 ((uintptr_t)mpw.data.raw + inl_pad);
1543 max = tx_mlx5_wq_tailroom(txq,
1544 (void *)(uintptr_t)mpw.data.raw);
1545 /* Copy inline header. */
1546 mpw.data.raw = (volatile void *)
1548 (void *)(uintptr_t)mpw.data.raw,
1551 (void *)(uintptr_t)txq->wqes,
1553 max = tx_mlx5_wq_tailroom(txq,
1554 (void *)(uintptr_t)mpw.data.raw);
1555 /* Copy packet data. */
1556 mpw.data.raw = (volatile void *)
1558 (void *)(uintptr_t)mpw.data.raw,
1561 (void *)(uintptr_t)txq->wqes,
1564 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1565 /* No need to get completion as the entire packet is
1566 * copied to WQ. Free the buf right away.
1568 rte_pktmbuf_free_seg(buf);
1569 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1570 /* Add pad in the next packet if any. */
1571 inl_pad = (((uintptr_t)mpw.data.raw +
1572 (MLX5_WQE_DWORD_SIZE - 1)) &
1573 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1574 (uintptr_t)mpw.data.raw;
1576 /* No inline. Load a dseg of packet pointer. */
1577 volatile rte_v128u32_t *dseg;
1579 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1580 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1581 assert(length == DATA_LEN(buf));
1582 if (!tx_mlx5_wq_tailroom(txq,
1583 (void *)((uintptr_t)mpw.data.raw
1585 dseg = (volatile void *)txq->wqes;
1587 dseg = (volatile void *)
1588 ((uintptr_t)mpw.data.raw +
1590 (*txq->elts)[elts_head++ & elts_m] = buf;
1591 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1593 *dseg = (rte_v128u32_t) {
1594 rte_cpu_to_be_32(length),
1595 mlx5_tx_mb2mr(txq, buf),
1599 mpw.data.raw = (volatile void *)(dseg + 1);
1600 mpw.total_len += (inl_pad + sizeof(*dseg));
1603 mpw_room -= (inl_pad + sizeof(*dseg));
1606 #ifdef MLX5_PMD_SOFT_COUNTERS
1607 /* Increment sent bytes counter. */
1608 txq->stats.obytes += length;
1611 } while (i < pkts_n);
1612 /* Take a shortcut if nothing must be sent. */
1613 if (unlikely(i == 0))
1615 /* Check whether completion threshold has been reached. */
1616 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1617 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1618 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1619 volatile struct mlx5_wqe *wqe = mpw.wqe;
1621 /* Request completion on last WQE. */
1622 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1623 /* Save elts_head in unused "immediate" field of WQE. */
1624 wqe->ctrl[3] = elts_head;
1626 txq->mpw_comp = txq->wqe_ci;
1631 txq->elts_comp += j;
1633 #ifdef MLX5_PMD_SOFT_COUNTERS
1634 /* Increment sent packets counter. */
1635 txq->stats.opackets += i;
1637 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1638 mlx5_empw_close(txq, &mpw);
1639 /* Ring QP doorbell. */
1640 mlx5_tx_dbrec(txq, mpw.wqe);
1641 txq->elts_head = elts_head;
1646 * DPDK callback for TX with Enhanced MPW support.
1649 * Generic pointer to TX queue structure.
1651 * Packets to transmit.
1653 * Number of packets in array.
1656 * Number of packets successfully transmitted (<= pkts_n).
1659 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1661 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1664 while (pkts_n > nb_tx) {
1668 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1670 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1675 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1677 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1687 * Translate RX completion flags to packet type.
1690 * Pointer to RX queue structure.
1694 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1697 * Packet type for struct rte_mbuf.
1699 static inline uint32_t
1700 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1703 uint8_t pinfo = cqe->pkt_info;
1704 uint16_t ptype = cqe->hdr_type_etc;
1707 * The index to the array should have:
1708 * bit[1:0] = l3_hdr_type
1709 * bit[4:2] = l4_hdr_type
1712 * bit[7] = outer_l3_type
1714 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1715 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1719 * Get size of the next packet for a given CQE. For compressed CQEs, the
1720 * consumer index is updated only once all packets of the current one have
1724 * Pointer to RX queue.
1727 * @param[out] rss_hash
1728 * Packet RSS Hash result.
1731 * Packet size in bytes (0 if there is none), -1 in case of completion
1735 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1736 uint16_t cqe_cnt, uint32_t *rss_hash)
1738 struct rxq_zip *zip = &rxq->zip;
1739 uint16_t cqe_n = cqe_cnt + 1;
1743 /* Process compressed data in the CQE and mini arrays. */
1745 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1746 (volatile struct mlx5_mini_cqe8 (*)[8])
1747 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1749 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1750 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1751 if ((++zip->ai & 7) == 0) {
1752 /* Invalidate consumed CQEs */
1755 while (idx != end) {
1756 (*rxq->cqes)[idx & cqe_cnt].op_own =
1757 MLX5_CQE_INVALIDATE;
1761 * Increment consumer index to skip the number of
1762 * CQEs consumed. Hardware leaves holes in the CQ
1763 * ring for software use.
1768 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1769 /* Invalidate the rest */
1773 while (idx != end) {
1774 (*rxq->cqes)[idx & cqe_cnt].op_own =
1775 MLX5_CQE_INVALIDATE;
1778 rxq->cq_ci = zip->cq_ci;
1781 /* No compressed data, get next CQE and verify if it is compressed. */
1786 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1787 if (unlikely(ret == 1))
1790 op_own = cqe->op_own;
1792 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1793 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1794 (volatile struct mlx5_mini_cqe8 (*)[8])
1795 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1798 /* Fix endianness. */
1799 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1801 * Current mini array position is the one returned by
1804 * If completion comprises several mini arrays, as a
1805 * special case the second one is located 7 CQEs after
1806 * the initial CQE instead of 8 for subsequent ones.
1808 zip->ca = rxq->cq_ci;
1809 zip->na = zip->ca + 7;
1810 /* Compute the next non compressed CQE. */
1812 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1813 /* Get packet size to return. */
1814 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1815 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1817 /* Prefetch all the entries to be invalidated */
1820 while (idx != end) {
1821 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1825 len = rte_be_to_cpu_32(cqe->byte_cnt);
1826 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1828 /* Error while receiving packet. */
1829 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1836 * Translate RX completion flags to offload flags.
1842 * Offload flags (ol_flags) for struct rte_mbuf.
1844 static inline uint32_t
1845 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1847 uint32_t ol_flags = 0;
1848 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1852 MLX5_CQE_RX_L3_HDR_VALID,
1853 PKT_RX_IP_CKSUM_GOOD) |
1855 MLX5_CQE_RX_L4_HDR_VALID,
1856 PKT_RX_L4_CKSUM_GOOD);
1861 * Fill in mbuf fields from RX completion flags.
1862 * Note that pkt->ol_flags should be initialized outside of this function.
1865 * Pointer to RX queue.
1870 * @param rss_hash_res
1871 * Packet RSS Hash result.
1874 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1875 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1877 /* Update packet information. */
1878 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1879 if (rss_hash_res && rxq->rss_hash) {
1880 pkt->hash.rss = rss_hash_res;
1881 pkt->ol_flags |= PKT_RX_RSS_HASH;
1883 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1884 pkt->ol_flags |= PKT_RX_FDIR;
1885 if (cqe->sop_drop_qpn !=
1886 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1887 uint32_t mark = cqe->sop_drop_qpn;
1889 pkt->ol_flags |= PKT_RX_FDIR_ID;
1890 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1894 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1895 if (rxq->vlan_strip &&
1896 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1897 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1898 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1900 if (rxq->hw_timestamp) {
1901 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1902 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1907 * DPDK callback for RX.
1910 * Generic pointer to RX queue structure.
1912 * Array to store received packets.
1914 * Maximum number of packets in array.
1917 * Number of packets successfully received (<= pkts_n).
1920 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1922 struct mlx5_rxq_data *rxq = dpdk_rxq;
1923 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1924 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1925 const unsigned int sges_n = rxq->sges_n;
1926 struct rte_mbuf *pkt = NULL;
1927 struct rte_mbuf *seg = NULL;
1928 volatile struct mlx5_cqe *cqe =
1929 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1931 unsigned int rq_ci = rxq->rq_ci << sges_n;
1932 int len = 0; /* keep its value across iterations. */
1935 unsigned int idx = rq_ci & wqe_cnt;
1936 volatile struct mlx5_wqe_data_seg *wqe =
1937 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1938 struct rte_mbuf *rep = (*rxq->elts)[idx];
1939 uint32_t rss_hash_res = 0;
1947 rep = rte_mbuf_raw_alloc(rxq->mp);
1948 if (unlikely(rep == NULL)) {
1949 ++rxq->stats.rx_nombuf;
1952 * no buffers before we even started,
1953 * bail out silently.
1957 while (pkt != seg) {
1958 assert(pkt != (*rxq->elts)[idx]);
1962 rte_mbuf_raw_free(pkt);
1968 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1969 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1972 rte_mbuf_raw_free(rep);
1975 if (unlikely(len == -1)) {
1976 /* RX error, packet is likely too large. */
1977 rte_mbuf_raw_free(rep);
1978 ++rxq->stats.idropped;
1982 assert(len >= (rxq->crc_present << 2));
1984 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1985 if (rxq->crc_present)
1986 len -= ETHER_CRC_LEN;
1989 DATA_LEN(rep) = DATA_LEN(seg);
1990 PKT_LEN(rep) = PKT_LEN(seg);
1991 SET_DATA_OFF(rep, DATA_OFF(seg));
1992 PORT(rep) = PORT(seg);
1993 (*rxq->elts)[idx] = rep;
1995 * Fill NIC descriptor with the new buffer. The lkey and size
1996 * of the buffers are already known, only the buffer address
1999 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
2000 /* If there's only one MR, no need to replace LKey in WQE. */
2001 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2002 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
2003 if (len > DATA_LEN(seg)) {
2004 len -= DATA_LEN(seg);
2009 DATA_LEN(seg) = len;
2010 #ifdef MLX5_PMD_SOFT_COUNTERS
2011 /* Increment bytes counter. */
2012 rxq->stats.ibytes += PKT_LEN(pkt);
2014 /* Return packet. */
2020 /* Align consumer index to the next stride. */
2025 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2027 /* Update the consumer index. */
2028 rxq->rq_ci = rq_ci >> sges_n;
2030 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2032 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2033 #ifdef MLX5_PMD_SOFT_COUNTERS
2034 /* Increment packets counter. */
2035 rxq->stats.ipackets += i;
2041 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
2043 struct mlx5_mprq_buf *buf = opaque;
2045 if (rte_atomic16_read(&buf->refcnt) == 1) {
2046 rte_mempool_put(buf->mp, buf);
2047 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
2048 rte_atomic16_set(&buf->refcnt, 1);
2049 rte_mempool_put(buf->mp, buf);
2054 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
2056 mlx5_mprq_buf_free_cb(NULL, buf);
2060 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
2062 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
2063 volatile struct mlx5_wqe_data_seg *wqe =
2064 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
2067 assert(rep != NULL);
2068 /* Replace MPRQ buf. */
2069 (*rxq->mprq_bufs)[rq_idx] = rep;
2071 addr = mlx5_mprq_buf_addr(rep);
2072 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
2073 /* If there's only one MR, no need to replace LKey in WQE. */
2074 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
2075 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
2076 /* Stash a mbuf for next replacement. */
2077 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
2078 rxq->mprq_repl = rep;
2080 rxq->mprq_repl = NULL;
2084 * DPDK callback for RX with Multi-Packet RQ support.
2087 * Generic pointer to RX queue structure.
2089 * Array to store received packets.
2091 * Maximum number of packets in array.
2094 * Number of packets successfully received (<= pkts_n).
2097 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2099 struct mlx5_rxq_data *rxq = dpdk_rxq;
2100 const unsigned int strd_n = 1 << rxq->strd_num_n;
2101 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
2102 const unsigned int strd_shift =
2103 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
2104 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
2105 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
2106 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2108 uint16_t rq_ci = rxq->rq_ci;
2109 uint16_t strd_idx = rxq->strd_ci;
2110 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2112 while (i < pkts_n) {
2113 struct rte_mbuf *pkt;
2117 uint16_t consumed_strd;
2120 uint32_t rss_hash_res = 0;
2122 if (strd_idx == strd_n) {
2123 /* Replace WQE only if the buffer is still in use. */
2124 if (rte_atomic16_read(&buf->refcnt) > 1) {
2125 mprq_buf_replace(rxq, rq_ci & wq_mask);
2126 /* Release the old buffer. */
2127 mlx5_mprq_buf_free(buf);
2128 } else if (unlikely(rxq->mprq_repl == NULL)) {
2129 struct mlx5_mprq_buf *rep;
2132 * Currently, the MPRQ mempool is out of buffer
2133 * and doing memcpy regardless of the size of Rx
2134 * packet. Retry allocation to get back to
2137 if (!rte_mempool_get(rxq->mprq_mp,
2139 rxq->mprq_repl = rep;
2141 /* Advance to the next WQE. */
2144 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
2146 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
2147 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &rss_hash_res);
2150 if (unlikely(ret == -1)) {
2151 /* RX error, packet is likely too large. */
2152 ++rxq->stats.idropped;
2156 consumed_strd = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
2157 MLX5_MPRQ_STRIDE_NUM_SHIFT;
2158 assert(consumed_strd);
2159 /* Calculate offset before adding up stride index. */
2160 offset = strd_idx * strd_sz + strd_shift;
2161 strd_idx += consumed_strd;
2162 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
2165 * Currently configured to receive a packet per a stride. But if
2166 * MTU is adjusted through kernel interface, device could
2167 * consume multiple strides without raising an error. In this
2168 * case, the packet should be dropped because it is bigger than
2169 * the max_rx_pkt_len.
2171 if (unlikely(consumed_strd > 1)) {
2172 ++rxq->stats.idropped;
2175 pkt = rte_pktmbuf_alloc(rxq->mp);
2176 if (unlikely(pkt == NULL)) {
2177 ++rxq->stats.rx_nombuf;
2180 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
2181 assert((int)len >= (rxq->crc_present << 2));
2182 if (rxq->crc_present)
2183 len -= ETHER_CRC_LEN;
2184 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf), offset);
2185 /* Initialize the offload flag. */
2188 * Memcpy packets to the target mbuf if:
2189 * - The size of packet is smaller than mprq_max_memcpy_len.
2190 * - Out of buffer in the Mempool for Multi-Packet RQ.
2192 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
2194 * When memcpy'ing packet due to out-of-buffer, the
2195 * packet must be smaller than the target mbuf.
2197 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2198 rte_pktmbuf_free_seg(pkt);
2199 ++rxq->stats.idropped;
2202 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
2204 rte_iova_t buf_iova;
2205 struct rte_mbuf_ext_shared_info *shinfo;
2206 uint16_t buf_len = consumed_strd * strd_sz;
2208 /* Increment the refcnt of the whole chunk. */
2209 rte_atomic16_add_return(&buf->refcnt, 1);
2210 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
2212 addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
2214 * MLX5 device doesn't use iova but it is necessary in a
2215 * case where the Rx packet is transmitted via a
2218 buf_iova = rte_mempool_virt2iova(buf) +
2219 RTE_PTR_DIFF(addr, buf);
2220 shinfo = rte_pktmbuf_ext_shinfo_init_helper(addr,
2221 &buf_len, mlx5_mprq_buf_free_cb, buf);
2223 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
2224 * attaching the stride to mbuf and more offload flags
2225 * will be added below by calling rxq_cq_to_mbuf().
2226 * Other fields will be overwritten.
2228 rte_pktmbuf_attach_extbuf(pkt, addr, buf_iova, buf_len,
2230 rte_pktmbuf_reset_headroom(pkt);
2231 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
2233 * Prevent potential overflow due to MTU change through
2236 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
2237 rte_pktmbuf_free_seg(pkt);
2238 ++rxq->stats.idropped;
2242 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
2244 DATA_LEN(pkt) = len;
2245 PORT(pkt) = rxq->port_id;
2246 #ifdef MLX5_PMD_SOFT_COUNTERS
2247 /* Increment bytes counter. */
2248 rxq->stats.ibytes += PKT_LEN(pkt);
2250 /* Return packet. */
2254 /* Update the consumer indexes. */
2255 rxq->strd_ci = strd_idx;
2257 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2258 if (rq_ci != rxq->rq_ci) {
2261 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2263 #ifdef MLX5_PMD_SOFT_COUNTERS
2264 /* Increment packets counter. */
2265 rxq->stats.ipackets += i;
2271 * Dummy DPDK callback for TX.
2273 * This function is used to temporarily replace the real callback during
2274 * unsafe control operations on the queue, or in case of error.
2277 * Generic pointer to TX queue structure.
2279 * Packets to transmit.
2281 * Number of packets in array.
2284 * Number of packets successfully transmitted (<= pkts_n).
2287 removed_tx_burst(void *dpdk_txq __rte_unused,
2288 struct rte_mbuf **pkts __rte_unused,
2289 uint16_t pkts_n __rte_unused)
2295 * Dummy DPDK callback for RX.
2297 * This function is used to temporarily replace the real callback during
2298 * unsafe control operations on the queue, or in case of error.
2301 * Generic pointer to RX queue structure.
2303 * Array to store received packets.
2305 * Maximum number of packets in array.
2308 * Number of packets successfully received (<= pkts_n).
2311 removed_rx_burst(void *dpdk_txq __rte_unused,
2312 struct rte_mbuf **pkts __rte_unused,
2313 uint16_t pkts_n __rte_unused)
2319 * Vectorized Rx/Tx routines are not compiled in when required vector
2320 * instructions are not supported on a target architecture. The following null
2321 * stubs are needed for linkage when those are not included outside of this file
2322 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2325 uint16_t __attribute__((weak))
2326 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2327 struct rte_mbuf **pkts __rte_unused,
2328 uint16_t pkts_n __rte_unused)
2333 uint16_t __attribute__((weak))
2334 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2335 struct rte_mbuf **pkts __rte_unused,
2336 uint16_t pkts_n __rte_unused)
2341 uint16_t __attribute__((weak))
2342 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2343 struct rte_mbuf **pkts __rte_unused,
2344 uint16_t pkts_n __rte_unused)
2349 int __attribute__((weak))
2350 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2355 int __attribute__((weak))
2356 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2361 int __attribute__((weak))
2362 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2367 int __attribute__((weak))
2368 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)