1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
32 #include "mlx5_utils.h"
33 #include "mlx5_rxtx.h"
34 #include "mlx5_autoconf.h"
35 #include "mlx5_defs.h"
38 /* TX burst subroutines return codes. */
39 enum mlx5_txcmp_code {
40 MLX5_TXCMP_CODE_EXIT = 0,
41 MLX5_TXCMP_CODE_ERROR,
42 MLX5_TXCMP_CODE_SINGLE,
43 MLX5_TXCMP_CODE_MULTI,
49 * These defines are used to configure Tx burst routine option set
50 * supported at compile time. The not specified options are optimized out
51 * out due to if conditions can be explicitly calculated at compile time.
52 * The offloads with bigger runtime check (require more CPU cycles to
53 * skip) overhead should have the bigger index - this is needed to
54 * select the better matching routine function if no exact match and
55 * some offloads are not actually requested.
57 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
58 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
59 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
60 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
61 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
62 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
63 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
64 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
67 /* The most common offloads groups. */
68 #define MLX5_TXOFF_CONFIG_NONE 0
69 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
70 MLX5_TXOFF_CONFIG_TSO | \
71 MLX5_TXOFF_CONFIG_SWP | \
72 MLX5_TXOFF_CONFIG_CSUM | \
73 MLX5_TXOFF_CONFIG_INLINE | \
74 MLX5_TXOFF_CONFIG_VLAN | \
75 MLX5_TXOFF_CONFIG_METADATA)
77 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
79 #define MLX5_TXOFF_DECL(func, olx) \
80 static uint16_t mlx5_tx_burst_##func(void *txq, \
81 struct rte_mbuf **pkts, \
84 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
85 pkts, pkts_n, (olx)); \
88 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
90 static __rte_always_inline uint32_t
91 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
93 static __rte_always_inline int
94 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
95 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
97 static __rte_always_inline uint32_t
98 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
100 static __rte_always_inline void
101 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
102 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
104 static __rte_always_inline void
105 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
106 const unsigned int strd_n);
109 mlx5_queue_state_modify(struct rte_eth_dev *dev,
110 struct mlx5_mp_arg_queue_state_modify *sm);
113 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
114 volatile struct mlx5_cqe *restrict cqe,
118 mlx5_lro_update_hdr(uint8_t *restrict padd,
119 volatile struct mlx5_cqe *restrict cqe,
122 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
123 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
126 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
127 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
130 * Build a table to translate Rx completion flags to packet type.
132 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
135 mlx5_set_ptype_table(void)
138 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
140 /* Last entry must not be overwritten, reserved for errored packet. */
141 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
142 (*p)[i] = RTE_PTYPE_UNKNOWN;
144 * The index to the array should have:
145 * bit[1:0] = l3_hdr_type
146 * bit[4:2] = l4_hdr_type
149 * bit[7] = outer_l3_type
152 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
154 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_L4_NONFRAG;
156 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_L4_NONFRAG;
159 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
166 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
168 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
170 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
172 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
174 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
177 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
181 /* Repeat with outer_l3_type being set. Just in case. */
182 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
183 RTE_PTYPE_L4_NONFRAG;
184 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
185 RTE_PTYPE_L4_NONFRAG;
186 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
190 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
192 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
194 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
196 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
200 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
202 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
204 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
208 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
209 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L4_NONFRAG;
211 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
213 RTE_PTYPE_INNER_L4_NONFRAG;
214 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
215 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
216 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L4_NONFRAG;
218 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
219 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L4_NONFRAG;
221 /* Tunneled - Fragmented */
222 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L4_FRAG;
225 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L4_FRAG;
228 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
229 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L4_FRAG;
231 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
232 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L4_FRAG;
235 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
262 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_TCP;
265 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
266 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L4_TCP;
268 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
269 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L4_TCP;
272 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L4_UDP;
275 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L4_UDP;
278 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
279 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L4_UDP;
281 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
282 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_INNER_L4_UDP;
287 * Build a table to translate packet to checksum type of Verbs.
290 mlx5_set_cksum_table(void)
296 * The index should have:
297 * bit[0] = PKT_TX_TCP_SEG
298 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
299 * bit[4] = PKT_TX_IP_CKSUM
300 * bit[8] = PKT_TX_OUTER_IP_CKSUM
303 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
306 /* Tunneled packet. */
307 if (i & (1 << 8)) /* Outer IP. */
308 v |= MLX5_ETH_WQE_L3_CSUM;
309 if (i & (1 << 4)) /* Inner IP. */
310 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
311 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
312 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
315 if (i & (1 << 4)) /* IP. */
316 v |= MLX5_ETH_WQE_L3_CSUM;
317 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
318 v |= MLX5_ETH_WQE_L4_CSUM;
320 mlx5_cksum_table[i] = v;
325 * Build a table to translate packet type of mbuf to SWP type of Verbs.
328 mlx5_set_swp_types_table(void)
334 * The index should have:
335 * bit[0:1] = PKT_TX_L4_MASK
336 * bit[4] = PKT_TX_IPV6
337 * bit[8] = PKT_TX_OUTER_IPV6
338 * bit[9] = PKT_TX_OUTER_UDP
340 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
343 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
345 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
347 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
348 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
349 v |= MLX5_ETH_WQE_L4_INNER_UDP;
350 mlx5_swp_types_table[i] = v;
355 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
356 * Flags must be preliminary initialized to zero.
359 * Pointer to burst routine local context.
361 * Pointer to store Software Parser flags
363 * Configured Tx offloads mask. It is fully defined at
364 * compile time and may be used for optimization.
367 * Software Parser offsets packed in dword.
368 * Software Parser flags are set by pointer.
370 static __rte_always_inline uint32_t
371 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
376 unsigned int idx, off;
379 if (!MLX5_TXOFF_CONFIG(SWP))
381 ol = loc->mbuf->ol_flags;
382 tunnel = ol & PKT_TX_TUNNEL_MASK;
384 * Check whether Software Parser is required.
385 * Only customized tunnels may ask for.
387 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
390 * The index should have:
391 * bit[0:1] = PKT_TX_L4_MASK
392 * bit[4] = PKT_TX_IPV6
393 * bit[8] = PKT_TX_OUTER_IPV6
394 * bit[9] = PKT_TX_OUTER_UDP
396 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
397 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
398 *swp_flags = mlx5_swp_types_table[idx];
400 * Set offsets for SW parser. Since ConnectX-5, SW parser just
401 * complements HW parser. SW parser starts to engage only if HW parser
402 * can't reach a header. For the older devices, HW parser will not kick
403 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
404 * should be set regardless of HW offload.
406 off = loc->mbuf->outer_l2_len;
407 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
408 off += sizeof(struct rte_vlan_hdr);
409 set = (off >> 1) << 8; /* Outer L3 offset. */
410 off += loc->mbuf->outer_l3_len;
411 if (tunnel == PKT_TX_TUNNEL_UDP)
412 set |= off >> 1; /* Outer L4 offset. */
413 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
414 const uint64_t csum = ol & PKT_TX_L4_MASK;
415 off += loc->mbuf->l2_len;
416 set |= (off >> 1) << 24; /* Inner L3 offset. */
417 if (csum == PKT_TX_TCP_CKSUM ||
418 csum == PKT_TX_UDP_CKSUM ||
419 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
420 off += loc->mbuf->l3_len;
421 set |= (off >> 1) << 16; /* Inner L4 offset. */
424 set = rte_cpu_to_le_32(set);
429 * Convert the Checksum offloads to Verbs.
432 * Pointer to the mbuf.
435 * Converted checksum flags.
437 static __rte_always_inline uint8_t
438 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
441 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
442 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
443 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
446 * The index should have:
447 * bit[0] = PKT_TX_TCP_SEG
448 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
449 * bit[4] = PKT_TX_IP_CKSUM
450 * bit[8] = PKT_TX_OUTER_IP_CKSUM
453 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
454 return mlx5_cksum_table[idx];
458 * Internal function to compute the number of used descriptors in an RX queue
464 * The number of used rx descriptor.
467 rx_queue_count(struct mlx5_rxq_data *rxq)
469 struct rxq_zip *zip = &rxq->zip;
470 volatile struct mlx5_cqe *cqe;
471 const unsigned int cqe_n = (1 << rxq->cqe_n);
472 const unsigned int cqe_cnt = cqe_n - 1;
476 /* if we are processing a compressed cqe */
478 used = zip->cqe_cnt - zip->ca;
484 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
485 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
489 op_own = cqe->op_own;
490 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
491 n = rte_be_to_cpu_32(cqe->byte_cnt);
496 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
498 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
503 * DPDK callback to check the status of a rx descriptor.
508 * The index of the descriptor in the ring.
511 * The status of the tx descriptor.
514 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
516 struct mlx5_rxq_data *rxq = rx_queue;
517 struct mlx5_rxq_ctrl *rxq_ctrl =
518 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
519 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
521 if (dev->rx_pkt_burst != mlx5_rx_burst) {
525 if (offset >= (1 << rxq->elts_n)) {
529 if (offset < rx_queue_count(rxq))
530 return RTE_ETH_RX_DESC_DONE;
531 return RTE_ETH_RX_DESC_AVAIL;
535 * DPDK callback to get the number of used descriptors in a RX queue
538 * Pointer to the device structure.
544 * The number of used rx descriptor.
545 * -EINVAL if the queue is invalid
548 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
550 struct mlx5_priv *priv = dev->data->dev_private;
551 struct mlx5_rxq_data *rxq;
553 if (dev->rx_pkt_burst != mlx5_rx_burst) {
557 rxq = (*priv->rxqs)[rx_queue_id];
562 return rx_queue_count(rxq);
565 #define MLX5_SYSTEM_LOG_DIR "/var/log"
567 * Dump debug information to log file.
572 * If not NULL this string is printed as a header to the output
573 * and the output will be in hexadecimal view.
575 * This is the buffer address to print out.
577 * The number of bytes to dump out.
580 mlx5_dump_debug_information(const char *fname, const char *hex_title,
581 const void *buf, unsigned int hex_len)
585 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
586 fd = fopen(path, "a+");
588 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
589 MKSTR(path2, "./%s", fname);
590 fd = fopen(path2, "a+");
592 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
595 DRV_LOG(INFO, "New debug dump in file %s", path2);
597 DRV_LOG(INFO, "New debug dump in file %s", path);
600 rte_hexdump(fd, hex_title, buf, hex_len);
602 fprintf(fd, "%s", (const char *)buf);
603 fprintf(fd, "\n\n\n");
608 * Move QP from error state to running state and initialize indexes.
611 * Pointer to TX queue control structure.
614 * 0 on success, else -1.
617 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
619 struct mlx5_mp_arg_queue_state_modify sm = {
621 .queue_id = txq_ctrl->txq.idx,
624 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
626 txq_ctrl->txq.wqe_ci = 0;
627 txq_ctrl->txq.wqe_pi = 0;
628 txq_ctrl->txq.elts_comp = 0;
632 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
634 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
636 static const uint8_t magic[] = "seen";
640 for (i = 0; i < sizeof(magic); ++i)
641 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
643 err_cqe->rsvd1[i] = magic[i];
652 * Pointer to TX queue structure.
654 * Pointer to the error CQE.
657 * Negative value if queue recovery failed, otherwise
658 * the error completion entry is handled successfully.
661 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
662 volatile struct mlx5_err_cqe *err_cqe)
664 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
665 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
666 struct mlx5_txq_ctrl *txq_ctrl =
667 container_of(txq, struct mlx5_txq_ctrl, txq);
668 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
669 int seen = check_err_cqe_seen(err_cqe);
671 if (!seen && txq_ctrl->dump_file_n <
672 txq_ctrl->priv->config.max_dump_files_num) {
673 MKSTR(err_str, "Unexpected CQE error syndrome "
674 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
675 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
676 txq->cqe_s, txq->qp_num_8s >> 8,
677 rte_be_to_cpu_16(err_cqe->wqe_counter),
678 txq->wqe_ci, txq->cq_ci);
679 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
680 PORT_ID(txq_ctrl->priv), txq->idx,
681 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
682 mlx5_dump_debug_information(name, NULL, err_str, 0);
683 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
684 (const void *)((uintptr_t)
688 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
689 (const void *)((uintptr_t)
693 txq_ctrl->dump_file_n++;
697 * Count errors in WQEs units.
698 * Later it can be improved to count error packets,
699 * for example, by SQ parsing to find how much packets
700 * should be counted for each WQE.
702 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
704 if (tx_recover_qp(txq_ctrl)) {
705 /* Recovering failed - retry later on the same WQE. */
708 /* Release all the remaining buffers. */
709 txq_free_elts(txq_ctrl);
715 * Translate RX completion flags to packet type.
718 * Pointer to RX queue structure.
722 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
725 * Packet type for struct rte_mbuf.
727 static inline uint32_t
728 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
731 uint8_t pinfo = cqe->pkt_info;
732 uint16_t ptype = cqe->hdr_type_etc;
735 * The index to the array should have:
736 * bit[1:0] = l3_hdr_type
737 * bit[4:2] = l4_hdr_type
740 * bit[7] = outer_l3_type
742 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
743 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
747 * Initialize Rx WQ and indexes.
750 * Pointer to RX queue structure.
753 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
755 const unsigned int wqe_n = 1 << rxq->elts_n;
758 for (i = 0; (i != wqe_n); ++i) {
759 volatile struct mlx5_wqe_data_seg *scat;
763 if (mlx5_rxq_mprq_enabled(rxq)) {
764 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
766 scat = &((volatile struct mlx5_wqe_mprq *)
768 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
769 1 << rxq->strd_num_n);
770 byte_count = (1 << rxq->strd_sz_n) *
771 (1 << rxq->strd_num_n);
773 struct rte_mbuf *buf = (*rxq->elts)[i];
775 scat = &((volatile struct mlx5_wqe_data_seg *)
777 addr = rte_pktmbuf_mtod(buf, uintptr_t);
778 byte_count = DATA_LEN(buf);
780 /* scat->addr must be able to store a pointer. */
781 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
782 *scat = (struct mlx5_wqe_data_seg){
783 .addr = rte_cpu_to_be_64(addr),
784 .byte_count = rte_cpu_to_be_32(byte_count),
785 .lkey = mlx5_rx_addr2mr(rxq, addr),
788 rxq->consumed_strd = 0;
789 rxq->decompressed = 0;
791 rxq->zip = (struct rxq_zip){
794 /* Update doorbell counter. */
795 rxq->rq_ci = wqe_n >> rxq->sges_n;
797 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
801 * Modify a Verbs/DevX queue state.
802 * This must be called from the primary process.
805 * Pointer to Ethernet device.
807 * State modify request parameters.
810 * 0 in case of success else non-zero value and rte_errno is set.
813 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
814 const struct mlx5_mp_arg_queue_state_modify *sm)
817 struct mlx5_priv *priv = dev->data->dev_private;
820 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
821 struct mlx5_rxq_ctrl *rxq_ctrl =
822 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
824 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
825 struct ibv_wq_attr mod = {
826 .attr_mask = IBV_WQ_ATTR_STATE,
827 .wq_state = sm->state,
830 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
831 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
832 struct mlx5_devx_modify_rq_attr rq_attr;
834 memset(&rq_attr, 0, sizeof(rq_attr));
835 if (sm->state == IBV_WQS_RESET) {
836 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
837 rq_attr.state = MLX5_RQC_STATE_RST;
838 } else if (sm->state == IBV_WQS_RDY) {
839 rq_attr.rq_state = MLX5_RQC_STATE_RST;
840 rq_attr.state = MLX5_RQC_STATE_RDY;
841 } else if (sm->state == IBV_WQS_ERR) {
842 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
843 rq_attr.state = MLX5_RQC_STATE_ERR;
845 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
849 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
850 sm->state, strerror(errno));
855 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
856 struct mlx5_txq_ctrl *txq_ctrl =
857 container_of(txq, struct mlx5_txq_ctrl, txq);
858 struct ibv_qp_attr mod = {
859 .qp_state = IBV_QPS_RESET,
860 .port_num = (uint8_t)priv->ibv_port,
862 struct ibv_qp *qp = txq_ctrl->obj->qp;
864 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
866 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
867 "%s", strerror(errno));
871 mod.qp_state = IBV_QPS_INIT;
872 ret = mlx5_glue->modify_qp(qp, &mod,
873 (IBV_QP_STATE | IBV_QP_PORT));
875 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
880 mod.qp_state = IBV_QPS_RTR;
881 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
883 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
888 mod.qp_state = IBV_QPS_RTS;
889 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
891 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
901 * Modify a Verbs queue state.
904 * Pointer to Ethernet device.
906 * State modify request parameters.
909 * 0 in case of success else non-zero value.
912 mlx5_queue_state_modify(struct rte_eth_dev *dev,
913 struct mlx5_mp_arg_queue_state_modify *sm)
917 switch (rte_eal_process_type()) {
918 case RTE_PROC_PRIMARY:
919 ret = mlx5_queue_state_modify_primary(dev, sm);
921 case RTE_PROC_SECONDARY:
922 ret = mlx5_mp_req_queue_state_modify(dev, sm);
932 * The function inserts the RQ state to reset when the first error CQE is
933 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
934 * it moves the RQ state to ready and initializes the RQ.
935 * Next CQE identification and error counting are in the caller responsibility.
938 * Pointer to RX queue structure.
940 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
941 * 0 when called from non-vectorized Rx burst.
944 * -1 in case of recovery error, otherwise the CQE status.
947 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
949 const uint16_t cqe_n = 1 << rxq->cqe_n;
950 const uint16_t cqe_mask = cqe_n - 1;
951 const unsigned int wqe_n = 1 << rxq->elts_n;
952 struct mlx5_rxq_ctrl *rxq_ctrl =
953 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
955 volatile struct mlx5_cqe *cqe;
956 volatile struct mlx5_err_cqe *err_cqe;
958 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
960 struct mlx5_mp_arg_queue_state_modify sm;
963 switch (rxq->err_state) {
964 case MLX5_RXQ_ERR_STATE_NO_ERROR:
965 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
967 case MLX5_RXQ_ERR_STATE_NEED_RESET:
969 sm.queue_id = rxq->idx;
970 sm.state = IBV_WQS_RESET;
971 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
973 if (rxq_ctrl->dump_file_n <
974 rxq_ctrl->priv->config.max_dump_files_num) {
975 MKSTR(err_str, "Unexpected CQE error syndrome "
976 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
977 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
978 rxq->cqn, rxq_ctrl->wqn,
979 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
980 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
981 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
982 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
983 mlx5_dump_debug_information(name, NULL, err_str, 0);
984 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
985 (const void *)((uintptr_t)
987 sizeof(*u.cqe) * cqe_n);
988 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
989 (const void *)((uintptr_t)
992 rxq_ctrl->dump_file_n++;
994 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
996 case MLX5_RXQ_ERR_STATE_NEED_READY:
997 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
998 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1000 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1003 * The RQ consumer index must be zeroed while moving
1004 * from RESET state to RDY state.
1006 *rxq->rq_db = rte_cpu_to_be_32(0);
1009 sm.queue_id = rxq->idx;
1010 sm.state = IBV_WQS_RDY;
1011 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1015 const uint16_t q_mask = wqe_n - 1;
1017 struct rte_mbuf **elt;
1019 unsigned int n = wqe_n - (rxq->rq_ci -
1022 for (i = 0; i < (int)n; ++i) {
1023 elt_idx = (rxq->rq_ci + i) & q_mask;
1024 elt = &(*rxq->elts)[elt_idx];
1025 *elt = rte_mbuf_raw_alloc(rxq->mp);
1027 for (i--; i >= 0; --i) {
1028 elt_idx = (rxq->rq_ci +
1032 rte_pktmbuf_free_seg
1038 for (i = 0; i < (int)wqe_n; ++i) {
1039 elt = &(*rxq->elts)[i];
1041 (uint16_t)((*elt)->buf_len -
1042 rte_pktmbuf_headroom(*elt));
1044 /* Padding with a fake mbuf for vec Rx. */
1045 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1046 (*rxq->elts)[wqe_n + i] =
1049 mlx5_rxq_initialize(rxq);
1050 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1059 * Get size of the next packet for a given CQE. For compressed CQEs, the
1060 * consumer index is updated only once all packets of the current one have
1064 * Pointer to RX queue.
1068 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1072 * 0 in case of empty CQE, otherwise the packet size in bytes.
1075 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1076 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1078 struct rxq_zip *zip = &rxq->zip;
1079 uint16_t cqe_n = cqe_cnt + 1;
1085 /* Process compressed data in the CQE and mini arrays. */
1087 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1088 (volatile struct mlx5_mini_cqe8 (*)[8])
1089 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1092 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1093 *mcqe = &(*mc)[zip->ai & 7];
1094 if ((++zip->ai & 7) == 0) {
1095 /* Invalidate consumed CQEs */
1098 while (idx != end) {
1099 (*rxq->cqes)[idx & cqe_cnt].op_own =
1100 MLX5_CQE_INVALIDATE;
1104 * Increment consumer index to skip the number
1105 * of CQEs consumed. Hardware leaves holes in
1106 * the CQ ring for software use.
1111 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1112 /* Invalidate the rest */
1116 while (idx != end) {
1117 (*rxq->cqes)[idx & cqe_cnt].op_own =
1118 MLX5_CQE_INVALIDATE;
1121 rxq->cq_ci = zip->cq_ci;
1125 * No compressed data, get next CQE and verify if it is
1132 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1133 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1134 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1136 ret = mlx5_rx_err_handle(rxq, 0);
1137 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1145 op_own = cqe->op_own;
1146 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1147 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1148 (volatile struct mlx5_mini_cqe8 (*)[8])
1149 (uintptr_t)(&(*rxq->cqes)
1153 /* Fix endianness. */
1154 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1156 * Current mini array position is the one
1157 * returned by check_cqe64().
1159 * If completion comprises several mini arrays,
1160 * as a special case the second one is located
1161 * 7 CQEs after the initial CQE instead of 8
1162 * for subsequent ones.
1164 zip->ca = rxq->cq_ci;
1165 zip->na = zip->ca + 7;
1166 /* Compute the next non compressed CQE. */
1168 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1169 /* Get packet size to return. */
1170 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1173 /* Prefetch all to be invalidated */
1176 while (idx != end) {
1177 rte_prefetch0(&(*rxq->cqes)[(idx) &
1182 len = rte_be_to_cpu_32(cqe->byte_cnt);
1185 if (unlikely(rxq->err_state)) {
1186 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1187 ++rxq->stats.idropped;
1195 * Translate RX completion flags to offload flags.
1201 * Offload flags (ol_flags) for struct rte_mbuf.
1203 static inline uint32_t
1204 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1206 uint32_t ol_flags = 0;
1207 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1211 MLX5_CQE_RX_L3_HDR_VALID,
1212 PKT_RX_IP_CKSUM_GOOD) |
1214 MLX5_CQE_RX_L4_HDR_VALID,
1215 PKT_RX_L4_CKSUM_GOOD);
1220 * Fill in mbuf fields from RX completion flags.
1221 * Note that pkt->ol_flags should be initialized outside of this function.
1224 * Pointer to RX queue.
1229 * @param rss_hash_res
1230 * Packet RSS Hash result.
1233 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1234 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1236 /* Update packet information. */
1237 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1238 if (rss_hash_res && rxq->rss_hash) {
1239 pkt->hash.rss = rss_hash_res;
1240 pkt->ol_flags |= PKT_RX_RSS_HASH;
1242 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1243 pkt->ol_flags |= PKT_RX_FDIR;
1244 if (cqe->sop_drop_qpn !=
1245 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1246 uint32_t mark = cqe->sop_drop_qpn;
1248 pkt->ol_flags |= PKT_RX_FDIR_ID;
1249 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1252 if (rte_flow_dynf_metadata_avail() && cqe->flow_table_metadata) {
1253 pkt->ol_flags |= PKT_RX_DYNF_METADATA;
1254 *RTE_FLOW_DYNF_METADATA(pkt) = cqe->flow_table_metadata;
1257 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1258 if (rxq->vlan_strip &&
1259 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1260 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1261 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1263 if (rxq->hw_timestamp) {
1264 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1265 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1270 * DPDK callback for RX.
1273 * Generic pointer to RX queue structure.
1275 * Array to store received packets.
1277 * Maximum number of packets in array.
1280 * Number of packets successfully received (<= pkts_n).
1283 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1285 struct mlx5_rxq_data *rxq = dpdk_rxq;
1286 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1287 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1288 const unsigned int sges_n = rxq->sges_n;
1289 struct rte_mbuf *pkt = NULL;
1290 struct rte_mbuf *seg = NULL;
1291 volatile struct mlx5_cqe *cqe =
1292 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1294 unsigned int rq_ci = rxq->rq_ci << sges_n;
1295 int len = 0; /* keep its value across iterations. */
1298 unsigned int idx = rq_ci & wqe_cnt;
1299 volatile struct mlx5_wqe_data_seg *wqe =
1300 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1301 struct rte_mbuf *rep = (*rxq->elts)[idx];
1302 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1303 uint32_t rss_hash_res;
1311 rep = rte_mbuf_raw_alloc(rxq->mp);
1312 if (unlikely(rep == NULL)) {
1313 ++rxq->stats.rx_nombuf;
1316 * no buffers before we even started,
1317 * bail out silently.
1321 while (pkt != seg) {
1322 assert(pkt != (*rxq->elts)[idx]);
1326 rte_mbuf_raw_free(pkt);
1332 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1333 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1335 rte_mbuf_raw_free(rep);
1339 assert(len >= (rxq->crc_present << 2));
1340 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1341 /* If compressed, take hash result from mini-CQE. */
1342 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1344 mcqe->rx_hash_result);
1345 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1346 if (rxq->crc_present)
1347 len -= RTE_ETHER_CRC_LEN;
1349 if (cqe->lro_num_seg > 1) {
1351 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1353 pkt->ol_flags |= PKT_RX_LRO;
1354 pkt->tso_segsz = len / cqe->lro_num_seg;
1357 DATA_LEN(rep) = DATA_LEN(seg);
1358 PKT_LEN(rep) = PKT_LEN(seg);
1359 SET_DATA_OFF(rep, DATA_OFF(seg));
1360 PORT(rep) = PORT(seg);
1361 (*rxq->elts)[idx] = rep;
1363 * Fill NIC descriptor with the new buffer. The lkey and size
1364 * of the buffers are already known, only the buffer address
1367 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1368 /* If there's only one MR, no need to replace LKey in WQE. */
1369 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1370 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1371 if (len > DATA_LEN(seg)) {
1372 len -= DATA_LEN(seg);
1377 DATA_LEN(seg) = len;
1378 #ifdef MLX5_PMD_SOFT_COUNTERS
1379 /* Increment bytes counter. */
1380 rxq->stats.ibytes += PKT_LEN(pkt);
1382 /* Return packet. */
1387 /* Align consumer index to the next stride. */
1392 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1394 /* Update the consumer index. */
1395 rxq->rq_ci = rq_ci >> sges_n;
1397 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1399 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1400 #ifdef MLX5_PMD_SOFT_COUNTERS
1401 /* Increment packets counter. */
1402 rxq->stats.ipackets += i;
1408 * Update LRO packet TCP header.
1409 * The HW LRO feature doesn't update the TCP header after coalescing the
1410 * TCP segments but supplies information in CQE to fill it by SW.
1413 * Pointer to the TCP header.
1415 * Pointer to the completion entry..
1417 * The L3 pseudo-header checksum.
1420 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1421 volatile struct mlx5_cqe *restrict cqe,
1424 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1425 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1427 * The HW calculates only the TCP payload checksum, need to complete
1428 * the TCP header checksum and the L3 pseudo-header checksum.
1430 uint32_t csum = phcsum + cqe->csum;
1432 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1433 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1434 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1435 tcp->recv_ack = cqe->lro_ack_seq_num;
1436 tcp->rx_win = cqe->lro_tcp_win;
1438 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1439 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1441 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1442 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1443 csum = (~csum) & 0xffff;
1450 * Update LRO packet headers.
1451 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1452 * TCP segments but supply information in CQE to fill it by SW.
1455 * The packet address.
1457 * Pointer to the completion entry..
1459 * The packet length.
1462 mlx5_lro_update_hdr(uint8_t *restrict padd,
1463 volatile struct mlx5_cqe *restrict cqe,
1467 struct rte_ether_hdr *eth;
1468 struct rte_vlan_hdr *vlan;
1469 struct rte_ipv4_hdr *ipv4;
1470 struct rte_ipv6_hdr *ipv6;
1471 struct rte_tcp_hdr *tcp;
1476 uint16_t proto = h.eth->ether_type;
1480 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1481 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1482 proto = h.vlan->eth_proto;
1485 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1486 h.ipv4->time_to_live = cqe->lro_min_ttl;
1487 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1488 h.ipv4->hdr_checksum = 0;
1489 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1490 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1493 h.ipv6->hop_limits = cqe->lro_min_ttl;
1494 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1496 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1499 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1503 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1505 struct mlx5_mprq_buf *buf = opaque;
1507 if (rte_atomic16_read(&buf->refcnt) == 1) {
1508 rte_mempool_put(buf->mp, buf);
1509 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1510 rte_atomic16_set(&buf->refcnt, 1);
1511 rte_mempool_put(buf->mp, buf);
1516 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1518 mlx5_mprq_buf_free_cb(NULL, buf);
1522 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1523 const unsigned int strd_n)
1525 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1526 volatile struct mlx5_wqe_data_seg *wqe =
1527 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1530 assert(rep != NULL);
1531 /* Replace MPRQ buf. */
1532 (*rxq->mprq_bufs)[rq_idx] = rep;
1534 addr = mlx5_mprq_buf_addr(rep, strd_n);
1535 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1536 /* If there's only one MR, no need to replace LKey in WQE. */
1537 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1538 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1539 /* Stash a mbuf for next replacement. */
1540 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1541 rxq->mprq_repl = rep;
1543 rxq->mprq_repl = NULL;
1547 * DPDK callback for RX with Multi-Packet RQ support.
1550 * Generic pointer to RX queue structure.
1552 * Array to store received packets.
1554 * Maximum number of packets in array.
1557 * Number of packets successfully received (<= pkts_n).
1560 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1562 struct mlx5_rxq_data *rxq = dpdk_rxq;
1563 const unsigned int strd_n = 1 << rxq->strd_num_n;
1564 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1565 const unsigned int strd_shift =
1566 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1567 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1568 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1569 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1571 uint32_t rq_ci = rxq->rq_ci;
1572 uint16_t consumed_strd = rxq->consumed_strd;
1573 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1574 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1576 while (i < pkts_n) {
1577 struct rte_mbuf *pkt;
1585 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1586 uint32_t rss_hash_res = 0;
1587 uint8_t lro_num_seg;
1589 if (consumed_strd == strd_n) {
1590 /* Replace WQE only if the buffer is still in use. */
1591 if (rte_atomic16_read(&buf->refcnt) > 1) {
1592 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1593 /* Release the old buffer. */
1594 mlx5_mprq_buf_free(buf);
1595 } else if (unlikely(rxq->mprq_repl == NULL)) {
1596 struct mlx5_mprq_buf *rep;
1599 * Currently, the MPRQ mempool is out of buffer
1600 * and doing memcpy regardless of the size of Rx
1601 * packet. Retry allocation to get back to
1604 if (!rte_mempool_get(rxq->mprq_mp,
1606 rxq->mprq_repl = rep;
1608 /* Advance to the next WQE. */
1611 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1613 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1614 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1618 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1619 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1621 consumed_strd += strd_cnt;
1622 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1625 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1626 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1628 /* mini-CQE for MPRQ doesn't have hash result. */
1629 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1631 assert(strd_idx < strd_n);
1632 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1633 lro_num_seg = cqe->lro_num_seg;
1635 * Currently configured to receive a packet per a stride. But if
1636 * MTU is adjusted through kernel interface, device could
1637 * consume multiple strides without raising an error. In this
1638 * case, the packet should be dropped because it is bigger than
1639 * the max_rx_pkt_len.
1641 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1642 ++rxq->stats.idropped;
1645 pkt = rte_pktmbuf_alloc(rxq->mp);
1646 if (unlikely(pkt == NULL)) {
1647 ++rxq->stats.rx_nombuf;
1650 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1651 assert((int)len >= (rxq->crc_present << 2));
1652 if (rxq->crc_present)
1653 len -= RTE_ETHER_CRC_LEN;
1654 offset = strd_idx * strd_sz + strd_shift;
1655 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1657 * Memcpy packets to the target mbuf if:
1658 * - The size of packet is smaller than mprq_max_memcpy_len.
1659 * - Out of buffer in the Mempool for Multi-Packet RQ.
1661 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1663 * When memcpy'ing packet due to out-of-buffer, the
1664 * packet must be smaller than the target mbuf.
1666 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1667 rte_pktmbuf_free_seg(pkt);
1668 ++rxq->stats.idropped;
1671 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1672 DATA_LEN(pkt) = len;
1674 rte_iova_t buf_iova;
1675 struct rte_mbuf_ext_shared_info *shinfo;
1676 uint16_t buf_len = strd_cnt * strd_sz;
1679 /* Increment the refcnt of the whole chunk. */
1680 rte_atomic16_add_return(&buf->refcnt, 1);
1681 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1683 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1685 * MLX5 device doesn't use iova but it is necessary in a
1686 * case where the Rx packet is transmitted via a
1689 buf_iova = rte_mempool_virt2iova(buf) +
1690 RTE_PTR_DIFF(buf_addr, buf);
1691 shinfo = &buf->shinfos[strd_idx];
1692 rte_mbuf_ext_refcnt_set(shinfo, 1);
1694 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1695 * attaching the stride to mbuf and more offload flags
1696 * will be added below by calling rxq_cq_to_mbuf().
1697 * Other fields will be overwritten.
1699 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1701 /* Set mbuf head-room. */
1702 pkt->data_off = headroom_sz;
1703 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1705 * Prevent potential overflow due to MTU change through
1708 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1709 rte_pktmbuf_free_seg(pkt);
1710 ++rxq->stats.idropped;
1713 DATA_LEN(pkt) = len;
1715 * LRO packet may consume all the stride memory, in this
1716 * case packet head-room space is not guaranteed so must
1717 * to add an empty mbuf for the head-room.
1719 if (!rxq->strd_headroom_en) {
1720 struct rte_mbuf *headroom_mbuf =
1721 rte_pktmbuf_alloc(rxq->mp);
1723 if (unlikely(headroom_mbuf == NULL)) {
1724 rte_pktmbuf_free_seg(pkt);
1725 ++rxq->stats.rx_nombuf;
1728 PORT(pkt) = rxq->port_id;
1729 NEXT(headroom_mbuf) = pkt;
1730 pkt = headroom_mbuf;
1734 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1735 if (lro_num_seg > 1) {
1736 mlx5_lro_update_hdr(addr, cqe, len);
1737 pkt->ol_flags |= PKT_RX_LRO;
1738 pkt->tso_segsz = strd_sz;
1741 PORT(pkt) = rxq->port_id;
1742 #ifdef MLX5_PMD_SOFT_COUNTERS
1743 /* Increment bytes counter. */
1744 rxq->stats.ibytes += PKT_LEN(pkt);
1746 /* Return packet. */
1750 /* Update the consumer indexes. */
1751 rxq->consumed_strd = consumed_strd;
1753 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1754 if (rq_ci != rxq->rq_ci) {
1757 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1759 #ifdef MLX5_PMD_SOFT_COUNTERS
1760 /* Increment packets counter. */
1761 rxq->stats.ipackets += i;
1767 * Dummy DPDK callback for TX.
1769 * This function is used to temporarily replace the real callback during
1770 * unsafe control operations on the queue, or in case of error.
1773 * Generic pointer to TX queue structure.
1775 * Packets to transmit.
1777 * Number of packets in array.
1780 * Number of packets successfully transmitted (<= pkts_n).
1783 removed_tx_burst(void *dpdk_txq __rte_unused,
1784 struct rte_mbuf **pkts __rte_unused,
1785 uint16_t pkts_n __rte_unused)
1792 * Dummy DPDK callback for RX.
1794 * This function is used to temporarily replace the real callback during
1795 * unsafe control operations on the queue, or in case of error.
1798 * Generic pointer to RX queue structure.
1800 * Array to store received packets.
1802 * Maximum number of packets in array.
1805 * Number of packets successfully received (<= pkts_n).
1808 removed_rx_burst(void *dpdk_txq __rte_unused,
1809 struct rte_mbuf **pkts __rte_unused,
1810 uint16_t pkts_n __rte_unused)
1817 * Vectorized Rx/Tx routines are not compiled in when required vector
1818 * instructions are not supported on a target architecture. The following null
1819 * stubs are needed for linkage when those are not included outside of this file
1820 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1824 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1825 struct rte_mbuf **pkts __rte_unused,
1826 uint16_t pkts_n __rte_unused)
1832 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1838 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1844 * Free the mbufs from the linear array of pointers.
1847 * Pointer to array of packets to be free.
1849 * Number of packets to be freed.
1851 * Configured Tx offloads mask. It is fully defined at
1852 * compile time and may be used for optimization.
1854 static __rte_always_inline void
1855 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1856 unsigned int pkts_n,
1857 unsigned int olx __rte_unused)
1859 struct rte_mempool *pool = NULL;
1860 struct rte_mbuf **p_free = NULL;
1861 struct rte_mbuf *mbuf;
1862 unsigned int n_free = 0;
1865 * The implemented algorithm eliminates
1866 * copying pointers to temporary array
1867 * for rte_mempool_put_bulk() calls.
1874 * Decrement mbuf reference counter, detach
1875 * indirect and external buffers if needed.
1877 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1878 if (likely(mbuf != NULL)) {
1879 assert(mbuf == *pkts);
1880 if (likely(n_free != 0)) {
1881 if (unlikely(pool != mbuf->pool))
1882 /* From different pool. */
1885 /* Start new scan array. */
1892 if (unlikely(pkts_n == 0)) {
1898 * This happens if mbuf is still referenced.
1899 * We can't put it back to the pool, skip.
1903 if (unlikely(n_free != 0))
1904 /* There is some array to free.*/
1906 if (unlikely(pkts_n == 0))
1907 /* Last mbuf, nothing to free. */
1913 * This loop is implemented to avoid multiple
1914 * inlining of rte_mempool_put_bulk().
1920 * Free the array of pre-freed mbufs
1921 * belonging to the same memory pool.
1923 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1924 if (unlikely(mbuf != NULL)) {
1925 /* There is the request to start new scan. */
1930 if (likely(pkts_n != 0))
1933 * This is the last mbuf to be freed.
1934 * Do one more loop iteration to complete.
1935 * This is rare case of the last unique mbuf.
1940 if (likely(pkts_n == 0))
1949 * Free the mbuf from the elts ring buffer till new tail.
1952 * Pointer to Tx queue structure.
1954 * Index in elts to free up to, becomes new elts tail.
1956 * Configured Tx offloads mask. It is fully defined at
1957 * compile time and may be used for optimization.
1959 static __rte_always_inline void
1960 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1962 unsigned int olx __rte_unused)
1964 uint16_t n_elts = tail - txq->elts_tail;
1967 assert(n_elts <= txq->elts_s);
1969 * Implement a loop to support ring buffer wraparound
1970 * with single inlining of mlx5_tx_free_mbuf().
1975 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1976 part = RTE_MIN(part, n_elts);
1978 assert(part <= txq->elts_s);
1979 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1981 txq->elts_tail += part;
1987 * Store the mbuf being sent into elts ring buffer.
1988 * On Tx completion these mbufs will be freed.
1991 * Pointer to Tx queue structure.
1993 * Pointer to array of packets to be stored.
1995 * Number of packets to be stored.
1997 * Configured Tx offloads mask. It is fully defined at
1998 * compile time and may be used for optimization.
2000 static __rte_always_inline void
2001 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
2002 struct rte_mbuf **restrict pkts,
2003 unsigned int pkts_n,
2004 unsigned int olx __rte_unused)
2007 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2011 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2013 assert(part <= txq->elts_s);
2014 /* This code is a good candidate for vectorizing with SIMD. */
2015 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2017 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2018 txq->elts_head += pkts_n;
2019 if (unlikely(part < pkts_n))
2020 /* The copy is wrapping around the elts array. */
2021 rte_memcpy((void *)elts, (void *)(pkts + part),
2022 (pkts_n - part) * sizeof(struct rte_mbuf *));
2026 * Update completion queue consuming index via doorbell
2027 * and flush the completed data buffers.
2030 * Pointer to TX queue structure.
2031 * @param valid CQE pointer
2032 * if not NULL update txq->wqe_pi and flush the buffers
2034 * Configured Tx offloads mask. It is fully defined at
2035 * compile time and may be used for optimization.
2037 static __rte_always_inline void
2038 mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
2039 volatile struct mlx5_cqe *last_cqe,
2040 unsigned int olx __rte_unused)
2042 if (likely(last_cqe != NULL)) {
2045 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2046 tail = ((volatile struct mlx5_wqe_cseg *)
2047 (txq->wqes + (txq->wqe_pi & txq->wqe_m)))->misc;
2048 if (likely(tail != txq->elts_tail)) {
2049 mlx5_tx_free_elts(txq, tail, olx);
2050 assert(tail == txq->elts_tail);
2056 * Manage TX completions. This routine checks the CQ for
2057 * arrived CQEs, deduces the last accomplished WQE in SQ,
2058 * updates SQ producing index and frees all completed mbufs.
2061 * Pointer to TX queue structure.
2063 * Configured Tx offloads mask. It is fully defined at
2064 * compile time and may be used for optimization.
2066 * NOTE: not inlined intentionally, it makes tx_burst
2067 * routine smaller, simple and faster - from experiments.
2070 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2071 unsigned int olx __rte_unused)
2073 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2074 volatile struct mlx5_cqe *last_cqe = NULL;
2075 uint16_t ci = txq->cq_ci;
2078 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2079 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2081 volatile struct mlx5_cqe *cqe;
2083 cqe = &txq->cqes[ci & txq->cqe_m];
2084 ret = check_cqe(cqe, txq->cqe_s, ci);
2085 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2086 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2087 /* No new CQEs in completion queue. */
2088 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2092 * Some error occurred, try to restart.
2093 * We have no barrier after WQE related Doorbell
2094 * written, make sure all writes are completed
2095 * here, before we might perform SQ reset.
2098 ret = mlx5_tx_error_cqe_handle
2099 (txq, (volatile struct mlx5_err_cqe *)cqe);
2100 if (unlikely(ret < 0)) {
2102 * Some error occurred on queue error
2103 * handling, we do not advance the index
2104 * here, allowing to retry on next call.
2109 * We are going to fetch all entries with
2110 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2115 /* Normal transmit completion. */
2123 * We have to restrict the amount of processed CQEs
2124 * in one tx_burst routine call. The CQ may be large
2125 * and many CQEs may be updated by the NIC in one
2126 * transaction. Buffers freeing is time consuming,
2127 * multiple iterations may introduce significant
2133 if (likely(ci != txq->cq_ci)) {
2135 * Update completion queue consuming index
2136 * and ring doorbell to notify hardware.
2138 rte_compiler_barrier();
2140 *txq->cq_db = rte_cpu_to_be_32(ci);
2141 mlx5_tx_comp_flush(txq, last_cqe, olx);
2146 * Check if the completion request flag should be set in the last WQE.
2147 * Both pushed mbufs and WQEs are monitored and the completion request
2148 * flag is set if any of thresholds is reached.
2151 * Pointer to TX queue structure.
2153 * Pointer to burst routine local context.
2155 * Configured Tx offloads mask. It is fully defined at
2156 * compile time and may be used for optimization.
2158 static __rte_always_inline void
2159 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2160 struct mlx5_txq_local *restrict loc,
2163 uint16_t head = txq->elts_head;
2166 part = MLX5_TXOFF_CONFIG(INLINE) ?
2167 0 : loc->pkts_sent - loc->pkts_copy;
2169 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2170 (MLX5_TXOFF_CONFIG(INLINE) &&
2171 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2172 volatile struct mlx5_wqe *last = loc->wqe_last;
2174 txq->elts_comp = head;
2175 if (MLX5_TXOFF_CONFIG(INLINE))
2176 txq->wqe_comp = txq->wqe_ci;
2177 /* Request unconditional completion on last WQE. */
2178 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2179 MLX5_COMP_MODE_OFFSET);
2180 /* Save elts_head in unused "immediate" field of WQE. */
2181 last->cseg.misc = head;
2183 * A CQE slot must always be available. Count the
2184 * issued CEQ "always" request instead of production
2185 * index due to here can be CQE with errors and
2186 * difference with ci may become inconsistent.
2188 assert(txq->cqe_s > ++txq->cq_pi);
2193 * DPDK callback to check the status of a tx descriptor.
2198 * The index of the descriptor in the ring.
2201 * The status of the tx descriptor.
2204 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2206 struct mlx5_txq_data *restrict txq = tx_queue;
2209 mlx5_tx_handle_completion(txq, 0);
2210 used = txq->elts_head - txq->elts_tail;
2212 return RTE_ETH_TX_DESC_FULL;
2213 return RTE_ETH_TX_DESC_DONE;
2217 * Build the Control Segment with specified opcode:
2218 * - MLX5_OPCODE_SEND
2219 * - MLX5_OPCODE_ENHANCED_MPSW
2223 * Pointer to TX queue structure.
2225 * Pointer to burst routine local context.
2227 * Pointer to WQE to fill with built Control Segment.
2229 * Supposed length of WQE in segments.
2231 * SQ WQE opcode to put into Control Segment.
2233 * Configured Tx offloads mask. It is fully defined at
2234 * compile time and may be used for optimization.
2236 static __rte_always_inline void
2237 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2238 struct mlx5_txq_local *restrict loc __rte_unused,
2239 struct mlx5_wqe *restrict wqe,
2241 unsigned int opcode,
2242 unsigned int olx __rte_unused)
2244 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2246 /* For legacy MPW replace the EMPW by TSO with modifier. */
2247 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2248 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2249 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2250 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2251 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2252 MLX5_COMP_MODE_OFFSET);
2253 cs->misc = RTE_BE32(0);
2257 * Build the Ethernet Segment without inlined data.
2258 * Supports Software Parser, Checksums and VLAN
2259 * insertion Tx offload features.
2262 * Pointer to TX queue structure.
2264 * Pointer to burst routine local context.
2266 * Pointer to WQE to fill with built Ethernet Segment.
2268 * Configured Tx offloads mask. It is fully defined at
2269 * compile time and may be used for optimization.
2271 static __rte_always_inline void
2272 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2273 struct mlx5_txq_local *restrict loc,
2274 struct mlx5_wqe *restrict wqe,
2277 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2281 * Calculate and set check sum flags first, dword field
2282 * in segment may be shared with Software Parser flags.
2284 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2285 es->flags = rte_cpu_to_le_32(csum);
2287 * Calculate and set Software Parser offsets and flags.
2288 * These flags a set for custom UDP and IP tunnel packets.
2290 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2291 /* Fill metadata field if needed. */
2292 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2293 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2294 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2295 /* Engage VLAN tag insertion feature if requested. */
2296 if (MLX5_TXOFF_CONFIG(VLAN) &&
2297 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2299 * We should get here only if device support
2300 * this feature correctly.
2302 assert(txq->vlan_en);
2303 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2304 loc->mbuf->vlan_tci);
2306 es->inline_hdr = RTE_BE32(0);
2311 * Build the Ethernet Segment with minimal inlined data
2312 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2313 * used to fill the gap in single WQEBB WQEs.
2314 * Supports Software Parser, Checksums and VLAN
2315 * insertion Tx offload features.
2318 * Pointer to TX queue structure.
2320 * Pointer to burst routine local context.
2322 * Pointer to WQE to fill with built Ethernet Segment.
2324 * Length of VLAN tag insertion if any.
2326 * Configured Tx offloads mask. It is fully defined at
2327 * compile time and may be used for optimization.
2329 static __rte_always_inline void
2330 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2331 struct mlx5_txq_local *restrict loc,
2332 struct mlx5_wqe *restrict wqe,
2336 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2338 uint8_t *psrc, *pdst;
2341 * Calculate and set check sum flags first, dword field
2342 * in segment may be shared with Software Parser flags.
2344 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2345 es->flags = rte_cpu_to_le_32(csum);
2347 * Calculate and set Software Parser offsets and flags.
2348 * These flags a set for custom UDP and IP tunnel packets.
2350 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2351 /* Fill metadata field if needed. */
2352 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2353 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2354 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2355 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2357 sizeof(rte_v128u32_t)),
2358 "invalid Ethernet Segment data size");
2359 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2361 sizeof(struct rte_vlan_hdr) +
2362 2 * RTE_ETHER_ADDR_LEN),
2363 "invalid Ethernet Segment data size");
2364 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2365 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2366 es->inline_data = *(unaligned_uint16_t *)psrc;
2367 psrc += sizeof(uint16_t);
2368 pdst = (uint8_t *)(es + 1);
2369 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2370 /* Implement VLAN tag insertion as part inline data. */
2371 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2372 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2373 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2374 /* Insert VLAN ethertype + VLAN tag. */
2375 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2376 ((RTE_ETHER_TYPE_VLAN << 16) |
2377 loc->mbuf->vlan_tci);
2378 pdst += sizeof(struct rte_vlan_hdr);
2379 /* Copy the rest two bytes from packet data. */
2380 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2381 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2383 /* Fill the gap in the title WQEBB with inline data. */
2384 rte_mov16(pdst, psrc);
2389 * Build the Ethernet Segment with entire packet
2390 * data inlining. Checks the boundary of WQEBB and
2391 * ring buffer wrapping, supports Software Parser,
2392 * Checksums and VLAN insertion Tx offload features.
2395 * Pointer to TX queue structure.
2397 * Pointer to burst routine local context.
2399 * Pointer to WQE to fill with built Ethernet Segment.
2401 * Length of VLAN tag insertion if any.
2403 * Length of data to inline (VLAN included, if any).
2405 * TSO flag, set mss field from the packet.
2407 * Configured Tx offloads mask. It is fully defined at
2408 * compile time and may be used for optimization.
2411 * Pointer to the next Data Segment (aligned and wrapped around).
2413 static __rte_always_inline struct mlx5_wqe_dseg *
2414 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2415 struct mlx5_txq_local *restrict loc,
2416 struct mlx5_wqe *restrict wqe,
2422 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2424 uint8_t *psrc, *pdst;
2428 * Calculate and set check sum flags first, dword field
2429 * in segment may be shared with Software Parser flags.
2431 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2434 csum |= loc->mbuf->tso_segsz;
2435 es->flags = rte_cpu_to_be_32(csum);
2437 es->flags = rte_cpu_to_le_32(csum);
2440 * Calculate and set Software Parser offsets and flags.
2441 * These flags a set for custom UDP and IP tunnel packets.
2443 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2444 /* Fill metadata field if needed. */
2445 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2446 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2447 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2448 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2450 sizeof(rte_v128u32_t)),
2451 "invalid Ethernet Segment data size");
2452 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2454 sizeof(struct rte_vlan_hdr) +
2455 2 * RTE_ETHER_ADDR_LEN),
2456 "invalid Ethernet Segment data size");
2457 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2458 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2459 es->inline_data = *(unaligned_uint16_t *)psrc;
2460 psrc += sizeof(uint16_t);
2461 pdst = (uint8_t *)(es + 1);
2462 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2463 /* Implement VLAN tag insertion as part inline data. */
2464 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2465 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2466 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2467 /* Insert VLAN ethertype + VLAN tag. */
2468 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2469 ((RTE_ETHER_TYPE_VLAN << 16) |
2470 loc->mbuf->vlan_tci);
2471 pdst += sizeof(struct rte_vlan_hdr);
2472 /* Copy the rest two bytes from packet data. */
2473 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2474 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2475 psrc += sizeof(uint16_t);
2477 /* Fill the gap in the title WQEBB with inline data. */
2478 rte_mov16(pdst, psrc);
2479 psrc += sizeof(rte_v128u32_t);
2481 pdst = (uint8_t *)(es + 2);
2482 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2483 assert(pdst < (uint8_t *)txq->wqes_end);
2484 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2486 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2487 return (struct mlx5_wqe_dseg *)pdst;
2490 * The WQEBB space availability is checked by caller.
2491 * Here we should be aware of WQE ring buffer wraparound only.
2493 part = (uint8_t *)txq->wqes_end - pdst;
2494 part = RTE_MIN(part, inlen);
2496 rte_memcpy(pdst, psrc, part);
2498 if (likely(!inlen)) {
2500 * If return value is not used by the caller
2501 * the code below will be optimized out.
2504 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2505 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2506 pdst = (uint8_t *)txq->wqes;
2507 return (struct mlx5_wqe_dseg *)pdst;
2509 pdst = (uint8_t *)txq->wqes;
2516 * Copy data from chain of mbuf to the specified linear buffer.
2517 * Checksums and VLAN insertion Tx offload features. If data
2518 * from some mbuf copied completely this mbuf is freed. Local
2519 * structure is used to keep the byte stream state.
2522 * Pointer to the destination linear buffer.
2524 * Pointer to burst routine local context.
2526 * Length of data to be copied.
2528 * Configured Tx offloads mask. It is fully defined at
2529 * compile time and may be used for optimization.
2531 static __rte_always_inline void
2532 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2533 struct mlx5_txq_local *restrict loc,
2535 unsigned int olx __rte_unused)
2537 struct rte_mbuf *mbuf;
2538 unsigned int part, dlen;
2543 /* Allow zero length packets, must check first. */
2544 dlen = rte_pktmbuf_data_len(loc->mbuf);
2545 if (dlen <= loc->mbuf_off) {
2546 /* Exhausted packet, just free. */
2548 loc->mbuf = mbuf->next;
2549 rte_pktmbuf_free_seg(mbuf);
2551 assert(loc->mbuf_nseg > 1);
2556 dlen -= loc->mbuf_off;
2557 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2559 part = RTE_MIN(len, dlen);
2560 rte_memcpy(pdst, psrc, part);
2561 loc->mbuf_off += part;
2564 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2566 /* Exhausted packet, just free. */
2568 loc->mbuf = mbuf->next;
2569 rte_pktmbuf_free_seg(mbuf);
2571 assert(loc->mbuf_nseg >= 1);
2581 * Build the Ethernet Segment with inlined data from
2582 * multi-segment packet. Checks the boundary of WQEBB
2583 * and ring buffer wrapping, supports Software Parser,
2584 * Checksums and VLAN insertion Tx offload features.
2587 * Pointer to TX queue structure.
2589 * Pointer to burst routine local context.
2591 * Pointer to WQE to fill with built Ethernet Segment.
2593 * Length of VLAN tag insertion if any.
2595 * Length of data to inline (VLAN included, if any).
2597 * TSO flag, set mss field from the packet.
2599 * Configured Tx offloads mask. It is fully defined at
2600 * compile time and may be used for optimization.
2603 * Pointer to the next Data Segment (aligned and
2604 * possible NOT wrapped around - caller should do
2605 * wrapping check on its own).
2607 static __rte_always_inline struct mlx5_wqe_dseg *
2608 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2609 struct mlx5_txq_local *restrict loc,
2610 struct mlx5_wqe *restrict wqe,
2616 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2622 * Calculate and set check sum flags first, uint32_t field
2623 * in segment may be shared with Software Parser flags.
2625 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2628 csum |= loc->mbuf->tso_segsz;
2629 es->flags = rte_cpu_to_be_32(csum);
2631 es->flags = rte_cpu_to_le_32(csum);
2634 * Calculate and set Software Parser offsets and flags.
2635 * These flags a set for custom UDP and IP tunnel packets.
2637 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2638 /* Fill metadata field if needed. */
2639 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2640 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2641 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2642 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2644 sizeof(rte_v128u32_t)),
2645 "invalid Ethernet Segment data size");
2646 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2648 sizeof(struct rte_vlan_hdr) +
2649 2 * RTE_ETHER_ADDR_LEN),
2650 "invalid Ethernet Segment data size");
2651 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2652 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2653 pdst = (uint8_t *)&es->inline_data;
2654 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2655 /* Implement VLAN tag insertion as part inline data. */
2656 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2657 pdst += 2 * RTE_ETHER_ADDR_LEN;
2658 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2659 ((RTE_ETHER_TYPE_VLAN << 16) |
2660 loc->mbuf->vlan_tci);
2661 pdst += sizeof(struct rte_vlan_hdr);
2662 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2664 assert(pdst < (uint8_t *)txq->wqes_end);
2666 * The WQEBB space availability is checked by caller.
2667 * Here we should be aware of WQE ring buffer wraparound only.
2669 part = (uint8_t *)txq->wqes_end - pdst;
2670 part = RTE_MIN(part, inlen);
2673 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2675 if (likely(!inlen)) {
2677 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2678 return (struct mlx5_wqe_dseg *)pdst;
2680 pdst = (uint8_t *)txq->wqes;
2686 * Build the Data Segment of pointer type.
2689 * Pointer to TX queue structure.
2691 * Pointer to burst routine local context.
2693 * Pointer to WQE to fill with built Data Segment.
2695 * Data buffer to point.
2697 * Data buffer length.
2699 * Configured Tx offloads mask. It is fully defined at
2700 * compile time and may be used for optimization.
2702 static __rte_always_inline void
2703 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2704 struct mlx5_txq_local *restrict loc,
2705 struct mlx5_wqe_dseg *restrict dseg,
2708 unsigned int olx __rte_unused)
2712 dseg->bcount = rte_cpu_to_be_32(len);
2713 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2714 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2718 * Build the Data Segment of pointer type or inline
2719 * if data length is less than buffer in minimal
2720 * Data Segment size.
2723 * Pointer to TX queue structure.
2725 * Pointer to burst routine local context.
2727 * Pointer to WQE to fill with built Data Segment.
2729 * Data buffer to point.
2731 * Data buffer length.
2733 * Configured Tx offloads mask. It is fully defined at
2734 * compile time and may be used for optimization.
2736 static __rte_always_inline void
2737 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2738 struct mlx5_txq_local *restrict loc,
2739 struct mlx5_wqe_dseg *restrict dseg,
2742 unsigned int olx __rte_unused)
2748 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2749 dseg->bcount = rte_cpu_to_be_32(len);
2750 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2751 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2755 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2756 /* Unrolled implementation of generic rte_memcpy. */
2757 dst = (uintptr_t)&dseg->inline_data[0];
2758 src = (uintptr_t)buf;
2760 #ifdef RTE_ARCH_STRICT_ALIGN
2761 assert(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2762 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2763 dst += sizeof(uint32_t);
2764 src += sizeof(uint32_t);
2765 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2766 dst += sizeof(uint32_t);
2767 src += sizeof(uint32_t);
2769 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2770 dst += sizeof(uint64_t);
2771 src += sizeof(uint64_t);
2775 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2776 dst += sizeof(uint32_t);
2777 src += sizeof(uint32_t);
2780 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2781 dst += sizeof(uint16_t);
2782 src += sizeof(uint16_t);
2785 *(uint8_t *)dst = *(uint8_t *)src;
2789 * Build the Data Segment of inlined data from single
2790 * segment packet, no VLAN insertion.
2793 * Pointer to TX queue structure.
2795 * Pointer to burst routine local context.
2797 * Pointer to WQE to fill with built Data Segment.
2799 * Data buffer to point.
2801 * Data buffer length.
2803 * Configured Tx offloads mask. It is fully defined at
2804 * compile time and may be used for optimization.
2807 * Pointer to the next Data Segment after inlined data.
2808 * Ring buffer wraparound check is needed. We do not
2809 * do it here because it may not be needed for the
2810 * last packet in the eMPW session.
2812 static __rte_always_inline struct mlx5_wqe_dseg *
2813 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2814 struct mlx5_txq_local *restrict loc __rte_unused,
2815 struct mlx5_wqe_dseg *restrict dseg,
2818 unsigned int olx __rte_unused)
2823 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2824 pdst = &dseg->inline_data[0];
2826 * The WQEBB space availability is checked by caller.
2827 * Here we should be aware of WQE ring buffer wraparound only.
2829 part = (uint8_t *)txq->wqes_end - pdst;
2830 part = RTE_MIN(part, len);
2832 rte_memcpy(pdst, buf, part);
2836 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2837 /* Note: no final wraparound check here. */
2838 return (struct mlx5_wqe_dseg *)pdst;
2840 pdst = (uint8_t *)txq->wqes;
2847 * Build the Data Segment of inlined data from single
2848 * segment packet with VLAN insertion.
2851 * Pointer to TX queue structure.
2853 * Pointer to burst routine local context.
2855 * Pointer to the dseg fill with built Data Segment.
2857 * Data buffer to point.
2859 * Data buffer length.
2861 * Configured Tx offloads mask. It is fully defined at
2862 * compile time and may be used for optimization.
2865 * Pointer to the next Data Segment after inlined data.
2866 * Ring buffer wraparound check is needed.
2868 static __rte_always_inline struct mlx5_wqe_dseg *
2869 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2870 struct mlx5_txq_local *restrict loc __rte_unused,
2871 struct mlx5_wqe_dseg *restrict dseg,
2874 unsigned int olx __rte_unused)
2880 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2881 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2882 (2 * RTE_ETHER_ADDR_LEN),
2883 "invalid Data Segment data size");
2884 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2885 MLX5_ETH_WQE_DATA_INLINE);
2886 pdst = &dseg->inline_data[0];
2887 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2888 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2889 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2890 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2891 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2892 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2893 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2894 pdst = (uint8_t *)txq->wqes;
2895 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2896 loc->mbuf->vlan_tci);
2897 pdst += sizeof(struct rte_vlan_hdr);
2899 * The WQEBB space availability is checked by caller.
2900 * Here we should be aware of WQE ring buffer wraparound only.
2902 part = (uint8_t *)txq->wqes_end - pdst;
2903 part = RTE_MIN(part, len);
2905 rte_memcpy(pdst, buf, part);
2909 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2910 /* Note: no final wraparound check here. */
2911 return (struct mlx5_wqe_dseg *)pdst;
2913 pdst = (uint8_t *)txq->wqes;
2920 * Build the Ethernet Segment with optionally inlined data with
2921 * VLAN insertion and following Data Segments (if any) from
2922 * multi-segment packet. Used by ordinary send and TSO.
2925 * Pointer to TX queue structure.
2927 * Pointer to burst routine local context.
2929 * Pointer to WQE to fill with built Ethernet/Data Segments.
2931 * Length of VLAN header to insert, 0 means no VLAN insertion.
2933 * Data length to inline. For TSO this parameter specifies
2934 * exact value, for ordinary send routine can be aligned by
2935 * caller to provide better WQE space saving and data buffer
2936 * start address alignment. This length includes VLAN header
2939 * Zero means ordinary send, inlined data can be extended,
2940 * otherwise this is TSO, inlined data length is fixed.
2942 * Configured Tx offloads mask. It is fully defined at
2943 * compile time and may be used for optimization.
2946 * Actual size of built WQE in segments.
2948 static __rte_always_inline unsigned int
2949 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2950 struct mlx5_txq_local *restrict loc,
2951 struct mlx5_wqe *restrict wqe,
2955 unsigned int olx __rte_unused)
2957 struct mlx5_wqe_dseg *restrict dseg;
2960 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2961 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2964 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2965 if (!loc->mbuf_nseg)
2968 * There are still some mbuf remaining, not inlined.
2969 * The first mbuf may be partially inlined and we
2970 * must process the possible non-zero data offset.
2972 if (loc->mbuf_off) {
2977 * Exhausted packets must be dropped before.
2978 * Non-zero offset means there are some data
2979 * remained in the packet.
2981 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2982 assert(rte_pktmbuf_data_len(loc->mbuf));
2983 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2985 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2987 * Build the pointer/minimal data Data Segment.
2988 * Do ring buffer wrapping check in advance.
2990 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2991 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2992 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2993 /* Store the mbuf to be freed on completion. */
2994 assert(loc->elts_free);
2995 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2998 if (--loc->mbuf_nseg == 0)
3000 loc->mbuf = loc->mbuf->next;
3004 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3005 struct rte_mbuf *mbuf;
3007 /* Zero length segment found, just skip. */
3009 loc->mbuf = loc->mbuf->next;
3010 rte_pktmbuf_free_seg(mbuf);
3011 if (--loc->mbuf_nseg == 0)
3014 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3015 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3018 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3019 rte_pktmbuf_data_len(loc->mbuf), olx);
3020 assert(loc->elts_free);
3021 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3024 if (--loc->mbuf_nseg == 0)
3026 loc->mbuf = loc->mbuf->next;
3031 /* Calculate actual segments used from the dseg pointer. */
3032 if ((uintptr_t)wqe < (uintptr_t)dseg)
3033 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3035 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3036 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3041 * Tx one packet function for multi-segment TSO. Supports all
3042 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3043 * sends one packet per WQE.
3045 * This routine is responsible for storing processed mbuf
3046 * into elts ring buffer and update elts_head.
3049 * Pointer to TX queue structure.
3051 * Pointer to burst routine local context.
3053 * Configured Tx offloads mask. It is fully defined at
3054 * compile time and may be used for optimization.
3057 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3058 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3059 * Local context variables partially updated.
3061 static __rte_always_inline enum mlx5_txcmp_code
3062 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3063 struct mlx5_txq_local *restrict loc,
3066 struct mlx5_wqe *restrict wqe;
3067 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3070 * Calculate data length to be inlined to estimate
3071 * the required space in WQE ring buffer.
3073 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3074 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3075 vlan = sizeof(struct rte_vlan_hdr);
3076 inlen = loc->mbuf->l2_len + vlan +
3077 loc->mbuf->l3_len + loc->mbuf->l4_len;
3078 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3079 return MLX5_TXCMP_CODE_ERROR;
3080 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3081 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3082 /* Packet must contain all TSO headers. */
3083 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3084 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3085 inlen > (dlen + vlan)))
3086 return MLX5_TXCMP_CODE_ERROR;
3087 assert(inlen >= txq->inlen_mode);
3089 * Check whether there are enough free WQEBBs:
3091 * - Ethernet Segment
3092 * - First Segment of inlined Ethernet data
3093 * - ... data continued ...
3094 * - Data Segments of pointer/min inline type
3096 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3097 MLX5_ESEG_MIN_INLINE_SIZE +
3099 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3100 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3101 return MLX5_TXCMP_CODE_EXIT;
3102 /* Check for maximal WQE size. */
3103 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3104 return MLX5_TXCMP_CODE_ERROR;
3105 #ifdef MLX5_PMD_SOFT_COUNTERS
3106 /* Update sent data bytes/packets counters. */
3107 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3108 loc->mbuf->tso_segsz;
3110 * One will be added for mbuf itself
3111 * at the end of the mlx5_tx_burst from
3112 * loc->pkts_sent field.
3115 txq->stats.opackets += ntcp;
3116 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3118 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3119 loc->wqe_last = wqe;
3120 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3121 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3122 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3123 txq->wqe_ci += (ds + 3) / 4;
3124 loc->wqe_free -= (ds + 3) / 4;
3125 return MLX5_TXCMP_CODE_MULTI;
3129 * Tx one packet function for multi-segment SEND. Supports all
3130 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3131 * sends one packet per WQE, without any data inlining in
3134 * This routine is responsible for storing processed mbuf
3135 * into elts ring buffer and update elts_head.
3138 * Pointer to TX queue structure.
3140 * Pointer to burst routine local context.
3142 * Configured Tx offloads mask. It is fully defined at
3143 * compile time and may be used for optimization.
3146 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3147 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3148 * Local context variables partially updated.
3150 static __rte_always_inline enum mlx5_txcmp_code
3151 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3152 struct mlx5_txq_local *restrict loc,
3155 struct mlx5_wqe_dseg *restrict dseg;
3156 struct mlx5_wqe *restrict wqe;
3157 unsigned int ds, nseg;
3159 assert(NB_SEGS(loc->mbuf) > 1);
3161 * No inline at all, it means the CPU cycles saving
3162 * is prioritized at configuration, we should not
3163 * copy any packet data to WQE.
3165 nseg = NB_SEGS(loc->mbuf);
3167 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3168 return MLX5_TXCMP_CODE_EXIT;
3169 /* Check for maximal WQE size. */
3170 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3171 return MLX5_TXCMP_CODE_ERROR;
3173 * Some Tx offloads may cause an error if
3174 * packet is not long enough, check against
3175 * assumed minimal length.
3177 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3178 return MLX5_TXCMP_CODE_ERROR;
3179 #ifdef MLX5_PMD_SOFT_COUNTERS
3180 /* Update sent data bytes counter. */
3181 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3182 if (MLX5_TXOFF_CONFIG(VLAN) &&
3183 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3184 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3187 * SEND WQE, one WQEBB:
3188 * - Control Segment, SEND opcode
3189 * - Ethernet Segment, optional VLAN, no inline
3190 * - Data Segments, pointer only type
3192 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3193 loc->wqe_last = wqe;
3194 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3195 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3196 dseg = &wqe->dseg[0];
3198 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3199 struct rte_mbuf *mbuf;
3202 * Zero length segment found, have to
3203 * correct total size of WQE in segments.
3204 * It is supposed to be rare occasion, so
3205 * in normal case (no zero length segments)
3206 * we avoid extra writing to the Control
3210 wqe->cseg.sq_ds -= RTE_BE32(1);
3212 loc->mbuf = mbuf->next;
3213 rte_pktmbuf_free_seg(mbuf);
3219 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3220 rte_pktmbuf_data_len(loc->mbuf), olx);
3221 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3226 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3227 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3228 loc->mbuf = loc->mbuf->next;
3231 txq->wqe_ci += (ds + 3) / 4;
3232 loc->wqe_free -= (ds + 3) / 4;
3233 return MLX5_TXCMP_CODE_MULTI;
3237 * Tx one packet function for multi-segment SEND. Supports all
3238 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3239 * sends one packet per WQE, with data inlining in
3240 * Ethernet Segment and minimal Data Segments.
3242 * This routine is responsible for storing processed mbuf
3243 * into elts ring buffer and update elts_head.
3246 * Pointer to TX queue structure.
3248 * Pointer to burst routine local context.
3250 * Configured Tx offloads mask. It is fully defined at
3251 * compile time and may be used for optimization.
3254 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3255 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3256 * Local context variables partially updated.
3258 static __rte_always_inline enum mlx5_txcmp_code
3259 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3260 struct mlx5_txq_local *restrict loc,
3263 struct mlx5_wqe *restrict wqe;
3264 unsigned int ds, inlen, dlen, vlan = 0;
3266 assert(MLX5_TXOFF_CONFIG(INLINE));
3267 assert(NB_SEGS(loc->mbuf) > 1);
3269 * First calculate data length to be inlined
3270 * to estimate the required space for WQE.
3272 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3273 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3274 vlan = sizeof(struct rte_vlan_hdr);
3275 inlen = dlen + vlan;
3276 /* Check against minimal length. */
3277 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3278 return MLX5_TXCMP_CODE_ERROR;
3279 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3280 if (inlen > txq->inlen_send) {
3281 struct rte_mbuf *mbuf;
3286 * Packet length exceeds the allowed inline
3287 * data length, check whether the minimal
3288 * inlining is required.
3290 if (txq->inlen_mode) {
3291 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3292 assert(txq->inlen_mode <= txq->inlen_send);
3293 inlen = txq->inlen_mode;
3295 if (!vlan || txq->vlan_en) {
3297 * VLAN insertion will be done inside by HW.
3298 * It is not utmost effective - VLAN flag is
3299 * checked twice, but we should proceed the
3300 * inlining length correctly and take into
3301 * account the VLAN header being inserted.
3303 return mlx5_tx_packet_multi_send
3306 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3309 * Now we know the minimal amount of data is requested
3310 * to inline. Check whether we should inline the buffers
3311 * from the chain beginning to eliminate some mbufs.
3314 nxlen = rte_pktmbuf_data_len(mbuf);
3315 if (unlikely(nxlen <= txq->inlen_send)) {
3316 /* We can inline first mbuf at least. */
3317 if (nxlen < inlen) {
3320 /* Scan mbufs till inlen filled. */
3325 nxlen = rte_pktmbuf_data_len(mbuf);
3327 } while (unlikely(nxlen < inlen));
3328 if (unlikely(nxlen > txq->inlen_send)) {
3329 /* We cannot inline entire mbuf. */
3330 smlen = inlen - smlen;
3331 start = rte_pktmbuf_mtod_offset
3332 (mbuf, uintptr_t, smlen);
3339 /* There should be not end of packet. */
3341 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3342 } while (unlikely(nxlen < txq->inlen_send));
3344 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3346 * Check whether we can do inline to align start
3347 * address of data buffer to cacheline.
3350 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3351 if (unlikely(start)) {
3353 if (start <= txq->inlen_send)
3358 * Check whether there are enough free WQEBBs:
3360 * - Ethernet Segment
3361 * - First Segment of inlined Ethernet data
3362 * - ... data continued ...
3363 * - Data Segments of pointer/min inline type
3365 * Estimate the number of Data Segments conservatively,
3366 * supposing no any mbufs is being freed during inlining.
3368 assert(inlen <= txq->inlen_send);
3369 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3370 MLX5_ESEG_MIN_INLINE_SIZE +
3372 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3373 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3374 return MLX5_TXCMP_CODE_EXIT;
3375 /* Check for maximal WQE size. */
3376 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3377 return MLX5_TXCMP_CODE_ERROR;
3378 #ifdef MLX5_PMD_SOFT_COUNTERS
3379 /* Update sent data bytes/packets counters. */
3380 txq->stats.obytes += dlen + vlan;
3382 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3383 loc->wqe_last = wqe;
3384 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3385 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3386 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3387 txq->wqe_ci += (ds + 3) / 4;
3388 loc->wqe_free -= (ds + 3) / 4;
3389 return MLX5_TXCMP_CODE_MULTI;
3393 * Tx burst function for multi-segment packets. Supports all
3394 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3395 * sends one packet per WQE. Function stops sending if it
3396 * encounters the single-segment packet.
3398 * This routine is responsible for storing processed mbuf
3399 * into elts ring buffer and update elts_head.
3402 * Pointer to TX queue structure.
3404 * Packets to transmit.
3406 * Number of packets in array.
3408 * Pointer to burst routine local context.
3410 * Configured Tx offloads mask. It is fully defined at
3411 * compile time and may be used for optimization.
3414 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3415 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3416 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3417 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3418 * Local context variables updated.
3420 static __rte_always_inline enum mlx5_txcmp_code
3421 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3422 struct rte_mbuf **restrict pkts,
3423 unsigned int pkts_n,
3424 struct mlx5_txq_local *restrict loc,
3427 assert(loc->elts_free && loc->wqe_free);
3428 assert(pkts_n > loc->pkts_sent);
3429 pkts += loc->pkts_sent + 1;
3430 pkts_n -= loc->pkts_sent;
3432 enum mlx5_txcmp_code ret;
3434 assert(NB_SEGS(loc->mbuf) > 1);
3436 * Estimate the number of free elts quickly but
3437 * conservatively. Some segment may be fully inlined
3438 * and freed, ignore this here - precise estimation
3441 if (loc->elts_free < NB_SEGS(loc->mbuf))
3442 return MLX5_TXCMP_CODE_EXIT;
3443 if (MLX5_TXOFF_CONFIG(TSO) &&
3444 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3445 /* Proceed with multi-segment TSO. */
3446 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3447 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3448 /* Proceed with multi-segment SEND with inlining. */
3449 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3451 /* Proceed with multi-segment SEND w/o inlining. */
3452 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3454 if (ret == MLX5_TXCMP_CODE_EXIT)
3455 return MLX5_TXCMP_CODE_EXIT;
3456 if (ret == MLX5_TXCMP_CODE_ERROR)
3457 return MLX5_TXCMP_CODE_ERROR;
3458 /* WQE is built, go to the next packet. */
3461 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3462 return MLX5_TXCMP_CODE_EXIT;
3463 loc->mbuf = *pkts++;
3465 rte_prefetch0(*pkts);
3466 if (likely(NB_SEGS(loc->mbuf) > 1))
3468 /* Here ends the series of multi-segment packets. */
3469 if (MLX5_TXOFF_CONFIG(TSO) &&
3470 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3471 return MLX5_TXCMP_CODE_TSO;
3472 return MLX5_TXCMP_CODE_SINGLE;
3478 * Tx burst function for single-segment packets with TSO.
3479 * Supports all types of Tx offloads, except multi-packets.
3480 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3481 * Function stops sending if it encounters the multi-segment
3482 * packet or packet without TSO requested.
3484 * The routine is responsible for storing processed mbuf
3485 * into elts ring buffer and update elts_head if inline
3486 * offloads is requested due to possible early freeing
3487 * of the inlined mbufs (can not store pkts array in elts
3491 * Pointer to TX queue structure.
3493 * Packets to transmit.
3495 * Number of packets in array.
3497 * Pointer to burst routine local context.
3499 * Configured Tx offloads mask. It is fully defined at
3500 * compile time and may be used for optimization.
3503 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3504 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3505 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3506 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3507 * Local context variables updated.
3509 static __rte_always_inline enum mlx5_txcmp_code
3510 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3511 struct rte_mbuf **restrict pkts,
3512 unsigned int pkts_n,
3513 struct mlx5_txq_local *restrict loc,
3516 assert(loc->elts_free && loc->wqe_free);
3517 assert(pkts_n > loc->pkts_sent);
3518 pkts += loc->pkts_sent + 1;
3519 pkts_n -= loc->pkts_sent;
3521 struct mlx5_wqe_dseg *restrict dseg;
3522 struct mlx5_wqe *restrict wqe;
3523 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3526 assert(NB_SEGS(loc->mbuf) == 1);
3527 dlen = rte_pktmbuf_data_len(loc->mbuf);
3528 if (MLX5_TXOFF_CONFIG(VLAN) &&
3529 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3530 vlan = sizeof(struct rte_vlan_hdr);
3533 * First calculate the WQE size to check
3534 * whether we have enough space in ring buffer.
3536 hlen = loc->mbuf->l2_len + vlan +
3537 loc->mbuf->l3_len + loc->mbuf->l4_len;
3538 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3539 return MLX5_TXCMP_CODE_ERROR;
3540 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3541 hlen += loc->mbuf->outer_l2_len +
3542 loc->mbuf->outer_l3_len;
3543 /* Segment must contain all TSO headers. */
3544 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3545 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3546 hlen > (dlen + vlan)))
3547 return MLX5_TXCMP_CODE_ERROR;
3549 * Check whether there are enough free WQEBBs:
3551 * - Ethernet Segment
3552 * - First Segment of inlined Ethernet data
3553 * - ... data continued ...
3554 * - Finishing Data Segment of pointer type
3556 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3557 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3558 if (loc->wqe_free < ((ds + 3) / 4))
3559 return MLX5_TXCMP_CODE_EXIT;
3560 #ifdef MLX5_PMD_SOFT_COUNTERS
3561 /* Update sent data bytes/packets counters. */
3562 ntcp = (dlen + vlan - hlen +
3563 loc->mbuf->tso_segsz - 1) /
3564 loc->mbuf->tso_segsz;
3566 * One will be added for mbuf itself at the end
3567 * of the mlx5_tx_burst from loc->pkts_sent field.
3570 txq->stats.opackets += ntcp;
3571 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3574 * Build the TSO WQE:
3576 * - Ethernet Segment with hlen bytes inlined
3577 * - Data Segment of pointer type
3579 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3580 loc->wqe_last = wqe;
3581 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3582 MLX5_OPCODE_TSO, olx);
3583 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3584 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3585 dlen -= hlen - vlan;
3586 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3588 * WQE is built, update the loop parameters
3589 * and go to the next packet.
3591 txq->wqe_ci += (ds + 3) / 4;
3592 loc->wqe_free -= (ds + 3) / 4;
3593 if (MLX5_TXOFF_CONFIG(INLINE))
3594 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3598 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3599 return MLX5_TXCMP_CODE_EXIT;
3600 loc->mbuf = *pkts++;
3602 rte_prefetch0(*pkts);
3603 if (MLX5_TXOFF_CONFIG(MULTI) &&
3604 unlikely(NB_SEGS(loc->mbuf) > 1))
3605 return MLX5_TXCMP_CODE_MULTI;
3606 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3607 return MLX5_TXCMP_CODE_SINGLE;
3608 /* Continue with the next TSO packet. */
3614 * Analyze the packet and select the best method to send.
3617 * Pointer to TX queue structure.
3619 * Pointer to burst routine local context.
3621 * Configured Tx offloads mask. It is fully defined at
3622 * compile time and may be used for optimization.
3624 * The predefined flag whether do complete check for
3625 * multi-segment packets and TSO.
3628 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3629 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3630 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3631 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3633 static __rte_always_inline enum mlx5_txcmp_code
3634 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3635 struct mlx5_txq_local *restrict loc,
3639 /* Check for multi-segment packet. */
3641 MLX5_TXOFF_CONFIG(MULTI) &&
3642 unlikely(NB_SEGS(loc->mbuf) > 1))
3643 return MLX5_TXCMP_CODE_MULTI;
3644 /* Check for TSO packet. */
3646 MLX5_TXOFF_CONFIG(TSO) &&
3647 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3648 return MLX5_TXCMP_CODE_TSO;
3649 /* Check if eMPW is enabled at all. */
3650 if (!MLX5_TXOFF_CONFIG(EMPW))
3651 return MLX5_TXCMP_CODE_SINGLE;
3652 /* Check if eMPW can be engaged. */
3653 if (MLX5_TXOFF_CONFIG(VLAN) &&
3654 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3655 (!MLX5_TXOFF_CONFIG(INLINE) ||
3656 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3657 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3659 * eMPW does not support VLAN insertion offload,
3660 * we have to inline the entire packet but
3661 * packet is too long for inlining.
3663 return MLX5_TXCMP_CODE_SINGLE;
3665 return MLX5_TXCMP_CODE_EMPW;
3669 * Check the next packet attributes to match with the eMPW batch ones.
3670 * In addition, for legacy MPW the packet length is checked either.
3673 * Pointer to TX queue structure.
3675 * Pointer to Ethernet Segment of eMPW batch.
3677 * Pointer to burst routine local context.
3679 * Length of previous packet in MPW descriptor.
3681 * Configured Tx offloads mask. It is fully defined at
3682 * compile time and may be used for optimization.
3685 * true - packet match with eMPW batch attributes.
3686 * false - no match, eMPW should be restarted.
3688 static __rte_always_inline bool
3689 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3690 struct mlx5_wqe_eseg *restrict es,
3691 struct mlx5_txq_local *restrict loc,
3695 uint8_t swp_flags = 0;
3697 /* Compare the checksum flags, if any. */
3698 if (MLX5_TXOFF_CONFIG(CSUM) &&
3699 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3701 /* Compare the Software Parser offsets and flags. */
3702 if (MLX5_TXOFF_CONFIG(SWP) &&
3703 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3704 es->swp_flags != swp_flags))
3706 /* Fill metadata field if needed. */
3707 if (MLX5_TXOFF_CONFIG(METADATA) &&
3708 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3709 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3711 /* Legacy MPW can send packets with the same lengt only. */
3712 if (MLX5_TXOFF_CONFIG(MPW) &&
3713 dlen != rte_pktmbuf_data_len(loc->mbuf))
3715 /* There must be no VLAN packets in eMPW loop. */
3716 if (MLX5_TXOFF_CONFIG(VLAN))
3717 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3722 * Update send loop variables and WQE for eMPW loop
3723 * without data inlining. Number of Data Segments is
3724 * equal to the number of sent packets.
3727 * Pointer to TX queue structure.
3729 * Pointer to burst routine local context.
3731 * Number of packets/Data Segments/Packets.
3733 * Accumulated statistics, bytes sent
3735 * Configured Tx offloads mask. It is fully defined at
3736 * compile time and may be used for optimization.
3739 * true - packet match with eMPW batch attributes.
3740 * false - no match, eMPW should be restarted.
3742 static __rte_always_inline void
3743 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3744 struct mlx5_txq_local *restrict loc,
3747 unsigned int olx __rte_unused)
3749 assert(!MLX5_TXOFF_CONFIG(INLINE));
3750 #ifdef MLX5_PMD_SOFT_COUNTERS
3751 /* Update sent data bytes counter. */
3752 txq->stats.obytes += slen;
3756 loc->elts_free -= ds;
3757 loc->pkts_sent += ds;
3759 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3760 txq->wqe_ci += (ds + 3) / 4;
3761 loc->wqe_free -= (ds + 3) / 4;
3765 * Update send loop variables and WQE for eMPW loop
3766 * with data inlining. Gets the size of pushed descriptors
3767 * and data to the WQE.
3770 * Pointer to TX queue structure.
3772 * Pointer to burst routine local context.
3774 * Total size of descriptor/data in bytes.
3776 * Accumulated statistics, data bytes sent.
3778 * Configured Tx offloads mask. It is fully defined at
3779 * compile time and may be used for optimization.
3782 * true - packet match with eMPW batch attributes.
3783 * false - no match, eMPW should be restarted.
3785 static __rte_always_inline void
3786 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3787 struct mlx5_txq_local *restrict loc,
3790 unsigned int olx __rte_unused)
3792 assert(MLX5_TXOFF_CONFIG(INLINE));
3793 assert((len % MLX5_WSEG_SIZE) == 0);
3794 #ifdef MLX5_PMD_SOFT_COUNTERS
3795 /* Update sent data bytes counter. */
3796 txq->stats.obytes += slen;
3800 len = len / MLX5_WSEG_SIZE + 2;
3801 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3802 txq->wqe_ci += (len + 3) / 4;
3803 loc->wqe_free -= (len + 3) / 4;
3807 * The set of Tx burst functions for single-segment packets
3808 * without TSO and with Multi-Packet Writing feature support.
3809 * Supports all types of Tx offloads, except multi-packets
3812 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3813 * as many packet per WQE as it can. If eMPW is not configured
3814 * or packet can not be sent with eMPW (VLAN insertion) the
3815 * ordinary SEND opcode is used and only one packet placed
3818 * Functions stop sending if it encounters the multi-segment
3819 * packet or packet with TSO requested.
3821 * The routines are responsible for storing processed mbuf
3822 * into elts ring buffer and update elts_head if inlining
3823 * offload is requested. Otherwise the copying mbufs to elts
3824 * can be postponed and completed at the end of burst routine.
3827 * Pointer to TX queue structure.
3829 * Packets to transmit.
3831 * Number of packets in array.
3833 * Pointer to burst routine local context.
3835 * Configured Tx offloads mask. It is fully defined at
3836 * compile time and may be used for optimization.
3839 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3840 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3841 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3842 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3843 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3844 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3846 * Local context variables updated.
3849 * The routine sends packets with MLX5_OPCODE_EMPW
3850 * without inlining, this is dedicated optimized branch.
3851 * No VLAN insertion is supported.
3853 static __rte_always_inline enum mlx5_txcmp_code
3854 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3855 struct rte_mbuf **restrict pkts,
3856 unsigned int pkts_n,
3857 struct mlx5_txq_local *restrict loc,
3861 * Subroutine is the part of mlx5_tx_burst_single()
3862 * and sends single-segment packet with eMPW opcode
3863 * without data inlining.
3865 assert(!MLX5_TXOFF_CONFIG(INLINE));
3866 assert(MLX5_TXOFF_CONFIG(EMPW));
3867 assert(loc->elts_free && loc->wqe_free);
3868 assert(pkts_n > loc->pkts_sent);
3869 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3870 pkts += loc->pkts_sent + 1;
3871 pkts_n -= loc->pkts_sent;
3873 struct mlx5_wqe_dseg *restrict dseg;
3874 struct mlx5_wqe_eseg *restrict eseg;
3875 enum mlx5_txcmp_code ret;
3876 unsigned int part, loop;
3877 unsigned int slen = 0;
3880 assert(NB_SEGS(loc->mbuf) == 1);
3881 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
3882 MLX5_MPW_MAX_PACKETS :
3883 MLX5_EMPW_MAX_PACKETS);
3884 if (unlikely(loc->elts_free < part)) {
3885 /* We have no enough elts to save all mbufs. */
3886 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3887 return MLX5_TXCMP_CODE_EXIT;
3888 /* But we still able to send at least minimal eMPW. */
3889 part = loc->elts_free;
3891 /* Check whether we have enough WQEs */
3892 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3893 if (unlikely(loc->wqe_free <
3894 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3895 return MLX5_TXCMP_CODE_EXIT;
3896 part = (loc->wqe_free * 4) - 2;
3898 if (likely(part > 1))
3899 rte_prefetch0(*pkts);
3900 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3902 * Build eMPW title WQEBB:
3903 * - Control Segment, eMPW opcode
3904 * - Ethernet Segment, no inline
3906 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3907 MLX5_OPCODE_ENHANCED_MPSW, olx);
3908 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3909 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3910 eseg = &loc->wqe_last->eseg;
3911 dseg = &loc->wqe_last->dseg[0];
3913 /* Store the packet length for legacy MPW. */
3914 if (MLX5_TXOFF_CONFIG(MPW))
3915 eseg->mss = rte_cpu_to_be_16
3916 (rte_pktmbuf_data_len(loc->mbuf));
3918 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3919 #ifdef MLX5_PMD_SOFT_COUNTERS
3920 /* Update sent data bytes counter. */
3925 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3927 if (unlikely(--loop == 0))
3929 loc->mbuf = *pkts++;
3930 if (likely(loop > 1))
3931 rte_prefetch0(*pkts);
3932 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3934 * Unroll the completion code to avoid
3935 * returning variable value - it results in
3936 * unoptimized sequent checking in caller.
3938 if (ret == MLX5_TXCMP_CODE_MULTI) {
3940 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3941 if (unlikely(!loc->elts_free ||
3943 return MLX5_TXCMP_CODE_EXIT;
3944 return MLX5_TXCMP_CODE_MULTI;
3946 assert(NB_SEGS(loc->mbuf) == 1);
3947 if (ret == MLX5_TXCMP_CODE_TSO) {
3949 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3950 if (unlikely(!loc->elts_free ||
3952 return MLX5_TXCMP_CODE_EXIT;
3953 return MLX5_TXCMP_CODE_TSO;
3955 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3957 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3958 if (unlikely(!loc->elts_free ||
3960 return MLX5_TXCMP_CODE_EXIT;
3961 return MLX5_TXCMP_CODE_SINGLE;
3963 if (ret != MLX5_TXCMP_CODE_EMPW) {
3966 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3967 return MLX5_TXCMP_CODE_ERROR;
3970 * Check whether packet parameters coincide
3971 * within assumed eMPW batch:
3972 * - check sum settings
3974 * - software parser settings
3975 * - packets length (legacy MPW only)
3977 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
3980 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3981 if (unlikely(!loc->elts_free ||
3983 return MLX5_TXCMP_CODE_EXIT;
3987 /* Packet attributes match, continue the same eMPW. */
3989 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3990 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3992 /* eMPW is built successfully, update loop parameters. */
3994 assert(pkts_n >= part);
3995 #ifdef MLX5_PMD_SOFT_COUNTERS
3996 /* Update sent data bytes counter. */
3997 txq->stats.obytes += slen;
3999 loc->elts_free -= part;
4000 loc->pkts_sent += part;
4001 txq->wqe_ci += (2 + part + 3) / 4;
4002 loc->wqe_free -= (2 + part + 3) / 4;
4004 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4005 return MLX5_TXCMP_CODE_EXIT;
4006 loc->mbuf = *pkts++;
4007 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4008 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4010 /* Continue sending eMPW batches. */
4016 * The routine sends packets with MLX5_OPCODE_EMPW
4017 * with inlining, optionally supports VLAN insertion.
4019 static __rte_always_inline enum mlx5_txcmp_code
4020 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
4021 struct rte_mbuf **restrict pkts,
4022 unsigned int pkts_n,
4023 struct mlx5_txq_local *restrict loc,
4027 * Subroutine is the part of mlx5_tx_burst_single()
4028 * and sends single-segment packet with eMPW opcode
4029 * with data inlining.
4031 assert(MLX5_TXOFF_CONFIG(INLINE));
4032 assert(MLX5_TXOFF_CONFIG(EMPW));
4033 assert(loc->elts_free && loc->wqe_free);
4034 assert(pkts_n > loc->pkts_sent);
4035 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4036 pkts += loc->pkts_sent + 1;
4037 pkts_n -= loc->pkts_sent;
4039 struct mlx5_wqe_dseg *restrict dseg;
4040 struct mlx5_wqe_eseg *restrict eseg;
4041 enum mlx5_txcmp_code ret;
4042 unsigned int room, part, nlim;
4043 unsigned int slen = 0;
4045 assert(NB_SEGS(loc->mbuf) == 1);
4047 * Limits the amount of packets in one WQE
4048 * to improve CQE latency generation.
4050 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4051 MLX5_MPW_INLINE_MAX_PACKETS :
4052 MLX5_EMPW_MAX_PACKETS);
4053 /* Check whether we have minimal amount WQEs */
4054 if (unlikely(loc->wqe_free <
4055 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4056 return MLX5_TXCMP_CODE_EXIT;
4057 if (likely(pkts_n > 1))
4058 rte_prefetch0(*pkts);
4059 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4061 * Build eMPW title WQEBB:
4062 * - Control Segment, eMPW opcode, zero DS
4063 * - Ethernet Segment, no inline
4065 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
4066 MLX5_OPCODE_ENHANCED_MPSW, olx);
4067 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4068 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4069 eseg = &loc->wqe_last->eseg;
4070 dseg = &loc->wqe_last->dseg[0];
4071 /* Store the packet length for legacy MPW. */
4072 if (MLX5_TXOFF_CONFIG(MPW))
4073 eseg->mss = rte_cpu_to_be_16
4074 (rte_pktmbuf_data_len(loc->mbuf));
4075 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4076 loc->wqe_free) * MLX5_WQE_SIZE -
4077 MLX5_WQE_CSEG_SIZE -
4079 /* Build WQE till we have space, packets and resources. */
4082 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4083 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4086 assert(room >= MLX5_WQE_DSEG_SIZE);
4087 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
4088 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4090 * Some Tx offloads may cause an error if
4091 * packet is not long enough, check against
4092 * assumed minimal length.
4094 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4096 if (unlikely(!part))
4097 return MLX5_TXCMP_CODE_ERROR;
4099 * We have some successfully built
4100 * packet Data Segments to send.
4102 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4103 return MLX5_TXCMP_CODE_ERROR;
4105 /* Inline or not inline - that's the Question. */
4106 if (dlen > txq->inlen_empw)
4108 /* Inline entire packet, optional VLAN insertion. */
4109 tlen = sizeof(dseg->bcount) + dlen;
4110 if (MLX5_TXOFF_CONFIG(VLAN) &&
4111 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4113 * The packet length must be checked in
4114 * mlx5_tx_able_to_empw() and packet
4115 * fits into inline length guaranteed.
4117 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
4119 tlen += sizeof(struct rte_vlan_hdr);
4122 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4124 #ifdef MLX5_PMD_SOFT_COUNTERS
4125 /* Update sent data bytes counter. */
4126 slen += sizeof(struct rte_vlan_hdr);
4131 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4134 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4135 assert(room >= tlen);
4138 * Packet data are completely inlined,
4139 * free the packet immediately.
4141 rte_pktmbuf_free_seg(loc->mbuf);
4145 * Not inlinable VLAN packets are
4146 * proceeded outside of this routine.
4148 assert(room >= MLX5_WQE_DSEG_SIZE);
4149 if (MLX5_TXOFF_CONFIG(VLAN))
4150 assert(!(loc->mbuf->ol_flags &
4152 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4153 /* We have to store mbuf in elts.*/
4154 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4155 room -= MLX5_WQE_DSEG_SIZE;
4156 /* Ring buffer wraparound is checked at the loop end.*/
4159 #ifdef MLX5_PMD_SOFT_COUNTERS
4160 /* Update sent data bytes counter. */
4166 if (unlikely(!pkts_n || !loc->elts_free)) {
4168 * We have no resources/packets to
4169 * continue build descriptors.
4172 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4173 return MLX5_TXCMP_CODE_EXIT;
4175 loc->mbuf = *pkts++;
4176 if (likely(pkts_n > 1))
4177 rte_prefetch0(*pkts);
4178 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4180 * Unroll the completion code to avoid
4181 * returning variable value - it results in
4182 * unoptimized sequent checking in caller.
4184 if (ret == MLX5_TXCMP_CODE_MULTI) {
4186 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4187 if (unlikely(!loc->elts_free ||
4189 return MLX5_TXCMP_CODE_EXIT;
4190 return MLX5_TXCMP_CODE_MULTI;
4192 assert(NB_SEGS(loc->mbuf) == 1);
4193 if (ret == MLX5_TXCMP_CODE_TSO) {
4195 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4196 if (unlikely(!loc->elts_free ||
4198 return MLX5_TXCMP_CODE_EXIT;
4199 return MLX5_TXCMP_CODE_TSO;
4201 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4203 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4204 if (unlikely(!loc->elts_free ||
4206 return MLX5_TXCMP_CODE_EXIT;
4207 return MLX5_TXCMP_CODE_SINGLE;
4209 if (ret != MLX5_TXCMP_CODE_EMPW) {
4212 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4213 return MLX5_TXCMP_CODE_ERROR;
4215 /* Check if we have minimal room left. */
4217 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4220 * Check whether packet parameters coincide
4221 * within assumed eMPW batch:
4222 * - check sum settings
4224 * - software parser settings
4225 * - packets length (legacy MPW only)
4227 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx))
4229 /* Packet attributes match, continue the same eMPW. */
4230 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4231 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4234 * We get here to close an existing eMPW
4235 * session and start the new one.
4239 if (unlikely(!part))
4240 return MLX5_TXCMP_CODE_EXIT;
4241 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4242 if (unlikely(!loc->elts_free ||
4244 return MLX5_TXCMP_CODE_EXIT;
4245 /* Continue the loop with new eMPW session. */
4251 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4252 * Data inlining and VLAN insertion are supported.
4254 static __rte_always_inline enum mlx5_txcmp_code
4255 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4256 struct rte_mbuf **restrict pkts,
4257 unsigned int pkts_n,
4258 struct mlx5_txq_local *restrict loc,
4262 * Subroutine is the part of mlx5_tx_burst_single()
4263 * and sends single-segment packet with SEND opcode.
4265 assert(loc->elts_free && loc->wqe_free);
4266 assert(pkts_n > loc->pkts_sent);
4267 pkts += loc->pkts_sent + 1;
4268 pkts_n -= loc->pkts_sent;
4270 struct mlx5_wqe *restrict wqe;
4271 enum mlx5_txcmp_code ret;
4273 assert(NB_SEGS(loc->mbuf) == 1);
4274 if (MLX5_TXOFF_CONFIG(INLINE)) {
4275 unsigned int inlen, vlan = 0;
4277 inlen = rte_pktmbuf_data_len(loc->mbuf);
4278 if (MLX5_TXOFF_CONFIG(VLAN) &&
4279 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4280 vlan = sizeof(struct rte_vlan_hdr);
4282 static_assert((sizeof(struct rte_vlan_hdr) +
4283 sizeof(struct rte_ether_hdr)) ==
4284 MLX5_ESEG_MIN_INLINE_SIZE,
4285 "invalid min inline data size");
4288 * If inlining is enabled at configuration time
4289 * the limit must be not less than minimal size.
4290 * Otherwise we would do extra check for data
4291 * size to avoid crashes due to length overflow.
4293 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4294 if (inlen <= txq->inlen_send) {
4295 unsigned int seg_n, wqe_n;
4297 rte_prefetch0(rte_pktmbuf_mtod
4298 (loc->mbuf, uint8_t *));
4299 /* Check against minimal length. */
4300 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4301 return MLX5_TXCMP_CODE_ERROR;
4303 * Completely inlined packet data WQE:
4304 * - Control Segment, SEND opcode
4305 * - Ethernet Segment, no VLAN insertion
4306 * - Data inlined, VLAN optionally inserted
4307 * - Alignment to MLX5_WSEG_SIZE
4308 * Have to estimate amount of WQEBBs
4310 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4311 MLX5_ESEG_MIN_INLINE_SIZE +
4312 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4313 /* Check if there are enough WQEBBs. */
4314 wqe_n = (seg_n + 3) / 4;
4315 if (wqe_n > loc->wqe_free)
4316 return MLX5_TXCMP_CODE_EXIT;
4317 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4318 loc->wqe_last = wqe;
4319 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4320 MLX5_OPCODE_SEND, olx);
4321 mlx5_tx_eseg_data(txq, loc, wqe,
4322 vlan, inlen, 0, olx);
4323 txq->wqe_ci += wqe_n;
4324 loc->wqe_free -= wqe_n;
4326 * Packet data are completely inlined,
4327 * free the packet immediately.
4329 rte_pktmbuf_free_seg(loc->mbuf);
4330 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4331 MLX5_TXOFF_CONFIG(MPW)) &&
4334 * If minimal inlining is requested the eMPW
4335 * feature should be disabled due to data is
4336 * inlined into Ethernet Segment, which can
4337 * not contain inlined data for eMPW due to
4338 * segment shared for all packets.
4340 struct mlx5_wqe_dseg *restrict dseg;
4345 * The inline-mode settings require
4346 * to inline the specified amount of
4347 * data bytes to the Ethernet Segment.
4348 * We should check the free space in
4349 * WQE ring buffer to inline partially.
4351 assert(txq->inlen_send >= txq->inlen_mode);
4352 assert(inlen > txq->inlen_mode);
4353 assert(txq->inlen_mode >=
4354 MLX5_ESEG_MIN_INLINE_SIZE);
4356 * Check whether there are enough free WQEBBs:
4358 * - Ethernet Segment
4359 * - First Segment of inlined Ethernet data
4360 * - ... data continued ...
4361 * - Finishing Data Segment of pointer type
4363 ds = (MLX5_WQE_CSEG_SIZE +
4364 MLX5_WQE_ESEG_SIZE +
4365 MLX5_WQE_DSEG_SIZE +
4367 MLX5_ESEG_MIN_INLINE_SIZE +
4368 MLX5_WQE_DSEG_SIZE +
4369 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4370 if (loc->wqe_free < ((ds + 3) / 4))
4371 return MLX5_TXCMP_CODE_EXIT;
4373 * Build the ordinary SEND WQE:
4375 * - Ethernet Segment, inline inlen_mode bytes
4376 * - Data Segment of pointer type
4378 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4379 loc->wqe_last = wqe;
4380 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4381 MLX5_OPCODE_SEND, olx);
4382 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4385 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4386 txq->inlen_mode - vlan;
4387 inlen -= txq->inlen_mode;
4388 mlx5_tx_dseg_ptr(txq, loc, dseg,
4391 * WQE is built, update the loop parameters
4392 * and got to the next packet.
4394 txq->wqe_ci += (ds + 3) / 4;
4395 loc->wqe_free -= (ds + 3) / 4;
4396 /* We have to store mbuf in elts.*/
4397 assert(MLX5_TXOFF_CONFIG(INLINE));
4398 txq->elts[txq->elts_head++ & txq->elts_m] =
4406 * Partially inlined packet data WQE, we have
4407 * some space in title WQEBB, we can fill it
4408 * with some packet data. It takes one WQEBB,
4409 * it is available, no extra space check:
4410 * - Control Segment, SEND opcode
4411 * - Ethernet Segment, no VLAN insertion
4412 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4413 * - Data Segment, pointer type
4415 * We also get here if VLAN insertion is not
4416 * supported by HW, the inline is enabled.
4418 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4419 loc->wqe_last = wqe;
4420 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4421 MLX5_OPCODE_SEND, olx);
4422 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4423 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4424 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4426 * The length check is performed above, by
4427 * comparing with txq->inlen_send. We should
4428 * not get overflow here.
4430 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4431 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4432 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4436 /* We have to store mbuf in elts.*/
4437 assert(MLX5_TXOFF_CONFIG(INLINE));
4438 txq->elts[txq->elts_head++ & txq->elts_m] =
4442 #ifdef MLX5_PMD_SOFT_COUNTERS
4443 /* Update sent data bytes counter. */
4444 txq->stats.obytes += vlan +
4445 rte_pktmbuf_data_len(loc->mbuf);
4449 * No inline at all, it means the CPU cycles saving
4450 * is prioritized at configuration, we should not
4451 * copy any packet data to WQE.
4453 * SEND WQE, one WQEBB:
4454 * - Control Segment, SEND opcode
4455 * - Ethernet Segment, optional VLAN, no inline
4456 * - Data Segment, pointer type
4458 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4459 loc->wqe_last = wqe;
4460 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4461 MLX5_OPCODE_SEND, olx);
4462 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4464 (txq, loc, &wqe->dseg[0],
4465 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4466 rte_pktmbuf_data_len(loc->mbuf), olx);
4470 * We should not store mbuf pointer in elts
4471 * if no inlining is configured, this is done
4472 * by calling routine in a batch copy.
4474 assert(!MLX5_TXOFF_CONFIG(INLINE));
4476 #ifdef MLX5_PMD_SOFT_COUNTERS
4477 /* Update sent data bytes counter. */
4478 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4479 if (MLX5_TXOFF_CONFIG(VLAN) &&
4480 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4481 txq->stats.obytes +=
4482 sizeof(struct rte_vlan_hdr);
4487 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4488 return MLX5_TXCMP_CODE_EXIT;
4489 loc->mbuf = *pkts++;
4491 rte_prefetch0(*pkts);
4492 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4493 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4499 static __rte_always_inline enum mlx5_txcmp_code
4500 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4501 struct rte_mbuf **restrict pkts,
4502 unsigned int pkts_n,
4503 struct mlx5_txq_local *restrict loc,
4506 enum mlx5_txcmp_code ret;
4508 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4509 if (ret == MLX5_TXCMP_CODE_SINGLE)
4511 assert(ret == MLX5_TXCMP_CODE_EMPW);
4513 /* Optimize for inline/no inline eMPW send. */
4514 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4515 mlx5_tx_burst_empw_inline
4516 (txq, pkts, pkts_n, loc, olx) :
4517 mlx5_tx_burst_empw_simple
4518 (txq, pkts, pkts_n, loc, olx);
4519 if (ret != MLX5_TXCMP_CODE_SINGLE)
4521 /* The resources to send one packet should remain. */
4522 assert(loc->elts_free && loc->wqe_free);
4524 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4525 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4526 if (ret != MLX5_TXCMP_CODE_EMPW)
4528 /* The resources to send one packet should remain. */
4529 assert(loc->elts_free && loc->wqe_free);
4534 * DPDK Tx callback template. This is configured template
4535 * used to generate routines optimized for specified offload setup.
4536 * One of this generated functions is chosen at SQ configuration
4540 * Generic pointer to TX queue structure.
4542 * Packets to transmit.
4544 * Number of packets in array.
4546 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4547 * values. Should be static to take compile time static configuration
4551 * Number of packets successfully transmitted (<= pkts_n).
4553 static __rte_always_inline uint16_t
4554 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4555 struct rte_mbuf **restrict pkts,
4559 struct mlx5_txq_local loc;
4560 enum mlx5_txcmp_code ret;
4563 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4564 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4565 if (unlikely(!pkts_n))
4569 loc.wqe_last = NULL;
4572 loc.pkts_loop = loc.pkts_sent;
4574 * Check if there are some CQEs, if any:
4575 * - process an encountered errors
4576 * - process the completed WQEs
4577 * - free related mbufs
4578 * - doorbell the NIC about processed CQEs
4580 rte_prefetch0(*(pkts + loc.pkts_sent));
4581 mlx5_tx_handle_completion(txq, olx);
4583 * Calculate the number of available resources - elts and WQEs.
4584 * There are two possible different scenarios:
4585 * - no data inlining into WQEs, one WQEBB may contains upto
4586 * four packets, in this case elts become scarce resource
4587 * - data inlining into WQEs, one packet may require multiple
4588 * WQEBBs, the WQEs become the limiting factor.
4590 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4591 loc.elts_free = txq->elts_s -
4592 (uint16_t)(txq->elts_head - txq->elts_tail);
4593 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4594 loc.wqe_free = txq->wqe_s -
4595 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4596 if (unlikely(!loc.elts_free || !loc.wqe_free))
4600 * Fetch the packet from array. Usually this is
4601 * the first packet in series of multi/single
4604 loc.mbuf = *(pkts + loc.pkts_sent);
4605 /* Dedicated branch for multi-segment packets. */
4606 if (MLX5_TXOFF_CONFIG(MULTI) &&
4607 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4609 * Multi-segment packet encountered.
4610 * Hardware is able to process it only
4611 * with SEND/TSO opcodes, one packet
4612 * per WQE, do it in dedicated routine.
4615 assert(loc.pkts_sent >= loc.pkts_copy);
4616 part = loc.pkts_sent - loc.pkts_copy;
4617 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4619 * There are some single-segment mbufs not
4620 * stored in elts. The mbufs must be in the
4621 * same order as WQEs, so we must copy the
4622 * mbufs to elts here, before the coming
4623 * multi-segment packet mbufs is appended.
4625 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4627 loc.pkts_copy = loc.pkts_sent;
4629 assert(pkts_n > loc.pkts_sent);
4630 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4631 if (!MLX5_TXOFF_CONFIG(INLINE))
4632 loc.pkts_copy = loc.pkts_sent;
4634 * These returned code checks are supposed
4635 * to be optimized out due to routine inlining.
4637 if (ret == MLX5_TXCMP_CODE_EXIT) {
4639 * The routine returns this code when
4640 * all packets are sent or there is no
4641 * enough resources to complete request.
4645 if (ret == MLX5_TXCMP_CODE_ERROR) {
4647 * The routine returns this code when
4648 * some error in the incoming packets
4651 txq->stats.oerrors++;
4654 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4656 * The single-segment packet was encountered
4657 * in the array, try to send it with the
4658 * best optimized way, possible engaging eMPW.
4660 goto enter_send_single;
4662 if (MLX5_TXOFF_CONFIG(TSO) &&
4663 ret == MLX5_TXCMP_CODE_TSO) {
4665 * The single-segment TSO packet was
4666 * encountered in the array.
4668 goto enter_send_tso;
4670 /* We must not get here. Something is going wrong. */
4672 txq->stats.oerrors++;
4675 /* Dedicated branch for single-segment TSO packets. */
4676 if (MLX5_TXOFF_CONFIG(TSO) &&
4677 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4679 * TSO might require special way for inlining
4680 * (dedicated parameters) and is sent with
4681 * MLX5_OPCODE_TSO opcode only, provide this
4682 * in dedicated branch.
4685 assert(NB_SEGS(loc.mbuf) == 1);
4686 assert(pkts_n > loc.pkts_sent);
4687 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4689 * These returned code checks are supposed
4690 * to be optimized out due to routine inlining.
4692 if (ret == MLX5_TXCMP_CODE_EXIT)
4694 if (ret == MLX5_TXCMP_CODE_ERROR) {
4695 txq->stats.oerrors++;
4698 if (ret == MLX5_TXCMP_CODE_SINGLE)
4699 goto enter_send_single;
4700 if (MLX5_TXOFF_CONFIG(MULTI) &&
4701 ret == MLX5_TXCMP_CODE_MULTI) {
4703 * The multi-segment packet was
4704 * encountered in the array.
4706 goto enter_send_multi;
4708 /* We must not get here. Something is going wrong. */
4710 txq->stats.oerrors++;
4714 * The dedicated branch for the single-segment packets
4715 * without TSO. Often these ones can be sent using
4716 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4717 * The routine builds the WQEs till it encounters
4718 * the TSO or multi-segment packet (in case if these
4719 * offloads are requested at SQ configuration time).
4722 assert(pkts_n > loc.pkts_sent);
4723 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4725 * These returned code checks are supposed
4726 * to be optimized out due to routine inlining.
4728 if (ret == MLX5_TXCMP_CODE_EXIT)
4730 if (ret == MLX5_TXCMP_CODE_ERROR) {
4731 txq->stats.oerrors++;
4734 if (MLX5_TXOFF_CONFIG(MULTI) &&
4735 ret == MLX5_TXCMP_CODE_MULTI) {
4737 * The multi-segment packet was
4738 * encountered in the array.
4740 goto enter_send_multi;
4742 if (MLX5_TXOFF_CONFIG(TSO) &&
4743 ret == MLX5_TXCMP_CODE_TSO) {
4745 * The single-segment TSO packet was
4746 * encountered in the array.
4748 goto enter_send_tso;
4750 /* We must not get here. Something is going wrong. */
4752 txq->stats.oerrors++;
4756 * Main Tx loop is completed, do the rest:
4757 * - set completion request if thresholds are reached
4758 * - doorbell the hardware
4759 * - copy the rest of mbufs to elts (if any)
4761 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4762 /* Take a shortcut if nothing is sent. */
4763 if (unlikely(loc.pkts_sent == loc.pkts_loop))
4765 /* Request CQE generation if limits are reached. */
4766 mlx5_tx_request_completion(txq, &loc, olx);
4768 * Ring QP doorbell immediately after WQE building completion
4769 * to improve latencies. The pure software related data treatment
4770 * can be completed after doorbell. Tx CQEs for this SQ are
4771 * processed in this thread only by the polling.
4773 * The rdma core library can map doorbell register in two ways,
4774 * depending on the environment variable "MLX5_SHUT_UP_BF":
4776 * - as regular cached memory, the variable is either missing or
4777 * set to zero. This type of mapping may cause the significant
4778 * doorbell register writing latency and requires explicit
4779 * memory write barrier to mitigate this issue and prevent
4782 * - as non-cached memory, the variable is present and set to
4783 * not "0" value. This type of mapping may cause performance
4784 * impact under heavy loading conditions but the explicit write
4785 * memory barrier is not required and it may improve core
4788 * - the legacy behaviour (prior 19.08 release) was to use some
4789 * heuristics to decide whether write memory barrier should
4790 * be performed. This behavior is supported with specifying
4791 * tx_db_nc=2, write barrier is skipped if application
4792 * provides the full recommended burst of packets, it
4793 * supposes the next packets are coming and the write barrier
4794 * will be issued on the next burst (after descriptor writing,
4797 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
4798 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
4799 /* Not all of the mbufs may be stored into elts yet. */
4800 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4801 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4803 * There are some single-segment mbufs not stored in elts.
4804 * It can be only if the last packet was single-segment.
4805 * The copying is gathered into one place due to it is
4806 * a good opportunity to optimize that with SIMD.
4807 * Unfortunately if inlining is enabled the gaps in
4808 * pointer array may happen due to early freeing of the
4811 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4812 loc.pkts_copy = loc.pkts_sent;
4814 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4815 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4816 if (pkts_n > loc.pkts_sent) {
4818 * If burst size is large there might be no enough CQE
4819 * fetched from completion queue and no enough resources
4820 * freed to send all the packets.
4825 #ifdef MLX5_PMD_SOFT_COUNTERS
4826 /* Increment sent packets counter. */
4827 txq->stats.opackets += loc.pkts_sent;
4829 return loc.pkts_sent;
4832 /* Generate routines with Enhanced Multi-Packet Write support. */
4833 MLX5_TXOFF_DECL(full_empw,
4834 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4836 MLX5_TXOFF_DECL(none_empw,
4837 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4839 MLX5_TXOFF_DECL(md_empw,
4840 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4842 MLX5_TXOFF_DECL(mt_empw,
4843 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4844 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4846 MLX5_TXOFF_DECL(mtsc_empw,
4847 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4848 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4849 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4851 MLX5_TXOFF_DECL(mti_empw,
4852 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4853 MLX5_TXOFF_CONFIG_INLINE |
4854 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4856 MLX5_TXOFF_DECL(mtv_empw,
4857 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4858 MLX5_TXOFF_CONFIG_VLAN |
4859 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4861 MLX5_TXOFF_DECL(mtiv_empw,
4862 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4863 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4864 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4866 MLX5_TXOFF_DECL(sc_empw,
4867 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4868 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4870 MLX5_TXOFF_DECL(sci_empw,
4871 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4872 MLX5_TXOFF_CONFIG_INLINE |
4873 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4875 MLX5_TXOFF_DECL(scv_empw,
4876 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4877 MLX5_TXOFF_CONFIG_VLAN |
4878 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4880 MLX5_TXOFF_DECL(sciv_empw,
4881 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4882 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4883 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4885 MLX5_TXOFF_DECL(i_empw,
4886 MLX5_TXOFF_CONFIG_INLINE |
4887 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4889 MLX5_TXOFF_DECL(v_empw,
4890 MLX5_TXOFF_CONFIG_VLAN |
4891 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4893 MLX5_TXOFF_DECL(iv_empw,
4894 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4895 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4897 /* Generate routines without Enhanced Multi-Packet Write support. */
4898 MLX5_TXOFF_DECL(full,
4899 MLX5_TXOFF_CONFIG_FULL)
4901 MLX5_TXOFF_DECL(none,
4902 MLX5_TXOFF_CONFIG_NONE)
4905 MLX5_TXOFF_CONFIG_METADATA)
4908 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4909 MLX5_TXOFF_CONFIG_METADATA)
4911 MLX5_TXOFF_DECL(mtsc,
4912 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4913 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4914 MLX5_TXOFF_CONFIG_METADATA)
4916 MLX5_TXOFF_DECL(mti,
4917 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4918 MLX5_TXOFF_CONFIG_INLINE |
4919 MLX5_TXOFF_CONFIG_METADATA)
4922 MLX5_TXOFF_DECL(mtv,
4923 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4924 MLX5_TXOFF_CONFIG_VLAN |
4925 MLX5_TXOFF_CONFIG_METADATA)
4928 MLX5_TXOFF_DECL(mtiv,
4929 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4930 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4931 MLX5_TXOFF_CONFIG_METADATA)
4934 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4935 MLX5_TXOFF_CONFIG_METADATA)
4937 MLX5_TXOFF_DECL(sci,
4938 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4939 MLX5_TXOFF_CONFIG_INLINE |
4940 MLX5_TXOFF_CONFIG_METADATA)
4943 MLX5_TXOFF_DECL(scv,
4944 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4945 MLX5_TXOFF_CONFIG_VLAN |
4946 MLX5_TXOFF_CONFIG_METADATA)
4949 MLX5_TXOFF_DECL(sciv,
4950 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4951 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4952 MLX5_TXOFF_CONFIG_METADATA)
4955 MLX5_TXOFF_CONFIG_INLINE |
4956 MLX5_TXOFF_CONFIG_METADATA)
4959 MLX5_TXOFF_CONFIG_VLAN |
4960 MLX5_TXOFF_CONFIG_METADATA)
4963 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4964 MLX5_TXOFF_CONFIG_METADATA)
4967 * Generate routines with Legacy Multi-Packet Write support.
4968 * This mode is supported by ConnectX-4LX only and imposes
4969 * offload limitations, not supported:
4970 * - ACL/Flows (metadata are becoming meaningless)
4971 * - WQE Inline headers
4972 * - SRIOV (E-Switch offloads)
4974 * - tunnel encapsulation/decapsulation
4977 MLX5_TXOFF_DECL(none_mpw,
4978 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
4979 MLX5_TXOFF_CONFIG_MPW)
4981 MLX5_TXOFF_DECL(mci_mpw,
4982 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
4983 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
4984 MLX5_TXOFF_CONFIG_MPW)
4986 MLX5_TXOFF_DECL(mc_mpw,
4987 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
4988 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
4990 MLX5_TXOFF_DECL(i_mpw,
4991 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
4992 MLX5_TXOFF_CONFIG_MPW)
4995 * Array of declared and compiled Tx burst function and corresponding
4996 * supported offloads set. The array is used to select the Tx burst
4997 * function for specified offloads set at Tx queue configuration time.
5000 eth_tx_burst_t func;
5003 MLX5_TXOFF_INFO(full_empw,
5004 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5005 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5006 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5007 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5009 MLX5_TXOFF_INFO(none_empw,
5010 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5012 MLX5_TXOFF_INFO(md_empw,
5013 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5015 MLX5_TXOFF_INFO(mt_empw,
5016 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5017 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5019 MLX5_TXOFF_INFO(mtsc_empw,
5020 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5021 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5022 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5024 MLX5_TXOFF_INFO(mti_empw,
5025 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5026 MLX5_TXOFF_CONFIG_INLINE |
5027 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5029 MLX5_TXOFF_INFO(mtv_empw,
5030 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5031 MLX5_TXOFF_CONFIG_VLAN |
5032 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5034 MLX5_TXOFF_INFO(mtiv_empw,
5035 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5036 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5037 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5039 MLX5_TXOFF_INFO(sc_empw,
5040 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5041 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5043 MLX5_TXOFF_INFO(sci_empw,
5044 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5045 MLX5_TXOFF_CONFIG_INLINE |
5046 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5048 MLX5_TXOFF_INFO(scv_empw,
5049 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5050 MLX5_TXOFF_CONFIG_VLAN |
5051 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5053 MLX5_TXOFF_INFO(sciv_empw,
5054 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5055 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5056 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5058 MLX5_TXOFF_INFO(i_empw,
5059 MLX5_TXOFF_CONFIG_INLINE |
5060 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5062 MLX5_TXOFF_INFO(v_empw,
5063 MLX5_TXOFF_CONFIG_VLAN |
5064 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5066 MLX5_TXOFF_INFO(iv_empw,
5067 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5068 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5070 MLX5_TXOFF_INFO(full,
5071 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5072 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5073 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5074 MLX5_TXOFF_CONFIG_METADATA)
5076 MLX5_TXOFF_INFO(none,
5077 MLX5_TXOFF_CONFIG_NONE)
5080 MLX5_TXOFF_CONFIG_METADATA)
5083 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5084 MLX5_TXOFF_CONFIG_METADATA)
5086 MLX5_TXOFF_INFO(mtsc,
5087 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5088 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5089 MLX5_TXOFF_CONFIG_METADATA)
5091 MLX5_TXOFF_INFO(mti,
5092 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5093 MLX5_TXOFF_CONFIG_INLINE |
5094 MLX5_TXOFF_CONFIG_METADATA)
5096 MLX5_TXOFF_INFO(mtv,
5097 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5098 MLX5_TXOFF_CONFIG_VLAN |
5099 MLX5_TXOFF_CONFIG_METADATA)
5101 MLX5_TXOFF_INFO(mtiv,
5102 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5103 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5104 MLX5_TXOFF_CONFIG_METADATA)
5107 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5108 MLX5_TXOFF_CONFIG_METADATA)
5110 MLX5_TXOFF_INFO(sci,
5111 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5112 MLX5_TXOFF_CONFIG_INLINE |
5113 MLX5_TXOFF_CONFIG_METADATA)
5115 MLX5_TXOFF_INFO(scv,
5116 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5117 MLX5_TXOFF_CONFIG_VLAN |
5118 MLX5_TXOFF_CONFIG_METADATA)
5120 MLX5_TXOFF_INFO(sciv,
5121 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5122 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5123 MLX5_TXOFF_CONFIG_METADATA)
5126 MLX5_TXOFF_CONFIG_INLINE |
5127 MLX5_TXOFF_CONFIG_METADATA)
5130 MLX5_TXOFF_CONFIG_VLAN |
5131 MLX5_TXOFF_CONFIG_METADATA)
5134 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5135 MLX5_TXOFF_CONFIG_METADATA)
5137 MLX5_TXOFF_INFO(none_mpw,
5138 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5139 MLX5_TXOFF_CONFIG_MPW)
5141 MLX5_TXOFF_INFO(mci_mpw,
5142 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5143 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5144 MLX5_TXOFF_CONFIG_MPW)
5146 MLX5_TXOFF_INFO(mc_mpw,
5147 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5148 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5150 MLX5_TXOFF_INFO(i_mpw,
5151 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5152 MLX5_TXOFF_CONFIG_MPW)
5156 * Configure the Tx function to use. The routine checks configured
5157 * Tx offloads for the device and selects appropriate Tx burst
5158 * routine. There are multiple Tx burst routines compiled from
5159 * the same template in the most optimal way for the dedicated
5163 * Pointer to private data structure.
5166 * Pointer to selected Tx burst function.
5169 mlx5_select_tx_function(struct rte_eth_dev *dev)
5171 struct mlx5_priv *priv = dev->data->dev_private;
5172 struct mlx5_dev_config *config = &priv->config;
5173 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5174 unsigned int diff = 0, olx = 0, i, m;
5176 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5177 MLX5_DSEG_MAX, "invalid WQE max size");
5178 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5179 "invalid WQE Control Segment size");
5180 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5181 "invalid WQE Ethernet Segment size");
5182 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5183 "invalid WQE Data Segment size");
5184 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5185 "invalid WQE size");
5187 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5188 /* We should support Multi-Segment Packets. */
5189 olx |= MLX5_TXOFF_CONFIG_MULTI;
5191 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5192 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5193 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5194 DEV_TX_OFFLOAD_IP_TNL_TSO |
5195 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5196 /* We should support TCP Send Offload. */
5197 olx |= MLX5_TXOFF_CONFIG_TSO;
5199 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5200 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5201 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5202 /* We should support Software Parser for Tunnels. */
5203 olx |= MLX5_TXOFF_CONFIG_SWP;
5205 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5206 DEV_TX_OFFLOAD_UDP_CKSUM |
5207 DEV_TX_OFFLOAD_TCP_CKSUM |
5208 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5209 /* We should support IP/TCP/UDP Checksums. */
5210 olx |= MLX5_TXOFF_CONFIG_CSUM;
5212 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5213 /* We should support VLAN insertion. */
5214 olx |= MLX5_TXOFF_CONFIG_VLAN;
5216 if (priv->txqs_n && (*priv->txqs)[0]) {
5217 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5219 if (txd->inlen_send) {
5221 * Check the data inline requirements. Data inline
5222 * is enabled on per device basis, we can check
5223 * the first Tx queue only.
5225 * If device does not support VLAN insertion in WQE
5226 * and some queues are requested to perform VLAN
5227 * insertion offload than inline must be enabled.
5229 olx |= MLX5_TXOFF_CONFIG_INLINE;
5232 if (config->mps == MLX5_MPW_ENHANCED &&
5233 config->txq_inline_min <= 0) {
5235 * The NIC supports Enhanced Multi-Packet Write
5236 * and does not require minimal inline data.
5238 olx |= MLX5_TXOFF_CONFIG_EMPW;
5240 if (rte_flow_dynf_metadata_avail()) {
5241 /* We should support Flow metadata. */
5242 olx |= MLX5_TXOFF_CONFIG_METADATA;
5244 if (config->mps == MLX5_MPW) {
5246 * The NIC supports Legacy Multi-Packet Write.
5247 * The MLX5_TXOFF_CONFIG_MPW controls the
5248 * descriptor building method in combination
5249 * with MLX5_TXOFF_CONFIG_EMPW.
5251 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5252 MLX5_TXOFF_CONFIG_SWP |
5253 MLX5_TXOFF_CONFIG_VLAN |
5254 MLX5_TXOFF_CONFIG_METADATA)))
5255 olx |= MLX5_TXOFF_CONFIG_EMPW |
5256 MLX5_TXOFF_CONFIG_MPW;
5259 * Scan the routines table to find the minimal
5260 * satisfying routine with requested offloads.
5262 m = RTE_DIM(txoff_func);
5263 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5266 tmp = txoff_func[i].olx;
5268 /* Meets requested offloads exactly.*/
5272 if ((tmp & olx) != olx) {
5273 /* Does not meet requested offloads at all. */
5276 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5277 /* Do not enable eMPW if not configured. */
5279 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5280 /* Do not enable inlining if not configured. */
5283 * Some routine meets the requirements.
5284 * Check whether it has minimal amount
5285 * of not requested offloads.
5287 tmp = __builtin_popcountl(tmp & ~olx);
5288 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5289 /* First or better match, save and continue. */
5295 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5296 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5297 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5298 /* Lighter not requested offload. */
5303 if (m >= RTE_DIM(txoff_func)) {
5304 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5305 " for requested offloads %04X",
5306 dev->data->port_id, olx);
5309 DRV_LOG(DEBUG, "port %u has selected Tx function"
5310 " supporting offloads %04X/%04X",
5311 dev->data->port_id, olx, txoff_func[m].olx);
5312 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5313 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5314 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5315 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5316 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5317 DRV_LOG(DEBUG, "\tSWP (software parser)");
5318 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5319 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5320 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5321 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5322 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5323 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5324 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5325 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5326 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5327 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5328 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5330 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5332 return txoff_func[m].func;