1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, uint32_t *rss_hash);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
46 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
47 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
51 * Build a table to translate Rx completion flags to packet type.
53 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
56 mlx5_set_ptype_table(void)
59 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
61 /* Last entry must not be overwritten, reserved for errored packet. */
62 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
63 (*p)[i] = RTE_PTYPE_UNKNOWN;
65 * The index to the array should have:
66 * bit[1:0] = l3_hdr_type
67 * bit[4:2] = l4_hdr_type
70 * bit[7] = outer_l3_type
73 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
75 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
77 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
80 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
82 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
85 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
89 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
91 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
93 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
95 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
98 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
100 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
102 /* Repeat with outer_l3_type being set. Just in case. */
103 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
107 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
109 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
111 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
113 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
115 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
117 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
119 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
121 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
123 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
125 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
128 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
130 RTE_PTYPE_INNER_L4_NONFRAG;
131 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
132 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
133 RTE_PTYPE_INNER_L4_NONFRAG;
134 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
136 RTE_PTYPE_INNER_L4_NONFRAG;
137 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
138 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
139 RTE_PTYPE_INNER_L4_NONFRAG;
140 /* Tunneled - Fragmented */
141 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L4_FRAG;
144 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
146 RTE_PTYPE_INNER_L4_FRAG;
147 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L4_FRAG;
150 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L4_FRAG;
154 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L4_TCP;
157 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L4_TCP;
160 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
162 RTE_PTYPE_INNER_L4_TCP;
163 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L4_TCP;
166 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
191 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L4_UDP;
194 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L4_UDP;
197 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
199 RTE_PTYPE_INNER_L4_UDP;
200 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
202 RTE_PTYPE_INNER_L4_UDP;
206 * Return the size of tailroom of WQ.
209 * Pointer to TX queue structure.
211 * Pointer to tail of WQ.
217 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
220 tailroom = (uintptr_t)(txq->wqes) +
221 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
227 * Copy data to tailroom of circular queue.
230 * Pointer to destination.
234 * Number of bytes to copy.
236 * Pointer to head of queue.
238 * Size of tailroom from dst.
241 * Pointer after copied data.
244 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
245 void *base, size_t tailroom)
250 rte_memcpy(dst, src, tailroom);
251 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
253 ret = (uint8_t *)base + n - tailroom;
255 rte_memcpy(dst, src, n);
256 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
262 * Inline TSO headers into WQE.
265 * 0 on success, negative errno value on failure.
268 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
272 uint16_t *pkt_inline_sz,
276 uint16_t *tso_header_sz)
278 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
279 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
281 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
282 const uint8_t tunneled = txq->tunnel_en &&
283 (buf->ol_flags & (PKT_TX_TUNNEL_GRE |
284 PKT_TX_TUNNEL_VXLAN));
287 *tso_segsz = buf->tso_segsz;
288 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
289 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
290 txq->stats.oerrors++;
294 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
295 *cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
297 *cs_flags |= MLX5_ETH_WQE_L4_CSUM;
299 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER)) {
300 txq->stats.oerrors++;
303 copy_b = *tso_header_sz - *pkt_inline_sz;
304 /* First seg must contain all TSO headers. */
305 assert(copy_b <= *length);
306 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
308 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
309 if (unlikely(*max_wqe < n_wqe))
312 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
315 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
316 *pkt_inline_sz += copy_b;
322 * DPDK callback to check the status of a tx descriptor.
327 * The index of the descriptor in the ring.
330 * The status of the tx descriptor.
333 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
335 struct mlx5_txq_data *txq = tx_queue;
338 mlx5_tx_complete(txq);
339 used = txq->elts_head - txq->elts_tail;
341 return RTE_ETH_TX_DESC_FULL;
342 return RTE_ETH_TX_DESC_DONE;
346 * DPDK callback to check the status of a rx descriptor.
351 * The index of the descriptor in the ring.
354 * The status of the tx descriptor.
357 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
359 struct mlx5_rxq_data *rxq = rx_queue;
360 struct rxq_zip *zip = &rxq->zip;
361 volatile struct mlx5_cqe *cqe;
362 const unsigned int cqe_n = (1 << rxq->cqe_n);
363 const unsigned int cqe_cnt = cqe_n - 1;
367 /* if we are processing a compressed cqe */
369 used = zip->cqe_cnt - zip->ca;
375 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
376 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
380 op_own = cqe->op_own;
381 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
382 n = rte_be_to_cpu_32(cqe->byte_cnt);
387 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
389 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
391 return RTE_ETH_RX_DESC_DONE;
392 return RTE_ETH_RX_DESC_AVAIL;
396 * DPDK callback for TX.
399 * Generic pointer to TX queue structure.
401 * Packets to transmit.
403 * Number of packets in array.
406 * Number of packets successfully transmitted (<= pkts_n).
409 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
411 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
412 uint16_t elts_head = txq->elts_head;
413 const uint16_t elts_n = 1 << txq->elts_n;
414 const uint16_t elts_m = elts_n - 1;
421 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
422 unsigned int segs_n = 0;
423 const unsigned int max_inline = txq->max_inline;
425 if (unlikely(!pkts_n))
427 /* Prefetch first packet cacheline. */
428 rte_prefetch0(*pkts);
429 /* Start processing. */
430 mlx5_tx_complete(txq);
431 max_elts = (elts_n - (elts_head - txq->elts_tail));
432 /* A CQE slot must always be available. */
433 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
434 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
435 if (unlikely(!max_wqe))
438 struct rte_mbuf *buf = NULL;
440 volatile struct mlx5_wqe_v *wqe = NULL;
441 volatile rte_v128u32_t *dseg = NULL;
444 unsigned int sg = 0; /* counter of additional segs attached. */
446 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
447 uint16_t tso_header_sz = 0;
451 uint16_t tso_segsz = 0;
452 #ifdef MLX5_PMD_SOFT_COUNTERS
453 uint32_t total_length = 0;
459 segs_n = buf->nb_segs;
461 * Make sure there is enough room to store this packet and
462 * that one ring entry remains unused.
465 if (max_elts < segs_n)
469 if (unlikely(--max_wqe == 0))
471 wqe = (volatile struct mlx5_wqe_v *)
472 tx_mlx5_wqe(txq, txq->wqe_ci);
473 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
475 rte_prefetch0(*(pkts + 1));
476 addr = rte_pktmbuf_mtod(buf, uintptr_t);
477 length = DATA_LEN(buf);
478 ehdr = (((uint8_t *)addr)[1] << 8) |
479 ((uint8_t *)addr)[0];
480 #ifdef MLX5_PMD_SOFT_COUNTERS
481 total_length = length;
483 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
484 txq->stats.oerrors++;
487 /* Update element. */
488 (*txq->elts)[elts_head & elts_m] = buf;
489 /* Prefetch next buffer data. */
492 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
493 cs_flags = txq_ol_cksum_to_cs(txq, buf);
494 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
495 /* Replace the Ethernet type by the VLAN if necessary. */
496 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
497 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
499 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
503 /* Copy Destination and source mac address. */
504 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
506 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
507 /* Copy missing two bytes to end the DSeg. */
508 memcpy((uint8_t *)raw + len + sizeof(vlan),
509 ((uint8_t *)addr) + len, 2);
513 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
514 MLX5_WQE_DWORD_SIZE);
515 length -= pkt_inline_sz;
516 addr += pkt_inline_sz;
518 raw += MLX5_WQE_DWORD_SIZE;
519 tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
521 ret = inline_tso(txq, buf, &length, &cs_flags,
522 &addr, &pkt_inline_sz,
524 &tso_segsz, &tso_header_sz);
525 if (ret == -EINVAL) {
527 } else if (ret == -EAGAIN) {
529 wqe->ctrl = (rte_v128u32_t){
530 rte_cpu_to_be_32(txq->wqe_ci << 8),
531 rte_cpu_to_be_32(txq->qp_num_8s | 1),
536 #ifdef MLX5_PMD_SOFT_COUNTERS
543 /* Inline if enough room. */
544 if (max_inline || tso) {
546 uintptr_t end = (uintptr_t)
547 (((uintptr_t)txq->wqes) +
548 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
549 unsigned int inline_room = max_inline *
550 RTE_CACHE_LINE_SIZE -
551 (pkt_inline_sz - 2) -
557 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
558 RTE_CACHE_LINE_SIZE);
559 copy_b = (addr_end > addr) ?
560 RTE_MIN((addr_end - addr), length) : 0;
561 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
563 * One Dseg remains in the current WQE. To
564 * keep the computation positive, it is
565 * removed after the bytes to Dseg conversion.
567 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
569 if (unlikely(max_wqe < n))
573 inl = rte_cpu_to_be_32(copy_b |
575 rte_memcpy((void *)raw,
576 (void *)&inl, sizeof(inl));
578 pkt_inline_sz += sizeof(inl);
580 rte_memcpy((void *)raw, (void *)addr, copy_b);
583 pkt_inline_sz += copy_b;
586 * 2 DWORDs consumed by the WQE header + ETH segment +
587 * the size of the inline part of the packet.
589 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
591 if (ds % (MLX5_WQE_SIZE /
592 MLX5_WQE_DWORD_SIZE) == 0) {
593 if (unlikely(--max_wqe == 0))
595 dseg = (volatile rte_v128u32_t *)
596 tx_mlx5_wqe(txq, txq->wqe_ci +
599 dseg = (volatile rte_v128u32_t *)
601 (ds * MLX5_WQE_DWORD_SIZE));
604 } else if (!segs_n) {
608 inline_room -= copy_b;
612 addr = rte_pktmbuf_mtod(buf, uintptr_t);
613 length = DATA_LEN(buf);
614 #ifdef MLX5_PMD_SOFT_COUNTERS
615 total_length += length;
617 (*txq->elts)[++elts_head & elts_m] = buf;
622 * No inline has been done in the packet, only the
623 * Ethernet Header as been stored.
625 dseg = (volatile rte_v128u32_t *)
626 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
629 /* Add the remaining packet as a simple ds. */
630 addr = rte_cpu_to_be_64(addr);
631 *dseg = (rte_v128u32_t){
632 rte_cpu_to_be_32(length),
633 mlx5_tx_mb2mr(txq, buf),
646 * Spill on next WQE when the current one does not have
647 * enough room left. Size of WQE must a be a multiple
648 * of data segment size.
650 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
651 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
652 if (unlikely(--max_wqe == 0))
654 dseg = (volatile rte_v128u32_t *)
655 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
656 rte_prefetch0(tx_mlx5_wqe(txq,
657 txq->wqe_ci + ds / 4 + 1));
664 length = DATA_LEN(buf);
665 #ifdef MLX5_PMD_SOFT_COUNTERS
666 total_length += length;
668 /* Store segment information. */
669 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
670 *dseg = (rte_v128u32_t){
671 rte_cpu_to_be_32(length),
672 mlx5_tx_mb2mr(txq, buf),
676 (*txq->elts)[++elts_head & elts_m] = buf;
680 if (ds > MLX5_DSEG_MAX) {
681 txq->stats.oerrors++;
688 /* Initialize known and common part of the WQE structure. */
690 wqe->ctrl = (rte_v128u32_t){
691 rte_cpu_to_be_32((txq->wqe_ci << 8) |
693 rte_cpu_to_be_32(txq->qp_num_8s | ds),
697 wqe->eseg = (rte_v128u32_t){
699 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
701 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
704 wqe->ctrl = (rte_v128u32_t){
705 rte_cpu_to_be_32((txq->wqe_ci << 8) |
707 rte_cpu_to_be_32(txq->qp_num_8s | ds),
711 wqe->eseg = (rte_v128u32_t){
715 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
719 txq->wqe_ci += (ds + 3) / 4;
720 /* Save the last successful WQE for completion request */
721 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
722 #ifdef MLX5_PMD_SOFT_COUNTERS
723 /* Increment sent bytes counter. */
724 txq->stats.obytes += total_length;
726 } while (i < pkts_n);
727 /* Take a shortcut if nothing must be sent. */
728 if (unlikely((i + k) == 0))
730 txq->elts_head += (i + j);
731 /* Check whether completion threshold has been reached. */
732 comp = txq->elts_comp + i + j + k;
733 if (comp >= MLX5_TX_COMP_THRESH) {
734 /* Request completion on last WQE. */
735 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
736 /* Save elts_head in unused "immediate" field of WQE. */
737 last_wqe->ctrl3 = txq->elts_head;
743 txq->elts_comp = comp;
745 #ifdef MLX5_PMD_SOFT_COUNTERS
746 /* Increment sent packets counter. */
747 txq->stats.opackets += i;
749 /* Ring QP doorbell. */
750 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
755 * Open a MPW session.
758 * Pointer to TX queue structure.
760 * Pointer to MPW session structure.
765 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
767 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
768 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
769 (volatile struct mlx5_wqe_data_seg (*)[])
770 tx_mlx5_wqe(txq, idx + 1);
772 mpw->state = MLX5_MPW_STATE_OPENED;
776 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
777 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
778 mpw->wqe->eseg.inline_hdr_sz = 0;
779 mpw->wqe->eseg.rsvd0 = 0;
780 mpw->wqe->eseg.rsvd1 = 0;
781 mpw->wqe->eseg.rsvd2 = 0;
782 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
785 mpw->wqe->ctrl[2] = 0;
786 mpw->wqe->ctrl[3] = 0;
787 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
788 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
789 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
790 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
791 mpw->data.dseg[2] = &(*dseg)[0];
792 mpw->data.dseg[3] = &(*dseg)[1];
793 mpw->data.dseg[4] = &(*dseg)[2];
797 * Close a MPW session.
800 * Pointer to TX queue structure.
802 * Pointer to MPW session structure.
805 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
807 unsigned int num = mpw->pkts_n;
810 * Store size in multiple of 16 bytes. Control and Ethernet segments
813 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
814 mpw->state = MLX5_MPW_STATE_CLOSED;
819 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
820 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
824 * DPDK callback for TX with MPW support.
827 * Generic pointer to TX queue structure.
829 * Packets to transmit.
831 * Number of packets in array.
834 * Number of packets successfully transmitted (<= pkts_n).
837 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
839 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
840 uint16_t elts_head = txq->elts_head;
841 const uint16_t elts_n = 1 << txq->elts_n;
842 const uint16_t elts_m = elts_n - 1;
848 struct mlx5_mpw mpw = {
849 .state = MLX5_MPW_STATE_CLOSED,
852 if (unlikely(!pkts_n))
854 /* Prefetch first packet cacheline. */
855 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
856 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
857 /* Start processing. */
858 mlx5_tx_complete(txq);
859 max_elts = (elts_n - (elts_head - txq->elts_tail));
860 /* A CQE slot must always be available. */
861 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
862 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
863 if (unlikely(!max_wqe))
866 struct rte_mbuf *buf = *(pkts++);
868 unsigned int segs_n = buf->nb_segs;
872 * Make sure there is enough room to store this packet and
873 * that one ring entry remains unused.
876 if (max_elts < segs_n)
878 /* Do not bother with large packets MPW cannot handle. */
879 if (segs_n > MLX5_MPW_DSEG_MAX) {
880 txq->stats.oerrors++;
885 cs_flags = txq_ol_cksum_to_cs(txq, buf);
886 /* Retrieve packet information. */
887 length = PKT_LEN(buf);
889 /* Start new session if packet differs. */
890 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
891 ((mpw.len != length) ||
893 (mpw.wqe->eseg.cs_flags != cs_flags)))
894 mlx5_mpw_close(txq, &mpw);
895 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
897 * Multi-Packet WQE consumes at most two WQE.
898 * mlx5_mpw_new() expects to be able to use such
901 if (unlikely(max_wqe < 2))
904 mlx5_mpw_new(txq, &mpw, length);
905 mpw.wqe->eseg.cs_flags = cs_flags;
907 /* Multi-segment packets must be alone in their MPW. */
908 assert((segs_n == 1) || (mpw.pkts_n == 0));
909 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
913 volatile struct mlx5_wqe_data_seg *dseg;
917 (*txq->elts)[elts_head++ & elts_m] = buf;
918 dseg = mpw.data.dseg[mpw.pkts_n];
919 addr = rte_pktmbuf_mtod(buf, uintptr_t);
920 *dseg = (struct mlx5_wqe_data_seg){
921 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
922 .lkey = mlx5_tx_mb2mr(txq, buf),
923 .addr = rte_cpu_to_be_64(addr),
925 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
926 length += DATA_LEN(buf);
932 assert(length == mpw.len);
933 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
934 mlx5_mpw_close(txq, &mpw);
935 #ifdef MLX5_PMD_SOFT_COUNTERS
936 /* Increment sent bytes counter. */
937 txq->stats.obytes += length;
941 /* Take a shortcut if nothing must be sent. */
942 if (unlikely(i == 0))
944 /* Check whether completion threshold has been reached. */
945 /* "j" includes both packets and segments. */
946 comp = txq->elts_comp + j;
947 if (comp >= MLX5_TX_COMP_THRESH) {
948 volatile struct mlx5_wqe *wqe = mpw.wqe;
950 /* Request completion on last WQE. */
951 wqe->ctrl[2] = rte_cpu_to_be_32(8);
952 /* Save elts_head in unused "immediate" field of WQE. */
953 wqe->ctrl[3] = elts_head;
959 txq->elts_comp = comp;
961 #ifdef MLX5_PMD_SOFT_COUNTERS
962 /* Increment sent packets counter. */
963 txq->stats.opackets += i;
965 /* Ring QP doorbell. */
966 if (mpw.state == MLX5_MPW_STATE_OPENED)
967 mlx5_mpw_close(txq, &mpw);
968 mlx5_tx_dbrec(txq, mpw.wqe);
969 txq->elts_head = elts_head;
974 * Open a MPW inline session.
977 * Pointer to TX queue structure.
979 * Pointer to MPW session structure.
984 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
987 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
988 struct mlx5_wqe_inl_small *inl;
990 mpw->state = MLX5_MPW_INL_STATE_OPENED;
994 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
995 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
998 mpw->wqe->ctrl[2] = 0;
999 mpw->wqe->ctrl[3] = 0;
1000 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1001 mpw->wqe->eseg.inline_hdr_sz = 0;
1002 mpw->wqe->eseg.cs_flags = 0;
1003 mpw->wqe->eseg.rsvd0 = 0;
1004 mpw->wqe->eseg.rsvd1 = 0;
1005 mpw->wqe->eseg.rsvd2 = 0;
1006 inl = (struct mlx5_wqe_inl_small *)
1007 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1008 mpw->data.raw = (uint8_t *)&inl->raw;
1012 * Close a MPW inline session.
1015 * Pointer to TX queue structure.
1017 * Pointer to MPW session structure.
1020 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1023 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1024 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1026 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1028 * Store size in multiple of 16 bytes. Control and Ethernet segments
1031 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1033 mpw->state = MLX5_MPW_STATE_CLOSED;
1034 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1035 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1039 * DPDK callback for TX with MPW inline support.
1042 * Generic pointer to TX queue structure.
1044 * Packets to transmit.
1046 * Number of packets in array.
1049 * Number of packets successfully transmitted (<= pkts_n).
1052 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1055 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1056 uint16_t elts_head = txq->elts_head;
1057 const uint16_t elts_n = 1 << txq->elts_n;
1058 const uint16_t elts_m = elts_n - 1;
1064 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1065 struct mlx5_mpw mpw = {
1066 .state = MLX5_MPW_STATE_CLOSED,
1069 * Compute the maximum number of WQE which can be consumed by inline
1072 * - 1 control segment,
1073 * - 1 Ethernet segment,
1074 * - N Dseg from the inline request.
1076 const unsigned int wqe_inl_n =
1077 ((2 * MLX5_WQE_DWORD_SIZE +
1078 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1079 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1081 if (unlikely(!pkts_n))
1083 /* Prefetch first packet cacheline. */
1084 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1085 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1086 /* Start processing. */
1087 mlx5_tx_complete(txq);
1088 max_elts = (elts_n - (elts_head - txq->elts_tail));
1089 /* A CQE slot must always be available. */
1090 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1092 struct rte_mbuf *buf = *(pkts++);
1095 unsigned int segs_n = buf->nb_segs;
1099 * Make sure there is enough room to store this packet and
1100 * that one ring entry remains unused.
1103 if (max_elts < segs_n)
1105 /* Do not bother with large packets MPW cannot handle. */
1106 if (segs_n > MLX5_MPW_DSEG_MAX) {
1107 txq->stats.oerrors++;
1113 * Compute max_wqe in case less WQE were consumed in previous
1116 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1117 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1118 /* Retrieve packet information. */
1119 length = PKT_LEN(buf);
1120 /* Start new session if packet differs. */
1121 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1122 if ((mpw.len != length) ||
1124 (mpw.wqe->eseg.cs_flags != cs_flags))
1125 mlx5_mpw_close(txq, &mpw);
1126 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1127 if ((mpw.len != length) ||
1129 (length > inline_room) ||
1130 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1131 mlx5_mpw_inline_close(txq, &mpw);
1133 txq->max_inline * RTE_CACHE_LINE_SIZE;
1136 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1137 if ((segs_n != 1) ||
1138 (length > inline_room)) {
1140 * Multi-Packet WQE consumes at most two WQE.
1141 * mlx5_mpw_new() expects to be able to use
1144 if (unlikely(max_wqe < 2))
1147 mlx5_mpw_new(txq, &mpw, length);
1148 mpw.wqe->eseg.cs_flags = cs_flags;
1150 if (unlikely(max_wqe < wqe_inl_n))
1152 max_wqe -= wqe_inl_n;
1153 mlx5_mpw_inline_new(txq, &mpw, length);
1154 mpw.wqe->eseg.cs_flags = cs_flags;
1157 /* Multi-segment packets must be alone in their MPW. */
1158 assert((segs_n == 1) || (mpw.pkts_n == 0));
1159 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1160 assert(inline_room ==
1161 txq->max_inline * RTE_CACHE_LINE_SIZE);
1162 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1166 volatile struct mlx5_wqe_data_seg *dseg;
1169 (*txq->elts)[elts_head++ & elts_m] = buf;
1170 dseg = mpw.data.dseg[mpw.pkts_n];
1171 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1172 *dseg = (struct mlx5_wqe_data_seg){
1174 rte_cpu_to_be_32(DATA_LEN(buf)),
1175 .lkey = mlx5_tx_mb2mr(txq, buf),
1176 .addr = rte_cpu_to_be_64(addr),
1178 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1179 length += DATA_LEN(buf);
1185 assert(length == mpw.len);
1186 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1187 mlx5_mpw_close(txq, &mpw);
1191 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1192 assert(length <= inline_room);
1193 assert(length == DATA_LEN(buf));
1194 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1195 (*txq->elts)[elts_head++ & elts_m] = buf;
1196 /* Maximum number of bytes before wrapping. */
1197 max = ((((uintptr_t)(txq->wqes)) +
1200 (uintptr_t)mpw.data.raw);
1202 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1205 mpw.data.raw = (volatile void *)txq->wqes;
1206 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1207 (void *)(addr + max),
1209 mpw.data.raw += length - max;
1211 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1217 (volatile void *)txq->wqes;
1219 mpw.data.raw += length;
1222 mpw.total_len += length;
1224 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1225 mlx5_mpw_inline_close(txq, &mpw);
1227 txq->max_inline * RTE_CACHE_LINE_SIZE;
1229 inline_room -= length;
1232 #ifdef MLX5_PMD_SOFT_COUNTERS
1233 /* Increment sent bytes counter. */
1234 txq->stats.obytes += length;
1238 /* Take a shortcut if nothing must be sent. */
1239 if (unlikely(i == 0))
1241 /* Check whether completion threshold has been reached. */
1242 /* "j" includes both packets and segments. */
1243 comp = txq->elts_comp + j;
1244 if (comp >= MLX5_TX_COMP_THRESH) {
1245 volatile struct mlx5_wqe *wqe = mpw.wqe;
1247 /* Request completion on last WQE. */
1248 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1249 /* Save elts_head in unused "immediate" field of WQE. */
1250 wqe->ctrl[3] = elts_head;
1256 txq->elts_comp = comp;
1258 #ifdef MLX5_PMD_SOFT_COUNTERS
1259 /* Increment sent packets counter. */
1260 txq->stats.opackets += i;
1262 /* Ring QP doorbell. */
1263 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1264 mlx5_mpw_inline_close(txq, &mpw);
1265 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1266 mlx5_mpw_close(txq, &mpw);
1267 mlx5_tx_dbrec(txq, mpw.wqe);
1268 txq->elts_head = elts_head;
1273 * Open an Enhanced MPW session.
1276 * Pointer to TX queue structure.
1278 * Pointer to MPW session structure.
1283 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1285 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1287 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1289 mpw->total_len = sizeof(struct mlx5_wqe);
1290 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1292 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1293 (txq->wqe_ci << 8) |
1294 MLX5_OPCODE_ENHANCED_MPSW);
1295 mpw->wqe->ctrl[2] = 0;
1296 mpw->wqe->ctrl[3] = 0;
1297 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1298 if (unlikely(padding)) {
1299 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1301 /* Pad the first 2 DWORDs with zero-length inline header. */
1302 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1303 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1304 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1305 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1306 /* Start from the next WQEBB. */
1307 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1309 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1314 * Close an Enhanced MPW session.
1317 * Pointer to TX queue structure.
1319 * Pointer to MPW session structure.
1322 * Number of consumed WQEs.
1324 static inline uint16_t
1325 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1329 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1332 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1333 MLX5_WQE_DS(mpw->total_len));
1334 mpw->state = MLX5_MPW_STATE_CLOSED;
1335 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1341 * TX with Enhanced MPW support.
1344 * Pointer to TX queue structure.
1346 * Packets to transmit.
1348 * Number of packets in array.
1351 * Number of packets successfully transmitted (<= pkts_n).
1353 static inline uint16_t
1354 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1357 uint16_t elts_head = txq->elts_head;
1358 const uint16_t elts_n = 1 << txq->elts_n;
1359 const uint16_t elts_m = elts_n - 1;
1364 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1365 unsigned int mpw_room = 0;
1366 unsigned int inl_pad = 0;
1368 struct mlx5_mpw mpw = {
1369 .state = MLX5_MPW_STATE_CLOSED,
1372 if (unlikely(!pkts_n))
1374 /* Start processing. */
1375 mlx5_tx_complete(txq);
1376 max_elts = (elts_n - (elts_head - txq->elts_tail));
1377 /* A CQE slot must always be available. */
1378 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1379 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1380 if (unlikely(!max_wqe))
1383 struct rte_mbuf *buf = *(pkts++);
1385 unsigned int do_inline = 0; /* Whether inline is possible. */
1389 /* Multi-segmented packet is handled in slow-path outside. */
1390 assert(NB_SEGS(buf) == 1);
1391 /* Make sure there is enough room to store this packet. */
1392 if (max_elts - j == 0)
1394 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1395 /* Retrieve packet information. */
1396 length = PKT_LEN(buf);
1397 /* Start new session if:
1398 * - multi-segment packet
1399 * - no space left even for a dseg
1400 * - next packet can be inlined with a new WQE
1403 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1404 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1406 (length <= txq->inline_max_packet_sz &&
1407 inl_pad + sizeof(inl_hdr) + length >
1409 (mpw.wqe->eseg.cs_flags != cs_flags))
1410 max_wqe -= mlx5_empw_close(txq, &mpw);
1412 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1413 /* In Enhanced MPW, inline as much as the budget is
1414 * allowed. The remaining space is to be filled with
1415 * dsegs. If the title WQEBB isn't padded, it will have
1418 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1419 (max_inline ? max_inline :
1420 pkts_n * MLX5_WQE_DWORD_SIZE) +
1422 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1424 /* Don't pad the title WQEBB to not waste WQ. */
1425 mlx5_empw_new(txq, &mpw, 0);
1426 mpw_room -= mpw.total_len;
1428 do_inline = length <= txq->inline_max_packet_sz &&
1429 sizeof(inl_hdr) + length <= mpw_room &&
1431 mpw.wqe->eseg.cs_flags = cs_flags;
1433 /* Evaluate whether the next packet can be inlined.
1434 * Inlininig is possible when:
1435 * - length is less than configured value
1436 * - length fits for remaining space
1437 * - not required to fill the title WQEBB with dsegs
1440 length <= txq->inline_max_packet_sz &&
1441 inl_pad + sizeof(inl_hdr) + length <=
1443 (!txq->mpw_hdr_dseg ||
1444 mpw.total_len >= MLX5_WQE_SIZE);
1446 if (max_inline && do_inline) {
1447 /* Inline packet into WQE. */
1450 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1451 assert(length == DATA_LEN(buf));
1452 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1453 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1454 mpw.data.raw = (volatile void *)
1455 ((uintptr_t)mpw.data.raw + inl_pad);
1456 max = tx_mlx5_wq_tailroom(txq,
1457 (void *)(uintptr_t)mpw.data.raw);
1458 /* Copy inline header. */
1459 mpw.data.raw = (volatile void *)
1461 (void *)(uintptr_t)mpw.data.raw,
1464 (void *)(uintptr_t)txq->wqes,
1466 max = tx_mlx5_wq_tailroom(txq,
1467 (void *)(uintptr_t)mpw.data.raw);
1468 /* Copy packet data. */
1469 mpw.data.raw = (volatile void *)
1471 (void *)(uintptr_t)mpw.data.raw,
1474 (void *)(uintptr_t)txq->wqes,
1477 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1478 /* No need to get completion as the entire packet is
1479 * copied to WQ. Free the buf right away.
1481 rte_pktmbuf_free_seg(buf);
1482 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1483 /* Add pad in the next packet if any. */
1484 inl_pad = (((uintptr_t)mpw.data.raw +
1485 (MLX5_WQE_DWORD_SIZE - 1)) &
1486 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1487 (uintptr_t)mpw.data.raw;
1489 /* No inline. Load a dseg of packet pointer. */
1490 volatile rte_v128u32_t *dseg;
1492 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1493 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1494 assert(length == DATA_LEN(buf));
1495 if (!tx_mlx5_wq_tailroom(txq,
1496 (void *)((uintptr_t)mpw.data.raw
1498 dseg = (volatile void *)txq->wqes;
1500 dseg = (volatile void *)
1501 ((uintptr_t)mpw.data.raw +
1503 (*txq->elts)[elts_head++ & elts_m] = buf;
1504 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1506 *dseg = (rte_v128u32_t) {
1507 rte_cpu_to_be_32(length),
1508 mlx5_tx_mb2mr(txq, buf),
1512 mpw.data.raw = (volatile void *)(dseg + 1);
1513 mpw.total_len += (inl_pad + sizeof(*dseg));
1516 mpw_room -= (inl_pad + sizeof(*dseg));
1519 #ifdef MLX5_PMD_SOFT_COUNTERS
1520 /* Increment sent bytes counter. */
1521 txq->stats.obytes += length;
1524 } while (i < pkts_n);
1525 /* Take a shortcut if nothing must be sent. */
1526 if (unlikely(i == 0))
1528 /* Check whether completion threshold has been reached. */
1529 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1530 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1531 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1532 volatile struct mlx5_wqe *wqe = mpw.wqe;
1534 /* Request completion on last WQE. */
1535 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1536 /* Save elts_head in unused "immediate" field of WQE. */
1537 wqe->ctrl[3] = elts_head;
1539 txq->mpw_comp = txq->wqe_ci;
1544 txq->elts_comp += j;
1546 #ifdef MLX5_PMD_SOFT_COUNTERS
1547 /* Increment sent packets counter. */
1548 txq->stats.opackets += i;
1550 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1551 mlx5_empw_close(txq, &mpw);
1552 /* Ring QP doorbell. */
1553 mlx5_tx_dbrec(txq, mpw.wqe);
1554 txq->elts_head = elts_head;
1559 * DPDK callback for TX with Enhanced MPW support.
1562 * Generic pointer to TX queue structure.
1564 * Packets to transmit.
1566 * Number of packets in array.
1569 * Number of packets successfully transmitted (<= pkts_n).
1572 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1574 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1577 while (pkts_n > nb_tx) {
1581 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1583 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1588 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1590 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1600 * Translate RX completion flags to packet type.
1605 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1608 * Packet type for struct rte_mbuf.
1610 static inline uint32_t
1611 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1614 uint8_t pinfo = cqe->pkt_info;
1615 uint16_t ptype = cqe->hdr_type_etc;
1618 * The index to the array should have:
1619 * bit[1:0] = l3_hdr_type
1620 * bit[4:2] = l4_hdr_type
1623 * bit[7] = outer_l3_type
1625 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1626 return mlx5_ptype_table[idx];
1630 * Get size of the next packet for a given CQE. For compressed CQEs, the
1631 * consumer index is updated only once all packets of the current one have
1635 * Pointer to RX queue.
1638 * @param[out] rss_hash
1639 * Packet RSS Hash result.
1642 * Packet size in bytes (0 if there is none), -1 in case of completion
1646 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1647 uint16_t cqe_cnt, uint32_t *rss_hash)
1649 struct rxq_zip *zip = &rxq->zip;
1650 uint16_t cqe_n = cqe_cnt + 1;
1654 /* Process compressed data in the CQE and mini arrays. */
1656 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1657 (volatile struct mlx5_mini_cqe8 (*)[8])
1658 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1660 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1661 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1662 if ((++zip->ai & 7) == 0) {
1663 /* Invalidate consumed CQEs */
1666 while (idx != end) {
1667 (*rxq->cqes)[idx & cqe_cnt].op_own =
1668 MLX5_CQE_INVALIDATE;
1672 * Increment consumer index to skip the number of
1673 * CQEs consumed. Hardware leaves holes in the CQ
1674 * ring for software use.
1679 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1680 /* Invalidate the rest */
1684 while (idx != end) {
1685 (*rxq->cqes)[idx & cqe_cnt].op_own =
1686 MLX5_CQE_INVALIDATE;
1689 rxq->cq_ci = zip->cq_ci;
1692 /* No compressed data, get next CQE and verify if it is compressed. */
1697 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1698 if (unlikely(ret == 1))
1701 op_own = cqe->op_own;
1703 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1704 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1705 (volatile struct mlx5_mini_cqe8 (*)[8])
1706 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1709 /* Fix endianness. */
1710 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1712 * Current mini array position is the one returned by
1715 * If completion comprises several mini arrays, as a
1716 * special case the second one is located 7 CQEs after
1717 * the initial CQE instead of 8 for subsequent ones.
1719 zip->ca = rxq->cq_ci;
1720 zip->na = zip->ca + 7;
1721 /* Compute the next non compressed CQE. */
1723 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1724 /* Get packet size to return. */
1725 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1726 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1728 /* Prefetch all the entries to be invalidated */
1731 while (idx != end) {
1732 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1736 len = rte_be_to_cpu_32(cqe->byte_cnt);
1737 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1739 /* Error while receiving packet. */
1740 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1747 * Translate RX completion flags to offload flags.
1750 * Pointer to RX queue structure.
1755 * Offload flags (ol_flags) for struct rte_mbuf.
1757 static inline uint32_t
1758 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1760 uint32_t ol_flags = 0;
1761 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1765 MLX5_CQE_RX_L3_HDR_VALID,
1766 PKT_RX_IP_CKSUM_GOOD) |
1768 MLX5_CQE_RX_L4_HDR_VALID,
1769 PKT_RX_L4_CKSUM_GOOD);
1770 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1773 MLX5_CQE_RX_L3_HDR_VALID,
1774 PKT_RX_IP_CKSUM_GOOD) |
1776 MLX5_CQE_RX_L4_HDR_VALID,
1777 PKT_RX_L4_CKSUM_GOOD);
1782 * DPDK callback for RX.
1785 * Generic pointer to RX queue structure.
1787 * Array to store received packets.
1789 * Maximum number of packets in array.
1792 * Number of packets successfully received (<= pkts_n).
1795 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1797 struct mlx5_rxq_data *rxq = dpdk_rxq;
1798 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1799 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1800 const unsigned int sges_n = rxq->sges_n;
1801 struct rte_mbuf *pkt = NULL;
1802 struct rte_mbuf *seg = NULL;
1803 volatile struct mlx5_cqe *cqe =
1804 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1806 unsigned int rq_ci = rxq->rq_ci << sges_n;
1807 int len = 0; /* keep its value across iterations. */
1810 unsigned int idx = rq_ci & wqe_cnt;
1811 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1812 struct rte_mbuf *rep = (*rxq->elts)[idx];
1813 uint32_t rss_hash_res = 0;
1821 rep = rte_mbuf_raw_alloc(rxq->mp);
1822 if (unlikely(rep == NULL)) {
1823 ++rxq->stats.rx_nombuf;
1826 * no buffers before we even started,
1827 * bail out silently.
1831 while (pkt != seg) {
1832 assert(pkt != (*rxq->elts)[idx]);
1836 rte_mbuf_raw_free(pkt);
1842 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1843 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1846 rte_mbuf_raw_free(rep);
1849 if (unlikely(len == -1)) {
1850 /* RX error, packet is likely too large. */
1851 rte_mbuf_raw_free(rep);
1852 ++rxq->stats.idropped;
1856 assert(len >= (rxq->crc_present << 2));
1857 /* Update packet information. */
1858 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1860 if (rss_hash_res && rxq->rss_hash) {
1861 pkt->hash.rss = rss_hash_res;
1862 pkt->ol_flags = PKT_RX_RSS_HASH;
1865 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1866 pkt->ol_flags |= PKT_RX_FDIR;
1867 if (cqe->sop_drop_qpn !=
1868 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1869 uint32_t mark = cqe->sop_drop_qpn;
1871 pkt->ol_flags |= PKT_RX_FDIR_ID;
1873 mlx5_flow_mark_get(mark);
1876 if (rxq->csum | rxq->csum_l2tun)
1877 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1878 if (rxq->vlan_strip &&
1879 (cqe->hdr_type_etc &
1880 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1881 pkt->ol_flags |= PKT_RX_VLAN |
1882 PKT_RX_VLAN_STRIPPED;
1884 rte_be_to_cpu_16(cqe->vlan_info);
1886 if (rxq->hw_timestamp) {
1888 rte_be_to_cpu_64(cqe->timestamp);
1889 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1891 if (rxq->crc_present)
1892 len -= ETHER_CRC_LEN;
1895 DATA_LEN(rep) = DATA_LEN(seg);
1896 PKT_LEN(rep) = PKT_LEN(seg);
1897 SET_DATA_OFF(rep, DATA_OFF(seg));
1898 PORT(rep) = PORT(seg);
1899 (*rxq->elts)[idx] = rep;
1901 * Fill NIC descriptor with the new buffer. The lkey and size
1902 * of the buffers are already known, only the buffer address
1905 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1906 if (len > DATA_LEN(seg)) {
1907 len -= DATA_LEN(seg);
1912 DATA_LEN(seg) = len;
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914 /* Increment bytes counter. */
1915 rxq->stats.ibytes += PKT_LEN(pkt);
1917 /* Return packet. */
1923 /* Align consumer index to the next stride. */
1928 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1930 /* Update the consumer index. */
1931 rxq->rq_ci = rq_ci >> sges_n;
1933 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1935 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1936 #ifdef MLX5_PMD_SOFT_COUNTERS
1937 /* Increment packets counter. */
1938 rxq->stats.ipackets += i;
1944 * Dummy DPDK callback for TX.
1946 * This function is used to temporarily replace the real callback during
1947 * unsafe control operations on the queue, or in case of error.
1950 * Generic pointer to TX queue structure.
1952 * Packets to transmit.
1954 * Number of packets in array.
1957 * Number of packets successfully transmitted (<= pkts_n).
1960 removed_tx_burst(void *dpdk_txq __rte_unused,
1961 struct rte_mbuf **pkts __rte_unused,
1962 uint16_t pkts_n __rte_unused)
1968 * Dummy DPDK callback for RX.
1970 * This function is used to temporarily replace the real callback during
1971 * unsafe control operations on the queue, or in case of error.
1974 * Generic pointer to RX queue structure.
1976 * Array to store received packets.
1978 * Maximum number of packets in array.
1981 * Number of packets successfully received (<= pkts_n).
1984 removed_rx_burst(void *dpdk_txq __rte_unused,
1985 struct rte_mbuf **pkts __rte_unused,
1986 uint16_t pkts_n __rte_unused)
1992 * Vectorized Rx/Tx routines are not compiled in when required vector
1993 * instructions are not supported on a target architecture. The following null
1994 * stubs are needed for linkage when those are not included outside of this file
1995 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1998 uint16_t __attribute__((weak))
1999 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2000 struct rte_mbuf **pkts __rte_unused,
2001 uint16_t pkts_n __rte_unused)
2006 uint16_t __attribute__((weak))
2007 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2008 struct rte_mbuf **pkts __rte_unused,
2009 uint16_t pkts_n __rte_unused)
2014 uint16_t __attribute__((weak))
2015 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2016 struct rte_mbuf **pkts __rte_unused,
2017 uint16_t pkts_n __rte_unused)
2022 int __attribute__((weak))
2023 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2028 int __attribute__((weak))
2029 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2034 int __attribute__((weak))
2035 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2040 int __attribute__((weak))
2041 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)