drivers/net/mlx5/mlx5_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2015 6WIND S.A.
   3  * Copyright 2015 Mellanox Technologies, Ltd
   4  */
   5
   6 #include <assert.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <stdlib.h>
  10
  11 /* Verbs header. */
  12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  13 #ifdef PEDANTIC
  14 #pragma GCC diagnostic ignored "-Wpedantic"
  15 #endif
  16 #include <infiniband/verbs.h>
  17 #include <infiniband/mlx5dv.h>
  18 #ifdef PEDANTIC
  19 #pragma GCC diagnostic error "-Wpedantic"
  20 #endif
  21
  22 #include <rte_mbuf.h>
  23 #include <rte_mempool.h>
  24 #include <rte_prefetch.h>
  25 #include <rte_common.h>
  26 #include <rte_branch_prediction.h>
  27 #include <rte_ether.h>
  28
  29 #include "mlx5.h"
  30 #include "mlx5_utils.h"
  31 #include "mlx5_rxtx.h"
  32 #include "mlx5_autoconf.h"
  33 #include "mlx5_defs.h"
  34 #include "mlx5_prm.h"
  35
  36 static __rte_always_inline uint32_t
  37 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
  38
  39 static __rte_always_inline int
  40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
  41                  uint16_t cqe_cnt, uint32_t *rss_hash);
  42
  43 static __rte_always_inline uint32_t
  44 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
  45
  46 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
  47         [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
  48 };
  49
  50 /**
  51  * Build a table to translate Rx completion flags to packet type.
  52  *
  53  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
  54  */
  55 void
  56 mlx5_set_ptype_table(void)
  57 {
  58         unsigned int i;
  59         uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
  60
  61         /* Last entry must not be overwritten, reserved for errored packet. */
  62         for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
  63                 (*p)[i] = RTE_PTYPE_UNKNOWN;
  64         /*
  65          * The index to the array should have:
  66          * bit[1:0] = l3_hdr_type
  67          * bit[4:2] = l4_hdr_type
  68          * bit[5] = ip_frag
  69          * bit[6] = tunneled
  70          * bit[7] = outer_l3_type
  71          */
  72         /* L2 */
  73         (*p)[0x00] = RTE_PTYPE_L2_ETHER;
  74         /* L3 */
  75         (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  76                      RTE_PTYPE_L4_NONFRAG;
  77         (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  78                      RTE_PTYPE_L4_NONFRAG;
  79         /* Fragmented */
  80         (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  81                      RTE_PTYPE_L4_FRAG;
  82         (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  83                      RTE_PTYPE_L4_FRAG;
  84         /* TCP */
  85         (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  86                      RTE_PTYPE_L4_TCP;
  87         (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  88                      RTE_PTYPE_L4_TCP;
  89         (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  90                      RTE_PTYPE_L4_TCP;
  91         (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  92                      RTE_PTYPE_L4_TCP;
  93         (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  94                      RTE_PTYPE_L4_TCP;
  95         (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
  96                      RTE_PTYPE_L4_TCP;
  97         /* UDP */
  98         (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
  99                      RTE_PTYPE_L4_UDP;
 100         (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 101                      RTE_PTYPE_L4_UDP;
 102         /* Repeat with outer_l3_type being set. Just in case. */
 103         (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 104                      RTE_PTYPE_L4_NONFRAG;
 105         (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 106                      RTE_PTYPE_L4_NONFRAG;
 107         (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 108                      RTE_PTYPE_L4_FRAG;
 109         (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 110                      RTE_PTYPE_L4_FRAG;
 111         (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 112                      RTE_PTYPE_L4_TCP;
 113         (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 114                      RTE_PTYPE_L4_TCP;
 115         (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 116                      RTE_PTYPE_L4_TCP;
 117         (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 118                      RTE_PTYPE_L4_TCP;
 119         (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 120                      RTE_PTYPE_L4_TCP;
 121         (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 122                      RTE_PTYPE_L4_TCP;
 123         (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 124                      RTE_PTYPE_L4_UDP;
 125         (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 126                      RTE_PTYPE_L4_UDP;
 127         /* Tunneled - L3 */
 128         (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 129                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 130                      RTE_PTYPE_INNER_L4_NONFRAG;
 131         (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 132                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 133                      RTE_PTYPE_INNER_L4_NONFRAG;
 134         (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 135                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 136                      RTE_PTYPE_INNER_L4_NONFRAG;
 137         (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 138                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 139                      RTE_PTYPE_INNER_L4_NONFRAG;
 140         /* Tunneled - Fragmented */
 141         (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 142                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 143                      RTE_PTYPE_INNER_L4_FRAG;
 144         (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 145                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 146                      RTE_PTYPE_INNER_L4_FRAG;
 147         (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 148                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 149                      RTE_PTYPE_INNER_L4_FRAG;
 150         (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 151                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 152                      RTE_PTYPE_INNER_L4_FRAG;
 153         /* Tunneled - TCP */
 154         (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 155                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 156                      RTE_PTYPE_INNER_L4_TCP;
 157         (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 158                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 159                      RTE_PTYPE_INNER_L4_TCP;
 160         (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 161                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 162                      RTE_PTYPE_INNER_L4_TCP;
 163         (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 164                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 165                      RTE_PTYPE_INNER_L4_TCP;
 166         (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 167                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 168                      RTE_PTYPE_INNER_L4_TCP;
 169         (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 170                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 171                      RTE_PTYPE_INNER_L4_TCP;
 172         (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 173                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 174                      RTE_PTYPE_INNER_L4_TCP;
 175         (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 176                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 177                      RTE_PTYPE_INNER_L4_TCP;
 178         (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 179                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 180                      RTE_PTYPE_INNER_L4_TCP;
 181         (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 182                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 183                      RTE_PTYPE_INNER_L4_TCP;
 184         (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 185                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 186                      RTE_PTYPE_INNER_L4_TCP;
 187         (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 188                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 189                      RTE_PTYPE_INNER_L4_TCP;
 190         /* Tunneled - UDP */
 191         (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 192                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 193                      RTE_PTYPE_INNER_L4_UDP;
 194         (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 195                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 196                      RTE_PTYPE_INNER_L4_UDP;
 197         (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 198                      RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 199                      RTE_PTYPE_INNER_L4_UDP;
 200         (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 201                      RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 202                      RTE_PTYPE_INNER_L4_UDP;
 203 }
 204
 205 /**
 206  * Return the size of tailroom of WQ.
 207  *
 208  * @param txq
 209  *   Pointer to TX queue structure.
 210  * @param addr
 211  *   Pointer to tail of WQ.
 212  *
 213  * @return
 214  *   Size of tailroom.
 215  */
 216 static inline size_t
 217 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
 218 {
 219         size_t tailroom;
 220         tailroom = (uintptr_t)(txq->wqes) +
 221                    (1 << txq->wqe_n) * MLX5_WQE_SIZE -
 222                    (uintptr_t)addr;
 223         return tailroom;
 224 }
 225
 226 /**
 227  * Copy data to tailroom of circular queue.
 228  *
 229  * @param dst
 230  *   Pointer to destination.
 231  * @param src
 232  *   Pointer to source.
 233  * @param n
 234  *   Number of bytes to copy.
 235  * @param base
 236  *   Pointer to head of queue.
 237  * @param tailroom
 238  *   Size of tailroom from dst.
 239  *
 240  * @return
 241  *   Pointer after copied data.
 242  */
 243 static inline void *
 244 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
 245                 void *base, size_t tailroom)
 246 {
 247         void *ret;
 248
 249         if (n > tailroom) {
 250                 rte_memcpy(dst, src, tailroom);
 251                 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
 252                            n - tailroom);
 253                 ret = (uint8_t *)base + n - tailroom;
 254         } else {
 255                 rte_memcpy(dst, src, n);
 256                 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
 257         }
 258         return ret;
 259 }
 260
 261 /**
 262  * Inline TSO headers into WQE.
 263  *
 264  * @return
 265  *   0 on success, negative errno value on failure.
 266  */
 267 static int
 268 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
 269            uint32_t *length,
 270            uint8_t *cs_flags,
 271            uintptr_t *addr,
 272            uint16_t *pkt_inline_sz,
 273            uint8_t **raw,
 274            uint16_t *max_wqe,
 275            uint16_t *tso_segsz,
 276            uint16_t *tso_header_sz)
 277 {
 278         uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
 279                                     (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 280         unsigned int copy_b;
 281         uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
 282         const uint8_t tunneled = txq->tunnel_en &&
 283                                  (buf->ol_flags & (PKT_TX_TUNNEL_GRE |
 284                                                    PKT_TX_TUNNEL_VXLAN));
 285         uint16_t n_wqe;
 286
 287         *tso_segsz = buf->tso_segsz;
 288         *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
 289         if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
 290                 txq->stats.oerrors++;
 291                 return -EINVAL;
 292         }
 293         if (tunneled) {
 294                 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
 295                 *cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
 296         } else {
 297                 *cs_flags |= MLX5_ETH_WQE_L4_CSUM;
 298         }
 299         if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER)) {
 300                 txq->stats.oerrors++;
 301                 return -EINVAL;
 302         }
 303         copy_b = *tso_header_sz - *pkt_inline_sz;
 304         /* First seg must contain all TSO headers. */
 305         assert(copy_b <= *length);
 306         if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
 307                 return -EAGAIN;
 308         n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 309         if (unlikely(*max_wqe < n_wqe))
 310                 return -EINVAL;
 311         *max_wqe -= n_wqe;
 312         rte_memcpy((void *)*raw, (void *)*addr, copy_b);
 313         *length -= copy_b;
 314         *addr += copy_b;
 315         copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
 316         *pkt_inline_sz += copy_b;
 317         *raw += copy_b;
 318         return 0;
 319 }
 320
 321 /**
 322  * DPDK callback to check the status of a tx descriptor.
 323  *
 324  * @param tx_queue
 325  *   The tx queue.
 326  * @param[in] offset
 327  *   The index of the descriptor in the ring.
 328  *
 329  * @return
 330  *   The status of the tx descriptor.
 331  */
 332 int
 333 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
 334 {
 335         struct mlx5_txq_data *txq = tx_queue;
 336         uint16_t used;
 337
 338         mlx5_tx_complete(txq);
 339         used = txq->elts_head - txq->elts_tail;
 340         if (offset < used)
 341                 return RTE_ETH_TX_DESC_FULL;
 342         return RTE_ETH_TX_DESC_DONE;
 343 }
 344
 345 /**
 346  * DPDK callback to check the status of a rx descriptor.
 347  *
 348  * @param rx_queue
 349  *   The rx queue.
 350  * @param[in] offset
 351  *   The index of the descriptor in the ring.
 352  *
 353  * @return
 354  *   The status of the tx descriptor.
 355  */
 356 int
 357 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
 358 {
 359         struct mlx5_rxq_data *rxq = rx_queue;
 360         struct rxq_zip *zip = &rxq->zip;
 361         volatile struct mlx5_cqe *cqe;
 362         const unsigned int cqe_n = (1 << rxq->cqe_n);
 363         const unsigned int cqe_cnt = cqe_n - 1;
 364         unsigned int cq_ci;
 365         unsigned int used;
 366
 367         /* if we are processing a compressed cqe */
 368         if (zip->ai) {
 369                 used = zip->cqe_cnt - zip->ca;
 370                 cq_ci = zip->cq_ci;
 371         } else {
 372                 used = 0;
 373                 cq_ci = rxq->cq_ci;
 374         }
 375         cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 376         while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
 377                 int8_t op_own;
 378                 unsigned int n;
 379
 380                 op_own = cqe->op_own;
 381                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
 382                         n = rte_be_to_cpu_32(cqe->byte_cnt);
 383                 else
 384                         n = 1;
 385                 cq_ci += n;
 386                 used += n;
 387                 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
 388         }
 389         used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
 390         if (offset < used)
 391                 return RTE_ETH_RX_DESC_DONE;
 392         return RTE_ETH_RX_DESC_AVAIL;
 393 }
 394
 395 /**
 396  * DPDK callback for TX.
 397  *
 398  * @param dpdk_txq
 399  *   Generic pointer to TX queue structure.
 400  * @param[in] pkts
 401  *   Packets to transmit.
 402  * @param pkts_n
 403  *   Number of packets in array.
 404  *
 405  * @return
 406  *   Number of packets successfully transmitted (<= pkts_n).
 407  */
 408 uint16_t
 409 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 410 {
 411         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 412         uint16_t elts_head = txq->elts_head;
 413         const uint16_t elts_n = 1 << txq->elts_n;
 414         const uint16_t elts_m = elts_n - 1;
 415         unsigned int i = 0;
 416         unsigned int j = 0;
 417         unsigned int k = 0;
 418         uint16_t max_elts;
 419         uint16_t max_wqe;
 420         unsigned int comp;
 421         volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
 422         unsigned int segs_n = 0;
 423         const unsigned int max_inline = txq->max_inline;
 424
 425         if (unlikely(!pkts_n))
 426                 return 0;
 427         /* Prefetch first packet cacheline. */
 428         rte_prefetch0(*pkts);
 429         /* Start processing. */
 430         mlx5_tx_complete(txq);
 431         max_elts = (elts_n - (elts_head - txq->elts_tail));
 432         /* A CQE slot must always be available. */
 433         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 434         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 435         if (unlikely(!max_wqe))
 436                 return 0;
 437         do {
 438                 struct rte_mbuf *buf = NULL;
 439                 uint8_t *raw;
 440                 volatile struct mlx5_wqe_v *wqe = NULL;
 441                 volatile rte_v128u32_t *dseg = NULL;
 442                 uint32_t length;
 443                 unsigned int ds = 0;
 444                 unsigned int sg = 0; /* counter of additional segs attached. */
 445                 uintptr_t addr;
 446                 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
 447                 uint16_t tso_header_sz = 0;
 448                 uint16_t ehdr;
 449                 uint8_t cs_flags;
 450                 uint64_t tso = 0;
 451                 uint16_t tso_segsz = 0;
 452 #ifdef MLX5_PMD_SOFT_COUNTERS
 453                 uint32_t total_length = 0;
 454 #endif
 455                 int ret;
 456
 457                 /* first_seg */
 458                 buf = *pkts;
 459                 segs_n = buf->nb_segs;
 460                 /*
 461                  * Make sure there is enough room to store this packet and
 462                  * that one ring entry remains unused.
 463                  */
 464                 assert(segs_n);
 465                 if (max_elts < segs_n)
 466                         break;
 467                 max_elts -= segs_n;
 468                 sg = --segs_n;
 469                 if (unlikely(--max_wqe == 0))
 470                         break;
 471                 wqe = (volatile struct mlx5_wqe_v *)
 472                         tx_mlx5_wqe(txq, txq->wqe_ci);
 473                 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 474                 if (pkts_n - i > 1)
 475                         rte_prefetch0(*(pkts + 1));
 476                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 477                 length = DATA_LEN(buf);
 478                 ehdr = (((uint8_t *)addr)[1] << 8) |
 479                        ((uint8_t *)addr)[0];
 480 #ifdef MLX5_PMD_SOFT_COUNTERS
 481                 total_length = length;
 482 #endif
 483                 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
 484                         txq->stats.oerrors++;
 485                         break;
 486                 }
 487                 /* Update element. */
 488                 (*txq->elts)[elts_head & elts_m] = buf;
 489                 /* Prefetch next buffer data. */
 490                 if (pkts_n - i > 1)
 491                         rte_prefetch0(
 492                             rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
 493                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 494                 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
 495                 /* Replace the Ethernet type by the VLAN if necessary. */
 496                 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
 497                         uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
 498                                                          buf->vlan_tci);
 499                         unsigned int len = 2 * ETHER_ADDR_LEN - 2;
 500
 501                         addr += 2;
 502                         length -= 2;
 503                         /* Copy Destination and source mac address. */
 504                         memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
 505                         /* Copy VLAN. */
 506                         memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
 507                         /* Copy missing two bytes to end the DSeg. */
 508                         memcpy((uint8_t *)raw + len + sizeof(vlan),
 509                                ((uint8_t *)addr) + len, 2);
 510                         addr += len + 2;
 511                         length -= (len + 2);
 512                 } else {
 513                         memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
 514                                MLX5_WQE_DWORD_SIZE);
 515                         length -= pkt_inline_sz;
 516                         addr += pkt_inline_sz;
 517                 }
 518                 raw += MLX5_WQE_DWORD_SIZE;
 519                 tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
 520                 if (tso) {
 521                         ret = inline_tso(txq, buf, &length, &cs_flags,
 522                                          &addr, &pkt_inline_sz,
 523                                          &raw, &max_wqe,
 524                                          &tso_segsz, &tso_header_sz);
 525                         if (ret == -EINVAL) {
 526                                 break;
 527                         } else if (ret == -EAGAIN) {
 528                                 /* NOP WQE. */
 529                                 wqe->ctrl = (rte_v128u32_t){
 530                                         rte_cpu_to_be_32(txq->wqe_ci << 8),
 531                                         rte_cpu_to_be_32(txq->qp_num_8s | 1),
 532                                         0,
 533                                         0,
 534                                 };
 535                                 ds = 1;
 536 #ifdef MLX5_PMD_SOFT_COUNTERS
 537                                 total_length = 0;
 538 #endif
 539                                 k++;
 540                                 goto next_wqe;
 541                         }
 542                 }
 543                 /* Inline if enough room. */
 544                 if (max_inline || tso) {
 545                         uint32_t inl = 0;
 546                         uintptr_t end = (uintptr_t)
 547                                 (((uintptr_t)txq->wqes) +
 548                                  (1 << txq->wqe_n) * MLX5_WQE_SIZE);
 549                         unsigned int inline_room = max_inline *
 550                                                    RTE_CACHE_LINE_SIZE -
 551                                                    (pkt_inline_sz - 2) -
 552                                                    !!tso * sizeof(inl);
 553                         uintptr_t addr_end;
 554                         unsigned int copy_b;
 555
 556 pkt_inline:
 557                         addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
 558                                                    RTE_CACHE_LINE_SIZE);
 559                         copy_b = (addr_end > addr) ?
 560                                  RTE_MIN((addr_end - addr), length) : 0;
 561                         if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
 562                                 /*
 563                                  * One Dseg remains in the current WQE.  To
 564                                  * keep the computation positive, it is
 565                                  * removed after the bytes to Dseg conversion.
 566                                  */
 567                                 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
 568
 569                                 if (unlikely(max_wqe < n))
 570                                         break;
 571                                 max_wqe -= n;
 572                                 if (tso && !inl) {
 573                                         inl = rte_cpu_to_be_32(copy_b |
 574                                                                MLX5_INLINE_SEG);
 575                                         rte_memcpy((void *)raw,
 576                                                    (void *)&inl, sizeof(inl));
 577                                         raw += sizeof(inl);
 578                                         pkt_inline_sz += sizeof(inl);
 579                                 }
 580                                 rte_memcpy((void *)raw, (void *)addr, copy_b);
 581                                 addr += copy_b;
 582                                 length -= copy_b;
 583                                 pkt_inline_sz += copy_b;
 584                         }
 585                         /*
 586                          * 2 DWORDs consumed by the WQE header + ETH segment +
 587                          * the size of the inline part of the packet.
 588                          */
 589                         ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
 590                         if (length > 0) {
 591                                 if (ds % (MLX5_WQE_SIZE /
 592                                           MLX5_WQE_DWORD_SIZE) == 0) {
 593                                         if (unlikely(--max_wqe == 0))
 594                                                 break;
 595                                         dseg = (volatile rte_v128u32_t *)
 596                                                tx_mlx5_wqe(txq, txq->wqe_ci +
 597                                                            ds / 4);
 598                                 } else {
 599                                         dseg = (volatile rte_v128u32_t *)
 600                                                 ((uintptr_t)wqe +
 601                                                  (ds * MLX5_WQE_DWORD_SIZE));
 602                                 }
 603                                 goto use_dseg;
 604                         } else if (!segs_n) {
 605                                 goto next_pkt;
 606                         } else {
 607                                 raw += copy_b;
 608                                 inline_room -= copy_b;
 609                                 --segs_n;
 610                                 buf = buf->next;
 611                                 assert(buf);
 612                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
 613                                 length = DATA_LEN(buf);
 614 #ifdef MLX5_PMD_SOFT_COUNTERS
 615                                 total_length += length;
 616 #endif
 617                                 (*txq->elts)[++elts_head & elts_m] = buf;
 618                                 goto pkt_inline;
 619                         }
 620                 } else {
 621                         /*
 622                          * No inline has been done in the packet, only the
 623                          * Ethernet Header as been stored.
 624                          */
 625                         dseg = (volatile rte_v128u32_t *)
 626                                 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
 627                         ds = 3;
 628 use_dseg:
 629                         /* Add the remaining packet as a simple ds. */
 630                         addr = rte_cpu_to_be_64(addr);
 631                         *dseg = (rte_v128u32_t){
 632                                 rte_cpu_to_be_32(length),
 633                                 mlx5_tx_mb2mr(txq, buf),
 634                                 addr,
 635                                 addr >> 32,
 636                         };
 637                         ++ds;
 638                         if (!segs_n)
 639                                 goto next_pkt;
 640                 }
 641 next_seg:
 642                 assert(buf);
 643                 assert(ds);
 644                 assert(wqe);
 645                 /*
 646                  * Spill on next WQE when the current one does not have
 647                  * enough room left. Size of WQE must a be a multiple
 648                  * of data segment size.
 649                  */
 650                 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
 651                 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
 652                         if (unlikely(--max_wqe == 0))
 653                                 break;
 654                         dseg = (volatile rte_v128u32_t *)
 655                                tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
 656                         rte_prefetch0(tx_mlx5_wqe(txq,
 657                                                   txq->wqe_ci + ds / 4 + 1));
 658                 } else {
 659                         ++dseg;
 660                 }
 661                 ++ds;
 662                 buf = buf->next;
 663                 assert(buf);
 664                 length = DATA_LEN(buf);
 665 #ifdef MLX5_PMD_SOFT_COUNTERS
 666                 total_length += length;
 667 #endif
 668                 /* Store segment information. */
 669                 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
 670                 *dseg = (rte_v128u32_t){
 671                         rte_cpu_to_be_32(length),
 672                         mlx5_tx_mb2mr(txq, buf),
 673                         addr,
 674                         addr >> 32,
 675                 };
 676                 (*txq->elts)[++elts_head & elts_m] = buf;
 677                 if (--segs_n)
 678                         goto next_seg;
 679 next_pkt:
 680                 if (ds > MLX5_DSEG_MAX) {
 681                         txq->stats.oerrors++;
 682                         break;
 683                 }
 684                 ++elts_head;
 685                 ++pkts;
 686                 ++i;
 687                 j += sg;
 688                 /* Initialize known and common part of the WQE structure. */
 689                 if (tso) {
 690                         wqe->ctrl = (rte_v128u32_t){
 691                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 692                                                  MLX5_OPCODE_TSO),
 693                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 694                                 0,
 695                                 0,
 696                         };
 697                         wqe->eseg = (rte_v128u32_t){
 698                                 0,
 699                                 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
 700                                 0,
 701                                 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
 702                         };
 703                 } else {
 704                         wqe->ctrl = (rte_v128u32_t){
 705                                 rte_cpu_to_be_32((txq->wqe_ci << 8) |
 706                                                  MLX5_OPCODE_SEND),
 707                                 rte_cpu_to_be_32(txq->qp_num_8s | ds),
 708                                 0,
 709                                 0,
 710                         };
 711                         wqe->eseg = (rte_v128u32_t){
 712                                 0,
 713                                 cs_flags,
 714                                 0,
 715                                 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
 716                         };
 717                 }
 718 next_wqe:
 719                 txq->wqe_ci += (ds + 3) / 4;
 720                 /* Save the last successful WQE for completion request */
 721                 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
 722 #ifdef MLX5_PMD_SOFT_COUNTERS
 723                 /* Increment sent bytes counter. */
 724                 txq->stats.obytes += total_length;
 725 #endif
 726         } while (i < pkts_n);
 727         /* Take a shortcut if nothing must be sent. */
 728         if (unlikely((i + k) == 0))
 729                 return 0;
 730         txq->elts_head += (i + j);
 731         /* Check whether completion threshold has been reached. */
 732         comp = txq->elts_comp + i + j + k;
 733         if (comp >= MLX5_TX_COMP_THRESH) {
 734                 /* Request completion on last WQE. */
 735                 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
 736                 /* Save elts_head in unused "immediate" field of WQE. */
 737                 last_wqe->ctrl3 = txq->elts_head;
 738                 txq->elts_comp = 0;
 739 #ifndef NDEBUG
 740                 ++txq->cq_pi;
 741 #endif
 742         } else {
 743                 txq->elts_comp = comp;
 744         }
 745 #ifdef MLX5_PMD_SOFT_COUNTERS
 746         /* Increment sent packets counter. */
 747         txq->stats.opackets += i;
 748 #endif
 749         /* Ring QP doorbell. */
 750         mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
 751         return i;
 752 }
 753
 754 /**
 755  * Open a MPW session.
 756  *
 757  * @param txq
 758  *   Pointer to TX queue structure.
 759  * @param mpw
 760  *   Pointer to MPW session structure.
 761  * @param length
 762  *   Packet length.
 763  */
 764 static inline void
 765 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
 766 {
 767         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 768         volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
 769                 (volatile struct mlx5_wqe_data_seg (*)[])
 770                 tx_mlx5_wqe(txq, idx + 1);
 771
 772         mpw->state = MLX5_MPW_STATE_OPENED;
 773         mpw->pkts_n = 0;
 774         mpw->len = length;
 775         mpw->total_len = 0;
 776         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 777         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
 778         mpw->wqe->eseg.inline_hdr_sz = 0;
 779         mpw->wqe->eseg.rsvd0 = 0;
 780         mpw->wqe->eseg.rsvd1 = 0;
 781         mpw->wqe->eseg.rsvd2 = 0;
 782         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 783                                              (txq->wqe_ci << 8) |
 784                                              MLX5_OPCODE_TSO);
 785         mpw->wqe->ctrl[2] = 0;
 786         mpw->wqe->ctrl[3] = 0;
 787         mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
 788                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
 789         mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
 790                 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
 791         mpw->data.dseg[2] = &(*dseg)[0];
 792         mpw->data.dseg[3] = &(*dseg)[1];
 793         mpw->data.dseg[4] = &(*dseg)[2];
 794 }
 795
 796 /**
 797  * Close a MPW session.
 798  *
 799  * @param txq
 800  *   Pointer to TX queue structure.
 801  * @param mpw
 802  *   Pointer to MPW session structure.
 803  */
 804 static inline void
 805 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
 806 {
 807         unsigned int num = mpw->pkts_n;
 808
 809         /*
 810          * Store size in multiple of 16 bytes. Control and Ethernet segments
 811          * count as 2.
 812          */
 813         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
 814         mpw->state = MLX5_MPW_STATE_CLOSED;
 815         if (num < 3)
 816                 ++txq->wqe_ci;
 817         else
 818                 txq->wqe_ci += 2;
 819         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 820         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 821 }
 822
 823 /**
 824  * DPDK callback for TX with MPW support.
 825  *
 826  * @param dpdk_txq
 827  *   Generic pointer to TX queue structure.
 828  * @param[in] pkts
 829  *   Packets to transmit.
 830  * @param pkts_n
 831  *   Number of packets in array.
 832  *
 833  * @return
 834  *   Number of packets successfully transmitted (<= pkts_n).
 835  */
 836 uint16_t
 837 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
 838 {
 839         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
 840         uint16_t elts_head = txq->elts_head;
 841         const uint16_t elts_n = 1 << txq->elts_n;
 842         const uint16_t elts_m = elts_n - 1;
 843         unsigned int i = 0;
 844         unsigned int j = 0;
 845         uint16_t max_elts;
 846         uint16_t max_wqe;
 847         unsigned int comp;
 848         struct mlx5_mpw mpw = {
 849                 .state = MLX5_MPW_STATE_CLOSED,
 850         };
 851
 852         if (unlikely(!pkts_n))
 853                 return 0;
 854         /* Prefetch first packet cacheline. */
 855         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
 856         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
 857         /* Start processing. */
 858         mlx5_tx_complete(txq);
 859         max_elts = (elts_n - (elts_head - txq->elts_tail));
 860         /* A CQE slot must always be available. */
 861         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
 862         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
 863         if (unlikely(!max_wqe))
 864                 return 0;
 865         do {
 866                 struct rte_mbuf *buf = *(pkts++);
 867                 uint32_t length;
 868                 unsigned int segs_n = buf->nb_segs;
 869                 uint32_t cs_flags;
 870
 871                 /*
 872                  * Make sure there is enough room to store this packet and
 873                  * that one ring entry remains unused.
 874                  */
 875                 assert(segs_n);
 876                 if (max_elts < segs_n)
 877                         break;
 878                 /* Do not bother with large packets MPW cannot handle. */
 879                 if (segs_n > MLX5_MPW_DSEG_MAX) {
 880                         txq->stats.oerrors++;
 881                         break;
 882                 }
 883                 max_elts -= segs_n;
 884                 --pkts_n;
 885                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
 886                 /* Retrieve packet information. */
 887                 length = PKT_LEN(buf);
 888                 assert(length);
 889                 /* Start new session if packet differs. */
 890                 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
 891                     ((mpw.len != length) ||
 892                      (segs_n != 1) ||
 893                      (mpw.wqe->eseg.cs_flags != cs_flags)))
 894                         mlx5_mpw_close(txq, &mpw);
 895                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
 896                         /*
 897                          * Multi-Packet WQE consumes at most two WQE.
 898                          * mlx5_mpw_new() expects to be able to use such
 899                          * resources.
 900                          */
 901                         if (unlikely(max_wqe < 2))
 902                                 break;
 903                         max_wqe -= 2;
 904                         mlx5_mpw_new(txq, &mpw, length);
 905                         mpw.wqe->eseg.cs_flags = cs_flags;
 906                 }
 907                 /* Multi-segment packets must be alone in their MPW. */
 908                 assert((segs_n == 1) || (mpw.pkts_n == 0));
 909 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 910                 length = 0;
 911 #endif
 912                 do {
 913                         volatile struct mlx5_wqe_data_seg *dseg;
 914                         uintptr_t addr;
 915
 916                         assert(buf);
 917                         (*txq->elts)[elts_head++ & elts_m] = buf;
 918                         dseg = mpw.data.dseg[mpw.pkts_n];
 919                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
 920                         *dseg = (struct mlx5_wqe_data_seg){
 921                                 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
 922                                 .lkey = mlx5_tx_mb2mr(txq, buf),
 923                                 .addr = rte_cpu_to_be_64(addr),
 924                         };
 925 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
 926                         length += DATA_LEN(buf);
 927 #endif
 928                         buf = buf->next;
 929                         ++mpw.pkts_n;
 930                         ++j;
 931                 } while (--segs_n);
 932                 assert(length == mpw.len);
 933                 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
 934                         mlx5_mpw_close(txq, &mpw);
 935 #ifdef MLX5_PMD_SOFT_COUNTERS
 936                 /* Increment sent bytes counter. */
 937                 txq->stats.obytes += length;
 938 #endif
 939                 ++i;
 940         } while (pkts_n);
 941         /* Take a shortcut if nothing must be sent. */
 942         if (unlikely(i == 0))
 943                 return 0;
 944         /* Check whether completion threshold has been reached. */
 945         /* "j" includes both packets and segments. */
 946         comp = txq->elts_comp + j;
 947         if (comp >= MLX5_TX_COMP_THRESH) {
 948                 volatile struct mlx5_wqe *wqe = mpw.wqe;
 949
 950                 /* Request completion on last WQE. */
 951                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
 952                 /* Save elts_head in unused "immediate" field of WQE. */
 953                 wqe->ctrl[3] = elts_head;
 954                 txq->elts_comp = 0;
 955 #ifndef NDEBUG
 956                 ++txq->cq_pi;
 957 #endif
 958         } else {
 959                 txq->elts_comp = comp;
 960         }
 961 #ifdef MLX5_PMD_SOFT_COUNTERS
 962         /* Increment sent packets counter. */
 963         txq->stats.opackets += i;
 964 #endif
 965         /* Ring QP doorbell. */
 966         if (mpw.state == MLX5_MPW_STATE_OPENED)
 967                 mlx5_mpw_close(txq, &mpw);
 968         mlx5_tx_dbrec(txq, mpw.wqe);
 969         txq->elts_head = elts_head;
 970         return i;
 971 }
 972
 973 /**
 974  * Open a MPW inline session.
 975  *
 976  * @param txq
 977  *   Pointer to TX queue structure.
 978  * @param mpw
 979  *   Pointer to MPW session structure.
 980  * @param length
 981  *   Packet length.
 982  */
 983 static inline void
 984 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
 985                     uint32_t length)
 986 {
 987         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
 988         struct mlx5_wqe_inl_small *inl;
 989
 990         mpw->state = MLX5_MPW_INL_STATE_OPENED;
 991         mpw->pkts_n = 0;
 992         mpw->len = length;
 993         mpw->total_len = 0;
 994         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
 995         mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
 996                                              (txq->wqe_ci << 8) |
 997                                              MLX5_OPCODE_TSO);
 998         mpw->wqe->ctrl[2] = 0;
 999         mpw->wqe->ctrl[3] = 0;
1000         mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1001         mpw->wqe->eseg.inline_hdr_sz = 0;
1002         mpw->wqe->eseg.cs_flags = 0;
1003         mpw->wqe->eseg.rsvd0 = 0;
1004         mpw->wqe->eseg.rsvd1 = 0;
1005         mpw->wqe->eseg.rsvd2 = 0;
1006         inl = (struct mlx5_wqe_inl_small *)
1007                 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1008         mpw->data.raw = (uint8_t *)&inl->raw;
1009 }
1010
1011 /**
1012  * Close a MPW inline session.
1013  *
1014  * @param txq
1015  *   Pointer to TX queue structure.
1016  * @param mpw
1017  *   Pointer to MPW session structure.
1018  */
1019 static inline void
1020 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1021 {
1022         unsigned int size;
1023         struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1024                 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1025
1026         size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1027         /*
1028          * Store size in multiple of 16 bytes. Control and Ethernet segments
1029          * count as 2.
1030          */
1031         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1032                                              MLX5_WQE_DS(size));
1033         mpw->state = MLX5_MPW_STATE_CLOSED;
1034         inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1035         txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1036 }
1037
1038 /**
1039  * DPDK callback for TX with MPW inline support.
1040  *
1041  * @param dpdk_txq
1042  *   Generic pointer to TX queue structure.
1043  * @param[in] pkts
1044  *   Packets to transmit.
1045  * @param pkts_n
1046  *   Number of packets in array.
1047  *
1048  * @return
1049  *   Number of packets successfully transmitted (<= pkts_n).
1050  */
1051 uint16_t
1052 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1053                          uint16_t pkts_n)
1054 {
1055         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1056         uint16_t elts_head = txq->elts_head;
1057         const uint16_t elts_n = 1 << txq->elts_n;
1058         const uint16_t elts_m = elts_n - 1;
1059         unsigned int i = 0;
1060         unsigned int j = 0;
1061         uint16_t max_elts;
1062         uint16_t max_wqe;
1063         unsigned int comp;
1064         unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1065         struct mlx5_mpw mpw = {
1066                 .state = MLX5_MPW_STATE_CLOSED,
1067         };
1068         /*
1069          * Compute the maximum number of WQE which can be consumed by inline
1070          * code.
1071          * - 2 DSEG for:
1072          *   - 1 control segment,
1073          *   - 1 Ethernet segment,
1074          * - N Dseg from the inline request.
1075          */
1076         const unsigned int wqe_inl_n =
1077                 ((2 * MLX5_WQE_DWORD_SIZE +
1078                   txq->max_inline * RTE_CACHE_LINE_SIZE) +
1079                  RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1080
1081         if (unlikely(!pkts_n))
1082                 return 0;
1083         /* Prefetch first packet cacheline. */
1084         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1085         rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1086         /* Start processing. */
1087         mlx5_tx_complete(txq);
1088         max_elts = (elts_n - (elts_head - txq->elts_tail));
1089         /* A CQE slot must always be available. */
1090         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1091         do {
1092                 struct rte_mbuf *buf = *(pkts++);
1093                 uintptr_t addr;
1094                 uint32_t length;
1095                 unsigned int segs_n = buf->nb_segs;
1096                 uint8_t cs_flags;
1097
1098                 /*
1099                  * Make sure there is enough room to store this packet and
1100                  * that one ring entry remains unused.
1101                  */
1102                 assert(segs_n);
1103                 if (max_elts < segs_n)
1104                         break;
1105                 /* Do not bother with large packets MPW cannot handle. */
1106                 if (segs_n > MLX5_MPW_DSEG_MAX) {
1107                         txq->stats.oerrors++;
1108                         break;
1109                 }
1110                 max_elts -= segs_n;
1111                 --pkts_n;
1112                 /*
1113                  * Compute max_wqe in case less WQE were consumed in previous
1114                  * iteration.
1115                  */
1116                 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1117                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1118                 /* Retrieve packet information. */
1119                 length = PKT_LEN(buf);
1120                 /* Start new session if packet differs. */
1121                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1122                         if ((mpw.len != length) ||
1123                             (segs_n != 1) ||
1124                             (mpw.wqe->eseg.cs_flags != cs_flags))
1125                                 mlx5_mpw_close(txq, &mpw);
1126                 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1127                         if ((mpw.len != length) ||
1128                             (segs_n != 1) ||
1129                             (length > inline_room) ||
1130                             (mpw.wqe->eseg.cs_flags != cs_flags)) {
1131                                 mlx5_mpw_inline_close(txq, &mpw);
1132                                 inline_room =
1133                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1134                         }
1135                 }
1136                 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1137                         if ((segs_n != 1) ||
1138                             (length > inline_room)) {
1139                                 /*
1140                                  * Multi-Packet WQE consumes at most two WQE.
1141                                  * mlx5_mpw_new() expects to be able to use
1142                                  * such resources.
1143                                  */
1144                                 if (unlikely(max_wqe < 2))
1145                                         break;
1146                                 max_wqe -= 2;
1147                                 mlx5_mpw_new(txq, &mpw, length);
1148                                 mpw.wqe->eseg.cs_flags = cs_flags;
1149                         } else {
1150                                 if (unlikely(max_wqe < wqe_inl_n))
1151                                         break;
1152                                 max_wqe -= wqe_inl_n;
1153                                 mlx5_mpw_inline_new(txq, &mpw, length);
1154                                 mpw.wqe->eseg.cs_flags = cs_flags;
1155                         }
1156                 }
1157                 /* Multi-segment packets must be alone in their MPW. */
1158                 assert((segs_n == 1) || (mpw.pkts_n == 0));
1159                 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1160                         assert(inline_room ==
1161                                txq->max_inline * RTE_CACHE_LINE_SIZE);
1162 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1163                         length = 0;
1164 #endif
1165                         do {
1166                                 volatile struct mlx5_wqe_data_seg *dseg;
1167
1168                                 assert(buf);
1169                                 (*txq->elts)[elts_head++ & elts_m] = buf;
1170                                 dseg = mpw.data.dseg[mpw.pkts_n];
1171                                 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1172                                 *dseg = (struct mlx5_wqe_data_seg){
1173                                         .byte_count =
1174                                                rte_cpu_to_be_32(DATA_LEN(buf)),
1175                                         .lkey = mlx5_tx_mb2mr(txq, buf),
1176                                         .addr = rte_cpu_to_be_64(addr),
1177                                 };
1178 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1179                                 length += DATA_LEN(buf);
1180 #endif
1181                                 buf = buf->next;
1182                                 ++mpw.pkts_n;
1183                                 ++j;
1184                         } while (--segs_n);
1185                         assert(length == mpw.len);
1186                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1187                                 mlx5_mpw_close(txq, &mpw);
1188                 } else {
1189                         unsigned int max;
1190
1191                         assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1192                         assert(length <= inline_room);
1193                         assert(length == DATA_LEN(buf));
1194                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1195                         (*txq->elts)[elts_head++ & elts_m] = buf;
1196                         /* Maximum number of bytes before wrapping. */
1197                         max = ((((uintptr_t)(txq->wqes)) +
1198                                 (1 << txq->wqe_n) *
1199                                 MLX5_WQE_SIZE) -
1200                                (uintptr_t)mpw.data.raw);
1201                         if (length > max) {
1202                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1203                                            (void *)addr,
1204                                            max);
1205                                 mpw.data.raw = (volatile void *)txq->wqes;
1206                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1207                                            (void *)(addr + max),
1208                                            length - max);
1209                                 mpw.data.raw += length - max;
1210                         } else {
1211                                 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1212                                            (void *)addr,
1213                                            length);
1214
1215                                 if (length == max)
1216                                         mpw.data.raw =
1217                                                 (volatile void *)txq->wqes;
1218                                 else
1219                                         mpw.data.raw += length;
1220                         }
1221                         ++mpw.pkts_n;
1222                         mpw.total_len += length;
1223                         ++j;
1224                         if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1225                                 mlx5_mpw_inline_close(txq, &mpw);
1226                                 inline_room =
1227                                         txq->max_inline * RTE_CACHE_LINE_SIZE;
1228                         } else {
1229                                 inline_room -= length;
1230                         }
1231                 }
1232 #ifdef MLX5_PMD_SOFT_COUNTERS
1233                 /* Increment sent bytes counter. */
1234                 txq->stats.obytes += length;
1235 #endif
1236                 ++i;
1237         } while (pkts_n);
1238         /* Take a shortcut if nothing must be sent. */
1239         if (unlikely(i == 0))
1240                 return 0;
1241         /* Check whether completion threshold has been reached. */
1242         /* "j" includes both packets and segments. */
1243         comp = txq->elts_comp + j;
1244         if (comp >= MLX5_TX_COMP_THRESH) {
1245                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1246
1247                 /* Request completion on last WQE. */
1248                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1249                 /* Save elts_head in unused "immediate" field of WQE. */
1250                 wqe->ctrl[3] = elts_head;
1251                 txq->elts_comp = 0;
1252 #ifndef NDEBUG
1253                 ++txq->cq_pi;
1254 #endif
1255         } else {
1256                 txq->elts_comp = comp;
1257         }
1258 #ifdef MLX5_PMD_SOFT_COUNTERS
1259         /* Increment sent packets counter. */
1260         txq->stats.opackets += i;
1261 #endif
1262         /* Ring QP doorbell. */
1263         if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1264                 mlx5_mpw_inline_close(txq, &mpw);
1265         else if (mpw.state == MLX5_MPW_STATE_OPENED)
1266                 mlx5_mpw_close(txq, &mpw);
1267         mlx5_tx_dbrec(txq, mpw.wqe);
1268         txq->elts_head = elts_head;
1269         return i;
1270 }
1271
1272 /**
1273  * Open an Enhanced MPW session.
1274  *
1275  * @param txq
1276  *   Pointer to TX queue structure.
1277  * @param mpw
1278  *   Pointer to MPW session structure.
1279  * @param length
1280  *   Packet length.
1281  */
1282 static inline void
1283 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1284 {
1285         uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1286
1287         mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1288         mpw->pkts_n = 0;
1289         mpw->total_len = sizeof(struct mlx5_wqe);
1290         mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1291         mpw->wqe->ctrl[0] =
1292                 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1293                                  (txq->wqe_ci << 8) |
1294                                  MLX5_OPCODE_ENHANCED_MPSW);
1295         mpw->wqe->ctrl[2] = 0;
1296         mpw->wqe->ctrl[3] = 0;
1297         memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1298         if (unlikely(padding)) {
1299                 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1300
1301                 /* Pad the first 2 DWORDs with zero-length inline header. */
1302                 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1303                 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1304                         rte_cpu_to_be_32(MLX5_INLINE_SEG);
1305                 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1306                 /* Start from the next WQEBB. */
1307                 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1308         } else {
1309                 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1310         }
1311 }
1312
1313 /**
1314  * Close an Enhanced MPW session.
1315  *
1316  * @param txq
1317  *   Pointer to TX queue structure.
1318  * @param mpw
1319  *   Pointer to MPW session structure.
1320  *
1321  * @return
1322  *   Number of consumed WQEs.
1323  */
1324 static inline uint16_t
1325 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1326 {
1327         uint16_t ret;
1328
1329         /* Store size in multiple of 16 bytes. Control and Ethernet segments
1330          * count as 2.
1331          */
1332         mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1333                                              MLX5_WQE_DS(mpw->total_len));
1334         mpw->state = MLX5_MPW_STATE_CLOSED;
1335         ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1336         txq->wqe_ci += ret;
1337         return ret;
1338 }
1339
1340 /**
1341  * TX with Enhanced MPW support.
1342  *
1343  * @param txq
1344  *   Pointer to TX queue structure.
1345  * @param[in] pkts
1346  *   Packets to transmit.
1347  * @param pkts_n
1348  *   Number of packets in array.
1349  *
1350  * @return
1351  *   Number of packets successfully transmitted (<= pkts_n).
1352  */
1353 static inline uint16_t
1354 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1355                uint16_t pkts_n)
1356 {
1357         uint16_t elts_head = txq->elts_head;
1358         const uint16_t elts_n = 1 << txq->elts_n;
1359         const uint16_t elts_m = elts_n - 1;
1360         unsigned int i = 0;
1361         unsigned int j = 0;
1362         uint16_t max_elts;
1363         uint16_t max_wqe;
1364         unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1365         unsigned int mpw_room = 0;
1366         unsigned int inl_pad = 0;
1367         uint32_t inl_hdr;
1368         struct mlx5_mpw mpw = {
1369                 .state = MLX5_MPW_STATE_CLOSED,
1370         };
1371
1372         if (unlikely(!pkts_n))
1373                 return 0;
1374         /* Start processing. */
1375         mlx5_tx_complete(txq);
1376         max_elts = (elts_n - (elts_head - txq->elts_tail));
1377         /* A CQE slot must always be available. */
1378         assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1379         max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1380         if (unlikely(!max_wqe))
1381                 return 0;
1382         do {
1383                 struct rte_mbuf *buf = *(pkts++);
1384                 uintptr_t addr;
1385                 unsigned int do_inline = 0; /* Whether inline is possible. */
1386                 uint32_t length;
1387                 uint8_t cs_flags;
1388
1389                 /* Multi-segmented packet is handled in slow-path outside. */
1390                 assert(NB_SEGS(buf) == 1);
1391                 /* Make sure there is enough room to store this packet. */
1392                 if (max_elts - j == 0)
1393                         break;
1394                 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1395                 /* Retrieve packet information. */
1396                 length = PKT_LEN(buf);
1397                 /* Start new session if:
1398                  * - multi-segment packet
1399                  * - no space left even for a dseg
1400                  * - next packet can be inlined with a new WQE
1401                  * - cs_flag differs
1402                  */
1403                 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1404                         if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1405                              mpw_room) ||
1406                             (length <= txq->inline_max_packet_sz &&
1407                              inl_pad + sizeof(inl_hdr) + length >
1408                              mpw_room) ||
1409                             (mpw.wqe->eseg.cs_flags != cs_flags))
1410                                 max_wqe -= mlx5_empw_close(txq, &mpw);
1411                 }
1412                 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1413                         /* In Enhanced MPW, inline as much as the budget is
1414                          * allowed. The remaining space is to be filled with
1415                          * dsegs. If the title WQEBB isn't padded, it will have
1416                          * 2 dsegs there.
1417                          */
1418                         mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1419                                            (max_inline ? max_inline :
1420                                             pkts_n * MLX5_WQE_DWORD_SIZE) +
1421                                            MLX5_WQE_SIZE);
1422                         if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1423                                 break;
1424                         /* Don't pad the title WQEBB to not waste WQ. */
1425                         mlx5_empw_new(txq, &mpw, 0);
1426                         mpw_room -= mpw.total_len;
1427                         inl_pad = 0;
1428                         do_inline = length <= txq->inline_max_packet_sz &&
1429                                     sizeof(inl_hdr) + length <= mpw_room &&
1430                                     !txq->mpw_hdr_dseg;
1431                         mpw.wqe->eseg.cs_flags = cs_flags;
1432                 } else {
1433                         /* Evaluate whether the next packet can be inlined.
1434                          * Inlininig is possible when:
1435                          * - length is less than configured value
1436                          * - length fits for remaining space
1437                          * - not required to fill the title WQEBB with dsegs
1438                          */
1439                         do_inline =
1440                                 length <= txq->inline_max_packet_sz &&
1441                                 inl_pad + sizeof(inl_hdr) + length <=
1442                                  mpw_room &&
1443                                 (!txq->mpw_hdr_dseg ||
1444                                  mpw.total_len >= MLX5_WQE_SIZE);
1445                 }
1446                 if (max_inline && do_inline) {
1447                         /* Inline packet into WQE. */
1448                         unsigned int max;
1449
1450                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1451                         assert(length == DATA_LEN(buf));
1452                         inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1453                         addr = rte_pktmbuf_mtod(buf, uintptr_t);
1454                         mpw.data.raw = (volatile void *)
1455                                 ((uintptr_t)mpw.data.raw + inl_pad);
1456                         max = tx_mlx5_wq_tailroom(txq,
1457                                         (void *)(uintptr_t)mpw.data.raw);
1458                         /* Copy inline header. */
1459                         mpw.data.raw = (volatile void *)
1460                                 mlx5_copy_to_wq(
1461                                           (void *)(uintptr_t)mpw.data.raw,
1462                                           &inl_hdr,
1463                                           sizeof(inl_hdr),
1464                                           (void *)(uintptr_t)txq->wqes,
1465                                           max);
1466                         max = tx_mlx5_wq_tailroom(txq,
1467                                         (void *)(uintptr_t)mpw.data.raw);
1468                         /* Copy packet data. */
1469                         mpw.data.raw = (volatile void *)
1470                                 mlx5_copy_to_wq(
1471                                           (void *)(uintptr_t)mpw.data.raw,
1472                                           (void *)addr,
1473                                           length,
1474                                           (void *)(uintptr_t)txq->wqes,
1475                                           max);
1476                         ++mpw.pkts_n;
1477                         mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1478                         /* No need to get completion as the entire packet is
1479                          * copied to WQ. Free the buf right away.
1480                          */
1481                         rte_pktmbuf_free_seg(buf);
1482                         mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1483                         /* Add pad in the next packet if any. */
1484                         inl_pad = (((uintptr_t)mpw.data.raw +
1485                                         (MLX5_WQE_DWORD_SIZE - 1)) &
1486                                         ~(MLX5_WQE_DWORD_SIZE - 1)) -
1487                                   (uintptr_t)mpw.data.raw;
1488                 } else {
1489                         /* No inline. Load a dseg of packet pointer. */
1490                         volatile rte_v128u32_t *dseg;
1491
1492                         assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1493                         assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1494                         assert(length == DATA_LEN(buf));
1495                         if (!tx_mlx5_wq_tailroom(txq,
1496                                         (void *)((uintptr_t)mpw.data.raw
1497                                                 + inl_pad)))
1498                                 dseg = (volatile void *)txq->wqes;
1499                         else
1500                                 dseg = (volatile void *)
1501                                         ((uintptr_t)mpw.data.raw +
1502                                          inl_pad);
1503                         (*txq->elts)[elts_head++ & elts_m] = buf;
1504                         addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1505                                                                  uintptr_t));
1506                         *dseg = (rte_v128u32_t) {
1507                                 rte_cpu_to_be_32(length),
1508                                 mlx5_tx_mb2mr(txq, buf),
1509                                 addr,
1510                                 addr >> 32,
1511                         };
1512                         mpw.data.raw = (volatile void *)(dseg + 1);
1513                         mpw.total_len += (inl_pad + sizeof(*dseg));
1514                         ++j;
1515                         ++mpw.pkts_n;
1516                         mpw_room -= (inl_pad + sizeof(*dseg));
1517                         inl_pad = 0;
1518                 }
1519 #ifdef MLX5_PMD_SOFT_COUNTERS
1520                 /* Increment sent bytes counter. */
1521                 txq->stats.obytes += length;
1522 #endif
1523                 ++i;
1524         } while (i < pkts_n);
1525         /* Take a shortcut if nothing must be sent. */
1526         if (unlikely(i == 0))
1527                 return 0;
1528         /* Check whether completion threshold has been reached. */
1529         if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1530                         (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1531                          (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1532                 volatile struct mlx5_wqe *wqe = mpw.wqe;
1533
1534                 /* Request completion on last WQE. */
1535                 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1536                 /* Save elts_head in unused "immediate" field of WQE. */
1537                 wqe->ctrl[3] = elts_head;
1538                 txq->elts_comp = 0;
1539                 txq->mpw_comp = txq->wqe_ci;
1540 #ifndef NDEBUG
1541                 ++txq->cq_pi;
1542 #endif
1543         } else {
1544                 txq->elts_comp += j;
1545         }
1546 #ifdef MLX5_PMD_SOFT_COUNTERS
1547         /* Increment sent packets counter. */
1548         txq->stats.opackets += i;
1549 #endif
1550         if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1551                 mlx5_empw_close(txq, &mpw);
1552         /* Ring QP doorbell. */
1553         mlx5_tx_dbrec(txq, mpw.wqe);
1554         txq->elts_head = elts_head;
1555         return i;
1556 }
1557
1558 /**
1559  * DPDK callback for TX with Enhanced MPW support.
1560  *
1561  * @param dpdk_txq
1562  *   Generic pointer to TX queue structure.
1563  * @param[in] pkts
1564  *   Packets to transmit.
1565  * @param pkts_n
1566  *   Number of packets in array.
1567  *
1568  * @return
1569  *   Number of packets successfully transmitted (<= pkts_n).
1570  */
1571 uint16_t
1572 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1573 {
1574         struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1575         uint16_t nb_tx = 0;
1576
1577         while (pkts_n > nb_tx) {
1578                 uint16_t n;
1579                 uint16_t ret;
1580
1581                 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1582                 if (n) {
1583                         ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1584                         if (!ret)
1585                                 break;
1586                         nb_tx += ret;
1587                 }
1588                 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1589                 if (n) {
1590                         ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1591                         if (!ret)
1592                                 break;
1593                         nb_tx += ret;
1594                 }
1595         }
1596         return nb_tx;
1597 }
1598
1599 /**
1600  * Translate RX completion flags to packet type.
1601  *
1602  * @param[in] cqe
1603  *   Pointer to CQE.
1604  *
1605  * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1606  *
1607  * @return
1608  *   Packet type for struct rte_mbuf.
1609  */
1610 static inline uint32_t
1611 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1612 {
1613         uint8_t idx;
1614         uint8_t pinfo = cqe->pkt_info;
1615         uint16_t ptype = cqe->hdr_type_etc;
1616
1617         /*
1618          * The index to the array should have:
1619          * bit[1:0] = l3_hdr_type
1620          * bit[4:2] = l4_hdr_type
1621          * bit[5] = ip_frag
1622          * bit[6] = tunneled
1623          * bit[7] = outer_l3_type
1624          */
1625         idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1626         return mlx5_ptype_table[idx];
1627 }
1628
1629 /**
1630  * Get size of the next packet for a given CQE. For compressed CQEs, the
1631  * consumer index is updated only once all packets of the current one have
1632  * been processed.
1633  *
1634  * @param rxq
1635  *   Pointer to RX queue.
1636  * @param cqe
1637  *   CQE to process.
1638  * @param[out] rss_hash
1639  *   Packet RSS Hash result.
1640  *
1641  * @return
1642  *   Packet size in bytes (0 if there is none), -1 in case of completion
1643  *   with error.
1644  */
1645 static inline int
1646 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1647                  uint16_t cqe_cnt, uint32_t *rss_hash)
1648 {
1649         struct rxq_zip *zip = &rxq->zip;
1650         uint16_t cqe_n = cqe_cnt + 1;
1651         int len = 0;
1652         uint16_t idx, end;
1653
1654         /* Process compressed data in the CQE and mini arrays. */
1655         if (zip->ai) {
1656                 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1657                         (volatile struct mlx5_mini_cqe8 (*)[8])
1658                         (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1659
1660                 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1661                 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1662                 if ((++zip->ai & 7) == 0) {
1663                         /* Invalidate consumed CQEs */
1664                         idx = zip->ca;
1665                         end = zip->na;
1666                         while (idx != end) {
1667                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1668                                         MLX5_CQE_INVALIDATE;
1669                                 ++idx;
1670                         }
1671                         /*
1672                          * Increment consumer index to skip the number of
1673                          * CQEs consumed. Hardware leaves holes in the CQ
1674                          * ring for software use.
1675                          */
1676                         zip->ca = zip->na;
1677                         zip->na += 8;
1678                 }
1679                 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1680                         /* Invalidate the rest */
1681                         idx = zip->ca;
1682                         end = zip->cq_ci;
1683
1684                         while (idx != end) {
1685                                 (*rxq->cqes)[idx & cqe_cnt].op_own =
1686                                         MLX5_CQE_INVALIDATE;
1687                                 ++idx;
1688                         }
1689                         rxq->cq_ci = zip->cq_ci;
1690                         zip->ai = 0;
1691                 }
1692         /* No compressed data, get next CQE and verify if it is compressed. */
1693         } else {
1694                 int ret;
1695                 int8_t op_own;
1696
1697                 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1698                 if (unlikely(ret == 1))
1699                         return 0;
1700                 ++rxq->cq_ci;
1701                 op_own = cqe->op_own;
1702                 rte_cio_rmb();
1703                 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1704                         volatile struct mlx5_mini_cqe8 (*mc)[8] =
1705                                 (volatile struct mlx5_mini_cqe8 (*)[8])
1706                                 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1707                                                           cqe_cnt].pkt_info);
1708
1709                         /* Fix endianness. */
1710                         zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1711                         /*
1712                          * Current mini array position is the one returned by
1713                          * check_cqe64().
1714                          *
1715                          * If completion comprises several mini arrays, as a
1716                          * special case the second one is located 7 CQEs after
1717                          * the initial CQE instead of 8 for subsequent ones.
1718                          */
1719                         zip->ca = rxq->cq_ci;
1720                         zip->na = zip->ca + 7;
1721                         /* Compute the next non compressed CQE. */
1722                         --rxq->cq_ci;
1723                         zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1724                         /* Get packet size to return. */
1725                         len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1726                         *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1727                         zip->ai = 1;
1728                         /* Prefetch all the entries to be invalidated */
1729                         idx = zip->ca;
1730                         end = zip->cq_ci;
1731                         while (idx != end) {
1732                                 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1733                                 ++idx;
1734                         }
1735                 } else {
1736                         len = rte_be_to_cpu_32(cqe->byte_cnt);
1737                         *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1738                 }
1739                 /* Error while receiving packet. */
1740                 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1741                         return -1;
1742         }
1743         return len;
1744 }
1745
1746 /**
1747  * Translate RX completion flags to offload flags.
1748  *
1749  * @param[in] rxq
1750  *   Pointer to RX queue structure.
1751  * @param[in] cqe
1752  *   Pointer to CQE.
1753  *
1754  * @return
1755  *   Offload flags (ol_flags) for struct rte_mbuf.
1756  */
1757 static inline uint32_t
1758 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1759 {
1760         uint32_t ol_flags = 0;
1761         uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1762
1763         ol_flags =
1764                 TRANSPOSE(flags,
1765                           MLX5_CQE_RX_L3_HDR_VALID,
1766                           PKT_RX_IP_CKSUM_GOOD) |
1767                 TRANSPOSE(flags,
1768                           MLX5_CQE_RX_L4_HDR_VALID,
1769                           PKT_RX_L4_CKSUM_GOOD);
1770         if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1771                 ol_flags |=
1772                         TRANSPOSE(flags,
1773                                   MLX5_CQE_RX_L3_HDR_VALID,
1774                                   PKT_RX_IP_CKSUM_GOOD) |
1775                         TRANSPOSE(flags,
1776                                   MLX5_CQE_RX_L4_HDR_VALID,
1777                                   PKT_RX_L4_CKSUM_GOOD);
1778         return ol_flags;
1779 }
1780
1781 /**
1782  * DPDK callback for RX.
1783  *
1784  * @param dpdk_rxq
1785  *   Generic pointer to RX queue structure.
1786  * @param[out] pkts
1787  *   Array to store received packets.
1788  * @param pkts_n
1789  *   Maximum number of packets in array.
1790  *
1791  * @return
1792  *   Number of packets successfully received (<= pkts_n).
1793  */
1794 uint16_t
1795 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1796 {
1797         struct mlx5_rxq_data *rxq = dpdk_rxq;
1798         const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1799         const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1800         const unsigned int sges_n = rxq->sges_n;
1801         struct rte_mbuf *pkt = NULL;
1802         struct rte_mbuf *seg = NULL;
1803         volatile struct mlx5_cqe *cqe =
1804                 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1805         unsigned int i = 0;
1806         unsigned int rq_ci = rxq->rq_ci << sges_n;
1807         int len = 0; /* keep its value across iterations. */
1808
1809         while (pkts_n) {
1810                 unsigned int idx = rq_ci & wqe_cnt;
1811                 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1812                 struct rte_mbuf *rep = (*rxq->elts)[idx];
1813                 uint32_t rss_hash_res = 0;
1814
1815                 if (pkt)
1816                         NEXT(seg) = rep;
1817                 seg = rep;
1818                 rte_prefetch0(seg);
1819                 rte_prefetch0(cqe);
1820                 rte_prefetch0(wqe);
1821                 rep = rte_mbuf_raw_alloc(rxq->mp);
1822                 if (unlikely(rep == NULL)) {
1823                         ++rxq->stats.rx_nombuf;
1824                         if (!pkt) {
1825                                 /*
1826                                  * no buffers before we even started,
1827                                  * bail out silently.
1828                                  */
1829                                 break;
1830                         }
1831                         while (pkt != seg) {
1832                                 assert(pkt != (*rxq->elts)[idx]);
1833                                 rep = NEXT(pkt);
1834                                 NEXT(pkt) = NULL;
1835                                 NB_SEGS(pkt) = 1;
1836                                 rte_mbuf_raw_free(pkt);
1837                                 pkt = rep;
1838                         }
1839                         break;
1840                 }
1841                 if (!pkt) {
1842                         cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1843                         len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1844                                                &rss_hash_res);
1845                         if (!len) {
1846                                 rte_mbuf_raw_free(rep);
1847                                 break;
1848                         }
1849                         if (unlikely(len == -1)) {
1850                                 /* RX error, packet is likely too large. */
1851                                 rte_mbuf_raw_free(rep);
1852                                 ++rxq->stats.idropped;
1853                                 goto skip;
1854                         }
1855                         pkt = seg;
1856                         assert(len >= (rxq->crc_present << 2));
1857                         /* Update packet information. */
1858                         pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1859                         pkt->ol_flags = 0;
1860                         if (rss_hash_res && rxq->rss_hash) {
1861                                 pkt->hash.rss = rss_hash_res;
1862                                 pkt->ol_flags = PKT_RX_RSS_HASH;
1863                         }
1864                         if (rxq->mark &&
1865                             MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1866                                 pkt->ol_flags |= PKT_RX_FDIR;
1867                                 if (cqe->sop_drop_qpn !=
1868                                     rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1869                                         uint32_t mark = cqe->sop_drop_qpn;
1870
1871                                         pkt->ol_flags |= PKT_RX_FDIR_ID;
1872                                         pkt->hash.fdir.hi =
1873                                                 mlx5_flow_mark_get(mark);
1874                                 }
1875                         }
1876                         if (rxq->csum | rxq->csum_l2tun)
1877                                 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1878                         if (rxq->vlan_strip &&
1879                             (cqe->hdr_type_etc &
1880                              rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1881                                 pkt->ol_flags |= PKT_RX_VLAN |
1882                                         PKT_RX_VLAN_STRIPPED;
1883                                 pkt->vlan_tci =
1884                                         rte_be_to_cpu_16(cqe->vlan_info);
1885                         }
1886                         if (rxq->hw_timestamp) {
1887                                 pkt->timestamp =
1888                                         rte_be_to_cpu_64(cqe->timestamp);
1889                                 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1890                         }
1891                         if (rxq->crc_present)
1892                                 len -= ETHER_CRC_LEN;
1893                         PKT_LEN(pkt) = len;
1894                 }
1895                 DATA_LEN(rep) = DATA_LEN(seg);
1896                 PKT_LEN(rep) = PKT_LEN(seg);
1897                 SET_DATA_OFF(rep, DATA_OFF(seg));
1898                 PORT(rep) = PORT(seg);
1899                 (*rxq->elts)[idx] = rep;
1900                 /*
1901                  * Fill NIC descriptor with the new buffer.  The lkey and size
1902                  * of the buffers are already known, only the buffer address
1903                  * changes.
1904                  */
1905                 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1906                 if (len > DATA_LEN(seg)) {
1907                         len -= DATA_LEN(seg);
1908                         ++NB_SEGS(pkt);
1909                         ++rq_ci;
1910                         continue;
1911                 }
1912                 DATA_LEN(seg) = len;
1913 #ifdef MLX5_PMD_SOFT_COUNTERS
1914                 /* Increment bytes counter. */
1915                 rxq->stats.ibytes += PKT_LEN(pkt);
1916 #endif
1917                 /* Return packet. */
1918                 *(pkts++) = pkt;
1919                 pkt = NULL;
1920                 --pkts_n;
1921                 ++i;
1922 skip:
1923                 /* Align consumer index to the next stride. */
1924                 rq_ci >>= sges_n;
1925                 ++rq_ci;
1926                 rq_ci <<= sges_n;
1927         }
1928         if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1929                 return 0;
1930         /* Update the consumer index. */
1931         rxq->rq_ci = rq_ci >> sges_n;
1932         rte_cio_wmb();
1933         *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1934         rte_cio_wmb();
1935         *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1936 #ifdef MLX5_PMD_SOFT_COUNTERS
1937         /* Increment packets counter. */
1938         rxq->stats.ipackets += i;
1939 #endif
1940         return i;
1941 }
1942
1943 /**
1944  * Dummy DPDK callback for TX.
1945  *
1946  * This function is used to temporarily replace the real callback during
1947  * unsafe control operations on the queue, or in case of error.
1948  *
1949  * @param dpdk_txq
1950  *   Generic pointer to TX queue structure.
1951  * @param[in] pkts
1952  *   Packets to transmit.
1953  * @param pkts_n
1954  *   Number of packets in array.
1955  *
1956  * @return
1957  *   Number of packets successfully transmitted (<= pkts_n).
1958  */
1959 uint16_t
1960 removed_tx_burst(void *dpdk_txq __rte_unused,
1961                  struct rte_mbuf **pkts __rte_unused,
1962                  uint16_t pkts_n __rte_unused)
1963 {
1964         return 0;
1965 }
1966
1967 /**
1968  * Dummy DPDK callback for RX.
1969  *
1970  * This function is used to temporarily replace the real callback during
1971  * unsafe control operations on the queue, or in case of error.
1972  *
1973  * @param dpdk_rxq
1974  *   Generic pointer to RX queue structure.
1975  * @param[out] pkts
1976  *   Array to store received packets.
1977  * @param pkts_n
1978  *   Maximum number of packets in array.
1979  *
1980  * @return
1981  *   Number of packets successfully received (<= pkts_n).
1982  */
1983 uint16_t
1984 removed_rx_burst(void *dpdk_txq __rte_unused,
1985                  struct rte_mbuf **pkts __rte_unused,
1986                  uint16_t pkts_n __rte_unused)
1987 {
1988         return 0;
1989 }
1990
1991 /*
1992  * Vectorized Rx/Tx routines are not compiled in when required vector
1993  * instructions are not supported on a target architecture. The following null
1994  * stubs are needed for linkage when those are not included outside of this file
1995  * (e.g.  mlx5_rxtx_vec_sse.c for x86).
1996  */
1997
1998 uint16_t __attribute__((weak))
1999 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2000                       struct rte_mbuf **pkts __rte_unused,
2001                       uint16_t pkts_n __rte_unused)
2002 {
2003         return 0;
2004 }
2005
2006 uint16_t __attribute__((weak))
2007 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2008                   struct rte_mbuf **pkts __rte_unused,
2009                   uint16_t pkts_n __rte_unused)
2010 {
2011         return 0;
2012 }
2013
2014 uint16_t __attribute__((weak))
2015 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2016                   struct rte_mbuf **pkts __rte_unused,
2017                   uint16_t pkts_n __rte_unused)
2018 {
2019         return 0;
2020 }
2021
2022 int __attribute__((weak))
2023 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2024 {
2025         return -ENOTSUP;
2026 }
2027
2028 int __attribute__((weak))
2029 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2030 {
2031         return -ENOTSUP;
2032 }
2033
2034 int __attribute__((weak))
2035 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2036 {
2037         return -ENOTSUP;
2038 }
2039
2040 int __attribute__((weak))
2041 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
2042 {
2043         return -ENOTSUP;
2044 }