4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_prefetch.h>
58 #include <rte_common.h>
59 #include <rte_branch_prediction.h>
60 #include <rte_ether.h>
62 #pragma GCC diagnostic error "-Wpedantic"
66 #include "mlx5_utils.h"
67 #include "mlx5_rxtx.h"
68 #include "mlx5_autoconf.h"
69 #include "mlx5_defs.h"
75 * Verify or set magic value in CQE.
84 check_cqe64_seen(volatile struct mlx5_cqe64 *cqe)
86 static const uint8_t magic[] = "seen";
87 volatile uint8_t (*buf)[sizeof(cqe->rsvd40)] = &cqe->rsvd40;
91 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
92 if (!ret || (*buf)[i] != magic[i]) {
102 check_cqe64(volatile struct mlx5_cqe64 *cqe,
103 unsigned int cqes_n, const uint16_t ci)
104 __attribute__((always_inline));
107 * Check whether CQE is valid.
112 * Size of completion queue.
117 * 0 on success, 1 on failure.
120 check_cqe64(volatile struct mlx5_cqe64 *cqe,
121 unsigned int cqes_n, const uint16_t ci)
123 uint16_t idx = ci & cqes_n;
124 uint8_t op_own = cqe->op_own;
125 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
126 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
128 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
129 return 1; /* No CQE. */
131 if ((op_code == MLX5_CQE_RESP_ERR) ||
132 (op_code == MLX5_CQE_REQ_ERR)) {
133 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
134 uint8_t syndrome = err_cqe->syndrome;
136 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
137 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
139 if (!check_cqe64_seen(cqe))
140 ERROR("unexpected CQE error %u (0x%02x)"
142 op_code, op_code, syndrome);
144 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
145 (op_code != MLX5_CQE_REQ)) {
146 if (!check_cqe64_seen(cqe))
147 ERROR("unexpected CQE opcode %u (0x%02x)",
156 txq_complete(struct txq *txq) __attribute__((always_inline));
159 * Manage TX completions.
161 * When sending a burst, mlx5_tx_burst() posts several WRs.
164 * Pointer to TX queue structure.
167 txq_complete(struct txq *txq)
169 const unsigned int cqe_n = txq->cqe_n;
170 const unsigned int elts_n = 1 << txq->elts_n;
171 const unsigned int cqe_cnt = cqe_n - 1;
172 uint16_t elts_free = txq->elts_tail;
174 uint16_t cq_ci = txq->cq_ci;
175 volatile struct mlx5_cqe64 *cqe = NULL;
176 volatile struct mlx5_wqe *wqe;
179 volatile struct mlx5_cqe64 *tmp;
181 tmp = &(*txq->cqes)[cq_ci & cqe_cnt].cqe64;
182 if (check_cqe64(tmp, cqe_n, cq_ci))
186 if (MLX5_CQE_FORMAT(cqe->op_own) == MLX5_COMPRESSED) {
187 if (!check_cqe64_seen(cqe))
188 ERROR("unexpected compressed CQE, TX stopped");
191 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
192 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
193 if (!check_cqe64_seen(cqe))
194 ERROR("unexpected error CQE, TX stopped");
200 if (unlikely(cqe == NULL))
202 wqe = &(*txq->wqes)[htons(cqe->wqe_counter) & (txq->wqe_n - 1)].hdr;
203 elts_tail = wqe->ctrl[3];
204 assert(elts_tail < txq->wqe_n);
206 while (elts_free != elts_tail) {
207 struct rte_mbuf *elt = (*txq->elts)[elts_free];
208 unsigned int elts_free_next =
209 (elts_free + 1) & (elts_n - 1);
210 struct rte_mbuf *elt_next = (*txq->elts)[elts_free_next];
214 memset(&(*txq->elts)[elts_free],
216 sizeof((*txq->elts)[elts_free]));
218 RTE_MBUF_PREFETCH_TO_FREE(elt_next);
219 /* Only one segment needs to be freed. */
220 rte_pktmbuf_free_seg(elt);
221 elts_free = elts_free_next;
224 txq->elts_tail = elts_tail;
225 /* Update the consumer index. */
227 *txq->cq_db = htonl(cq_ci);
231 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
232 * the cloned mbuf is allocated is returned instead.
238 * Memory pool where data is located for given mbuf.
240 static struct rte_mempool *
241 txq_mb2mp(struct rte_mbuf *buf)
243 if (unlikely(RTE_MBUF_INDIRECT(buf)))
244 return rte_mbuf_from_indirect(buf)->pool;
248 static inline uint32_t
249 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
250 __attribute__((always_inline));
253 * Get Memory Region (MR) <-> Memory Pool (MP) association from txq->mp2mr[].
254 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
255 * remove an entry first.
258 * Pointer to TX queue structure.
260 * Memory Pool for which a Memory Region lkey must be returned.
263 * mr->lkey on success, (uint32_t)-1 on failure.
265 static inline uint32_t
266 txq_mp2mr(struct txq *txq, struct rte_mempool *mp)
269 uint32_t lkey = (uint32_t)-1;
271 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
272 if (unlikely(txq->mp2mr[i].mp == NULL)) {
273 /* Unknown MP, add a new MR for it. */
276 if (txq->mp2mr[i].mp == mp) {
277 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
278 assert(htonl(txq->mp2mr[i].mr->lkey) ==
280 lkey = txq->mp2mr[i].lkey;
284 if (unlikely(lkey == (uint32_t)-1))
285 lkey = txq_mp2mr_reg(txq, mp, i);
290 * Write a regular WQE.
293 * Pointer to TX queue structure.
295 * Pointer to the WQE to fill.
302 * Number of DS elements consumed.
304 static inline unsigned int
305 mlx5_wqe_write(struct txq *txq, volatile struct mlx5_wqe *wqe,
306 struct rte_mbuf *buf, uint32_t length)
308 uint8_t *raw = (uint8_t *)(uintptr_t)&wqe->eseg.inline_hdr[0];
310 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE;
311 uintptr_t addr = rte_pktmbuf_mtod(buf, uintptr_t);
312 struct mlx5_wqe_data_seg *dseg = NULL;
314 assert(length >= MLX5_WQE_DWORD_SIZE);
315 /* Start the know and common part of the WQE structure. */
316 wqe->ctrl[0] = htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND);
323 /* Start by copying the Ethernet Header. */
324 rte_mov16((uint8_t *)raw, (uint8_t *)addr);
325 length -= MLX5_WQE_DWORD_SIZE;
326 addr += MLX5_WQE_DWORD_SIZE;
327 /* Replace the Ethernet type by the VLAN if necessary. */
328 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
329 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
331 memcpy((uint8_t *)(raw + MLX5_WQE_DWORD_SIZE - sizeof(vlan)),
332 &vlan, sizeof(vlan));
333 addr -= sizeof(vlan);
334 length += sizeof(vlan);
336 /* Inline if enough room. */
337 if (txq->max_inline != 0) {
338 uintptr_t end = (uintptr_t)&(*txq->wqes)[txq->wqe_n];
339 uint16_t max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
342 raw += MLX5_WQE_DWORD_SIZE;
343 room = end - (uintptr_t)raw;
344 if (room > max_inline) {
345 uintptr_t addr_end = (addr + max_inline) &
346 ~(RTE_CACHE_LINE_SIZE - 1);
347 uint16_t copy_b = ((addr_end - addr) > length) ?
351 rte_memcpy((void *)raw, (void *)addr, copy_b);
354 pkt_inline_sz += copy_b;
356 assert(addr <= addr_end);
358 /* Store the inlined packet size in the WQE. */
359 wqe->eseg.inline_hdr_sz = htons(pkt_inline_sz);
361 * 2 DWORDs consumed by the WQE header + 1 DSEG +
362 * the size of the inline part of the packet.
364 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
366 dseg = (struct mlx5_wqe_data_seg *)
367 ((uintptr_t)wqe + (ds * MLX5_WQE_DWORD_SIZE));
368 if ((uintptr_t)dseg >= end)
369 dseg = (struct mlx5_wqe_data_seg *)
370 ((uintptr_t)&(*txq->wqes)[0]);
374 /* Add the remaining packet as a simple ds. */
377 * No inline has been done in the packet, only the Ethernet
378 * Header as been stored.
380 wqe->eseg.inline_hdr_sz = htons(MLX5_WQE_DWORD_SIZE);
381 dseg = (struct mlx5_wqe_data_seg *)
382 ((uintptr_t)wqe + (ds * MLX5_WQE_DWORD_SIZE));
384 *dseg = (struct mlx5_wqe_data_seg) {
385 .addr = htonll(addr),
386 .byte_count = htonl(length),
387 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
391 wqe->ctrl[1] = htonl(txq->qp_num_8s | ds);
396 * Ring TX queue doorbell.
399 * Pointer to TX queue structure.
402 mlx5_tx_dbrec(struct txq *txq)
404 uint8_t *dst = (uint8_t *)((uintptr_t)txq->bf_reg + txq->bf_offset);
406 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
407 htonl(txq->qp_num_8s),
412 *txq->qp_db = htonl(txq->wqe_ci);
413 /* Ensure ordering between DB record and BF copy. */
415 rte_mov16(dst, (uint8_t *)data);
416 txq->bf_offset ^= txq->bf_buf_size;
423 * Pointer to TX queue structure.
425 * CQE consumer index.
428 tx_prefetch_cqe(struct txq *txq, uint16_t ci)
430 volatile struct mlx5_cqe64 *cqe;
432 cqe = &(*txq->cqes)[ci & (txq->cqe_n - 1)].cqe64;
440 * Pointer to TX queue structure.
442 * WQE consumer index.
445 tx_prefetch_wqe(struct txq *txq, uint16_t ci)
447 volatile struct mlx5_wqe64 *wqe;
449 wqe = &(*txq->wqes)[ci & (txq->wqe_n - 1)];
454 * DPDK callback for TX.
457 * Generic pointer to TX queue structure.
459 * Packets to transmit.
461 * Number of packets in array.
464 * Number of packets successfully transmitted (<= pkts_n).
467 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
469 struct txq *txq = (struct txq *)dpdk_txq;
470 uint16_t elts_head = txq->elts_head;
471 const unsigned int elts_n = 1 << txq->elts_n;
476 volatile struct mlx5_wqe *wqe = NULL;
478 if (unlikely(!pkts_n))
480 /* Prefetch first packet cacheline. */
481 tx_prefetch_cqe(txq, txq->cq_ci);
482 tx_prefetch_cqe(txq, txq->cq_ci + 1);
483 rte_prefetch0(*pkts);
484 /* Start processing. */
486 max = (elts_n - (elts_head - txq->elts_tail));
490 struct rte_mbuf *buf = *(pkts++);
491 unsigned int elts_head_next;
493 unsigned int segs_n = buf->nb_segs;
494 volatile struct mlx5_wqe_data_seg *dseg;
498 * Make sure there is enough room to store this packet and
499 * that one ring entry remains unused.
502 if (max < segs_n + 1)
506 elts_head_next = (elts_head + 1) & (elts_n - 1);
507 wqe = &(*txq->wqes)[txq->wqe_ci & (txq->wqe_n - 1)].hdr;
508 tx_prefetch_wqe(txq, txq->wqe_ci);
509 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
511 rte_prefetch0(*pkts);
512 length = DATA_LEN(buf);
513 /* Update element. */
514 (*txq->elts)[elts_head] = buf;
515 /* Prefetch next buffer data. */
517 rte_prefetch0(rte_pktmbuf_mtod(*pkts,
519 /* Should we enable HW CKSUM offload */
521 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
523 MLX5_ETH_WQE_L3_CSUM |
524 MLX5_ETH_WQE_L4_CSUM;
526 wqe->eseg.cs_flags = 0;
528 ds = mlx5_wqe_write(txq, wqe, buf, length);
531 dseg = (volatile struct mlx5_wqe_data_seg *)
532 (((uintptr_t)wqe) + ds * MLX5_WQE_DWORD_SIZE);
535 * Spill on next WQE when the current one does not have
536 * enough room left. Size of WQE must a be a multiple
537 * of data segment size.
539 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
540 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE)))
541 dseg = (volatile void *)
542 &(*txq->wqes)[txq->wqe_ci++ &
549 /* Store segment information. */
550 dseg->byte_count = htonl(DATA_LEN(buf));
551 dseg->lkey = txq_mp2mr(txq, txq_mb2mp(buf));
552 dseg->addr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
553 (*txq->elts)[elts_head_next] = buf;
554 elts_head_next = (elts_head_next + 1) & (elts_n - 1);
555 #ifdef MLX5_PMD_SOFT_COUNTERS
556 length += DATA_LEN(buf);
560 /* Update DS field in WQE. */
561 wqe->ctrl[1] &= htonl(0xffffffc0);
562 wqe->ctrl[1] |= htonl(ds & 0x3f);
564 #ifdef MLX5_PMD_SOFT_COUNTERS
565 /* Increment sent bytes counter. */
566 txq->stats.obytes += length;
568 /* Increment consumer index. */
569 txq->wqe_ci += (ds + 3) / 4;
570 elts_head = elts_head_next;
573 /* Take a shortcut if nothing must be sent. */
574 if (unlikely(i == 0))
576 /* Check whether completion threshold has been reached. */
577 comp = txq->elts_comp + i + j;
578 if (comp >= MLX5_TX_COMP_THRESH) {
579 /* Request completion on last WQE. */
580 wqe->ctrl[2] = htonl(8);
581 /* Save elts_head in unused "immediate" field of WQE. */
582 wqe->ctrl[3] = elts_head;
585 txq->elts_comp = comp;
587 #ifdef MLX5_PMD_SOFT_COUNTERS
588 /* Increment sent packets counter. */
589 txq->stats.opackets += i;
591 /* Ring QP doorbell. */
593 txq->elts_head = elts_head;
598 * Open a MPW session.
601 * Pointer to TX queue structure.
603 * Pointer to MPW session structure.
608 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
610 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
611 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
612 (volatile struct mlx5_wqe_data_seg (*)[])
613 (uintptr_t)&(*txq->wqes)[(idx + 1) & (txq->wqe_n - 1)];
615 mpw->state = MLX5_MPW_STATE_OPENED;
619 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
620 mpw->wqe->eseg.mss = htons(length);
621 mpw->wqe->eseg.inline_hdr_sz = 0;
622 mpw->wqe->eseg.rsvd0 = 0;
623 mpw->wqe->eseg.rsvd1 = 0;
624 mpw->wqe->eseg.rsvd2 = 0;
625 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
626 (txq->wqe_ci << 8) | MLX5_OPCODE_LSO_MPW);
627 mpw->wqe->ctrl[2] = 0;
628 mpw->wqe->ctrl[3] = 0;
629 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
630 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
631 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
632 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
633 mpw->data.dseg[2] = &(*dseg)[0];
634 mpw->data.dseg[3] = &(*dseg)[1];
635 mpw->data.dseg[4] = &(*dseg)[2];
639 * Close a MPW session.
642 * Pointer to TX queue structure.
644 * Pointer to MPW session structure.
647 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
649 unsigned int num = mpw->pkts_n;
652 * Store size in multiple of 16 bytes. Control and Ethernet segments
655 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
656 mpw->state = MLX5_MPW_STATE_CLOSED;
661 tx_prefetch_wqe(txq, txq->wqe_ci);
662 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
666 * DPDK callback for TX with MPW support.
669 * Generic pointer to TX queue structure.
671 * Packets to transmit.
673 * Number of packets in array.
676 * Number of packets successfully transmitted (<= pkts_n).
679 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
681 struct txq *txq = (struct txq *)dpdk_txq;
682 uint16_t elts_head = txq->elts_head;
683 const unsigned int elts_n = 1 << txq->elts_n;
688 struct mlx5_mpw mpw = {
689 .state = MLX5_MPW_STATE_CLOSED,
692 if (unlikely(!pkts_n))
694 /* Prefetch first packet cacheline. */
695 tx_prefetch_cqe(txq, txq->cq_ci);
696 tx_prefetch_wqe(txq, txq->wqe_ci);
697 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
698 /* Start processing. */
700 max = (elts_n - (elts_head - txq->elts_tail));
704 struct rte_mbuf *buf = *(pkts++);
705 unsigned int elts_head_next;
707 unsigned int segs_n = buf->nb_segs;
708 uint32_t cs_flags = 0;
711 * Make sure there is enough room to store this packet and
712 * that one ring entry remains unused.
715 if (max < segs_n + 1)
717 /* Do not bother with large packets MPW cannot handle. */
718 if (segs_n > MLX5_MPW_DSEG_MAX)
722 /* Should we enable HW CKSUM offload */
724 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
725 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
726 /* Retrieve packet information. */
727 length = PKT_LEN(buf);
729 /* Start new session if packet differs. */
730 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
731 ((mpw.len != length) ||
733 (mpw.wqe->eseg.cs_flags != cs_flags)))
734 mlx5_mpw_close(txq, &mpw);
735 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
736 mlx5_mpw_new(txq, &mpw, length);
737 mpw.wqe->eseg.cs_flags = cs_flags;
739 /* Multi-segment packets must be alone in their MPW. */
740 assert((segs_n == 1) || (mpw.pkts_n == 0));
741 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
745 volatile struct mlx5_wqe_data_seg *dseg;
748 elts_head_next = (elts_head + 1) & (elts_n - 1);
750 (*txq->elts)[elts_head] = buf;
751 dseg = mpw.data.dseg[mpw.pkts_n];
752 addr = rte_pktmbuf_mtod(buf, uintptr_t);
753 *dseg = (struct mlx5_wqe_data_seg){
754 .byte_count = htonl(DATA_LEN(buf)),
755 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
756 .addr = htonll(addr),
758 elts_head = elts_head_next;
759 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
760 length += DATA_LEN(buf);
766 assert(length == mpw.len);
767 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
768 mlx5_mpw_close(txq, &mpw);
769 elts_head = elts_head_next;
770 #ifdef MLX5_PMD_SOFT_COUNTERS
771 /* Increment sent bytes counter. */
772 txq->stats.obytes += length;
776 /* Take a shortcut if nothing must be sent. */
777 if (unlikely(i == 0))
779 /* Check whether completion threshold has been reached. */
780 /* "j" includes both packets and segments. */
781 comp = txq->elts_comp + j;
782 if (comp >= MLX5_TX_COMP_THRESH) {
783 volatile struct mlx5_wqe *wqe = mpw.wqe;
785 /* Request completion on last WQE. */
786 wqe->ctrl[2] = htonl(8);
787 /* Save elts_head in unused "immediate" field of WQE. */
788 wqe->ctrl[3] = elts_head;
791 txq->elts_comp = comp;
793 #ifdef MLX5_PMD_SOFT_COUNTERS
794 /* Increment sent packets counter. */
795 txq->stats.opackets += i;
797 /* Ring QP doorbell. */
798 if (mpw.state == MLX5_MPW_STATE_OPENED)
799 mlx5_mpw_close(txq, &mpw);
801 txq->elts_head = elts_head;
806 * Open a MPW inline session.
809 * Pointer to TX queue structure.
811 * Pointer to MPW session structure.
816 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
818 uint16_t idx = txq->wqe_ci & (txq->wqe_n - 1);
819 struct mlx5_wqe_inl_small *inl;
821 mpw->state = MLX5_MPW_INL_STATE_OPENED;
825 mpw->wqe = (volatile struct mlx5_wqe *)&(*txq->wqes)[idx].hdr;
826 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
828 MLX5_OPCODE_LSO_MPW);
829 mpw->wqe->ctrl[2] = 0;
830 mpw->wqe->ctrl[3] = 0;
831 mpw->wqe->eseg.mss = htons(length);
832 mpw->wqe->eseg.inline_hdr_sz = 0;
833 mpw->wqe->eseg.cs_flags = 0;
834 mpw->wqe->eseg.rsvd0 = 0;
835 mpw->wqe->eseg.rsvd1 = 0;
836 mpw->wqe->eseg.rsvd2 = 0;
837 inl = (struct mlx5_wqe_inl_small *)
838 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
839 mpw->data.raw = (uint8_t *)&inl->raw;
843 * Close a MPW inline session.
846 * Pointer to TX queue structure.
848 * Pointer to MPW session structure.
851 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
854 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
855 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
857 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
859 * Store size in multiple of 16 bytes. Control and Ethernet segments
862 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
863 mpw->state = MLX5_MPW_STATE_CLOSED;
864 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
865 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
869 * DPDK callback for TX with MPW inline support.
872 * Generic pointer to TX queue structure.
874 * Packets to transmit.
876 * Number of packets in array.
879 * Number of packets successfully transmitted (<= pkts_n).
882 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
885 struct txq *txq = (struct txq *)dpdk_txq;
886 uint16_t elts_head = txq->elts_head;
887 const unsigned int elts_n = 1 << txq->elts_n;
892 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
893 struct mlx5_mpw mpw = {
894 .state = MLX5_MPW_STATE_CLOSED,
897 if (unlikely(!pkts_n))
899 /* Prefetch first packet cacheline. */
900 tx_prefetch_cqe(txq, txq->cq_ci);
901 tx_prefetch_wqe(txq, txq->wqe_ci);
902 tx_prefetch_wqe(txq, txq->wqe_ci + 1);
903 /* Start processing. */
905 max = (elts_n - (elts_head - txq->elts_tail));
909 struct rte_mbuf *buf = *(pkts++);
910 unsigned int elts_head_next;
913 unsigned int segs_n = buf->nb_segs;
914 uint32_t cs_flags = 0;
917 * Make sure there is enough room to store this packet and
918 * that one ring entry remains unused.
921 if (max < segs_n + 1)
923 /* Do not bother with large packets MPW cannot handle. */
924 if (segs_n > MLX5_MPW_DSEG_MAX)
928 /* Should we enable HW CKSUM offload */
930 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
931 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
932 /* Retrieve packet information. */
933 length = PKT_LEN(buf);
934 /* Start new session if packet differs. */
935 if (mpw.state == MLX5_MPW_STATE_OPENED) {
936 if ((mpw.len != length) ||
938 (mpw.wqe->eseg.cs_flags != cs_flags))
939 mlx5_mpw_close(txq, &mpw);
940 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
941 if ((mpw.len != length) ||
943 (length > inline_room) ||
944 (mpw.wqe->eseg.cs_flags != cs_flags)) {
945 mlx5_mpw_inline_close(txq, &mpw);
947 txq->max_inline * RTE_CACHE_LINE_SIZE;
950 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
952 (length > inline_room)) {
953 mlx5_mpw_new(txq, &mpw, length);
954 mpw.wqe->eseg.cs_flags = cs_flags;
956 mlx5_mpw_inline_new(txq, &mpw, length);
957 mpw.wqe->eseg.cs_flags = cs_flags;
960 /* Multi-segment packets must be alone in their MPW. */
961 assert((segs_n == 1) || (mpw.pkts_n == 0));
962 if (mpw.state == MLX5_MPW_STATE_OPENED) {
963 assert(inline_room ==
964 txq->max_inline * RTE_CACHE_LINE_SIZE);
965 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
969 volatile struct mlx5_wqe_data_seg *dseg;
972 (elts_head + 1) & (elts_n - 1);
974 (*txq->elts)[elts_head] = buf;
975 dseg = mpw.data.dseg[mpw.pkts_n];
976 addr = rte_pktmbuf_mtod(buf, uintptr_t);
977 *dseg = (struct mlx5_wqe_data_seg){
978 .byte_count = htonl(DATA_LEN(buf)),
979 .lkey = txq_mp2mr(txq, txq_mb2mp(buf)),
980 .addr = htonll(addr),
982 elts_head = elts_head_next;
983 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
984 length += DATA_LEN(buf);
990 assert(length == mpw.len);
991 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
992 mlx5_mpw_close(txq, &mpw);
996 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
997 assert(length <= inline_room);
998 assert(length == DATA_LEN(buf));
999 elts_head_next = (elts_head + 1) & (elts_n - 1);
1000 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1001 (*txq->elts)[elts_head] = buf;
1002 /* Maximum number of bytes before wrapping. */
1003 max = ((uintptr_t)&(*txq->wqes)[txq->wqe_n] -
1004 (uintptr_t)mpw.data.raw);
1006 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1010 (volatile void *)&(*txq->wqes)[0];
1011 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1012 (void *)(addr + max),
1014 mpw.data.raw += length - max;
1016 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1019 mpw.data.raw += length;
1021 if ((uintptr_t)mpw.data.raw ==
1022 (uintptr_t)&(*txq->wqes)[txq->wqe_n])
1024 (volatile void *)&(*txq->wqes)[0];
1027 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1028 mlx5_mpw_inline_close(txq, &mpw);
1030 txq->max_inline * RTE_CACHE_LINE_SIZE;
1032 inline_room -= length;
1035 mpw.total_len += length;
1036 elts_head = elts_head_next;
1037 #ifdef MLX5_PMD_SOFT_COUNTERS
1038 /* Increment sent bytes counter. */
1039 txq->stats.obytes += length;
1043 /* Take a shortcut if nothing must be sent. */
1044 if (unlikely(i == 0))
1046 /* Check whether completion threshold has been reached. */
1047 /* "j" includes both packets and segments. */
1048 comp = txq->elts_comp + j;
1049 if (comp >= MLX5_TX_COMP_THRESH) {
1050 volatile struct mlx5_wqe *wqe = mpw.wqe;
1052 /* Request completion on last WQE. */
1053 wqe->ctrl[2] = htonl(8);
1054 /* Save elts_head in unused "immediate" field of WQE. */
1055 wqe->ctrl[3] = elts_head;
1058 txq->elts_comp = comp;
1060 #ifdef MLX5_PMD_SOFT_COUNTERS
1061 /* Increment sent packets counter. */
1062 txq->stats.opackets += i;
1064 /* Ring QP doorbell. */
1065 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1066 mlx5_mpw_inline_close(txq, &mpw);
1067 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1068 mlx5_mpw_close(txq, &mpw);
1070 txq->elts_head = elts_head;
1075 * Translate RX completion flags to packet type.
1080 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1083 * Packet type for struct rte_mbuf.
1085 static inline uint32_t
1086 rxq_cq_to_pkt_type(volatile struct mlx5_cqe64 *cqe)
1089 uint8_t flags = cqe->l4_hdr_type_etc;
1090 uint8_t info = cqe->rsvd0[0];
1092 if (info & IBV_EXP_CQ_RX_TUNNEL_PACKET)
1095 IBV_EXP_CQ_RX_OUTER_IPV4_PACKET,
1096 RTE_PTYPE_L3_IPV4) |
1098 IBV_EXP_CQ_RX_OUTER_IPV6_PACKET,
1099 RTE_PTYPE_L3_IPV6) |
1101 IBV_EXP_CQ_RX_IPV4_PACKET,
1102 RTE_PTYPE_INNER_L3_IPV4) |
1104 IBV_EXP_CQ_RX_IPV6_PACKET,
1105 RTE_PTYPE_INNER_L3_IPV6);
1109 MLX5_CQE_L3_HDR_TYPE_IPV6,
1110 RTE_PTYPE_L3_IPV6) |
1112 MLX5_CQE_L3_HDR_TYPE_IPV4,
1118 * Get size of the next packet for a given CQE. For compressed CQEs, the
1119 * consumer index is updated only once all packets of the current one have
1123 * Pointer to RX queue.
1128 * Packet size in bytes (0 if there is none), -1 in case of completion
1132 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe,
1135 struct rxq_zip *zip = &rxq->zip;
1136 uint16_t cqe_n = cqe_cnt + 1;
1139 /* Process compressed data in the CQE and mini arrays. */
1141 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1142 (volatile struct mlx5_mini_cqe8 (*)[8])
1143 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].cqe64);
1145 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1146 if ((++zip->ai & 7) == 0) {
1148 * Increment consumer index to skip the number of
1149 * CQEs consumed. Hardware leaves holes in the CQ
1150 * ring for software use.
1155 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1156 uint16_t idx = rxq->cq_ci;
1157 uint16_t end = zip->cq_ci;
1159 while (idx != end) {
1160 (*rxq->cqes)[idx & cqe_cnt].cqe64.op_own =
1161 MLX5_CQE_INVALIDATE;
1164 rxq->cq_ci = zip->cq_ci;
1167 /* No compressed data, get next CQE and verify if it is compressed. */
1172 ret = check_cqe64(cqe, cqe_n, rxq->cq_ci);
1173 if (unlikely(ret == 1))
1176 op_own = cqe->op_own;
1177 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1178 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1179 (volatile struct mlx5_mini_cqe8 (*)[8])
1180 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1183 /* Fix endianness. */
1184 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1186 * Current mini array position is the one returned by
1189 * If completion comprises several mini arrays, as a
1190 * special case the second one is located 7 CQEs after
1191 * the initial CQE instead of 8 for subsequent ones.
1193 zip->ca = rxq->cq_ci & cqe_cnt;
1194 zip->na = zip->ca + 7;
1195 /* Compute the next non compressed CQE. */
1197 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1198 /* Get packet size to return. */
1199 len = ntohl((*mc)[0].byte_cnt);
1202 len = ntohl(cqe->byte_cnt);
1204 /* Error while receiving packet. */
1205 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1212 * Translate RX completion flags to offload flags.
1215 * Pointer to RX queue structure.
1220 * Offload flags (ol_flags) for struct rte_mbuf.
1222 static inline uint32_t
1223 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe64 *cqe)
1225 uint32_t ol_flags = 0;
1226 uint8_t l3_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L3_HDR_TYPE_MASK;
1227 uint8_t l4_hdr = (cqe->l4_hdr_type_etc) & MLX5_CQE_L4_HDR_TYPE_MASK;
1228 uint8_t info = cqe->rsvd0[0];
1230 if ((l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV4) ||
1231 (l3_hdr == MLX5_CQE_L3_HDR_TYPE_IPV6))
1233 (!(cqe->hds_ip_ext & MLX5_CQE_L3_OK) *
1234 PKT_RX_IP_CKSUM_BAD);
1235 if ((l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP) ||
1236 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_EMP_ACK) ||
1237 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_TCP_ACK) ||
1238 (l4_hdr == MLX5_CQE_L4_HDR_TYPE_UDP))
1240 (!(cqe->hds_ip_ext & MLX5_CQE_L4_OK) *
1241 PKT_RX_L4_CKSUM_BAD);
1243 * PKT_RX_IP_CKSUM_BAD and PKT_RX_L4_CKSUM_BAD are used in place
1244 * of PKT_RX_EIP_CKSUM_BAD because the latter is not functional
1247 if ((info & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1249 TRANSPOSE(~cqe->l4_hdr_type_etc,
1250 IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
1251 PKT_RX_IP_CKSUM_BAD) |
1252 TRANSPOSE(~cqe->l4_hdr_type_etc,
1253 IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
1254 PKT_RX_L4_CKSUM_BAD);
1259 * DPDK callback for RX.
1262 * Generic pointer to RX queue structure.
1264 * Array to store received packets.
1266 * Maximum number of packets in array.
1269 * Number of packets successfully received (<= pkts_n).
1272 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1274 struct rxq *rxq = dpdk_rxq;
1275 const unsigned int cqe_cnt = rxq->cqe_n - 1;
1276 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1277 const unsigned int sges_n = rxq->sges_n;
1278 struct rte_mbuf *pkt = NULL;
1279 struct rte_mbuf *seg = NULL;
1280 volatile struct mlx5_cqe64 *cqe =
1281 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1283 unsigned int rq_ci = rxq->rq_ci << sges_n;
1287 unsigned int idx = rq_ci & wqe_cnt;
1288 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1289 struct rte_mbuf *rep = (*rxq->elts)[idx];
1297 rep = rte_mbuf_raw_alloc(rxq->mp);
1298 if (unlikely(rep == NULL)) {
1299 ++rxq->stats.rx_nombuf;
1302 * no buffers before we even started,
1303 * bail out silently.
1307 while (pkt != seg) {
1308 assert(pkt != (*rxq->elts)[idx]);
1310 rte_mbuf_refcnt_set(pkt, 0);
1311 __rte_mbuf_raw_free(pkt);
1317 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt].cqe64;
1318 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt);
1320 rte_mbuf_refcnt_set(rep, 0);
1321 __rte_mbuf_raw_free(rep);
1324 if (unlikely(len == -1)) {
1325 /* RX error, packet is likely too large. */
1326 rte_mbuf_refcnt_set(rep, 0);
1327 __rte_mbuf_raw_free(rep);
1328 ++rxq->stats.idropped;
1332 assert(len >= (rxq->crc_present << 2));
1333 /* Update packet information. */
1334 pkt->packet_type = 0;
1336 if (rxq->csum | rxq->csum_l2tun | rxq->vlan_strip |
1340 rxq_cq_to_pkt_type(cqe);
1342 rxq_cq_to_ol_flags(rxq, cqe);
1344 if (cqe->l4_hdr_type_etc &
1345 MLX5_CQE_VLAN_STRIPPED) {
1346 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1347 PKT_RX_VLAN_STRIPPED;
1348 pkt->vlan_tci = ntohs(cqe->vlan_info);
1350 if (rxq->crc_present)
1351 len -= ETHER_CRC_LEN;
1355 DATA_LEN(rep) = DATA_LEN(seg);
1356 PKT_LEN(rep) = PKT_LEN(seg);
1357 SET_DATA_OFF(rep, DATA_OFF(seg));
1358 NB_SEGS(rep) = NB_SEGS(seg);
1359 PORT(rep) = PORT(seg);
1361 (*rxq->elts)[idx] = rep;
1363 * Fill NIC descriptor with the new buffer. The lkey and size
1364 * of the buffers are already known, only the buffer address
1367 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1368 if (len > DATA_LEN(seg)) {
1369 len -= DATA_LEN(seg);
1374 DATA_LEN(seg) = len;
1375 #ifdef MLX5_PMD_SOFT_COUNTERS
1376 /* Increment bytes counter. */
1377 rxq->stats.ibytes += PKT_LEN(pkt);
1379 /* Return packet. */
1385 /* Align consumer index to the next stride. */
1390 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1392 /* Update the consumer index. */
1393 rxq->rq_ci = rq_ci >> sges_n;
1395 *rxq->cq_db = htonl(rxq->cq_ci);
1397 *rxq->rq_db = htonl(rxq->rq_ci);
1398 #ifdef MLX5_PMD_SOFT_COUNTERS
1399 /* Increment packets counter. */
1400 rxq->stats.ipackets += i;
1406 * Dummy DPDK callback for TX.
1408 * This function is used to temporarily replace the real callback during
1409 * unsafe control operations on the queue, or in case of error.
1412 * Generic pointer to TX queue structure.
1414 * Packets to transmit.
1416 * Number of packets in array.
1419 * Number of packets successfully transmitted (<= pkts_n).
1422 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1431 * Dummy DPDK callback for RX.
1433 * This function is used to temporarily replace the real callback during
1434 * unsafe control operations on the queue, or in case of error.
1437 * Generic pointer to RX queue structure.
1439 * Array to store received packets.
1441 * Maximum number of packets in array.
1444 * Number of packets successfully received (<= pkts_n).
1447 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)