1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include "mlx5_utils.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* TX burst subroutines return codes. */
38 enum mlx5_txcmp_code {
39 MLX5_TXCMP_CODE_EXIT = 0,
40 MLX5_TXCMP_CODE_ERROR,
41 MLX5_TXCMP_CODE_SINGLE,
42 MLX5_TXCMP_CODE_MULTI,
48 * These defines are used to configure Tx burst routine option set
49 * supported at compile time. The not specified options are optimized out
50 * out due to if conditions can be explicitly calculated at compile time.
51 * The offloads with bigger runtime check (require more CPU cycles to
52 * skip) overhead should have the bigger index - this is needed to
53 * select the better matching routine function if no exact match and
54 * some offloads are not actually requested.
56 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
57 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
58 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
59 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
60 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
61 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
62 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
63 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 /* The most common offloads groups. */
66 #define MLX5_TXOFF_CONFIG_NONE 0
67 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
68 MLX5_TXOFF_CONFIG_TSO | \
69 MLX5_TXOFF_CONFIG_SWP | \
70 MLX5_TXOFF_CONFIG_CSUM | \
71 MLX5_TXOFF_CONFIG_INLINE | \
72 MLX5_TXOFF_CONFIG_VLAN | \
73 MLX5_TXOFF_CONFIG_METADATA)
75 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
77 #define MLX5_TXOFF_DECL(func, olx) \
78 static uint16_t mlx5_tx_burst_##func(void *txq, \
79 struct rte_mbuf **pkts, \
82 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
83 pkts, pkts_n, (olx)); \
86 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
88 static __rte_always_inline uint32_t
89 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
91 static __rte_always_inline int
92 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
95 static __rte_always_inline uint32_t
96 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
98 static __rte_always_inline void
99 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
100 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
102 static __rte_always_inline void
103 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
104 const unsigned int strd_n);
107 mlx5_queue_state_modify(struct rte_eth_dev *dev,
108 struct mlx5_mp_arg_queue_state_modify *sm);
110 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
111 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
114 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
115 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
118 * Build a table to translate Rx completion flags to packet type.
120 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
123 mlx5_set_ptype_table(void)
126 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
128 /* Last entry must not be overwritten, reserved for errored packet. */
129 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
130 (*p)[i] = RTE_PTYPE_UNKNOWN;
132 * The index to the array should have:
133 * bit[1:0] = l3_hdr_type
134 * bit[4:2] = l4_hdr_type
137 * bit[7] = outer_l3_type
140 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
142 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
143 RTE_PTYPE_L4_NONFRAG;
144 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_L4_NONFRAG;
147 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
152 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
154 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
156 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
158 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
160 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
162 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
165 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
167 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 /* Repeat with outer_l3_type being set. Just in case. */
170 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_L4_NONFRAG;
172 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_L4_NONFRAG;
174 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
178 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
180 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
184 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
186 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
190 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
192 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
196 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_NONFRAG;
199 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L4_NONFRAG;
202 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
203 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_NONFRAG;
206 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 /* Tunneled - Fragmented */
210 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
212 RTE_PTYPE_INNER_L4_FRAG;
213 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_FRAG;
216 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_FRAG;
219 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
220 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L4_FRAG;
223 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_TCP;
226 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_TCP;
229 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_TCP;
232 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L4_TCP;
235 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L4_TCP;
238 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L4_TCP;
241 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_UDP;
263 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_UDP;
266 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_UDP;
269 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L4_UDP;
275 * Build a table to translate packet to checksum type of Verbs.
278 mlx5_set_cksum_table(void)
284 * The index should have:
285 * bit[0] = PKT_TX_TCP_SEG
286 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
287 * bit[4] = PKT_TX_IP_CKSUM
288 * bit[8] = PKT_TX_OUTER_IP_CKSUM
291 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
294 /* Tunneled packet. */
295 if (i & (1 << 8)) /* Outer IP. */
296 v |= MLX5_ETH_WQE_L3_CSUM;
297 if (i & (1 << 4)) /* Inner IP. */
298 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
299 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
300 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
303 if (i & (1 << 4)) /* IP. */
304 v |= MLX5_ETH_WQE_L3_CSUM;
305 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
306 v |= MLX5_ETH_WQE_L4_CSUM;
308 mlx5_cksum_table[i] = v;
313 * Build a table to translate packet type of mbuf to SWP type of Verbs.
316 mlx5_set_swp_types_table(void)
322 * The index should have:
323 * bit[0:1] = PKT_TX_L4_MASK
324 * bit[4] = PKT_TX_IPV6
325 * bit[8] = PKT_TX_OUTER_IPV6
326 * bit[9] = PKT_TX_OUTER_UDP
328 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
331 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
333 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
335 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
336 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
337 v |= MLX5_ETH_WQE_L4_INNER_UDP;
338 mlx5_swp_types_table[i] = v;
343 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
344 * Flags must be preliminary initialized to zero.
347 * Pointer to burst routine local context.
349 * Pointer to store Software Parser flags
351 * Configured Tx offloads mask. It is fully defined at
352 * compile time and may be used for optimization.
355 * Software Parser offsets packed in dword.
356 * Software Parser flags are set by pointer.
358 static __rte_always_inline uint32_t
359 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
364 unsigned int idx, off;
367 if (!MLX5_TXOFF_CONFIG(SWP))
369 ol = loc->mbuf->ol_flags;
370 tunnel = ol & PKT_TX_TUNNEL_MASK;
372 * Check whether Software Parser is required.
373 * Only customized tunnels may ask for.
375 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
378 * The index should have:
379 * bit[0:1] = PKT_TX_L4_MASK
380 * bit[4] = PKT_TX_IPV6
381 * bit[8] = PKT_TX_OUTER_IPV6
382 * bit[9] = PKT_TX_OUTER_UDP
384 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
385 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
386 *swp_flags = mlx5_swp_types_table[idx];
388 * Set offsets for SW parser. Since ConnectX-5, SW parser just
389 * complements HW parser. SW parser starts to engage only if HW parser
390 * can't reach a header. For the older devices, HW parser will not kick
391 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
392 * should be set regardless of HW offload.
394 off = loc->mbuf->outer_l2_len;
395 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
396 off += sizeof(struct rte_vlan_hdr);
397 set = (off >> 1) << 8; /* Outer L3 offset. */
398 off += loc->mbuf->outer_l3_len;
399 if (tunnel == PKT_TX_TUNNEL_UDP)
400 set |= off >> 1; /* Outer L4 offset. */
401 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
402 const uint64_t csum = ol & PKT_TX_L4_MASK;
403 off += loc->mbuf->l2_len;
404 set |= (off >> 1) << 24; /* Inner L3 offset. */
405 if (csum == PKT_TX_TCP_CKSUM ||
406 csum == PKT_TX_UDP_CKSUM ||
407 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
408 off += loc->mbuf->l3_len;
409 set |= (off >> 1) << 16; /* Inner L4 offset. */
412 set = rte_cpu_to_le_32(set);
417 * Convert the Checksum offloads to Verbs.
420 * Pointer to the mbuf.
423 * Converted checksum flags.
425 static __rte_always_inline uint8_t
426 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
429 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
430 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
431 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
434 * The index should have:
435 * bit[0] = PKT_TX_TCP_SEG
436 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
437 * bit[4] = PKT_TX_IP_CKSUM
438 * bit[8] = PKT_TX_OUTER_IP_CKSUM
441 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
442 return mlx5_cksum_table[idx];
446 * Internal function to compute the number of used descriptors in an RX queue
452 * The number of used rx descriptor.
455 rx_queue_count(struct mlx5_rxq_data *rxq)
457 struct rxq_zip *zip = &rxq->zip;
458 volatile struct mlx5_cqe *cqe;
459 const unsigned int cqe_n = (1 << rxq->cqe_n);
460 const unsigned int cqe_cnt = cqe_n - 1;
464 /* if we are processing a compressed cqe */
466 used = zip->cqe_cnt - zip->ca;
472 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
473 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
477 op_own = cqe->op_own;
478 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
479 n = rte_be_to_cpu_32(cqe->byte_cnt);
484 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
486 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
491 * DPDK callback to check the status of a rx descriptor.
496 * The index of the descriptor in the ring.
499 * The status of the tx descriptor.
502 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
504 struct mlx5_rxq_data *rxq = rx_queue;
505 struct mlx5_rxq_ctrl *rxq_ctrl =
506 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
507 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
509 if (dev->rx_pkt_burst != mlx5_rx_burst) {
513 if (offset >= (1 << rxq->elts_n)) {
517 if (offset < rx_queue_count(rxq))
518 return RTE_ETH_RX_DESC_DONE;
519 return RTE_ETH_RX_DESC_AVAIL;
523 * DPDK callback to get the number of used descriptors in a RX queue
526 * Pointer to the device structure.
532 * The number of used rx descriptor.
533 * -EINVAL if the queue is invalid
536 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
538 struct mlx5_priv *priv = dev->data->dev_private;
539 struct mlx5_rxq_data *rxq;
541 if (dev->rx_pkt_burst != mlx5_rx_burst) {
545 rxq = (*priv->rxqs)[rx_queue_id];
550 return rx_queue_count(rxq);
553 #define MLX5_SYSTEM_LOG_DIR "/var/log"
555 * Dump debug information to log file.
560 * If not NULL this string is printed as a header to the output
561 * and the output will be in hexadecimal view.
563 * This is the buffer address to print out.
565 * The number of bytes to dump out.
568 mlx5_dump_debug_information(const char *fname, const char *hex_title,
569 const void *buf, unsigned int hex_len)
573 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
574 fd = fopen(path, "a+");
576 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
578 MKSTR(path2, "./%s", fname);
579 fd = fopen(path2, "a+");
581 DRV_LOG(ERR, "cannot open %s for debug dump\n",
585 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
587 DRV_LOG(INFO, "New debug dump in file %s\n", path);
590 rte_hexdump(fd, hex_title, buf, hex_len);
592 fprintf(fd, "%s", (const char *)buf);
593 fprintf(fd, "\n\n\n");
598 * Move QP from error state to running state and initialize indexes.
601 * Pointer to TX queue control structure.
604 * 0 on success, else -1.
607 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
609 struct mlx5_mp_arg_queue_state_modify sm = {
611 .queue_id = txq_ctrl->txq.idx,
614 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
616 txq_ctrl->txq.wqe_ci = 0;
617 txq_ctrl->txq.wqe_pi = 0;
618 txq_ctrl->txq.elts_comp = 0;
622 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
624 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
626 static const uint8_t magic[] = "seen";
630 for (i = 0; i < sizeof(magic); ++i)
631 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
633 err_cqe->rsvd1[i] = magic[i];
642 * Pointer to TX queue structure.
644 * Pointer to the error CQE.
647 * The last Tx buffer element to free.
650 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
651 volatile struct mlx5_err_cqe *err_cqe)
653 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
654 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
655 struct mlx5_txq_ctrl *txq_ctrl =
656 container_of(txq, struct mlx5_txq_ctrl, txq);
657 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
658 int seen = check_err_cqe_seen(err_cqe);
660 if (!seen && txq_ctrl->dump_file_n <
661 txq_ctrl->priv->config.max_dump_files_num) {
662 MKSTR(err_str, "Unexpected CQE error syndrome "
663 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
664 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
665 txq->cqe_s, txq->qp_num_8s >> 8,
666 rte_be_to_cpu_16(err_cqe->wqe_counter),
667 txq->wqe_ci, txq->cq_ci);
668 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
669 PORT_ID(txq_ctrl->priv), txq->idx,
670 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
671 mlx5_dump_debug_information(name, NULL, err_str, 0);
672 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
673 (const void *)((uintptr_t)
677 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
678 (const void *)((uintptr_t)
682 txq_ctrl->dump_file_n++;
686 * Count errors in WQEs units.
687 * Later it can be improved to count error packets,
688 * for example, by SQ parsing to find how much packets
689 * should be counted for each WQE.
691 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
693 if (tx_recover_qp(txq_ctrl) == 0) {
695 /* Release all the remaining buffers. */
696 return txq->elts_head;
698 /* Recovering failed - try again later on the same WQE. */
702 /* Do not release buffers. */
703 return txq->elts_tail;
707 * Translate RX completion flags to packet type.
710 * Pointer to RX queue structure.
714 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
717 * Packet type for struct rte_mbuf.
719 static inline uint32_t
720 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
723 uint8_t pinfo = cqe->pkt_info;
724 uint16_t ptype = cqe->hdr_type_etc;
727 * The index to the array should have:
728 * bit[1:0] = l3_hdr_type
729 * bit[4:2] = l4_hdr_type
732 * bit[7] = outer_l3_type
734 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
735 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
739 * Initialize Rx WQ and indexes.
742 * Pointer to RX queue structure.
745 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
747 const unsigned int wqe_n = 1 << rxq->elts_n;
750 for (i = 0; (i != wqe_n); ++i) {
751 volatile struct mlx5_wqe_data_seg *scat;
755 if (mlx5_rxq_mprq_enabled(rxq)) {
756 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
758 scat = &((volatile struct mlx5_wqe_mprq *)
760 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
761 1 << rxq->strd_num_n);
762 byte_count = (1 << rxq->strd_sz_n) *
763 (1 << rxq->strd_num_n);
765 struct rte_mbuf *buf = (*rxq->elts)[i];
767 scat = &((volatile struct mlx5_wqe_data_seg *)
769 addr = rte_pktmbuf_mtod(buf, uintptr_t);
770 byte_count = DATA_LEN(buf);
772 /* scat->addr must be able to store a pointer. */
773 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
774 *scat = (struct mlx5_wqe_data_seg){
775 .addr = rte_cpu_to_be_64(addr),
776 .byte_count = rte_cpu_to_be_32(byte_count),
777 .lkey = mlx5_rx_addr2mr(rxq, addr),
780 rxq->consumed_strd = 0;
781 rxq->decompressed = 0;
783 rxq->zip = (struct rxq_zip){
786 /* Update doorbell counter. */
787 rxq->rq_ci = wqe_n >> rxq->sges_n;
789 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
793 * Modify a Verbs/DevX queue state.
794 * This must be called from the primary process.
797 * Pointer to Ethernet device.
799 * State modify request parameters.
802 * 0 in case of success else non-zero value and rte_errno is set.
805 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
806 const struct mlx5_mp_arg_queue_state_modify *sm)
809 struct mlx5_priv *priv = dev->data->dev_private;
812 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
813 struct mlx5_rxq_ctrl *rxq_ctrl =
814 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
816 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
817 struct ibv_wq_attr mod = {
818 .attr_mask = IBV_WQ_ATTR_STATE,
819 .wq_state = sm->state,
822 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
823 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
824 struct mlx5_devx_modify_rq_attr rq_attr;
826 memset(&rq_attr, 0, sizeof(rq_attr));
827 if (sm->state == IBV_WQS_RESET) {
828 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
829 rq_attr.state = MLX5_RQC_STATE_RST;
830 } else if (sm->state == IBV_WQS_RDY) {
831 rq_attr.rq_state = MLX5_RQC_STATE_RST;
832 rq_attr.state = MLX5_RQC_STATE_RDY;
833 } else if (sm->state == IBV_WQS_ERR) {
834 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
835 rq_attr.state = MLX5_RQC_STATE_ERR;
837 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
841 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s\n",
842 sm->state, strerror(errno));
847 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
848 struct mlx5_txq_ctrl *txq_ctrl =
849 container_of(txq, struct mlx5_txq_ctrl, txq);
850 struct ibv_qp_attr mod = {
851 .qp_state = IBV_QPS_RESET,
852 .port_num = (uint8_t)priv->ibv_port,
854 struct ibv_qp *qp = txq_ctrl->ibv->qp;
856 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
858 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
859 "%s\n", strerror(errno));
863 mod.qp_state = IBV_QPS_INIT;
864 ret = mlx5_glue->modify_qp(qp, &mod,
865 (IBV_QP_STATE | IBV_QP_PORT));
867 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s\n",
872 mod.qp_state = IBV_QPS_RTR;
873 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
875 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s\n",
880 mod.qp_state = IBV_QPS_RTS;
881 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
883 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s\n",
893 * Modify a Verbs queue state.
896 * Pointer to Ethernet device.
898 * State modify request parameters.
901 * 0 in case of success else non-zero value.
904 mlx5_queue_state_modify(struct rte_eth_dev *dev,
905 struct mlx5_mp_arg_queue_state_modify *sm)
909 switch (rte_eal_process_type()) {
910 case RTE_PROC_PRIMARY:
911 ret = mlx5_queue_state_modify_primary(dev, sm);
913 case RTE_PROC_SECONDARY:
914 ret = mlx5_mp_req_queue_state_modify(dev, sm);
924 * The function inserts the RQ state to reset when the first error CQE is
925 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
926 * it moves the RQ state to ready and initializes the RQ.
927 * Next CQE identification and error counting are in the caller responsibility.
930 * Pointer to RX queue structure.
931 * @param[in] mbuf_prepare
932 * Whether to prepare mbufs for the RQ.
935 * -1 in case of recovery error, otherwise the CQE status.
938 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
940 const uint16_t cqe_n = 1 << rxq->cqe_n;
941 const uint16_t cqe_mask = cqe_n - 1;
942 const unsigned int wqe_n = 1 << rxq->elts_n;
943 struct mlx5_rxq_ctrl *rxq_ctrl =
944 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
946 volatile struct mlx5_cqe *cqe;
947 volatile struct mlx5_err_cqe *err_cqe;
949 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
951 struct mlx5_mp_arg_queue_state_modify sm;
954 switch (rxq->err_state) {
955 case MLX5_RXQ_ERR_STATE_NO_ERROR:
956 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
958 case MLX5_RXQ_ERR_STATE_NEED_RESET:
960 sm.queue_id = rxq->idx;
961 sm.state = IBV_WQS_RESET;
962 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
964 if (rxq_ctrl->dump_file_n <
965 rxq_ctrl->priv->config.max_dump_files_num) {
966 MKSTR(err_str, "Unexpected CQE error syndrome "
967 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
968 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
969 rxq->cqn, rxq_ctrl->wqn,
970 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
971 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
972 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
973 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
974 mlx5_dump_debug_information(name, NULL, err_str, 0);
975 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
976 (const void *)((uintptr_t)
978 sizeof(*u.cqe) * cqe_n);
979 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
980 (const void *)((uintptr_t)
983 rxq_ctrl->dump_file_n++;
985 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
987 case MLX5_RXQ_ERR_STATE_NEED_READY:
988 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
989 if (ret == MLX5_CQE_STATUS_HW_OWN) {
991 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
994 * The RQ consumer index must be zeroed while moving
995 * from RESET state to RDY state.
997 *rxq->rq_db = rte_cpu_to_be_32(0);
1000 sm.queue_id = rxq->idx;
1001 sm.state = IBV_WQS_RDY;
1002 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1006 const uint16_t q_mask = wqe_n - 1;
1008 struct rte_mbuf **elt;
1010 unsigned int n = wqe_n - (rxq->rq_ci -
1013 for (i = 0; i < (int)n; ++i) {
1014 elt_idx = (rxq->rq_ci + i) & q_mask;
1015 elt = &(*rxq->elts)[elt_idx];
1016 *elt = rte_mbuf_raw_alloc(rxq->mp);
1018 for (i--; i >= 0; --i) {
1019 elt_idx = (rxq->rq_ci +
1023 rte_pktmbuf_free_seg
1030 mlx5_rxq_initialize(rxq);
1031 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1040 * Get size of the next packet for a given CQE. For compressed CQEs, the
1041 * consumer index is updated only once all packets of the current one have
1045 * Pointer to RX queue.
1049 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1053 * 0 in case of empty CQE, otherwise the packet size in bytes.
1056 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1057 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1059 struct rxq_zip *zip = &rxq->zip;
1060 uint16_t cqe_n = cqe_cnt + 1;
1066 /* Process compressed data in the CQE and mini arrays. */
1068 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1069 (volatile struct mlx5_mini_cqe8 (*)[8])
1070 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1073 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1074 *mcqe = &(*mc)[zip->ai & 7];
1075 if ((++zip->ai & 7) == 0) {
1076 /* Invalidate consumed CQEs */
1079 while (idx != end) {
1080 (*rxq->cqes)[idx & cqe_cnt].op_own =
1081 MLX5_CQE_INVALIDATE;
1085 * Increment consumer index to skip the number
1086 * of CQEs consumed. Hardware leaves holes in
1087 * the CQ ring for software use.
1092 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1093 /* Invalidate the rest */
1097 while (idx != end) {
1098 (*rxq->cqes)[idx & cqe_cnt].op_own =
1099 MLX5_CQE_INVALIDATE;
1102 rxq->cq_ci = zip->cq_ci;
1106 * No compressed data, get next CQE and verify if it is
1113 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1114 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1115 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1117 ret = mlx5_rx_err_handle(rxq, 0);
1118 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1126 op_own = cqe->op_own;
1127 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1128 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1129 (volatile struct mlx5_mini_cqe8 (*)[8])
1130 (uintptr_t)(&(*rxq->cqes)
1134 /* Fix endianness. */
1135 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1137 * Current mini array position is the one
1138 * returned by check_cqe64().
1140 * If completion comprises several mini arrays,
1141 * as a special case the second one is located
1142 * 7 CQEs after the initial CQE instead of 8
1143 * for subsequent ones.
1145 zip->ca = rxq->cq_ci;
1146 zip->na = zip->ca + 7;
1147 /* Compute the next non compressed CQE. */
1149 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1150 /* Get packet size to return. */
1151 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1154 /* Prefetch all to be invalidated */
1157 while (idx != end) {
1158 rte_prefetch0(&(*rxq->cqes)[(idx) &
1163 len = rte_be_to_cpu_32(cqe->byte_cnt);
1166 if (unlikely(rxq->err_state)) {
1167 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1168 ++rxq->stats.idropped;
1176 * Translate RX completion flags to offload flags.
1182 * Offload flags (ol_flags) for struct rte_mbuf.
1184 static inline uint32_t
1185 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1187 uint32_t ol_flags = 0;
1188 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1192 MLX5_CQE_RX_L3_HDR_VALID,
1193 PKT_RX_IP_CKSUM_GOOD) |
1195 MLX5_CQE_RX_L4_HDR_VALID,
1196 PKT_RX_L4_CKSUM_GOOD);
1201 * Fill in mbuf fields from RX completion flags.
1202 * Note that pkt->ol_flags should be initialized outside of this function.
1205 * Pointer to RX queue.
1210 * @param rss_hash_res
1211 * Packet RSS Hash result.
1214 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1215 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1217 /* Update packet information. */
1218 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1219 if (rss_hash_res && rxq->rss_hash) {
1220 pkt->hash.rss = rss_hash_res;
1221 pkt->ol_flags |= PKT_RX_RSS_HASH;
1223 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1224 pkt->ol_flags |= PKT_RX_FDIR;
1225 if (cqe->sop_drop_qpn !=
1226 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1227 uint32_t mark = cqe->sop_drop_qpn;
1229 pkt->ol_flags |= PKT_RX_FDIR_ID;
1230 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1234 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1235 if (rxq->vlan_strip &&
1236 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1237 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1238 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1240 if (rxq->hw_timestamp) {
1241 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1242 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1247 * DPDK callback for RX.
1250 * Generic pointer to RX queue structure.
1252 * Array to store received packets.
1254 * Maximum number of packets in array.
1257 * Number of packets successfully received (<= pkts_n).
1260 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1262 struct mlx5_rxq_data *rxq = dpdk_rxq;
1263 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1264 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1265 const unsigned int sges_n = rxq->sges_n;
1266 struct rte_mbuf *pkt = NULL;
1267 struct rte_mbuf *seg = NULL;
1268 volatile struct mlx5_cqe *cqe =
1269 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1271 unsigned int rq_ci = rxq->rq_ci << sges_n;
1272 int len = 0; /* keep its value across iterations. */
1275 unsigned int idx = rq_ci & wqe_cnt;
1276 volatile struct mlx5_wqe_data_seg *wqe =
1277 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1278 struct rte_mbuf *rep = (*rxq->elts)[idx];
1279 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1280 uint32_t rss_hash_res;
1288 rep = rte_mbuf_raw_alloc(rxq->mp);
1289 if (unlikely(rep == NULL)) {
1290 ++rxq->stats.rx_nombuf;
1293 * no buffers before we even started,
1294 * bail out silently.
1298 while (pkt != seg) {
1299 assert(pkt != (*rxq->elts)[idx]);
1303 rte_mbuf_raw_free(pkt);
1309 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1310 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1312 rte_mbuf_raw_free(rep);
1316 assert(len >= (rxq->crc_present << 2));
1318 /* If compressed, take hash result from mini-CQE. */
1319 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1321 mcqe->rx_hash_result);
1322 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1323 if (rxq->crc_present)
1324 len -= RTE_ETHER_CRC_LEN;
1327 DATA_LEN(rep) = DATA_LEN(seg);
1328 PKT_LEN(rep) = PKT_LEN(seg);
1329 SET_DATA_OFF(rep, DATA_OFF(seg));
1330 PORT(rep) = PORT(seg);
1331 (*rxq->elts)[idx] = rep;
1333 * Fill NIC descriptor with the new buffer. The lkey and size
1334 * of the buffers are already known, only the buffer address
1337 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1338 /* If there's only one MR, no need to replace LKey in WQE. */
1339 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1340 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1341 if (len > DATA_LEN(seg)) {
1342 len -= DATA_LEN(seg);
1347 DATA_LEN(seg) = len;
1348 #ifdef MLX5_PMD_SOFT_COUNTERS
1349 /* Increment bytes counter. */
1350 rxq->stats.ibytes += PKT_LEN(pkt);
1352 /* Return packet. */
1357 /* Align consumer index to the next stride. */
1362 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1364 /* Update the consumer index. */
1365 rxq->rq_ci = rq_ci >> sges_n;
1367 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1369 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1370 #ifdef MLX5_PMD_SOFT_COUNTERS
1371 /* Increment packets counter. */
1372 rxq->stats.ipackets += i;
1378 * Update LRO packet TCP header.
1379 * The HW LRO feature doesn't update the TCP header after coalescing the
1380 * TCP segments but supplies information in CQE to fill it by SW.
1383 * Pointer to the TCP header.
1385 * Pointer to the completion entry..
1387 * The L3 pseudo-header checksum.
1390 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1391 volatile struct mlx5_cqe *restrict cqe,
1394 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1395 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1397 * The HW calculates only the TCP payload checksum, need to complete
1398 * the TCP header checksum and the L3 pseudo-header checksum.
1400 uint32_t csum = phcsum + cqe->csum;
1402 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1403 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1404 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1405 tcp->recv_ack = cqe->lro_ack_seq_num;
1406 tcp->rx_win = cqe->lro_tcp_win;
1408 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1409 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1411 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1412 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1413 csum = (~csum) & 0xffff;
1420 * Update LRO packet headers.
1421 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1422 * TCP segments but supply information in CQE to fill it by SW.
1425 * The packet address.
1427 * Pointer to the completion entry..
1429 * The packet length.
1432 mlx5_lro_update_hdr(uint8_t *restrict padd,
1433 volatile struct mlx5_cqe *restrict cqe,
1437 struct rte_ether_hdr *eth;
1438 struct rte_vlan_hdr *vlan;
1439 struct rte_ipv4_hdr *ipv4;
1440 struct rte_ipv6_hdr *ipv6;
1441 struct rte_tcp_hdr *tcp;
1446 uint16_t proto = h.eth->ether_type;
1450 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1451 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1452 proto = h.vlan->eth_proto;
1455 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1456 h.ipv4->time_to_live = cqe->lro_min_ttl;
1457 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1458 h.ipv4->hdr_checksum = 0;
1459 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1460 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1463 h.ipv6->hop_limits = cqe->lro_min_ttl;
1464 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1466 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1469 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1473 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1475 struct mlx5_mprq_buf *buf = opaque;
1477 if (rte_atomic16_read(&buf->refcnt) == 1) {
1478 rte_mempool_put(buf->mp, buf);
1479 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1480 rte_atomic16_set(&buf->refcnt, 1);
1481 rte_mempool_put(buf->mp, buf);
1486 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1488 mlx5_mprq_buf_free_cb(NULL, buf);
1492 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1493 const unsigned int strd_n)
1495 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1496 volatile struct mlx5_wqe_data_seg *wqe =
1497 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1500 assert(rep != NULL);
1501 /* Replace MPRQ buf. */
1502 (*rxq->mprq_bufs)[rq_idx] = rep;
1504 addr = mlx5_mprq_buf_addr(rep, strd_n);
1505 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1506 /* If there's only one MR, no need to replace LKey in WQE. */
1507 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1508 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1509 /* Stash a mbuf for next replacement. */
1510 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1511 rxq->mprq_repl = rep;
1513 rxq->mprq_repl = NULL;
1517 * DPDK callback for RX with Multi-Packet RQ support.
1520 * Generic pointer to RX queue structure.
1522 * Array to store received packets.
1524 * Maximum number of packets in array.
1527 * Number of packets successfully received (<= pkts_n).
1530 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1532 struct mlx5_rxq_data *rxq = dpdk_rxq;
1533 const unsigned int strd_n = 1 << rxq->strd_num_n;
1534 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1535 const unsigned int strd_shift =
1536 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1537 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1538 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1539 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1541 uint32_t rq_ci = rxq->rq_ci;
1542 uint16_t consumed_strd = rxq->consumed_strd;
1543 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1545 while (i < pkts_n) {
1546 struct rte_mbuf *pkt;
1554 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1555 uint32_t rss_hash_res = 0;
1556 uint8_t lro_num_seg;
1558 if (consumed_strd == strd_n) {
1559 /* Replace WQE only if the buffer is still in use. */
1560 if (rte_atomic16_read(&buf->refcnt) > 1) {
1561 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1562 /* Release the old buffer. */
1563 mlx5_mprq_buf_free(buf);
1564 } else if (unlikely(rxq->mprq_repl == NULL)) {
1565 struct mlx5_mprq_buf *rep;
1568 * Currently, the MPRQ mempool is out of buffer
1569 * and doing memcpy regardless of the size of Rx
1570 * packet. Retry allocation to get back to
1573 if (!rte_mempool_get(rxq->mprq_mp,
1575 rxq->mprq_repl = rep;
1577 /* Advance to the next WQE. */
1580 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1582 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1583 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1587 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1588 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1590 consumed_strd += strd_cnt;
1591 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1594 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1595 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1597 /* mini-CQE for MPRQ doesn't have hash result. */
1598 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1600 assert(strd_idx < strd_n);
1601 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1602 lro_num_seg = cqe->lro_num_seg;
1604 * Currently configured to receive a packet per a stride. But if
1605 * MTU is adjusted through kernel interface, device could
1606 * consume multiple strides without raising an error. In this
1607 * case, the packet should be dropped because it is bigger than
1608 * the max_rx_pkt_len.
1610 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1611 ++rxq->stats.idropped;
1614 pkt = rte_pktmbuf_alloc(rxq->mp);
1615 if (unlikely(pkt == NULL)) {
1616 ++rxq->stats.rx_nombuf;
1619 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1620 assert((int)len >= (rxq->crc_present << 2));
1621 if (rxq->crc_present)
1622 len -= RTE_ETHER_CRC_LEN;
1623 offset = strd_idx * strd_sz + strd_shift;
1624 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1625 /* Initialize the offload flag. */
1628 * Memcpy packets to the target mbuf if:
1629 * - The size of packet is smaller than mprq_max_memcpy_len.
1630 * - Out of buffer in the Mempool for Multi-Packet RQ.
1632 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1634 * When memcpy'ing packet due to out-of-buffer, the
1635 * packet must be smaller than the target mbuf.
1637 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1638 rte_pktmbuf_free_seg(pkt);
1639 ++rxq->stats.idropped;
1642 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1644 rte_iova_t buf_iova;
1645 struct rte_mbuf_ext_shared_info *shinfo;
1646 uint16_t buf_len = strd_cnt * strd_sz;
1649 /* Increment the refcnt of the whole chunk. */
1650 rte_atomic16_add_return(&buf->refcnt, 1);
1651 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1653 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
1655 * MLX5 device doesn't use iova but it is necessary in a
1656 * case where the Rx packet is transmitted via a
1659 buf_iova = rte_mempool_virt2iova(buf) +
1660 RTE_PTR_DIFF(buf_addr, buf);
1661 shinfo = &buf->shinfos[strd_idx];
1662 rte_mbuf_ext_refcnt_set(shinfo, 1);
1664 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1665 * attaching the stride to mbuf and more offload flags
1666 * will be added below by calling rxq_cq_to_mbuf().
1667 * Other fields will be overwritten.
1669 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1671 rte_pktmbuf_reset_headroom(pkt);
1672 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1674 * Prevent potential overflow due to MTU change through
1677 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1678 rte_pktmbuf_free_seg(pkt);
1679 ++rxq->stats.idropped;
1683 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1684 if (lro_num_seg > 1) {
1685 mlx5_lro_update_hdr(addr, cqe, len);
1686 pkt->ol_flags |= PKT_RX_LRO;
1687 pkt->tso_segsz = strd_sz;
1690 DATA_LEN(pkt) = len;
1691 PORT(pkt) = rxq->port_id;
1692 #ifdef MLX5_PMD_SOFT_COUNTERS
1693 /* Increment bytes counter. */
1694 rxq->stats.ibytes += PKT_LEN(pkt);
1696 /* Return packet. */
1700 /* Update the consumer indexes. */
1701 rxq->consumed_strd = consumed_strd;
1703 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1704 if (rq_ci != rxq->rq_ci) {
1707 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1709 #ifdef MLX5_PMD_SOFT_COUNTERS
1710 /* Increment packets counter. */
1711 rxq->stats.ipackets += i;
1717 * Dummy DPDK callback for TX.
1719 * This function is used to temporarily replace the real callback during
1720 * unsafe control operations on the queue, or in case of error.
1723 * Generic pointer to TX queue structure.
1725 * Packets to transmit.
1727 * Number of packets in array.
1730 * Number of packets successfully transmitted (<= pkts_n).
1733 removed_tx_burst(void *dpdk_txq __rte_unused,
1734 struct rte_mbuf **pkts __rte_unused,
1735 uint16_t pkts_n __rte_unused)
1742 * Dummy DPDK callback for RX.
1744 * This function is used to temporarily replace the real callback during
1745 * unsafe control operations on the queue, or in case of error.
1748 * Generic pointer to RX queue structure.
1750 * Array to store received packets.
1752 * Maximum number of packets in array.
1755 * Number of packets successfully received (<= pkts_n).
1758 removed_rx_burst(void *dpdk_txq __rte_unused,
1759 struct rte_mbuf **pkts __rte_unused,
1760 uint16_t pkts_n __rte_unused)
1767 * Vectorized Rx/Tx routines are not compiled in when required vector
1768 * instructions are not supported on a target architecture. The following null
1769 * stubs are needed for linkage when those are not included outside of this file
1770 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1774 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1775 struct rte_mbuf **pkts __rte_unused,
1776 uint16_t pkts_n __rte_unused)
1782 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1788 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1794 * Free the mbufs from the linear array of pointers.
1797 * Pointer to array of packets to be free.
1799 * Number of packets to be freed.
1801 * Configured Tx offloads mask. It is fully defined at
1802 * compile time and may be used for optimization.
1804 static __rte_always_inline void
1805 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1806 unsigned int pkts_n,
1807 unsigned int olx __rte_unused)
1809 struct rte_mempool *pool = NULL;
1810 struct rte_mbuf **p_free = NULL;
1811 struct rte_mbuf *mbuf;
1812 unsigned int n_free = 0;
1815 * The implemented algorithm eliminates
1816 * copying pointers to temporary array
1817 * for rte_mempool_put_bulk() calls.
1824 * Decrement mbuf reference counter, detach
1825 * indirect and external buffers if needed.
1827 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1828 if (likely(mbuf != NULL)) {
1829 assert(mbuf == *pkts);
1830 if (likely(n_free != 0)) {
1831 if (unlikely(pool != mbuf->pool))
1832 /* From different pool. */
1835 /* Start new scan array. */
1842 if (unlikely(pkts_n == 0)) {
1848 * This happens if mbuf is still referenced.
1849 * We can't put it back to the pool, skip.
1853 if (unlikely(n_free != 0))
1854 /* There is some array to free.*/
1856 if (unlikely(pkts_n == 0))
1857 /* Last mbuf, nothing to free. */
1863 * This loop is implemented to avoid multiple
1864 * inlining of rte_mempool_put_bulk().
1870 * Free the array of pre-freed mbufs
1871 * belonging to the same memory pool.
1873 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1874 if (unlikely(mbuf != NULL)) {
1875 /* There is the request to start new scan. */
1880 if (likely(pkts_n != 0))
1883 * This is the last mbuf to be freed.
1884 * Do one more loop iteration to complete.
1885 * This is rare case of the last unique mbuf.
1890 if (likely(pkts_n == 0))
1899 * Free the mbuf from the elts ring buffer till new tail.
1902 * Pointer to Tx queue structure.
1904 * Index in elts to free up to, becomes new elts tail.
1906 * Configured Tx offloads mask. It is fully defined at
1907 * compile time and may be used for optimization.
1909 static __rte_always_inline void
1910 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1912 unsigned int olx __rte_unused)
1914 uint16_t n_elts = tail - txq->elts_tail;
1917 assert(n_elts <= txq->elts_s);
1919 * Implement a loop to support ring buffer wraparound
1920 * with single inlining of mlx5_tx_free_mbuf().
1925 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1926 part = RTE_MIN(part, n_elts);
1928 assert(part <= txq->elts_s);
1929 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1931 txq->elts_tail += part;
1937 * Store the mbuf being sent into elts ring buffer.
1938 * On Tx completion these mbufs will be freed.
1941 * Pointer to Tx queue structure.
1943 * Pointer to array of packets to be stored.
1945 * Number of packets to be stored.
1947 * Configured Tx offloads mask. It is fully defined at
1948 * compile time and may be used for optimization.
1950 static __rte_always_inline void
1951 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
1952 struct rte_mbuf **restrict pkts,
1953 unsigned int pkts_n,
1954 unsigned int olx __rte_unused)
1957 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
1961 part = txq->elts_s - (txq->elts_head & txq->elts_m);
1963 assert(part <= txq->elts_s);
1964 /* This code is a good candidate for vectorizing with SIMD. */
1965 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
1967 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
1968 txq->elts_head += pkts_n;
1969 if (unlikely(part < pkts_n))
1970 /* The copy is wrapping around the elts array. */
1971 rte_memcpy((void *)elts, (void *)(pkts + part),
1972 (pkts_n - part) * sizeof(struct rte_mbuf *));
1976 * Manage TX completions. This routine checks the CQ for
1977 * arrived CQEs, deduces the last accomplished WQE in SQ,
1978 * updates SQ producing index and frees all completed mbufs.
1981 * Pointer to TX queue structure.
1983 * Configured Tx offloads mask. It is fully defined at
1984 * compile time and may be used for optimization.
1986 * NOTE: not inlined intentionally, it makes tx_burst
1987 * routine smaller, simple and faster - from experiments.
1990 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
1991 unsigned int olx __rte_unused)
1993 bool update = false;
1997 volatile struct mlx5_wqe_cseg *cseg;
1998 volatile struct mlx5_cqe *cqe;
2001 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2002 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2003 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2004 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2005 /* No new CQEs in completion queue. */
2006 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2007 if (likely(update)) {
2008 /* Update the consumer index. */
2009 rte_compiler_barrier();
2011 rte_cpu_to_be_32(txq->cq_ci);
2015 /* Some error occurred, try to restart. */
2017 tail = mlx5_tx_error_cqe_handle
2018 (txq, (volatile struct mlx5_err_cqe *)cqe);
2020 /* Normal transmit completion. */
2023 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
2024 cseg = (volatile struct mlx5_wqe_cseg *)
2025 (txq->wqes + (txq->wqe_pi & txq->wqe_m));
2032 if (likely(tail != txq->elts_tail)) {
2033 /* Free data buffers from elts. */
2034 mlx5_tx_free_elts(txq, tail, olx);
2035 assert(tail == txq->elts_tail);
2042 * Check if the completion request flag should be set in the last WQE.
2043 * Both pushed mbufs and WQEs are monitored and the completion request
2044 * flag is set if any of thresholds is reached.
2047 * Pointer to TX queue structure.
2049 * Number of mbuf not stored yet in elts array.
2051 * Pointer to burst routine local context.
2053 * Configured Tx offloads mask. It is fully defined at
2054 * compile time and may be used for optimization.
2056 static __rte_always_inline void
2057 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2058 unsigned int n_mbuf,
2059 struct mlx5_txq_local *restrict loc,
2060 unsigned int olx __rte_unused)
2062 uint16_t head = txq->elts_head + n_mbuf;
2064 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2065 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres) {
2066 volatile struct mlx5_wqe *last = loc->wqe_last;
2068 txq->elts_comp = head;
2069 txq->wqe_comp = txq->wqe_ci;
2070 /* Request unconditional completion on last WQE. */
2071 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2072 MLX5_COMP_MODE_OFFSET);
2073 /* Save elts_head in unused "immediate" field of WQE. */
2074 last->cseg.misc = head;
2076 * A CQE slot must always be available. Count the
2077 * issued CEQ "always" request instead of production
2078 * index due to here can be CQE with errors and
2079 * difference with ci may become inconsistent.
2081 assert(txq->cqe_s > ++txq->cq_pi);
2086 * DPDK callback to check the status of a tx descriptor.
2091 * The index of the descriptor in the ring.
2094 * The status of the tx descriptor.
2097 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2099 struct mlx5_txq_data *restrict txq = tx_queue;
2102 mlx5_tx_handle_completion(txq, 0);
2103 used = txq->elts_head - txq->elts_tail;
2105 return RTE_ETH_TX_DESC_FULL;
2106 return RTE_ETH_TX_DESC_DONE;
2110 * Build the Control Segment with specified opcode:
2111 * - MLX5_OPCODE_SEND
2112 * - MLX5_OPCODE_ENHANCED_MPSW
2116 * Pointer to TX queue structure.
2118 * Pointer to burst routine local context.
2120 * Pointer to WQE to fill with built Control Segment.
2122 * Supposed length of WQE in segments.
2124 * SQ WQE opcode to put into Control Segment.
2126 * Configured Tx offloads mask. It is fully defined at
2127 * compile time and may be used for optimization.
2129 static __rte_always_inline void
2130 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2131 struct mlx5_txq_local *restrict loc __rte_unused,
2132 struct mlx5_wqe *restrict wqe,
2134 unsigned int opcode,
2135 unsigned int olx __rte_unused)
2137 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2139 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2140 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2141 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2142 MLX5_COMP_MODE_OFFSET);
2143 cs->misc = RTE_BE32(0);
2147 * Build the Ethernet Segment without inlined data.
2148 * Supports Software Parser, Checksums and VLAN
2149 * insertion Tx offload features.
2152 * Pointer to TX queue structure.
2154 * Pointer to burst routine local context.
2156 * Pointer to WQE to fill with built Ethernet Segment.
2158 * Configured Tx offloads mask. It is fully defined at
2159 * compile time and may be used for optimization.
2161 static __rte_always_inline void
2162 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2163 struct mlx5_txq_local *restrict loc,
2164 struct mlx5_wqe *restrict wqe,
2167 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2171 * Calculate and set check sum flags first, dword field
2172 * in segment may be shared with Software Parser flags.
2174 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2175 es->flags = rte_cpu_to_le_32(csum);
2177 * Calculate and set Software Parser offsets and flags.
2178 * These flags a set for custom UDP and IP tunnel packets.
2180 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2181 /* Fill metadata field if needed. */
2182 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2183 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2184 loc->mbuf->tx_metadata : 0 : 0;
2185 /* Engage VLAN tag insertion feature if requested. */
2186 if (MLX5_TXOFF_CONFIG(VLAN) &&
2187 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2189 * We should get here only if device support
2190 * this feature correctly.
2192 assert(txq->vlan_en);
2193 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2194 loc->mbuf->vlan_tci);
2196 es->inline_hdr = RTE_BE32(0);
2201 * Build the Ethernet Segment with minimal inlined data
2202 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2203 * used to fill the gap in single WQEBB WQEs.
2204 * Supports Software Parser, Checksums and VLAN
2205 * insertion Tx offload features.
2208 * Pointer to TX queue structure.
2210 * Pointer to burst routine local context.
2212 * Pointer to WQE to fill with built Ethernet Segment.
2214 * Length of VLAN tag insertion if any.
2216 * Configured Tx offloads mask. It is fully defined at
2217 * compile time and may be used for optimization.
2219 static __rte_always_inline void
2220 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2221 struct mlx5_txq_local *restrict loc,
2222 struct mlx5_wqe *restrict wqe,
2226 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2228 uint8_t *psrc, *pdst;
2231 * Calculate and set check sum flags first, dword field
2232 * in segment may be shared with Software Parser flags.
2234 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2235 es->flags = rte_cpu_to_le_32(csum);
2237 * Calculate and set Software Parser offsets and flags.
2238 * These flags a set for custom UDP and IP tunnel packets.
2240 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2241 /* Fill metadata field if needed. */
2242 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2243 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2244 loc->mbuf->tx_metadata : 0 : 0;
2245 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2247 sizeof(rte_v128u32_t)),
2248 "invalid Ethernet Segment data size");
2249 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2251 sizeof(struct rte_vlan_hdr) +
2252 2 * RTE_ETHER_ADDR_LEN),
2253 "invalid Ethernet Segment data size");
2254 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2255 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2256 es->inline_data = *(unaligned_uint16_t *)psrc;
2257 psrc += sizeof(uint16_t);
2258 pdst = (uint8_t *)(es + 1);
2259 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2260 /* Implement VLAN tag insertion as part inline data. */
2261 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2262 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2263 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2264 /* Insert VLAN ethertype + VLAN tag. */
2265 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2266 ((RTE_ETHER_TYPE_VLAN << 16) |
2267 loc->mbuf->vlan_tci);
2268 pdst += sizeof(struct rte_vlan_hdr);
2269 /* Copy the rest two bytes from packet data. */
2270 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2271 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2273 /* Fill the gap in the title WQEBB with inline data. */
2274 rte_mov16(pdst, psrc);
2279 * Build the Ethernet Segment with entire packet
2280 * data inlining. Checks the boundary of WQEBB and
2281 * ring buffer wrapping, supports Software Parser,
2282 * Checksums and VLAN insertion Tx offload features.
2285 * Pointer to TX queue structure.
2287 * Pointer to burst routine local context.
2289 * Pointer to WQE to fill with built Ethernet Segment.
2291 * Length of VLAN tag insertion if any.
2293 * Length of data to inline (VLAN included, if any).
2295 * TSO flag, set mss field from the packet.
2297 * Configured Tx offloads mask. It is fully defined at
2298 * compile time and may be used for optimization.
2301 * Pointer to the next Data Segment (aligned and wrapped around).
2303 static __rte_always_inline struct mlx5_wqe_dseg *
2304 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2305 struct mlx5_txq_local *restrict loc,
2306 struct mlx5_wqe *restrict wqe,
2312 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2314 uint8_t *psrc, *pdst;
2318 * Calculate and set check sum flags first, dword field
2319 * in segment may be shared with Software Parser flags.
2321 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2324 csum |= loc->mbuf->tso_segsz;
2325 es->flags = rte_cpu_to_be_32(csum);
2327 es->flags = rte_cpu_to_le_32(csum);
2330 * Calculate and set Software Parser offsets and flags.
2331 * These flags a set for custom UDP and IP tunnel packets.
2333 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2334 /* Fill metadata field if needed. */
2335 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2336 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2337 loc->mbuf->tx_metadata : 0 : 0;
2338 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2340 sizeof(rte_v128u32_t)),
2341 "invalid Ethernet Segment data size");
2342 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2344 sizeof(struct rte_vlan_hdr) +
2345 2 * RTE_ETHER_ADDR_LEN),
2346 "invalid Ethernet Segment data size");
2347 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2348 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2349 es->inline_data = *(unaligned_uint16_t *)psrc;
2350 psrc += sizeof(uint16_t);
2351 pdst = (uint8_t *)(es + 1);
2352 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2353 /* Implement VLAN tag insertion as part inline data. */
2354 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2355 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2356 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2357 /* Insert VLAN ethertype + VLAN tag. */
2358 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2359 ((RTE_ETHER_TYPE_VLAN << 16) |
2360 loc->mbuf->vlan_tci);
2361 pdst += sizeof(struct rte_vlan_hdr);
2362 /* Copy the rest two bytes from packet data. */
2363 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2364 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2365 psrc += sizeof(uint16_t);
2367 /* Fill the gap in the title WQEBB with inline data. */
2368 rte_mov16(pdst, psrc);
2369 psrc += sizeof(rte_v128u32_t);
2371 pdst = (uint8_t *)(es + 2);
2372 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2373 assert(pdst < (uint8_t *)txq->wqes_end);
2374 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2376 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2377 return (struct mlx5_wqe_dseg *)pdst;
2380 * The WQEBB space availability is checked by caller.
2381 * Here we should be aware of WQE ring buffer wraparound only.
2383 part = (uint8_t *)txq->wqes_end - pdst;
2384 part = RTE_MIN(part, inlen);
2386 rte_memcpy(pdst, psrc, part);
2388 if (likely(!inlen)) {
2390 * If return value is not used by the caller
2391 * the code below will be optimized out.
2394 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2395 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2396 pdst = (uint8_t *)txq->wqes;
2397 return (struct mlx5_wqe_dseg *)pdst;
2399 pdst = (uint8_t *)txq->wqes;
2406 * Copy data from chain of mbuf to the specified linear buffer.
2407 * Checksums and VLAN insertion Tx offload features. If data
2408 * from some mbuf copied completely this mbuf is freed. Local
2409 * structure is used to keep the byte stream state.
2412 * Pointer to the destination linear buffer.
2414 * Pointer to burst routine local context.
2416 * Length of data to be copied.
2418 * Configured Tx offloads mask. It is fully defined at
2419 * compile time and may be used for optimization.
2421 static __rte_always_inline void
2422 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2423 struct mlx5_txq_local *restrict loc,
2425 unsigned int olx __rte_unused)
2427 struct rte_mbuf *mbuf;
2428 unsigned int part, dlen;
2433 /* Allow zero length packets, must check first. */
2434 dlen = rte_pktmbuf_data_len(loc->mbuf);
2435 if (dlen <= loc->mbuf_off) {
2436 /* Exhausted packet, just free. */
2438 loc->mbuf = mbuf->next;
2439 rte_pktmbuf_free_seg(mbuf);
2441 assert(loc->mbuf_nseg > 1);
2446 dlen -= loc->mbuf_off;
2447 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2449 part = RTE_MIN(len, dlen);
2450 rte_memcpy(pdst, psrc, part);
2451 loc->mbuf_off += part;
2454 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2456 /* Exhausted packet, just free. */
2458 loc->mbuf = mbuf->next;
2459 rte_pktmbuf_free_seg(mbuf);
2461 assert(loc->mbuf_nseg >= 1);
2471 * Build the Ethernet Segment with inlined data from
2472 * multi-segment packet. Checks the boundary of WQEBB
2473 * and ring buffer wrapping, supports Software Parser,
2474 * Checksums and VLAN insertion Tx offload features.
2477 * Pointer to TX queue structure.
2479 * Pointer to burst routine local context.
2481 * Pointer to WQE to fill with built Ethernet Segment.
2483 * Length of VLAN tag insertion if any.
2485 * Length of data to inline (VLAN included, if any).
2487 * TSO flag, set mss field from the packet.
2489 * Configured Tx offloads mask. It is fully defined at
2490 * compile time and may be used for optimization.
2493 * Pointer to the next Data Segment (aligned and
2494 * possible NOT wrapped around - caller should do
2495 * wrapping check on its own).
2497 static __rte_always_inline struct mlx5_wqe_dseg *
2498 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2499 struct mlx5_txq_local *restrict loc,
2500 struct mlx5_wqe *restrict wqe,
2506 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2512 * Calculate and set check sum flags first, uint32_t field
2513 * in segment may be shared with Software Parser flags.
2515 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2518 csum |= loc->mbuf->tso_segsz;
2519 es->flags = rte_cpu_to_be_32(csum);
2521 es->flags = rte_cpu_to_le_32(csum);
2524 * Calculate and set Software Parser offsets and flags.
2525 * These flags a set for custom UDP and IP tunnel packets.
2527 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2528 /* Fill metadata field if needed. */
2529 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2530 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2531 loc->mbuf->tx_metadata : 0 : 0;
2532 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2534 sizeof(rte_v128u32_t)),
2535 "invalid Ethernet Segment data size");
2536 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2538 sizeof(struct rte_vlan_hdr) +
2539 2 * RTE_ETHER_ADDR_LEN),
2540 "invalid Ethernet Segment data size");
2541 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
2542 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2543 pdst = (uint8_t *)&es->inline_data;
2544 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2545 /* Implement VLAN tag insertion as part inline data. */
2546 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2547 pdst += 2 * RTE_ETHER_ADDR_LEN;
2548 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2549 ((RTE_ETHER_TYPE_VLAN << 16) |
2550 loc->mbuf->vlan_tci);
2551 pdst += sizeof(struct rte_vlan_hdr);
2552 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2554 assert(pdst < (uint8_t *)txq->wqes_end);
2556 * The WQEBB space availability is checked by caller.
2557 * Here we should be aware of WQE ring buffer wraparound only.
2559 part = (uint8_t *)txq->wqes_end - pdst;
2560 part = RTE_MIN(part, inlen);
2563 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2565 if (likely(!inlen)) {
2567 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2568 return (struct mlx5_wqe_dseg *)pdst;
2570 pdst = (uint8_t *)txq->wqes;
2576 * Build the Data Segment of pointer type.
2579 * Pointer to TX queue structure.
2581 * Pointer to burst routine local context.
2583 * Pointer to WQE to fill with built Data Segment.
2585 * Data buffer to point.
2587 * Data buffer length.
2589 * Configured Tx offloads mask. It is fully defined at
2590 * compile time and may be used for optimization.
2592 static __rte_always_inline void
2593 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2594 struct mlx5_txq_local *restrict loc,
2595 struct mlx5_wqe_dseg *restrict dseg,
2598 unsigned int olx __rte_unused)
2602 dseg->bcount = rte_cpu_to_be_32(len);
2603 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2604 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2608 * Build the Data Segment of pointer type or inline
2609 * if data length is less than buffer in minimal
2610 * Data Segment size.
2613 * Pointer to TX queue structure.
2615 * Pointer to burst routine local context.
2617 * Pointer to WQE to fill with built Data Segment.
2619 * Data buffer to point.
2621 * Data buffer length.
2623 * Configured Tx offloads mask. It is fully defined at
2624 * compile time and may be used for optimization.
2626 static __rte_always_inline void
2627 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2628 struct mlx5_txq_local *restrict loc,
2629 struct mlx5_wqe_dseg *restrict dseg,
2632 unsigned int olx __rte_unused)
2638 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2639 dseg->bcount = rte_cpu_to_be_32(len);
2640 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2641 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2645 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2646 /* Unrolled implementation of generic rte_memcpy. */
2647 dst = (uintptr_t)&dseg->inline_data[0];
2648 src = (uintptr_t)buf;
2649 #ifdef RTE_ARCH_STRICT_ALIGN
2650 memcpy(dst, src, len);
2653 *(uint64_t *)dst = *(uint64_t *)src;
2654 dst += sizeof(uint64_t);
2655 src += sizeof(uint64_t);
2658 *(uint32_t *)dst = *(uint32_t *)src;
2659 dst += sizeof(uint32_t);
2660 src += sizeof(uint32_t);
2663 *(uint16_t *)dst = *(uint16_t *)src;
2664 dst += sizeof(uint16_t);
2665 src += sizeof(uint16_t);
2668 *(uint8_t *)dst = *(uint8_t *)src;
2673 * Build the Data Segment of inlined data from single
2674 * segment packet, no VLAN insertion.
2677 * Pointer to TX queue structure.
2679 * Pointer to burst routine local context.
2681 * Pointer to WQE to fill with built Data Segment.
2683 * Data buffer to point.
2685 * Data buffer length.
2687 * Configured Tx offloads mask. It is fully defined at
2688 * compile time and may be used for optimization.
2691 * Pointer to the next Data Segment after inlined data.
2692 * Ring buffer wraparound check is needed. We do not
2693 * do it here because it may not be needed for the
2694 * last packet in the eMPW session.
2696 static __rte_always_inline struct mlx5_wqe_dseg *
2697 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2698 struct mlx5_txq_local *restrict loc __rte_unused,
2699 struct mlx5_wqe_dseg *restrict dseg,
2702 unsigned int olx __rte_unused)
2707 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2708 pdst = &dseg->inline_data[0];
2710 * The WQEBB space availability is checked by caller.
2711 * Here we should be aware of WQE ring buffer wraparound only.
2713 part = (uint8_t *)txq->wqes_end - pdst;
2714 part = RTE_MIN(part, len);
2716 rte_memcpy(pdst, buf, part);
2720 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2721 /* Note: no final wraparound check here. */
2722 return (struct mlx5_wqe_dseg *)pdst;
2724 pdst = (uint8_t *)txq->wqes;
2731 * Build the Data Segment of inlined data from single
2732 * segment packet with VLAN insertion.
2735 * Pointer to TX queue structure.
2737 * Pointer to burst routine local context.
2739 * Pointer to the dseg fill with built Data Segment.
2741 * Data buffer to point.
2743 * Data buffer length.
2745 * Configured Tx offloads mask. It is fully defined at
2746 * compile time and may be used for optimization.
2749 * Pointer to the next Data Segment after inlined data.
2750 * Ring buffer wraparound check is needed.
2752 static __rte_always_inline struct mlx5_wqe_dseg *
2753 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2754 struct mlx5_txq_local *restrict loc __rte_unused,
2755 struct mlx5_wqe_dseg *restrict dseg,
2758 unsigned int olx __rte_unused)
2764 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2765 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2766 (2 * RTE_ETHER_ADDR_LEN),
2767 "invalid Data Segment data size");
2768 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2769 MLX5_ETH_WQE_DATA_INLINE);
2770 pdst = &dseg->inline_data[0];
2771 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2772 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2773 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2774 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2775 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2776 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2777 loc->mbuf->vlan_tci);
2778 pdst += sizeof(struct rte_vlan_hdr);
2779 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2780 pdst = (uint8_t *)txq->wqes;
2782 * The WQEBB space availability is checked by caller.
2783 * Here we should be aware of WQE ring buffer wraparound only.
2785 part = (uint8_t *)txq->wqes_end - pdst;
2786 part = RTE_MIN(part, len);
2788 rte_memcpy(pdst, buf, part);
2792 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2793 /* Note: no final wraparound check here. */
2794 return (struct mlx5_wqe_dseg *)pdst;
2796 pdst = (uint8_t *)txq->wqes;
2803 * Build the Ethernet Segment with optionally inlined data with
2804 * VLAN insertion and following Data Segments (if any) from
2805 * multi-segment packet. Used by ordinary send and TSO.
2808 * Pointer to TX queue structure.
2810 * Pointer to burst routine local context.
2812 * Pointer to WQE to fill with built Ethernet/Data Segments.
2814 * Length of VLAN header to insert, 0 means no VLAN insertion.
2816 * Data length to inline. For TSO this parameter specifies
2817 * exact value, for ordinary send routine can be aligned by
2818 * caller to provide better WQE space saving and data buffer
2819 * start address alignment. This length includes VLAN header
2822 * Zero means ordinary send, inlined data can be extended,
2823 * otherwise this is TSO, inlined data length is fixed.
2825 * Configured Tx offloads mask. It is fully defined at
2826 * compile time and may be used for optimization.
2829 * Actual size of built WQE in segments.
2831 static __rte_always_inline unsigned int
2832 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2833 struct mlx5_txq_local *restrict loc,
2834 struct mlx5_wqe *restrict wqe,
2838 unsigned int olx __rte_unused)
2840 struct mlx5_wqe_dseg *restrict dseg;
2843 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2844 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2847 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2848 if (!loc->mbuf_nseg)
2851 * There are still some mbuf remaining, not inlined.
2852 * The first mbuf may be partially inlined and we
2853 * must process the possible non-zero data offset.
2855 if (loc->mbuf_off) {
2860 * Exhausted packets must be dropped before.
2861 * Non-zero offset means there are some data
2862 * remained in the packet.
2864 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2865 assert(rte_pktmbuf_data_len(loc->mbuf));
2866 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2868 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2870 * Build the pointer/minimal data Data Segment.
2871 * Do ring buffer wrapping check in advance.
2873 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2874 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2875 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2876 /* Store the mbuf to be freed on completion. */
2877 assert(loc->elts_free);
2878 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2881 if (--loc->mbuf_nseg == 0)
2883 loc->mbuf = loc->mbuf->next;
2887 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2888 struct rte_mbuf *mbuf;
2890 /* Zero length segment found, just skip. */
2892 loc->mbuf = loc->mbuf->next;
2893 rte_pktmbuf_free_seg(mbuf);
2894 if (--loc->mbuf_nseg == 0)
2897 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2898 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2901 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2902 rte_pktmbuf_data_len(loc->mbuf), olx);
2903 assert(loc->elts_free);
2904 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2907 if (--loc->mbuf_nseg == 0)
2909 loc->mbuf = loc->mbuf->next;
2914 /* Calculate actual segments used from the dseg pointer. */
2915 if ((uintptr_t)wqe < (uintptr_t)dseg)
2916 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
2918 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
2919 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
2924 * Tx one packet function for multi-segment TSO. Supports all
2925 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
2926 * sends one packet per WQE.
2928 * This routine is responsible for storing processed mbuf
2929 * into elts ring buffer and update elts_head.
2932 * Pointer to TX queue structure.
2934 * Pointer to burst routine local context.
2936 * Configured Tx offloads mask. It is fully defined at
2937 * compile time and may be used for optimization.
2940 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
2941 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
2942 * Local context variables partially updated.
2944 static __rte_always_inline enum mlx5_txcmp_code
2945 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
2946 struct mlx5_txq_local *restrict loc,
2949 struct mlx5_wqe *restrict wqe;
2950 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
2953 * Calculate data length to be inlined to estimate
2954 * the required space in WQE ring buffer.
2956 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
2957 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
2958 vlan = sizeof(struct rte_vlan_hdr);
2959 inlen = loc->mbuf->l2_len + vlan +
2960 loc->mbuf->l3_len + loc->mbuf->l4_len;
2961 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
2962 return MLX5_TXCMP_CODE_ERROR;
2963 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
2964 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
2965 /* Packet must contain all TSO headers. */
2966 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
2967 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
2968 inlen > (dlen + vlan)))
2969 return MLX5_TXCMP_CODE_ERROR;
2970 assert(inlen >= txq->inlen_mode);
2972 * Check whether there are enough free WQEBBs:
2974 * - Ethernet Segment
2975 * - First Segment of inlined Ethernet data
2976 * - ... data continued ...
2977 * - Data Segments of pointer/min inline type
2979 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
2980 MLX5_ESEG_MIN_INLINE_SIZE +
2982 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
2983 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
2984 return MLX5_TXCMP_CODE_EXIT;
2985 /* Check for maximal WQE size. */
2986 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
2987 return MLX5_TXCMP_CODE_ERROR;
2988 #ifdef MLX5_PMD_SOFT_COUNTERS
2989 /* Update sent data bytes/packets counters. */
2990 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
2991 loc->mbuf->tso_segsz;
2993 * One will be added for mbuf itself
2994 * at the end of the mlx5_tx_burst from
2995 * loc->pkts_sent field.
2998 txq->stats.opackets += ntcp;
2999 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3001 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3002 loc->wqe_last = wqe;
3003 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3004 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3005 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3006 txq->wqe_ci += (ds + 3) / 4;
3007 loc->wqe_free -= (ds + 3) / 4;
3008 return MLX5_TXCMP_CODE_MULTI;
3012 * Tx one packet function for multi-segment SEND. Supports all
3013 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3014 * sends one packet per WQE, without any data inlining in
3017 * This routine is responsible for storing processed mbuf
3018 * into elts ring buffer and update elts_head.
3021 * Pointer to TX queue structure.
3023 * Pointer to burst routine local context.
3025 * Configured Tx offloads mask. It is fully defined at
3026 * compile time and may be used for optimization.
3029 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3030 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3031 * Local context variables partially updated.
3033 static __rte_always_inline enum mlx5_txcmp_code
3034 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3035 struct mlx5_txq_local *restrict loc,
3038 struct mlx5_wqe_dseg *restrict dseg;
3039 struct mlx5_wqe *restrict wqe;
3040 unsigned int ds, nseg;
3042 assert(NB_SEGS(loc->mbuf) > 1);
3044 * No inline at all, it means the CPU cycles saving
3045 * is prioritized at configuration, we should not
3046 * copy any packet data to WQE.
3048 nseg = NB_SEGS(loc->mbuf);
3050 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3051 return MLX5_TXCMP_CODE_EXIT;
3052 /* Check for maximal WQE size. */
3053 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3054 return MLX5_TXCMP_CODE_ERROR;
3056 * Some Tx offloads may cause an error if
3057 * packet is not long enough, check against
3058 * assumed minimal length.
3060 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3061 return MLX5_TXCMP_CODE_ERROR;
3062 #ifdef MLX5_PMD_SOFT_COUNTERS
3063 /* Update sent data bytes counter. */
3064 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3065 if (MLX5_TXOFF_CONFIG(VLAN) &&
3066 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3067 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3070 * SEND WQE, one WQEBB:
3071 * - Control Segment, SEND opcode
3072 * - Ethernet Segment, optional VLAN, no inline
3073 * - Data Segments, pointer only type
3075 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3076 loc->wqe_last = wqe;
3077 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3078 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3079 dseg = &wqe->dseg[0];
3081 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3082 struct rte_mbuf *mbuf;
3085 * Zero length segment found, have to
3086 * correct total size of WQE in segments.
3087 * It is supposed to be rare occasion, so
3088 * in normal case (no zero length segments)
3089 * we avoid extra writing to the Control
3093 wqe->cseg.sq_ds -= RTE_BE32(1);
3095 loc->mbuf = mbuf->next;
3096 rte_pktmbuf_free_seg(mbuf);
3102 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3103 rte_pktmbuf_data_len(loc->mbuf), olx);
3104 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3109 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3110 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3111 loc->mbuf = loc->mbuf->next;
3114 txq->wqe_ci += (ds + 3) / 4;
3115 loc->wqe_free -= (ds + 3) / 4;
3116 return MLX5_TXCMP_CODE_MULTI;
3120 * Tx one packet function for multi-segment SEND. Supports all
3121 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3122 * sends one packet per WQE, with data inlining in
3123 * Ethernet Segment and minimal Data Segments.
3125 * This routine is responsible for storing processed mbuf
3126 * into elts ring buffer and update elts_head.
3129 * Pointer to TX queue structure.
3131 * Pointer to burst routine local context.
3133 * Configured Tx offloads mask. It is fully defined at
3134 * compile time and may be used for optimization.
3137 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3138 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3139 * Local context variables partially updated.
3141 static __rte_always_inline enum mlx5_txcmp_code
3142 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3143 struct mlx5_txq_local *restrict loc,
3146 struct mlx5_wqe *restrict wqe;
3147 unsigned int ds, inlen, dlen, vlan = 0;
3149 assert(MLX5_TXOFF_CONFIG(INLINE));
3150 assert(NB_SEGS(loc->mbuf) > 1);
3152 * First calculate data length to be inlined
3153 * to estimate the required space for WQE.
3155 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3156 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3157 vlan = sizeof(struct rte_vlan_hdr);
3158 inlen = dlen + vlan;
3159 /* Check against minimal length. */
3160 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3161 return MLX5_TXCMP_CODE_ERROR;
3162 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3163 if (inlen > txq->inlen_send) {
3164 struct rte_mbuf *mbuf;
3169 * Packet length exceeds the allowed inline
3170 * data length, check whether the minimal
3171 * inlining is required.
3173 if (txq->inlen_mode) {
3174 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3175 assert(txq->inlen_mode <= txq->inlen_send);
3176 inlen = txq->inlen_mode;
3178 if (!vlan || txq->vlan_en) {
3180 * VLAN insertion will be done inside by HW.
3181 * It is not utmost effective - VLAN flag is
3182 * checked twice, but we should proceed the
3183 * inlining length correctly and take into
3184 * account the VLAN header being inserted.
3186 return mlx5_tx_packet_multi_send
3189 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3192 * Now we know the minimal amount of data is requested
3193 * to inline. Check whether we should inline the buffers
3194 * from the chain beginning to eliminate some mbufs.
3197 nxlen = rte_pktmbuf_data_len(mbuf);
3198 if (unlikely(nxlen <= txq->inlen_send)) {
3199 /* We can inline first mbuf at least. */
3200 if (nxlen < inlen) {
3203 /* Scan mbufs till inlen filled. */
3208 nxlen = rte_pktmbuf_data_len(mbuf);
3210 } while (unlikely(nxlen < inlen));
3211 if (unlikely(nxlen > txq->inlen_send)) {
3212 /* We cannot inline entire mbuf. */
3213 smlen = inlen - smlen;
3214 start = rte_pktmbuf_mtod_offset
3215 (mbuf, uintptr_t, smlen);
3222 /* There should be not end of packet. */
3224 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3225 } while (unlikely(nxlen < txq->inlen_send));
3227 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3229 * Check whether we can do inline to align start
3230 * address of data buffer to cacheline.
3233 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3234 if (unlikely(start)) {
3236 if (start <= txq->inlen_send)
3241 * Check whether there are enough free WQEBBs:
3243 * - Ethernet Segment
3244 * - First Segment of inlined Ethernet data
3245 * - ... data continued ...
3246 * - Data Segments of pointer/min inline type
3248 * Estimate the number of Data Segments conservatively,
3249 * supposing no any mbufs is being freed during inlining.
3251 assert(inlen <= txq->inlen_send);
3252 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3253 MLX5_ESEG_MIN_INLINE_SIZE +
3255 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3256 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3257 return MLX5_TXCMP_CODE_EXIT;
3258 /* Check for maximal WQE size. */
3259 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3260 return MLX5_TXCMP_CODE_ERROR;
3261 #ifdef MLX5_PMD_SOFT_COUNTERS
3262 /* Update sent data bytes/packets counters. */
3263 txq->stats.obytes += dlen + vlan;
3265 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3266 loc->wqe_last = wqe;
3267 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3268 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3269 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3270 txq->wqe_ci += (ds + 3) / 4;
3271 loc->wqe_free -= (ds + 3) / 4;
3272 return MLX5_TXCMP_CODE_MULTI;
3276 * Tx burst function for multi-segment packets. Supports all
3277 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3278 * sends one packet per WQE. Function stops sending if it
3279 * encounters the single-segment packet.
3281 * This routine is responsible for storing processed mbuf
3282 * into elts ring buffer and update elts_head.
3285 * Pointer to TX queue structure.
3287 * Packets to transmit.
3289 * Number of packets in array.
3291 * Pointer to burst routine local context.
3293 * Configured Tx offloads mask. It is fully defined at
3294 * compile time and may be used for optimization.
3297 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3298 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3299 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3300 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3301 * Local context variables updated.
3303 static __rte_always_inline enum mlx5_txcmp_code
3304 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3305 struct rte_mbuf **restrict pkts,
3306 unsigned int pkts_n,
3307 struct mlx5_txq_local *restrict loc,
3310 assert(loc->elts_free && loc->wqe_free);
3311 assert(pkts_n > loc->pkts_sent);
3312 pkts += loc->pkts_sent + 1;
3313 pkts_n -= loc->pkts_sent;
3315 enum mlx5_txcmp_code ret;
3317 assert(NB_SEGS(loc->mbuf) > 1);
3319 * Estimate the number of free elts quickly but
3320 * conservatively. Some segment may be fully inlined
3321 * and freed, ignore this here - precise estimation
3324 if (loc->elts_free < NB_SEGS(loc->mbuf))
3325 return MLX5_TXCMP_CODE_EXIT;
3326 if (MLX5_TXOFF_CONFIG(TSO) &&
3327 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3328 /* Proceed with multi-segment TSO. */
3329 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3330 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3331 /* Proceed with multi-segment SEND with inlining. */
3332 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3334 /* Proceed with multi-segment SEND w/o inlining. */
3335 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3337 if (ret == MLX5_TXCMP_CODE_EXIT)
3338 return MLX5_TXCMP_CODE_EXIT;
3339 if (ret == MLX5_TXCMP_CODE_ERROR)
3340 return MLX5_TXCMP_CODE_ERROR;
3341 /* WQE is built, go to the next packet. */
3344 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3345 return MLX5_TXCMP_CODE_EXIT;
3346 loc->mbuf = *pkts++;
3348 rte_prefetch0(*pkts);
3349 if (likely(NB_SEGS(loc->mbuf) > 1))
3351 /* Here ends the series of multi-segment packets. */
3352 if (MLX5_TXOFF_CONFIG(TSO) &&
3353 unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3354 return MLX5_TXCMP_CODE_TSO;
3355 return MLX5_TXCMP_CODE_SINGLE;
3361 * Tx burst function for single-segment packets with TSO.
3362 * Supports all types of Tx offloads, except multi-packets.
3363 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3364 * Function stops sending if it encounters the multi-segment
3365 * packet or packet without TSO requested.
3367 * The routine is responsible for storing processed mbuf
3368 * into elts ring buffer and update elts_head if inline
3369 * offloads is requested due to possible early freeing
3370 * of the inlined mbufs (can not store pkts array in elts
3374 * Pointer to TX queue structure.
3376 * Packets to transmit.
3378 * Number of packets in array.
3380 * Pointer to burst routine local context.
3382 * Configured Tx offloads mask. It is fully defined at
3383 * compile time and may be used for optimization.
3386 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3387 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3388 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3389 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3390 * Local context variables updated.
3392 static __rte_always_inline enum mlx5_txcmp_code
3393 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3394 struct rte_mbuf **restrict pkts,
3395 unsigned int pkts_n,
3396 struct mlx5_txq_local *restrict loc,
3399 assert(loc->elts_free && loc->wqe_free);
3400 assert(pkts_n > loc->pkts_sent);
3401 pkts += loc->pkts_sent + 1;
3402 pkts_n -= loc->pkts_sent;
3404 struct mlx5_wqe_dseg *restrict dseg;
3405 struct mlx5_wqe *restrict wqe;
3406 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3409 assert(NB_SEGS(loc->mbuf) == 1);
3410 dlen = rte_pktmbuf_data_len(loc->mbuf);
3411 if (MLX5_TXOFF_CONFIG(VLAN) &&
3412 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3413 vlan = sizeof(struct rte_vlan_hdr);
3416 * First calculate the WQE size to check
3417 * whether we have enough space in ring buffer.
3419 hlen = loc->mbuf->l2_len + vlan +
3420 loc->mbuf->l3_len + loc->mbuf->l4_len;
3421 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3422 return MLX5_TXCMP_CODE_ERROR;
3423 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3424 hlen += loc->mbuf->outer_l2_len +
3425 loc->mbuf->outer_l3_len;
3426 /* Segment must contain all TSO headers. */
3427 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3428 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3429 hlen > (dlen + vlan)))
3430 return MLX5_TXCMP_CODE_ERROR;
3432 * Check whether there are enough free WQEBBs:
3434 * - Ethernet Segment
3435 * - First Segment of inlined Ethernet data
3436 * - ... data continued ...
3437 * - Finishing Data Segment of pointer type
3439 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3440 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3441 if (loc->wqe_free < ((ds + 3) / 4))
3442 return MLX5_TXCMP_CODE_EXIT;
3443 #ifdef MLX5_PMD_SOFT_COUNTERS
3444 /* Update sent data bytes/packets counters. */
3445 ntcp = (dlen + vlan - hlen +
3446 loc->mbuf->tso_segsz - 1) /
3447 loc->mbuf->tso_segsz;
3449 * One will be added for mbuf itself at the end
3450 * of the mlx5_tx_burst from loc->pkts_sent field.
3453 txq->stats.opackets += ntcp;
3454 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3457 * Build the TSO WQE:
3459 * - Ethernet Segment with hlen bytes inlined
3460 * - Data Segment of pointer type
3462 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3463 loc->wqe_last = wqe;
3464 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3465 MLX5_OPCODE_TSO, olx);
3466 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3467 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3468 dlen -= hlen - vlan;
3469 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3471 * WQE is built, update the loop parameters
3472 * and go to the next packet.
3474 txq->wqe_ci += (ds + 3) / 4;
3475 loc->wqe_free -= (ds + 3) / 4;
3476 if (MLX5_TXOFF_CONFIG(INLINE))
3477 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3481 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3482 return MLX5_TXCMP_CODE_EXIT;
3483 loc->mbuf = *pkts++;
3485 rte_prefetch0(*pkts);
3486 if (MLX5_TXOFF_CONFIG(MULTI) &&
3487 unlikely(NB_SEGS(loc->mbuf) > 1))
3488 return MLX5_TXCMP_CODE_MULTI;
3489 if (unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3490 return MLX5_TXCMP_CODE_SINGLE;
3491 /* Continue with the next TSO packet. */
3497 * Analyze the packet and select the best method to send.
3500 * Pointer to TX queue structure.
3502 * Pointer to burst routine local context.
3504 * Configured Tx offloads mask. It is fully defined at
3505 * compile time and may be used for optimization.
3507 * The predefined flag whether do complete check for
3508 * multi-segment packets and TSO.
3511 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3512 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3513 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3514 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3516 static __rte_always_inline enum mlx5_txcmp_code
3517 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3518 struct mlx5_txq_local *restrict loc,
3522 /* Check for multi-segment packet. */
3524 MLX5_TXOFF_CONFIG(MULTI) &&
3525 unlikely(NB_SEGS(loc->mbuf) > 1))
3526 return MLX5_TXCMP_CODE_MULTI;
3527 /* Check for TSO packet. */
3529 MLX5_TXOFF_CONFIG(TSO) &&
3530 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3531 return MLX5_TXCMP_CODE_TSO;
3532 /* Check if eMPW is enabled at all. */
3533 if (!MLX5_TXOFF_CONFIG(EMPW))
3534 return MLX5_TXCMP_CODE_SINGLE;
3535 /* Check if eMPW can be engaged. */
3536 if (MLX5_TXOFF_CONFIG(VLAN) &&
3537 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3538 (!MLX5_TXOFF_CONFIG(INLINE) ||
3539 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3540 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3542 * eMPW does not support VLAN insertion offload,
3543 * we have to inline the entire packet but
3544 * packet is too long for inlining.
3546 return MLX5_TXCMP_CODE_SINGLE;
3548 return MLX5_TXCMP_CODE_EMPW;
3552 * Check the next packet attributes to match with the eMPW batch ones.
3555 * Pointer to TX queue structure.
3557 * Pointer to Ethernet Segment of eMPW batch.
3559 * Pointer to burst routine local context.
3561 * Configured Tx offloads mask. It is fully defined at
3562 * compile time and may be used for optimization.
3565 * true - packet match with eMPW batch attributes.
3566 * false - no match, eMPW should be restarted.
3568 static __rte_always_inline bool
3569 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3570 struct mlx5_wqe_eseg *restrict es,
3571 struct mlx5_txq_local *restrict loc,
3574 uint8_t swp_flags = 0;
3576 /* Compare the checksum flags, if any. */
3577 if (MLX5_TXOFF_CONFIG(CSUM) &&
3578 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3580 /* Compare the Software Parser offsets and flags. */
3581 if (MLX5_TXOFF_CONFIG(SWP) &&
3582 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3583 es->swp_flags != swp_flags))
3585 /* Fill metadata field if needed. */
3586 if (MLX5_TXOFF_CONFIG(METADATA) &&
3587 es->metadata != (loc->mbuf->ol_flags & PKT_TX_METADATA ?
3588 loc->mbuf->tx_metadata : 0))
3590 /* There must be no VLAN packets in eMPW loop. */
3591 if (MLX5_TXOFF_CONFIG(VLAN))
3592 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3597 * Update send loop variables and WQE for eMPW loop
3598 * without data inlining. Number of Data Segments is
3599 * equal to the number of sent packets.
3602 * Pointer to TX queue structure.
3604 * Pointer to burst routine local context.
3606 * Number of packets/Data Segments/Packets.
3608 * Accumulated statistics, bytes sent
3610 * Configured Tx offloads mask. It is fully defined at
3611 * compile time and may be used for optimization.
3614 * true - packet match with eMPW batch attributes.
3615 * false - no match, eMPW should be restarted.
3617 static __rte_always_inline void
3618 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3619 struct mlx5_txq_local *restrict loc,
3622 unsigned int olx __rte_unused)
3624 assert(!MLX5_TXOFF_CONFIG(INLINE));
3625 #ifdef MLX5_PMD_SOFT_COUNTERS
3626 /* Update sent data bytes counter. */
3627 txq->stats.obytes += slen;
3631 loc->elts_free -= ds;
3632 loc->pkts_sent += ds;
3634 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3635 txq->wqe_ci += (ds + 3) / 4;
3636 loc->wqe_free -= (ds + 3) / 4;
3640 * Update send loop variables and WQE for eMPW loop
3641 * with data inlining. Gets the size of pushed descriptors
3642 * and data to the WQE.
3645 * Pointer to TX queue structure.
3647 * Pointer to burst routine local context.
3649 * Total size of descriptor/data in bytes.
3651 * Accumulated statistics, data bytes sent.
3653 * Configured Tx offloads mask. It is fully defined at
3654 * compile time and may be used for optimization.
3657 * true - packet match with eMPW batch attributes.
3658 * false - no match, eMPW should be restarted.
3660 static __rte_always_inline void
3661 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3662 struct mlx5_txq_local *restrict loc,
3665 unsigned int olx __rte_unused)
3667 assert(MLX5_TXOFF_CONFIG(INLINE));
3668 assert((len % MLX5_WSEG_SIZE) == 0);
3669 #ifdef MLX5_PMD_SOFT_COUNTERS
3670 /* Update sent data bytes counter. */
3671 txq->stats.obytes += slen;
3675 len = len / MLX5_WSEG_SIZE + 2;
3676 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3677 txq->wqe_ci += (len + 3) / 4;
3678 loc->wqe_free -= (len + 3) / 4;
3682 * The set of Tx burst functions for single-segment packets
3683 * without TSO and with Multi-Packet Writing feature support.
3684 * Supports all types of Tx offloads, except multi-packets
3687 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3688 * as many packet per WQE as it can. If eMPW is not configured
3689 * or packet can not be sent with eMPW (VLAN insertion) the
3690 * ordinary SEND opcode is used and only one packet placed
3693 * Functions stop sending if it encounters the multi-segment
3694 * packet or packet with TSO requested.
3696 * The routines are responsible for storing processed mbuf
3697 * into elts ring buffer and update elts_head if inlining
3698 * offload is requested. Otherwise the copying mbufs to elts
3699 * can be postponed and completed at the end of burst routine.
3702 * Pointer to TX queue structure.
3704 * Packets to transmit.
3706 * Number of packets in array.
3708 * Pointer to burst routine local context.
3710 * Configured Tx offloads mask. It is fully defined at
3711 * compile time and may be used for optimization.
3714 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3715 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3716 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3717 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3718 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3719 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3721 * Local context variables updated.
3724 * The routine sends packets with MLX5_OPCODE_EMPW
3725 * without inlining, this is dedicated optimized branch.
3726 * No VLAN insertion is supported.
3728 static __rte_always_inline enum mlx5_txcmp_code
3729 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3730 struct rte_mbuf **restrict pkts,
3731 unsigned int pkts_n,
3732 struct mlx5_txq_local *restrict loc,
3736 * Subroutine is the part of mlx5_tx_burst_single()
3737 * and sends single-segment packet with eMPW opcode
3738 * without data inlining.
3740 assert(!MLX5_TXOFF_CONFIG(INLINE));
3741 assert(MLX5_TXOFF_CONFIG(EMPW));
3742 assert(loc->elts_free && loc->wqe_free);
3743 assert(pkts_n > loc->pkts_sent);
3744 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3745 pkts += loc->pkts_sent + 1;
3746 pkts_n -= loc->pkts_sent;
3748 struct mlx5_wqe_dseg *restrict dseg;
3749 struct mlx5_wqe_eseg *restrict eseg;
3750 enum mlx5_txcmp_code ret;
3751 unsigned int part, loop;
3752 unsigned int slen = 0;
3755 part = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3756 if (unlikely(loc->elts_free < part)) {
3757 /* We have no enough elts to save all mbufs. */
3758 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3759 return MLX5_TXCMP_CODE_EXIT;
3760 /* But we still able to send at least minimal eMPW. */
3761 part = loc->elts_free;
3763 /* Check whether we have enough WQEs */
3764 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3765 if (unlikely(loc->wqe_free <
3766 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3767 return MLX5_TXCMP_CODE_EXIT;
3768 part = (loc->wqe_free * 4) - 2;
3770 if (likely(part > 1))
3771 rte_prefetch0(*pkts);
3772 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3774 * Build eMPW title WQEBB:
3775 * - Control Segment, eMPW opcode
3776 * - Ethernet Segment, no inline
3778 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3779 MLX5_OPCODE_ENHANCED_MPSW, olx);
3780 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3781 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3782 eseg = &loc->wqe_last->eseg;
3783 dseg = &loc->wqe_last->dseg[0];
3786 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3787 #ifdef MLX5_PMD_SOFT_COUNTERS
3788 /* Update sent data bytes counter. */
3793 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3795 if (unlikely(--loop == 0))
3797 loc->mbuf = *pkts++;
3798 if (likely(loop > 1))
3799 rte_prefetch0(*pkts);
3800 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3802 * Unroll the completion code to avoid
3803 * returning variable value - it results in
3804 * unoptimized sequent checking in caller.
3806 if (ret == MLX5_TXCMP_CODE_MULTI) {
3808 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3809 if (unlikely(!loc->elts_free ||
3811 return MLX5_TXCMP_CODE_EXIT;
3812 return MLX5_TXCMP_CODE_MULTI;
3814 if (ret == MLX5_TXCMP_CODE_TSO) {
3816 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3817 if (unlikely(!loc->elts_free ||
3819 return MLX5_TXCMP_CODE_EXIT;
3820 return MLX5_TXCMP_CODE_TSO;
3822 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3824 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3825 if (unlikely(!loc->elts_free ||
3827 return MLX5_TXCMP_CODE_EXIT;
3828 return MLX5_TXCMP_CODE_SINGLE;
3830 if (ret != MLX5_TXCMP_CODE_EMPW) {
3833 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3834 return MLX5_TXCMP_CODE_ERROR;
3837 * Check whether packet parameters coincide
3838 * within assumed eMPW batch:
3839 * - check sum settings
3841 * - software parser settings
3843 if (!mlx5_tx_match_empw(txq, eseg, loc, olx)) {
3846 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3847 if (unlikely(!loc->elts_free ||
3849 return MLX5_TXCMP_CODE_EXIT;
3852 /* Packet attributes match, continue the same eMPW. */
3854 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3855 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3857 /* eMPW is built successfully, update loop parameters. */
3859 assert(pkts_n >= part);
3860 #ifdef MLX5_PMD_SOFT_COUNTERS
3861 /* Update sent data bytes counter. */
3862 txq->stats.obytes += slen;
3864 loc->elts_free -= part;
3865 loc->pkts_sent += part;
3866 txq->wqe_ci += (2 + part + 3) / 4;
3867 loc->wqe_free -= (2 + part + 3) / 4;
3869 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3870 return MLX5_TXCMP_CODE_EXIT;
3871 loc->mbuf = *pkts++;
3872 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3873 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
3875 /* Continue sending eMPW batches. */
3881 * The routine sends packets with MLX5_OPCODE_EMPW
3882 * with inlining, optionally supports VLAN insertion.
3884 static __rte_always_inline enum mlx5_txcmp_code
3885 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
3886 struct rte_mbuf **restrict pkts,
3887 unsigned int pkts_n,
3888 struct mlx5_txq_local *restrict loc,
3892 * Subroutine is the part of mlx5_tx_burst_single()
3893 * and sends single-segment packet with eMPW opcode
3894 * with data inlining.
3896 assert(MLX5_TXOFF_CONFIG(INLINE));
3897 assert(MLX5_TXOFF_CONFIG(EMPW));
3898 assert(loc->elts_free && loc->wqe_free);
3899 assert(pkts_n > loc->pkts_sent);
3900 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3901 pkts += loc->pkts_sent + 1;
3902 pkts_n -= loc->pkts_sent;
3904 struct mlx5_wqe_dseg *restrict dseg;
3905 struct mlx5_wqe_eseg *restrict eseg;
3906 enum mlx5_txcmp_code ret;
3907 unsigned int room, part;
3908 unsigned int slen = 0;
3911 /* Check whether we have minimal amount WQEs */
3912 if (unlikely(loc->wqe_free <
3913 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3914 return MLX5_TXCMP_CODE_EXIT;
3915 if (likely(pkts_n > 1))
3916 rte_prefetch0(*pkts);
3917 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3919 * Build eMPW title WQEBB:
3920 * - Control Segment, eMPW opcode, zero DS
3921 * - Ethernet Segment, no inline
3923 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
3924 MLX5_OPCODE_ENHANCED_MPSW, olx);
3925 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3926 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3927 eseg = &loc->wqe_last->eseg;
3928 dseg = &loc->wqe_last->dseg[0];
3929 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
3930 loc->wqe_free) * MLX5_WQE_SIZE -
3931 MLX5_WQE_CSEG_SIZE -
3933 /* Build WQE till we have space, packets and resources. */
3936 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3937 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
3940 assert(room >= MLX5_WQE_DSEG_SIZE);
3941 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
3942 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
3944 * Some Tx offloads may cause an error if
3945 * packet is not long enough, check against
3946 * assumed minimal length.
3948 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
3950 if (unlikely(!part))
3951 return MLX5_TXCMP_CODE_ERROR;
3953 * We have some successfully built
3954 * packet Data Segments to send.
3956 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
3957 return MLX5_TXCMP_CODE_ERROR;
3959 /* Inline or not inline - that's the Question. */
3960 if (dlen > txq->inlen_empw)
3962 /* Inline entire packet, optional VLAN insertion. */
3963 tlen = sizeof(dseg->bcount) + dlen;
3964 if (MLX5_TXOFF_CONFIG(VLAN) &&
3965 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3967 * The packet length must be checked in
3968 * mlx5_tx_able_to_empw() and packet
3969 * fits into inline length guaranteed.
3971 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
3973 tlen += sizeof(struct rte_vlan_hdr);
3976 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
3978 #ifdef MLX5_PMD_SOFT_COUNTERS
3979 /* Update sent data bytes counter. */
3980 slen += sizeof(struct rte_vlan_hdr);
3985 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
3988 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
3989 assert(room >= tlen);
3992 * Packet data are completely inlined,
3993 * free the packet immediately.
3995 rte_pktmbuf_free_seg(loc->mbuf);
3999 * Not inlinable VLAN packets are
4000 * proceeded outside of this routine.
4002 assert(room >= MLX5_WQE_DSEG_SIZE);
4003 if (MLX5_TXOFF_CONFIG(VLAN))
4004 assert(!(loc->mbuf->ol_flags &
4006 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4007 /* We have to store mbuf in elts.*/
4008 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4009 room -= MLX5_WQE_DSEG_SIZE;
4010 /* Ring buffer wraparound is checked at the loop end.*/
4013 #ifdef MLX5_PMD_SOFT_COUNTERS
4014 /* Update sent data bytes counter. */
4020 if (unlikely(!pkts_n || !loc->elts_free)) {
4022 * We have no resources/packets to
4023 * continue build descriptors.
4026 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4027 return MLX5_TXCMP_CODE_EXIT;
4029 /* Check if we have minimal room left. */
4030 if (room < MLX5_WQE_DSEG_SIZE) {
4032 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4035 loc->mbuf = *pkts++;
4036 if (likely(pkts_n > 1))
4037 rte_prefetch0(*pkts);
4038 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4040 * Unroll the completion code to avoid
4041 * returning variable value - it results in
4042 * unoptimized sequent checking in caller.
4044 if (ret == MLX5_TXCMP_CODE_MULTI) {
4046 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4047 if (unlikely(!loc->elts_free ||
4049 return MLX5_TXCMP_CODE_EXIT;
4050 return MLX5_TXCMP_CODE_MULTI;
4052 if (ret == MLX5_TXCMP_CODE_TSO) {
4054 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4055 if (unlikely(!loc->elts_free ||
4057 return MLX5_TXCMP_CODE_EXIT;
4058 return MLX5_TXCMP_CODE_TSO;
4060 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4062 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4063 if (unlikely(!loc->elts_free ||
4065 return MLX5_TXCMP_CODE_EXIT;
4066 return MLX5_TXCMP_CODE_SINGLE;
4068 if (ret != MLX5_TXCMP_CODE_EMPW) {
4071 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4072 return MLX5_TXCMP_CODE_ERROR;
4075 * Check whether packet parameters coincide
4076 * within assumed eMPW batch:
4077 * - check sum settings
4079 * - software parser settings
4081 if (!mlx5_tx_match_empw(txq, eseg, loc, olx))
4083 /* Packet attributes match, continue the same eMPW. */
4084 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4085 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4088 * We get here to close an existing eMPW
4089 * session and start the new one.
4093 if (unlikely(!part))
4094 return MLX5_TXCMP_CODE_EXIT;
4095 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4096 if (unlikely(!loc->elts_free ||
4098 return MLX5_TXCMP_CODE_EXIT;
4105 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4106 * Data inlining and VLAN insertion are supported.
4108 static __rte_always_inline enum mlx5_txcmp_code
4109 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4110 struct rte_mbuf **restrict pkts,
4111 unsigned int pkts_n,
4112 struct mlx5_txq_local *restrict loc,
4116 * Subroutine is the part of mlx5_tx_burst_single()
4117 * and sends single-segment packet with SEND opcode.
4119 assert(loc->elts_free && loc->wqe_free);
4120 assert(pkts_n > loc->pkts_sent);
4121 pkts += loc->pkts_sent + 1;
4122 pkts_n -= loc->pkts_sent;
4124 struct mlx5_wqe *restrict wqe;
4125 enum mlx5_txcmp_code ret;
4127 assert(NB_SEGS(loc->mbuf) == 1);
4128 if (MLX5_TXOFF_CONFIG(INLINE)) {
4129 unsigned int inlen, vlan = 0;
4131 inlen = rte_pktmbuf_data_len(loc->mbuf);
4132 if (MLX5_TXOFF_CONFIG(VLAN) &&
4133 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4134 vlan = sizeof(struct rte_vlan_hdr);
4136 static_assert((sizeof(struct rte_vlan_hdr) +
4137 sizeof(struct rte_ether_hdr)) ==
4138 MLX5_ESEG_MIN_INLINE_SIZE,
4139 "invalid min inline data size");
4142 * If inlining is enabled at configuration time
4143 * the limit must be not less than minimal size.
4144 * Otherwise we would do extra check for data
4145 * size to avoid crashes due to length overflow.
4147 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4148 if (inlen <= txq->inlen_send) {
4149 unsigned int seg_n, wqe_n;
4151 rte_prefetch0(rte_pktmbuf_mtod
4152 (loc->mbuf, uint8_t *));
4153 /* Check against minimal length. */
4154 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4155 return MLX5_TXCMP_CODE_ERROR;
4157 * Completely inlined packet data WQE:
4158 * - Control Segment, SEND opcode
4159 * - Ethernet Segment, no VLAN insertion
4160 * - Data inlined, VLAN optionally inserted
4161 * - Alignment to MLX5_WSEG_SIZE
4162 * Have to estimate amount of WQEBBs
4164 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4165 MLX5_ESEG_MIN_INLINE_SIZE +
4166 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4167 /* Check if there are enough WQEBBs. */
4168 wqe_n = (seg_n + 3) / 4;
4169 if (wqe_n > loc->wqe_free)
4170 return MLX5_TXCMP_CODE_EXIT;
4171 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4172 loc->wqe_last = wqe;
4173 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4174 MLX5_OPCODE_SEND, olx);
4175 mlx5_tx_eseg_data(txq, loc, wqe,
4176 vlan, inlen, 0, olx);
4177 txq->wqe_ci += wqe_n;
4178 loc->wqe_free -= wqe_n;
4180 * Packet data are completely inlined,
4181 * free the packet immediately.
4183 rte_pktmbuf_free_seg(loc->mbuf);
4184 } else if (!MLX5_TXOFF_CONFIG(EMPW) &&
4187 * If minimal inlining is requested the eMPW
4188 * feature should be disabled due to data is
4189 * inlined into Ethernet Segment, which can
4190 * not contain inlined data for eMPW due to
4191 * segment shared for all packets.
4193 struct mlx5_wqe_dseg *restrict dseg;
4198 * The inline-mode settings require
4199 * to inline the specified amount of
4200 * data bytes to the Ethernet Segment.
4201 * We should check the free space in
4202 * WQE ring buffer to inline partially.
4204 assert(txq->inlen_send >= txq->inlen_mode);
4205 assert(inlen > txq->inlen_mode);
4206 assert(txq->inlen_mode >=
4207 MLX5_ESEG_MIN_INLINE_SIZE);
4209 * Check whether there are enough free WQEBBs:
4211 * - Ethernet Segment
4212 * - First Segment of inlined Ethernet data
4213 * - ... data continued ...
4214 * - Finishing Data Segment of pointer type
4216 ds = (MLX5_WQE_CSEG_SIZE +
4217 MLX5_WQE_ESEG_SIZE +
4218 MLX5_WQE_DSEG_SIZE +
4220 MLX5_ESEG_MIN_INLINE_SIZE +
4221 MLX5_WQE_DSEG_SIZE +
4222 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4223 if (loc->wqe_free < ((ds + 3) / 4))
4224 return MLX5_TXCMP_CODE_EXIT;
4226 * Build the ordinary SEND WQE:
4228 * - Ethernet Segment, inline inlen_mode bytes
4229 * - Data Segment of pointer type
4231 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4232 loc->wqe_last = wqe;
4233 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4234 MLX5_OPCODE_SEND, olx);
4235 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4238 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4239 txq->inlen_mode - vlan;
4240 inlen -= txq->inlen_mode;
4241 mlx5_tx_dseg_ptr(txq, loc, dseg,
4244 * WQE is built, update the loop parameters
4245 * and got to the next packet.
4247 txq->wqe_ci += (ds + 3) / 4;
4248 loc->wqe_free -= (ds + 3) / 4;
4249 /* We have to store mbuf in elts.*/
4250 assert(MLX5_TXOFF_CONFIG(INLINE));
4251 txq->elts[txq->elts_head++ & txq->elts_m] =
4259 * Partially inlined packet data WQE, we have
4260 * some space in title WQEBB, we can fill it
4261 * with some packet data. It takes one WQEBB,
4262 * it is available, no extra space check:
4263 * - Control Segment, SEND opcode
4264 * - Ethernet Segment, no VLAN insertion
4265 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4266 * - Data Segment, pointer type
4268 * We also get here if VLAN insertion is not
4269 * supported by HW, the inline is enabled.
4271 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4272 loc->wqe_last = wqe;
4273 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4274 MLX5_OPCODE_SEND, olx);
4275 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4276 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4277 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4279 * The length check is performed above, by
4280 * comparing with txq->inlen_send. We should
4281 * not get overflow here.
4283 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4284 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4285 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4289 /* We have to store mbuf in elts.*/
4290 assert(MLX5_TXOFF_CONFIG(INLINE));
4291 txq->elts[txq->elts_head++ & txq->elts_m] =
4295 #ifdef MLX5_PMD_SOFT_COUNTERS
4296 /* Update sent data bytes counter. */
4297 txq->stats.obytes += vlan +
4298 rte_pktmbuf_data_len(loc->mbuf);
4302 * No inline at all, it means the CPU cycles saving
4303 * is prioritized at configuration, we should not
4304 * copy any packet data to WQE.
4306 * SEND WQE, one WQEBB:
4307 * - Control Segment, SEND opcode
4308 * - Ethernet Segment, optional VLAN, no inline
4309 * - Data Segment, pointer type
4311 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4312 loc->wqe_last = wqe;
4313 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4314 MLX5_OPCODE_SEND, olx);
4315 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4317 (txq, loc, &wqe->dseg[0],
4318 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4319 rte_pktmbuf_data_len(loc->mbuf), olx);
4323 * We should not store mbuf pointer in elts
4324 * if no inlining is configured, this is done
4325 * by calling routine in a batch copy.
4327 assert(!MLX5_TXOFF_CONFIG(INLINE));
4329 #ifdef MLX5_PMD_SOFT_COUNTERS
4330 /* Update sent data bytes counter. */
4331 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4332 if (MLX5_TXOFF_CONFIG(VLAN) &&
4333 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4334 txq->stats.obytes +=
4335 sizeof(struct rte_vlan_hdr);
4340 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4341 return MLX5_TXCMP_CODE_EXIT;
4342 loc->mbuf = *pkts++;
4344 rte_prefetch0(*pkts);
4345 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4346 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4352 static __rte_always_inline enum mlx5_txcmp_code
4353 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4354 struct rte_mbuf **restrict pkts,
4355 unsigned int pkts_n,
4356 struct mlx5_txq_local *restrict loc,
4359 enum mlx5_txcmp_code ret;
4361 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4362 if (ret == MLX5_TXCMP_CODE_SINGLE)
4364 assert(ret == MLX5_TXCMP_CODE_EMPW);
4366 /* Optimize for inline/no inline eMPW send. */
4367 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4368 mlx5_tx_burst_empw_inline
4369 (txq, pkts, pkts_n, loc, olx) :
4370 mlx5_tx_burst_empw_simple
4371 (txq, pkts, pkts_n, loc, olx);
4372 if (ret != MLX5_TXCMP_CODE_SINGLE)
4374 /* The resources to send one packet should remain. */
4375 assert(loc->elts_free && loc->wqe_free);
4377 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4378 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4379 if (ret != MLX5_TXCMP_CODE_EMPW)
4381 /* The resources to send one packet should remain. */
4382 assert(loc->elts_free && loc->wqe_free);
4387 * DPDK Tx callback template. This is configured template
4388 * used to generate routines optimized for specified offload setup.
4389 * One of this generated functions is chosen at SQ configuration
4393 * Generic pointer to TX queue structure.
4395 * Packets to transmit.
4397 * Number of packets in array.
4399 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4400 * values. Should be static to take compile time static configuration
4404 * Number of packets successfully transmitted (<= pkts_n).
4406 static __rte_always_inline uint16_t
4407 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4408 struct rte_mbuf **restrict pkts,
4412 struct mlx5_txq_local loc;
4413 enum mlx5_txcmp_code ret;
4416 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4417 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4419 * Check if there are some CQEs, if any:
4420 * - process an encountered errors
4421 * - process the completed WQEs
4422 * - free related mbufs
4423 * - doorbell the NIC about processed CQEs
4425 if (unlikely(!pkts_n))
4427 rte_prefetch0(*pkts);
4428 mlx5_tx_handle_completion(txq, olx);
4430 * Calculate the number of available resources - elts and WQEs.
4431 * There are two possible different scenarios:
4432 * - no data inlining into WQEs, one WQEBB may contains upto
4433 * four packets, in this case elts become scarce resource
4434 * - data inlining into WQEs, one packet may require multiple
4435 * WQEBBs, the WQEs become the limiting factor.
4437 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4438 loc.elts_free = txq->elts_s -
4439 (uint16_t)(txq->elts_head - txq->elts_tail);
4440 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4441 loc.wqe_free = txq->wqe_s -
4442 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4443 if (unlikely(!loc.elts_free || !loc.wqe_free))
4447 loc.wqe_last = NULL;
4450 * Fetch the packet from array. Usually this is
4451 * the first packet in series of multi/single
4454 loc.mbuf = *(pkts + loc.pkts_sent);
4455 /* Dedicated branch for multi-segment packets. */
4456 if (MLX5_TXOFF_CONFIG(MULTI) &&
4457 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4459 * Multi-segment packet encountered.
4460 * Hardware is able to process it only
4461 * with SEND/TSO opcodes, one packet
4462 * per WQE, do it in dedicated routine.
4465 assert(loc.pkts_sent >= loc.pkts_copy);
4466 part = loc.pkts_sent - loc.pkts_copy;
4467 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4469 * There are some single-segment mbufs not
4470 * stored in elts. The mbufs must be in the
4471 * same order as WQEs, so we must copy the
4472 * mbufs to elts here, before the coming
4473 * multi-segment packet mbufs is appended.
4475 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4477 loc.pkts_copy = loc.pkts_sent;
4479 assert(pkts_n > loc.pkts_sent);
4480 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4481 if (!MLX5_TXOFF_CONFIG(INLINE))
4482 loc.pkts_copy = loc.pkts_sent;
4484 * These returned code checks are supposed
4485 * to be optimized out due to routine inlining.
4487 if (ret == MLX5_TXCMP_CODE_EXIT) {
4489 * The routine returns this code when
4490 * all packets are sent or there is no
4491 * enough resources to complete request.
4495 if (ret == MLX5_TXCMP_CODE_ERROR) {
4497 * The routine returns this code when
4498 * some error in the incoming packets
4501 txq->stats.oerrors++;
4504 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4506 * The single-segment packet was encountered
4507 * in the array, try to send it with the
4508 * best optimized way, possible engaging eMPW.
4510 goto enter_send_single;
4512 if (MLX5_TXOFF_CONFIG(TSO) &&
4513 ret == MLX5_TXCMP_CODE_TSO) {
4515 * The single-segment TSO packet was
4516 * encountered in the array.
4518 goto enter_send_tso;
4520 /* We must not get here. Something is going wrong. */
4522 txq->stats.oerrors++;
4525 /* Dedicated branch for single-segment TSO packets. */
4526 if (MLX5_TXOFF_CONFIG(TSO) &&
4527 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4529 * TSO might require special way for inlining
4530 * (dedicated parameters) and is sent with
4531 * MLX5_OPCODE_TSO opcode only, provide this
4532 * in dedicated branch.
4535 assert(NB_SEGS(loc.mbuf) == 1);
4536 assert(pkts_n > loc.pkts_sent);
4537 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4539 * These returned code checks are supposed
4540 * to be optimized out due to routine inlining.
4542 if (ret == MLX5_TXCMP_CODE_EXIT)
4544 if (ret == MLX5_TXCMP_CODE_ERROR) {
4545 txq->stats.oerrors++;
4548 if (ret == MLX5_TXCMP_CODE_SINGLE)
4549 goto enter_send_single;
4550 if (MLX5_TXOFF_CONFIG(MULTI) &&
4551 ret == MLX5_TXCMP_CODE_MULTI) {
4553 * The multi-segment packet was
4554 * encountered in the array.
4556 goto enter_send_multi;
4558 /* We must not get here. Something is going wrong. */
4560 txq->stats.oerrors++;
4564 * The dedicated branch for the single-segment packets
4565 * without TSO. Often these ones can be sent using
4566 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4567 * The routine builds the WQEs till it encounters
4568 * the TSO or multi-segment packet (in case if these
4569 * offloads are requested at SQ configuration time).
4572 assert(pkts_n > loc.pkts_sent);
4573 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4575 * These returned code checks are supposed
4576 * to be optimized out due to routine inlining.
4578 if (ret == MLX5_TXCMP_CODE_EXIT)
4580 if (ret == MLX5_TXCMP_CODE_ERROR) {
4581 txq->stats.oerrors++;
4584 if (MLX5_TXOFF_CONFIG(MULTI) &&
4585 ret == MLX5_TXCMP_CODE_MULTI) {
4587 * The multi-segment packet was
4588 * encountered in the array.
4590 goto enter_send_multi;
4592 if (MLX5_TXOFF_CONFIG(TSO) &&
4593 ret == MLX5_TXCMP_CODE_TSO) {
4595 * The single-segment TSO packet was
4596 * encountered in the array.
4598 goto enter_send_tso;
4600 /* We must not get here. Something is going wrong. */
4602 txq->stats.oerrors++;
4606 * Main Tx loop is completed, do the rest:
4607 * - set completion request if thresholds are reached
4608 * - doorbell the hardware
4609 * - copy the rest of mbufs to elts (if any)
4611 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4612 /* Take a shortcut if nothing is sent. */
4613 if (unlikely(loc.pkts_sent == 0))
4615 /* Not all of the mbufs may be stored into elts yet. */
4616 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4617 mlx5_tx_request_completion(txq, part, &loc, olx);
4619 * Ring QP doorbell immediately after WQE building completion
4620 * to improve latencies. The pure software related data treatment
4621 * can be completed after doorbell. Tx CQEs for this SQ are
4622 * processed in this thread only by the polling.
4624 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);
4625 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4627 * There are some single-segment mbufs not stored in elts.
4628 * It can be only if last packet was single-segment.
4629 * The copying is gathered into one place due to it is
4630 * a good opportunity to optimize that with SIMD.
4631 * Unfortunately if inlining is enabled the gaps in
4632 * pointer array may happen due to early freeing of the
4635 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4637 #ifdef MLX5_PMD_SOFT_COUNTERS
4638 /* Increment sent packets counter. */
4639 txq->stats.opackets += loc.pkts_sent;
4641 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4642 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4643 return loc.pkts_sent;
4646 /* Generate routines with Enhanced Multi-Packet Write support. */
4647 MLX5_TXOFF_DECL(full_empw,
4648 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4650 MLX5_TXOFF_DECL(none_empw,
4651 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4653 MLX5_TXOFF_DECL(md_empw,
4654 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4656 MLX5_TXOFF_DECL(mt_empw,
4657 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4658 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4660 MLX5_TXOFF_DECL(mtsc_empw,
4661 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4662 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4663 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4665 MLX5_TXOFF_DECL(mti_empw,
4666 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4667 MLX5_TXOFF_CONFIG_INLINE |
4668 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4670 MLX5_TXOFF_DECL(mtv_empw,
4671 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4672 MLX5_TXOFF_CONFIG_VLAN |
4673 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4675 MLX5_TXOFF_DECL(mtiv_empw,
4676 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4677 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4678 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4680 MLX5_TXOFF_DECL(sc_empw,
4681 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4682 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4684 MLX5_TXOFF_DECL(sci_empw,
4685 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4686 MLX5_TXOFF_CONFIG_INLINE |
4687 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4689 MLX5_TXOFF_DECL(scv_empw,
4690 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4691 MLX5_TXOFF_CONFIG_VLAN |
4692 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4694 MLX5_TXOFF_DECL(sciv_empw,
4695 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4696 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4697 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4699 MLX5_TXOFF_DECL(i_empw,
4700 MLX5_TXOFF_CONFIG_INLINE |
4701 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4703 MLX5_TXOFF_DECL(v_empw,
4704 MLX5_TXOFF_CONFIG_VLAN |
4705 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4707 MLX5_TXOFF_DECL(iv_empw,
4708 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4709 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4711 /* Generate routines without Enhanced Multi-Packet Write support. */
4712 MLX5_TXOFF_DECL(full,
4713 MLX5_TXOFF_CONFIG_FULL)
4715 MLX5_TXOFF_DECL(none,
4716 MLX5_TXOFF_CONFIG_NONE)
4719 MLX5_TXOFF_CONFIG_METADATA)
4722 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4723 MLX5_TXOFF_CONFIG_METADATA)
4725 MLX5_TXOFF_DECL(mtsc,
4726 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4727 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4728 MLX5_TXOFF_CONFIG_METADATA)
4730 MLX5_TXOFF_DECL(mti,
4731 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4732 MLX5_TXOFF_CONFIG_INLINE |
4733 MLX5_TXOFF_CONFIG_METADATA)
4736 MLX5_TXOFF_DECL(mtv,
4737 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4738 MLX5_TXOFF_CONFIG_VLAN |
4739 MLX5_TXOFF_CONFIG_METADATA)
4742 MLX5_TXOFF_DECL(mtiv,
4743 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4744 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4745 MLX5_TXOFF_CONFIG_METADATA)
4748 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4749 MLX5_TXOFF_CONFIG_METADATA)
4751 MLX5_TXOFF_DECL(sci,
4752 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4753 MLX5_TXOFF_CONFIG_INLINE |
4754 MLX5_TXOFF_CONFIG_METADATA)
4757 MLX5_TXOFF_DECL(scv,
4758 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4759 MLX5_TXOFF_CONFIG_VLAN |
4760 MLX5_TXOFF_CONFIG_METADATA)
4763 MLX5_TXOFF_DECL(sciv,
4764 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4765 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4766 MLX5_TXOFF_CONFIG_METADATA)
4769 MLX5_TXOFF_CONFIG_INLINE |
4770 MLX5_TXOFF_CONFIG_METADATA)
4773 MLX5_TXOFF_CONFIG_VLAN |
4774 MLX5_TXOFF_CONFIG_METADATA)
4777 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4778 MLX5_TXOFF_CONFIG_METADATA)
4781 * Array of declared and compiled Tx burst function and corresponding
4782 * supported offloads set. The array is used to select the Tx burst
4783 * function for specified offloads set at Tx queue configuration time.
4786 eth_tx_burst_t func;
4789 MLX5_TXOFF_INFO(full_empw,
4790 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4791 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4792 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4793 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4795 MLX5_TXOFF_INFO(none_empw,
4796 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4798 MLX5_TXOFF_INFO(md_empw,
4799 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4801 MLX5_TXOFF_INFO(mt_empw,
4802 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4803 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4805 MLX5_TXOFF_INFO(mtsc_empw,
4806 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4807 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4808 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4810 MLX5_TXOFF_INFO(mti_empw,
4811 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4812 MLX5_TXOFF_CONFIG_INLINE |
4813 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4815 MLX5_TXOFF_INFO(mtv_empw,
4816 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4817 MLX5_TXOFF_CONFIG_VLAN |
4818 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4820 MLX5_TXOFF_INFO(mtiv_empw,
4821 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4822 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4823 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4825 MLX5_TXOFF_INFO(sc_empw,
4826 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4827 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4829 MLX5_TXOFF_INFO(sci_empw,
4830 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4831 MLX5_TXOFF_CONFIG_INLINE |
4832 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4834 MLX5_TXOFF_INFO(scv_empw,
4835 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4836 MLX5_TXOFF_CONFIG_VLAN |
4837 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4839 MLX5_TXOFF_INFO(sciv_empw,
4840 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4841 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4842 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4844 MLX5_TXOFF_INFO(i_empw,
4845 MLX5_TXOFF_CONFIG_INLINE |
4846 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4848 MLX5_TXOFF_INFO(v_empw,
4849 MLX5_TXOFF_CONFIG_VLAN |
4850 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4852 MLX5_TXOFF_INFO(iv_empw,
4853 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4854 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4856 MLX5_TXOFF_INFO(full,
4857 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4858 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4859 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4860 MLX5_TXOFF_CONFIG_METADATA)
4862 MLX5_TXOFF_INFO(none,
4863 MLX5_TXOFF_CONFIG_NONE)
4866 MLX5_TXOFF_CONFIG_METADATA)
4869 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4870 MLX5_TXOFF_CONFIG_METADATA)
4872 MLX5_TXOFF_INFO(mtsc,
4873 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4874 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4875 MLX5_TXOFF_CONFIG_METADATA)
4877 MLX5_TXOFF_INFO(mti,
4878 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4879 MLX5_TXOFF_CONFIG_INLINE |
4880 MLX5_TXOFF_CONFIG_METADATA)
4883 MLX5_TXOFF_INFO(mtv,
4884 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4885 MLX5_TXOFF_CONFIG_VLAN |
4886 MLX5_TXOFF_CONFIG_METADATA)
4888 MLX5_TXOFF_INFO(mtiv,
4889 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4890 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4891 MLX5_TXOFF_CONFIG_METADATA)
4894 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4895 MLX5_TXOFF_CONFIG_METADATA)
4897 MLX5_TXOFF_INFO(sci,
4898 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4899 MLX5_TXOFF_CONFIG_INLINE |
4900 MLX5_TXOFF_CONFIG_METADATA)
4902 MLX5_TXOFF_INFO(scv,
4903 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4904 MLX5_TXOFF_CONFIG_VLAN |
4905 MLX5_TXOFF_CONFIG_METADATA)
4907 MLX5_TXOFF_INFO(sciv,
4908 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4909 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4910 MLX5_TXOFF_CONFIG_METADATA)
4913 MLX5_TXOFF_CONFIG_INLINE |
4914 MLX5_TXOFF_CONFIG_METADATA)
4917 MLX5_TXOFF_CONFIG_VLAN |
4918 MLX5_TXOFF_CONFIG_METADATA)
4921 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4922 MLX5_TXOFF_CONFIG_METADATA)
4926 * Configure the Tx function to use. The routine checks configured
4927 * Tx offloads for the device and selects appropriate Tx burst
4928 * routine. There are multiple Tx burst routines compiled from
4929 * the same template in the most optimal way for the dedicated
4933 * Pointer to private data structure.
4936 * Pointer to selected Tx burst function.
4939 mlx5_select_tx_function(struct rte_eth_dev *dev)
4941 struct mlx5_priv *priv = dev->data->dev_private;
4942 struct mlx5_dev_config *config = &priv->config;
4943 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
4944 unsigned int diff = 0, olx = 0, i, m;
4946 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
4947 MLX5_DSEG_MAX, "invalid WQE max size");
4948 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
4949 "invalid WQE Control Segment size");
4950 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
4951 "invalid WQE Ethernet Segment size");
4952 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
4953 "invalid WQE Data Segment size");
4954 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
4955 "invalid WQE size");
4957 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
4958 /* We should support Multi-Segment Packets. */
4959 olx |= MLX5_TXOFF_CONFIG_MULTI;
4961 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
4962 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
4963 DEV_TX_OFFLOAD_GRE_TNL_TSO |
4964 DEV_TX_OFFLOAD_IP_TNL_TSO |
4965 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
4966 /* We should support TCP Send Offload. */
4967 olx |= MLX5_TXOFF_CONFIG_TSO;
4969 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
4970 DEV_TX_OFFLOAD_UDP_TNL_TSO |
4971 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
4972 /* We should support Software Parser for Tunnels. */
4973 olx |= MLX5_TXOFF_CONFIG_SWP;
4975 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
4976 DEV_TX_OFFLOAD_UDP_CKSUM |
4977 DEV_TX_OFFLOAD_TCP_CKSUM |
4978 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
4979 /* We should support IP/TCP/UDP Checksums. */
4980 olx |= MLX5_TXOFF_CONFIG_CSUM;
4982 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
4983 /* We should support VLAN insertion. */
4984 olx |= MLX5_TXOFF_CONFIG_VLAN;
4986 if (priv->txqs_n && (*priv->txqs)[0]) {
4987 struct mlx5_txq_data *txd = (*priv->txqs)[0];
4989 if (txd->inlen_send) {
4991 * Check the data inline requirements. Data inline
4992 * is enabled on per device basis, we can check
4993 * the first Tx queue only.
4995 * If device does not support VLAN insertion in WQE
4996 * and some queues are requested to perform VLAN
4997 * insertion offload than inline must be enabled.
4999 olx |= MLX5_TXOFF_CONFIG_INLINE;
5002 if (config->mps == MLX5_MPW_ENHANCED &&
5003 config->txq_inline_min <= 0) {
5005 * The NIC supports Enhanced Multi-Packet Write.
5006 * We do not support legacy MPW due to its
5007 * hardware related problems, so we just ignore
5008 * legacy MLX5_MPW settings. There should be no
5009 * minimal required inline data.
5011 olx |= MLX5_TXOFF_CONFIG_EMPW;
5013 if (tx_offloads & DEV_TX_OFFLOAD_MATCH_METADATA) {
5014 /* We should support Flow metadata. */
5015 olx |= MLX5_TXOFF_CONFIG_METADATA;
5018 * Scan the routines table to find the minimal
5019 * satisfying routine with requested offloads.
5021 m = RTE_DIM(txoff_func);
5022 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5025 tmp = txoff_func[i].olx;
5027 /* Meets requested offloads exactly.*/
5031 if ((tmp & olx) != olx) {
5032 /* Does not meet requested offloads at all. */
5035 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5036 /* Do not enable eMPW if not configured. */
5038 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5039 /* Do not enable inlining if not configured. */
5042 * Some routine meets the requirements.
5043 * Check whether it has minimal amount
5044 * of not requested offloads.
5046 tmp = __builtin_popcountl(tmp & ~olx);
5047 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5048 /* First or better match, save and continue. */
5054 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5055 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5056 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5057 /* Lighter not requested offload. */
5062 if (m >= RTE_DIM(txoff_func)) {
5063 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5064 " for requested offloads %04X",
5065 dev->data->port_id, olx);
5068 DRV_LOG(DEBUG, "port %u has selected Tx function"
5069 " supporting offloads %04X/%04X",
5070 dev->data->port_id, olx, txoff_func[m].olx);
5071 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5072 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5073 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5074 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5075 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5076 DRV_LOG(DEBUG, "\tSWP (software parser)");
5077 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5078 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5079 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5080 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5081 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5082 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5083 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5084 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5085 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW)
5086 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5087 return txoff_func[m].func;