4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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13 * * Redistributions in binary form must reproduce the above copyright
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18 * contributors may be used to endorse or promote products derived
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5_hw.h>
46 #include <infiniband/arch.h>
48 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_mempool.h>
53 #include <rte_prefetch.h>
54 #include <rte_common.h>
55 #include <rte_branch_prediction.h>
56 #include <rte_ether.h>
59 #include "mlx5_utils.h"
60 #include "mlx5_rxtx.h"
61 #include "mlx5_autoconf.h"
62 #include "mlx5_defs.h"
65 static __rte_always_inline uint32_t
66 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
68 static __rte_always_inline int
69 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
70 uint16_t cqe_cnt, uint32_t *rss_hash);
72 static __rte_always_inline uint32_t
73 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe);
75 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
76 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
80 * Build a table to translate Rx completion flags to packet type.
82 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
85 mlx5_set_ptype_table(void)
88 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
90 /* Last entry must not be overwritten, reserved for errored packet. */
91 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
92 (*p)[i] = RTE_PTYPE_UNKNOWN;
94 * The index to the array should have:
95 * bit[1:0] = l3_hdr_type
96 * bit[4:2] = l4_hdr_type
99 * bit[7] = outer_l3_type
102 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
103 RTE_PTYPE_L4_NONFRAG;
104 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
105 RTE_PTYPE_L4_NONFRAG;
107 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
109 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
112 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
114 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
117 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
119 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
121 /* Repeat with outer_l3_type being set. Just in case. */
122 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
123 RTE_PTYPE_L4_NONFRAG;
124 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
125 RTE_PTYPE_L4_NONFRAG;
126 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
128 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
130 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
132 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
134 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
136 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
139 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L4_NONFRAG;
145 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
146 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L4_NONFRAG;
148 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L4_NONFRAG;
151 /* Tunneled - Fragmented */
152 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
153 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L4_FRAG;
155 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L4_FRAG;
158 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L4_FRAG;
161 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
162 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L4_FRAG;
165 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
172 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
175 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
178 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
193 * Return the size of tailroom of WQ.
196 * Pointer to TX queue structure.
198 * Pointer to tail of WQ.
204 tx_mlx5_wq_tailroom(struct txq *txq, void *addr)
207 tailroom = (uintptr_t)(txq->wqes) +
208 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
214 * Copy data to tailroom of circular queue.
217 * Pointer to destination.
221 * Number of bytes to copy.
223 * Pointer to head of queue.
225 * Size of tailroom from dst.
228 * Pointer after copied data.
231 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
232 void *base, size_t tailroom)
237 rte_memcpy(dst, src, tailroom);
238 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
240 ret = (uint8_t *)base + n - tailroom;
242 rte_memcpy(dst, src, n);
243 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
249 * DPDK callback to check the status of a tx descriptor.
254 * The index of the descriptor in the ring.
257 * The status of the tx descriptor.
260 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
262 struct txq *txq = tx_queue;
265 mlx5_tx_complete(txq);
266 used = txq->elts_head - txq->elts_tail;
268 return RTE_ETH_TX_DESC_FULL;
269 return RTE_ETH_TX_DESC_DONE;
273 * DPDK callback to check the status of a rx descriptor.
278 * The index of the descriptor in the ring.
281 * The status of the tx descriptor.
284 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
286 struct rxq *rxq = rx_queue;
287 struct rxq_zip *zip = &rxq->zip;
288 volatile struct mlx5_cqe *cqe;
289 const unsigned int cqe_n = (1 << rxq->cqe_n);
290 const unsigned int cqe_cnt = cqe_n - 1;
294 /* if we are processing a compressed cqe */
296 used = zip->cqe_cnt - zip->ca;
302 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
303 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
307 op_own = cqe->op_own;
308 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
309 n = ntohl(cqe->byte_cnt);
314 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
316 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
318 return RTE_ETH_RX_DESC_DONE;
319 return RTE_ETH_RX_DESC_AVAIL;
323 * DPDK callback for TX.
326 * Generic pointer to TX queue structure.
328 * Packets to transmit.
330 * Number of packets in array.
333 * Number of packets successfully transmitted (<= pkts_n).
336 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
338 struct txq *txq = (struct txq *)dpdk_txq;
339 uint16_t elts_head = txq->elts_head;
340 const uint16_t elts_n = 1 << txq->elts_n;
341 const uint16_t elts_m = elts_n - 1;
346 unsigned int max_inline = txq->max_inline;
347 const unsigned int inline_en = !!max_inline && txq->inline_en;
350 volatile struct mlx5_wqe_v *wqe = NULL;
351 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
352 unsigned int segs_n = 0;
353 struct rte_mbuf *buf = NULL;
356 if (unlikely(!pkts_n))
358 /* Prefetch first packet cacheline. */
359 rte_prefetch0(*pkts);
360 /* Start processing. */
361 mlx5_tx_complete(txq);
362 max_elts = (elts_n - (elts_head - txq->elts_tail));
363 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
364 if (unlikely(!max_wqe))
367 volatile rte_v128u32_t *dseg = NULL;
370 unsigned int sg = 0; /* counter of additional segs attached. */
373 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
374 uint16_t tso_header_sz = 0;
376 uint8_t cs_flags = 0;
378 uint16_t tso_segsz = 0;
379 #ifdef MLX5_PMD_SOFT_COUNTERS
380 uint32_t total_length = 0;
385 segs_n = buf->nb_segs;
387 * Make sure there is enough room to store this packet and
388 * that one ring entry remains unused.
391 if (max_elts < segs_n)
395 if (unlikely(--max_wqe == 0))
397 wqe = (volatile struct mlx5_wqe_v *)
398 tx_mlx5_wqe(txq, txq->wqe_ci);
399 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
401 rte_prefetch0(*(pkts + 1));
402 addr = rte_pktmbuf_mtod(buf, uintptr_t);
403 length = DATA_LEN(buf);
404 ehdr = (((uint8_t *)addr)[1] << 8) |
405 ((uint8_t *)addr)[0];
406 #ifdef MLX5_PMD_SOFT_COUNTERS
407 total_length = length;
409 if (length < (MLX5_WQE_DWORD_SIZE + 2))
411 /* Update element. */
412 (*txq->elts)[elts_head & elts_m] = buf;
413 /* Prefetch next buffer data. */
416 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
417 /* Should we enable HW CKSUM offload */
419 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
420 const uint64_t is_tunneled = buf->ol_flags &
422 PKT_TX_TUNNEL_VXLAN);
424 if (is_tunneled && txq->tunnel_en) {
425 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
426 MLX5_ETH_WQE_L4_INNER_CSUM;
427 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
428 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
430 cs_flags = MLX5_ETH_WQE_L3_CSUM |
431 MLX5_ETH_WQE_L4_CSUM;
434 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
435 /* Replace the Ethernet type by the VLAN if necessary. */
436 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
437 uint32_t vlan = htonl(0x81000000 | buf->vlan_tci);
438 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
442 /* Copy Destination and source mac address. */
443 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
445 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
446 /* Copy missing two bytes to end the DSeg. */
447 memcpy((uint8_t *)raw + len + sizeof(vlan),
448 ((uint8_t *)addr) + len, 2);
452 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
453 MLX5_WQE_DWORD_SIZE);
454 length -= pkt_inline_sz;
455 addr += pkt_inline_sz;
458 tso = buf->ol_flags & PKT_TX_TCP_SEG;
460 uintptr_t end = (uintptr_t)
461 (((uintptr_t)txq->wqes) +
465 uint8_t vlan_sz = (buf->ol_flags &
466 PKT_TX_VLAN_PKT) ? 4 : 0;
467 const uint64_t is_tunneled =
470 PKT_TX_TUNNEL_VXLAN);
472 tso_header_sz = buf->l2_len + vlan_sz +
473 buf->l3_len + buf->l4_len;
474 tso_segsz = buf->tso_segsz;
476 if (is_tunneled && txq->tunnel_en) {
477 tso_header_sz += buf->outer_l2_len +
479 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
481 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
483 if (unlikely(tso_header_sz >
484 MLX5_MAX_TSO_HEADER))
486 copy_b = tso_header_sz - pkt_inline_sz;
487 /* First seg must contain all headers. */
488 assert(copy_b <= length);
489 raw += MLX5_WQE_DWORD_SIZE;
491 ((end - (uintptr_t)raw) > copy_b)) {
492 uint16_t n = (MLX5_WQE_DS(copy_b) -
495 if (unlikely(max_wqe < n))
498 rte_memcpy((void *)raw,
499 (void *)addr, copy_b);
502 pkt_inline_sz += copy_b;
504 * Another DWORD will be added
505 * in the inline part.
507 raw += MLX5_WQE_DS(copy_b) *
508 MLX5_WQE_DWORD_SIZE -
512 wqe->ctrl = (rte_v128u32_t){
513 htonl(txq->wqe_ci << 8),
514 htonl(txq->qp_num_8s | 1),
525 /* Inline if enough room. */
526 if (inline_en || tso) {
527 uintptr_t end = (uintptr_t)
528 (((uintptr_t)txq->wqes) +
529 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
530 unsigned int inline_room = max_inline *
531 RTE_CACHE_LINE_SIZE -
533 uintptr_t addr_end = (addr + inline_room) &
534 ~(RTE_CACHE_LINE_SIZE - 1);
535 unsigned int copy_b = (addr_end > addr) ?
536 RTE_MIN((addr_end - addr), length) :
539 raw += MLX5_WQE_DWORD_SIZE;
540 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
542 * One Dseg remains in the current WQE. To
543 * keep the computation positive, it is
544 * removed after the bytes to Dseg conversion.
546 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
548 if (unlikely(max_wqe < n))
553 htonl(copy_b | MLX5_INLINE_SEG);
556 MLX5_WQE_DS(tso_header_sz) *
558 rte_memcpy((void *)raw,
559 (void *)&inl, sizeof(inl));
561 pkt_inline_sz += sizeof(inl);
563 rte_memcpy((void *)raw, (void *)addr, copy_b);
566 pkt_inline_sz += copy_b;
569 * 2 DWORDs consumed by the WQE header + ETH segment +
570 * the size of the inline part of the packet.
572 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
574 if (ds % (MLX5_WQE_SIZE /
575 MLX5_WQE_DWORD_SIZE) == 0) {
576 if (unlikely(--max_wqe == 0))
578 dseg = (volatile rte_v128u32_t *)
579 tx_mlx5_wqe(txq, txq->wqe_ci +
582 dseg = (volatile rte_v128u32_t *)
584 (ds * MLX5_WQE_DWORD_SIZE));
587 } else if (!segs_n) {
590 /* dseg will be advance as part of next_seg */
591 dseg = (volatile rte_v128u32_t *)
593 ((ds - 1) * MLX5_WQE_DWORD_SIZE));
598 * No inline has been done in the packet, only the
599 * Ethernet Header as been stored.
601 dseg = (volatile rte_v128u32_t *)
602 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
605 /* Add the remaining packet as a simple ds. */
606 naddr = htonll(addr);
607 *dseg = (rte_v128u32_t){
609 mlx5_tx_mb2mr(txq, buf),
622 * Spill on next WQE when the current one does not have
623 * enough room left. Size of WQE must a be a multiple
624 * of data segment size.
626 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
627 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
628 if (unlikely(--max_wqe == 0))
630 dseg = (volatile rte_v128u32_t *)
631 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
632 rte_prefetch0(tx_mlx5_wqe(txq,
633 txq->wqe_ci + ds / 4 + 1));
640 length = DATA_LEN(buf);
641 #ifdef MLX5_PMD_SOFT_COUNTERS
642 total_length += length;
644 /* Store segment information. */
645 naddr = htonll(rte_pktmbuf_mtod(buf, uintptr_t));
646 *dseg = (rte_v128u32_t){
648 mlx5_tx_mb2mr(txq, buf),
652 (*txq->elts)[++elts_head & elts_m] = buf;
654 /* Advance counter only if all segs are successfully posted. */
663 /* Initialize known and common part of the WQE structure. */
665 wqe->ctrl = (rte_v128u32_t){
666 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_TSO),
667 htonl(txq->qp_num_8s | ds),
671 wqe->eseg = (rte_v128u32_t){
673 cs_flags | (htons(tso_segsz) << 16),
675 (ehdr << 16) | htons(tso_header_sz),
678 wqe->ctrl = (rte_v128u32_t){
679 htonl((txq->wqe_ci << 8) | MLX5_OPCODE_SEND),
680 htonl(txq->qp_num_8s | ds),
684 wqe->eseg = (rte_v128u32_t){
688 (ehdr << 16) | htons(pkt_inline_sz),
692 txq->wqe_ci += (ds + 3) / 4;
693 /* Save the last successful WQE for completion request */
694 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
695 #ifdef MLX5_PMD_SOFT_COUNTERS
696 /* Increment sent bytes counter. */
697 txq->stats.obytes += total_length;
699 } while (i < pkts_n);
700 /* Take a shortcut if nothing must be sent. */
701 if (unlikely((i + k) == 0))
703 txq->elts_head += (i + j);
704 /* Check whether completion threshold has been reached. */
705 comp = txq->elts_comp + i + j + k;
706 if (comp >= MLX5_TX_COMP_THRESH) {
707 /* Request completion on last WQE. */
708 last_wqe->ctrl2 = htonl(8);
709 /* Save elts_head in unused "immediate" field of WQE. */
710 last_wqe->ctrl3 = txq->elts_head;
713 txq->elts_comp = comp;
715 #ifdef MLX5_PMD_SOFT_COUNTERS
716 /* Increment sent packets counter. */
717 txq->stats.opackets += i;
719 /* Ring QP doorbell. */
720 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
725 * Open a MPW session.
728 * Pointer to TX queue structure.
730 * Pointer to MPW session structure.
735 mlx5_mpw_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
737 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
738 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
739 (volatile struct mlx5_wqe_data_seg (*)[])
740 tx_mlx5_wqe(txq, idx + 1);
742 mpw->state = MLX5_MPW_STATE_OPENED;
746 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
747 mpw->wqe->eseg.mss = htons(length);
748 mpw->wqe->eseg.inline_hdr_sz = 0;
749 mpw->wqe->eseg.rsvd0 = 0;
750 mpw->wqe->eseg.rsvd1 = 0;
751 mpw->wqe->eseg.rsvd2 = 0;
752 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
753 (txq->wqe_ci << 8) | MLX5_OPCODE_TSO);
754 mpw->wqe->ctrl[2] = 0;
755 mpw->wqe->ctrl[3] = 0;
756 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
757 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
758 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
759 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
760 mpw->data.dseg[2] = &(*dseg)[0];
761 mpw->data.dseg[3] = &(*dseg)[1];
762 mpw->data.dseg[4] = &(*dseg)[2];
766 * Close a MPW session.
769 * Pointer to TX queue structure.
771 * Pointer to MPW session structure.
774 mlx5_mpw_close(struct txq *txq, struct mlx5_mpw *mpw)
776 unsigned int num = mpw->pkts_n;
779 * Store size in multiple of 16 bytes. Control and Ethernet segments
782 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | (2 + num));
783 mpw->state = MLX5_MPW_STATE_CLOSED;
788 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
789 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
793 * DPDK callback for TX with MPW support.
796 * Generic pointer to TX queue structure.
798 * Packets to transmit.
800 * Number of packets in array.
803 * Number of packets successfully transmitted (<= pkts_n).
806 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
808 struct txq *txq = (struct txq *)dpdk_txq;
809 uint16_t elts_head = txq->elts_head;
810 const uint16_t elts_n = 1 << txq->elts_n;
811 const uint16_t elts_m = elts_n - 1;
817 struct mlx5_mpw mpw = {
818 .state = MLX5_MPW_STATE_CLOSED,
821 if (unlikely(!pkts_n))
823 /* Prefetch first packet cacheline. */
824 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
825 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
826 /* Start processing. */
827 mlx5_tx_complete(txq);
828 max_elts = (elts_n - (elts_head - txq->elts_tail));
829 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
830 if (unlikely(!max_wqe))
833 struct rte_mbuf *buf = *(pkts++);
835 unsigned int segs_n = buf->nb_segs;
836 uint32_t cs_flags = 0;
839 * Make sure there is enough room to store this packet and
840 * that one ring entry remains unused.
843 if (max_elts < segs_n)
845 /* Do not bother with large packets MPW cannot handle. */
846 if (segs_n > MLX5_MPW_DSEG_MAX)
850 /* Should we enable HW CKSUM offload */
852 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
853 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
854 /* Retrieve packet information. */
855 length = PKT_LEN(buf);
857 /* Start new session if packet differs. */
858 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
859 ((mpw.len != length) ||
861 (mpw.wqe->eseg.cs_flags != cs_flags)))
862 mlx5_mpw_close(txq, &mpw);
863 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
865 * Multi-Packet WQE consumes at most two WQE.
866 * mlx5_mpw_new() expects to be able to use such
869 if (unlikely(max_wqe < 2))
872 mlx5_mpw_new(txq, &mpw, length);
873 mpw.wqe->eseg.cs_flags = cs_flags;
875 /* Multi-segment packets must be alone in their MPW. */
876 assert((segs_n == 1) || (mpw.pkts_n == 0));
877 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
881 volatile struct mlx5_wqe_data_seg *dseg;
885 (*txq->elts)[elts_head++ & elts_m] = buf;
886 dseg = mpw.data.dseg[mpw.pkts_n];
887 addr = rte_pktmbuf_mtod(buf, uintptr_t);
888 *dseg = (struct mlx5_wqe_data_seg){
889 .byte_count = htonl(DATA_LEN(buf)),
890 .lkey = mlx5_tx_mb2mr(txq, buf),
891 .addr = htonll(addr),
893 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
894 length += DATA_LEN(buf);
900 assert(length == mpw.len);
901 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
902 mlx5_mpw_close(txq, &mpw);
903 #ifdef MLX5_PMD_SOFT_COUNTERS
904 /* Increment sent bytes counter. */
905 txq->stats.obytes += length;
909 /* Take a shortcut if nothing must be sent. */
910 if (unlikely(i == 0))
912 /* Check whether completion threshold has been reached. */
913 /* "j" includes both packets and segments. */
914 comp = txq->elts_comp + j;
915 if (comp >= MLX5_TX_COMP_THRESH) {
916 volatile struct mlx5_wqe *wqe = mpw.wqe;
918 /* Request completion on last WQE. */
919 wqe->ctrl[2] = htonl(8);
920 /* Save elts_head in unused "immediate" field of WQE. */
921 wqe->ctrl[3] = elts_head;
924 txq->elts_comp = comp;
926 #ifdef MLX5_PMD_SOFT_COUNTERS
927 /* Increment sent packets counter. */
928 txq->stats.opackets += i;
930 /* Ring QP doorbell. */
931 if (mpw.state == MLX5_MPW_STATE_OPENED)
932 mlx5_mpw_close(txq, &mpw);
933 mlx5_tx_dbrec(txq, mpw.wqe);
934 txq->elts_head = elts_head;
939 * Open a MPW inline session.
942 * Pointer to TX queue structure.
944 * Pointer to MPW session structure.
949 mlx5_mpw_inline_new(struct txq *txq, struct mlx5_mpw *mpw, uint32_t length)
951 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
952 struct mlx5_wqe_inl_small *inl;
954 mpw->state = MLX5_MPW_INL_STATE_OPENED;
958 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
959 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_MPW << 24) |
962 mpw->wqe->ctrl[2] = 0;
963 mpw->wqe->ctrl[3] = 0;
964 mpw->wqe->eseg.mss = htons(length);
965 mpw->wqe->eseg.inline_hdr_sz = 0;
966 mpw->wqe->eseg.cs_flags = 0;
967 mpw->wqe->eseg.rsvd0 = 0;
968 mpw->wqe->eseg.rsvd1 = 0;
969 mpw->wqe->eseg.rsvd2 = 0;
970 inl = (struct mlx5_wqe_inl_small *)
971 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
972 mpw->data.raw = (uint8_t *)&inl->raw;
976 * Close a MPW inline session.
979 * Pointer to TX queue structure.
981 * Pointer to MPW session structure.
984 mlx5_mpw_inline_close(struct txq *txq, struct mlx5_mpw *mpw)
987 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
988 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
990 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
992 * Store size in multiple of 16 bytes. Control and Ethernet segments
995 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(size));
996 mpw->state = MLX5_MPW_STATE_CLOSED;
997 inl->byte_cnt = htonl(mpw->total_len | MLX5_INLINE_SEG);
998 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1002 * DPDK callback for TX with MPW inline support.
1005 * Generic pointer to TX queue structure.
1007 * Packets to transmit.
1009 * Number of packets in array.
1012 * Number of packets successfully transmitted (<= pkts_n).
1015 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1018 struct txq *txq = (struct txq *)dpdk_txq;
1019 uint16_t elts_head = txq->elts_head;
1020 const uint16_t elts_n = 1 << txq->elts_n;
1021 const uint16_t elts_m = elts_n - 1;
1027 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1028 struct mlx5_mpw mpw = {
1029 .state = MLX5_MPW_STATE_CLOSED,
1032 * Compute the maximum number of WQE which can be consumed by inline
1035 * - 1 control segment,
1036 * - 1 Ethernet segment,
1037 * - N Dseg from the inline request.
1039 const unsigned int wqe_inl_n =
1040 ((2 * MLX5_WQE_DWORD_SIZE +
1041 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1042 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1044 if (unlikely(!pkts_n))
1046 /* Prefetch first packet cacheline. */
1047 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1048 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1049 /* Start processing. */
1050 mlx5_tx_complete(txq);
1051 max_elts = (elts_n - (elts_head - txq->elts_tail));
1053 struct rte_mbuf *buf = *(pkts++);
1056 unsigned int segs_n = buf->nb_segs;
1057 uint32_t cs_flags = 0;
1060 * Make sure there is enough room to store this packet and
1061 * that one ring entry remains unused.
1064 if (max_elts < segs_n)
1066 /* Do not bother with large packets MPW cannot handle. */
1067 if (segs_n > MLX5_MPW_DSEG_MAX)
1072 * Compute max_wqe in case less WQE were consumed in previous
1075 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1076 /* Should we enable HW CKSUM offload */
1078 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1079 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1080 /* Retrieve packet information. */
1081 length = PKT_LEN(buf);
1082 /* Start new session if packet differs. */
1083 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1084 if ((mpw.len != length) ||
1086 (mpw.wqe->eseg.cs_flags != cs_flags))
1087 mlx5_mpw_close(txq, &mpw);
1088 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1089 if ((mpw.len != length) ||
1091 (length > inline_room) ||
1092 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1093 mlx5_mpw_inline_close(txq, &mpw);
1095 txq->max_inline * RTE_CACHE_LINE_SIZE;
1098 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1099 if ((segs_n != 1) ||
1100 (length > inline_room)) {
1102 * Multi-Packet WQE consumes at most two WQE.
1103 * mlx5_mpw_new() expects to be able to use
1106 if (unlikely(max_wqe < 2))
1109 mlx5_mpw_new(txq, &mpw, length);
1110 mpw.wqe->eseg.cs_flags = cs_flags;
1112 if (unlikely(max_wqe < wqe_inl_n))
1114 max_wqe -= wqe_inl_n;
1115 mlx5_mpw_inline_new(txq, &mpw, length);
1116 mpw.wqe->eseg.cs_flags = cs_flags;
1119 /* Multi-segment packets must be alone in their MPW. */
1120 assert((segs_n == 1) || (mpw.pkts_n == 0));
1121 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1122 assert(inline_room ==
1123 txq->max_inline * RTE_CACHE_LINE_SIZE);
1124 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1128 volatile struct mlx5_wqe_data_seg *dseg;
1131 (*txq->elts)[elts_head++ & elts_m] = buf;
1132 dseg = mpw.data.dseg[mpw.pkts_n];
1133 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1134 *dseg = (struct mlx5_wqe_data_seg){
1135 .byte_count = htonl(DATA_LEN(buf)),
1136 .lkey = mlx5_tx_mb2mr(txq, buf),
1137 .addr = htonll(addr),
1139 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1140 length += DATA_LEN(buf);
1146 assert(length == mpw.len);
1147 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1148 mlx5_mpw_close(txq, &mpw);
1152 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1153 assert(length <= inline_room);
1154 assert(length == DATA_LEN(buf));
1155 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1156 (*txq->elts)[elts_head++ & elts_m] = buf;
1157 /* Maximum number of bytes before wrapping. */
1158 max = ((((uintptr_t)(txq->wqes)) +
1161 (uintptr_t)mpw.data.raw);
1163 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1166 mpw.data.raw = (volatile void *)txq->wqes;
1167 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1168 (void *)(addr + max),
1170 mpw.data.raw += length - max;
1172 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1178 (volatile void *)txq->wqes;
1180 mpw.data.raw += length;
1183 mpw.total_len += length;
1185 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1186 mlx5_mpw_inline_close(txq, &mpw);
1188 txq->max_inline * RTE_CACHE_LINE_SIZE;
1190 inline_room -= length;
1193 #ifdef MLX5_PMD_SOFT_COUNTERS
1194 /* Increment sent bytes counter. */
1195 txq->stats.obytes += length;
1199 /* Take a shortcut if nothing must be sent. */
1200 if (unlikely(i == 0))
1202 /* Check whether completion threshold has been reached. */
1203 /* "j" includes both packets and segments. */
1204 comp = txq->elts_comp + j;
1205 if (comp >= MLX5_TX_COMP_THRESH) {
1206 volatile struct mlx5_wqe *wqe = mpw.wqe;
1208 /* Request completion on last WQE. */
1209 wqe->ctrl[2] = htonl(8);
1210 /* Save elts_head in unused "immediate" field of WQE. */
1211 wqe->ctrl[3] = elts_head;
1214 txq->elts_comp = comp;
1216 #ifdef MLX5_PMD_SOFT_COUNTERS
1217 /* Increment sent packets counter. */
1218 txq->stats.opackets += i;
1220 /* Ring QP doorbell. */
1221 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1222 mlx5_mpw_inline_close(txq, &mpw);
1223 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1224 mlx5_mpw_close(txq, &mpw);
1225 mlx5_tx_dbrec(txq, mpw.wqe);
1226 txq->elts_head = elts_head;
1231 * Open an Enhanced MPW session.
1234 * Pointer to TX queue structure.
1236 * Pointer to MPW session structure.
1241 mlx5_empw_new(struct txq *txq, struct mlx5_mpw *mpw, int padding)
1243 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1245 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1247 mpw->total_len = sizeof(struct mlx5_wqe);
1248 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1249 mpw->wqe->ctrl[0] = htonl((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1250 (txq->wqe_ci << 8) |
1251 MLX5_OPCODE_ENHANCED_MPSW);
1252 mpw->wqe->ctrl[2] = 0;
1253 mpw->wqe->ctrl[3] = 0;
1254 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1255 if (unlikely(padding)) {
1256 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1258 /* Pad the first 2 DWORDs with zero-length inline header. */
1259 *(volatile uint32_t *)addr = htonl(MLX5_INLINE_SEG);
1260 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1261 htonl(MLX5_INLINE_SEG);
1262 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1263 /* Start from the next WQEBB. */
1264 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1266 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1271 * Close an Enhanced MPW session.
1274 * Pointer to TX queue structure.
1276 * Pointer to MPW session structure.
1279 * Number of consumed WQEs.
1281 static inline uint16_t
1282 mlx5_empw_close(struct txq *txq, struct mlx5_mpw *mpw)
1286 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1289 mpw->wqe->ctrl[1] = htonl(txq->qp_num_8s | MLX5_WQE_DS(mpw->total_len));
1290 mpw->state = MLX5_MPW_STATE_CLOSED;
1291 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1297 * DPDK callback for TX with Enhanced MPW support.
1300 * Generic pointer to TX queue structure.
1302 * Packets to transmit.
1304 * Number of packets in array.
1307 * Number of packets successfully transmitted (<= pkts_n).
1310 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1312 struct txq *txq = (struct txq *)dpdk_txq;
1313 uint16_t elts_head = txq->elts_head;
1314 const uint16_t elts_n = 1 << txq->elts_n;
1315 const uint16_t elts_m = elts_n - 1;
1320 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1321 unsigned int mpw_room = 0;
1322 unsigned int inl_pad = 0;
1324 struct mlx5_mpw mpw = {
1325 .state = MLX5_MPW_STATE_CLOSED,
1328 if (unlikely(!pkts_n))
1330 /* Start processing. */
1331 mlx5_tx_complete(txq);
1332 max_elts = (elts_n - (elts_head - txq->elts_tail));
1333 /* A CQE slot must always be available. */
1334 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1335 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1336 if (unlikely(!max_wqe))
1339 struct rte_mbuf *buf = *(pkts++);
1343 unsigned int do_inline = 0; /* Whether inline is possible. */
1345 unsigned int segs_n = buf->nb_segs;
1346 uint32_t cs_flags = 0;
1349 * Make sure there is enough room to store this packet and
1350 * that one ring entry remains unused.
1353 if (max_elts - j < segs_n)
1355 /* Do not bother with large packets MPW cannot handle. */
1356 if (segs_n > MLX5_MPW_DSEG_MAX)
1358 /* Should we enable HW CKSUM offload. */
1360 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM))
1361 cs_flags = MLX5_ETH_WQE_L3_CSUM | MLX5_ETH_WQE_L4_CSUM;
1362 /* Retrieve packet information. */
1363 length = PKT_LEN(buf);
1364 /* Start new session if:
1365 * - multi-segment packet
1366 * - no space left even for a dseg
1367 * - next packet can be inlined with a new WQE
1369 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1372 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1373 if ((segs_n != 1) ||
1374 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1376 (length <= txq->inline_max_packet_sz &&
1377 inl_pad + sizeof(inl_hdr) + length >
1379 (mpw.wqe->eseg.cs_flags != cs_flags))
1380 max_wqe -= mlx5_empw_close(txq, &mpw);
1382 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1383 if (unlikely(segs_n != 1)) {
1384 /* Fall back to legacy MPW.
1385 * A MPW session consumes 2 WQEs at most to
1386 * include MLX5_MPW_DSEG_MAX pointers.
1388 if (unlikely(max_wqe < 2))
1390 mlx5_mpw_new(txq, &mpw, length);
1392 /* In Enhanced MPW, inline as much as the budget
1393 * is allowed. The remaining space is to be
1394 * filled with dsegs. If the title WQEBB isn't
1395 * padded, it will have 2 dsegs there.
1397 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1398 (max_inline ? max_inline :
1399 pkts_n * MLX5_WQE_DWORD_SIZE) +
1401 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1404 /* Don't pad the title WQEBB to not waste WQ. */
1405 mlx5_empw_new(txq, &mpw, 0);
1406 mpw_room -= mpw.total_len;
1409 length <= txq->inline_max_packet_sz &&
1410 sizeof(inl_hdr) + length <= mpw_room &&
1413 mpw.wqe->eseg.cs_flags = cs_flags;
1415 /* Evaluate whether the next packet can be inlined.
1416 * Inlininig is possible when:
1417 * - length is less than configured value
1418 * - length fits for remaining space
1419 * - not required to fill the title WQEBB with dsegs
1422 length <= txq->inline_max_packet_sz &&
1423 inl_pad + sizeof(inl_hdr) + length <=
1425 (!txq->mpw_hdr_dseg ||
1426 mpw.total_len >= MLX5_WQE_SIZE);
1428 /* Multi-segment packets must be alone in their MPW. */
1429 assert((segs_n == 1) || (mpw.pkts_n == 0));
1430 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1431 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1435 volatile struct mlx5_wqe_data_seg *dseg;
1438 (*txq->elts)[elts_head++ & elts_m] = buf;
1439 dseg = mpw.data.dseg[mpw.pkts_n];
1440 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1441 *dseg = (struct mlx5_wqe_data_seg){
1442 .byte_count = htonl(DATA_LEN(buf)),
1443 .lkey = mlx5_tx_mb2mr(txq, buf),
1444 .addr = htonll(addr),
1446 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1447 length += DATA_LEN(buf);
1453 /* A multi-segmented packet takes one MPW session.
1454 * TODO: Pack more multi-segmented packets if possible.
1456 mlx5_mpw_close(txq, &mpw);
1461 } else if (do_inline) {
1462 /* Inline packet into WQE. */
1465 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1466 assert(length == DATA_LEN(buf));
1467 inl_hdr = htonl(length | MLX5_INLINE_SEG);
1468 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1469 mpw.data.raw = (volatile void *)
1470 ((uintptr_t)mpw.data.raw + inl_pad);
1471 max = tx_mlx5_wq_tailroom(txq,
1472 (void *)(uintptr_t)mpw.data.raw);
1473 /* Copy inline header. */
1474 mpw.data.raw = (volatile void *)
1476 (void *)(uintptr_t)mpw.data.raw,
1479 (void *)(uintptr_t)txq->wqes,
1481 max = tx_mlx5_wq_tailroom(txq,
1482 (void *)(uintptr_t)mpw.data.raw);
1483 /* Copy packet data. */
1484 mpw.data.raw = (volatile void *)
1486 (void *)(uintptr_t)mpw.data.raw,
1489 (void *)(uintptr_t)txq->wqes,
1492 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1493 /* No need to get completion as the entire packet is
1494 * copied to WQ. Free the buf right away.
1496 rte_pktmbuf_free_seg(buf);
1497 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1498 /* Add pad in the next packet if any. */
1499 inl_pad = (((uintptr_t)mpw.data.raw +
1500 (MLX5_WQE_DWORD_SIZE - 1)) &
1501 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1502 (uintptr_t)mpw.data.raw;
1504 /* No inline. Load a dseg of packet pointer. */
1505 volatile rte_v128u32_t *dseg;
1507 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1508 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1509 assert(length == DATA_LEN(buf));
1510 if (!tx_mlx5_wq_tailroom(txq,
1511 (void *)((uintptr_t)mpw.data.raw
1513 dseg = (volatile void *)txq->wqes;
1515 dseg = (volatile void *)
1516 ((uintptr_t)mpw.data.raw +
1518 (*txq->elts)[elts_head++ & elts_m] = buf;
1519 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1520 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1521 rte_prefetch2((void *)(addr +
1522 n * RTE_CACHE_LINE_SIZE));
1523 naddr = htonll(addr);
1524 *dseg = (rte_v128u32_t) {
1526 mlx5_tx_mb2mr(txq, buf),
1530 mpw.data.raw = (volatile void *)(dseg + 1);
1531 mpw.total_len += (inl_pad + sizeof(*dseg));
1534 mpw_room -= (inl_pad + sizeof(*dseg));
1537 #ifdef MLX5_PMD_SOFT_COUNTERS
1538 /* Increment sent bytes counter. */
1539 txq->stats.obytes += length;
1542 } while (i < pkts_n);
1543 /* Take a shortcut if nothing must be sent. */
1544 if (unlikely(i == 0))
1546 /* Check whether completion threshold has been reached. */
1547 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1548 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1549 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1550 volatile struct mlx5_wqe *wqe = mpw.wqe;
1552 /* Request completion on last WQE. */
1553 wqe->ctrl[2] = htonl(8);
1554 /* Save elts_head in unused "immediate" field of WQE. */
1555 wqe->ctrl[3] = elts_head;
1557 txq->mpw_comp = txq->wqe_ci;
1560 txq->elts_comp += j;
1562 #ifdef MLX5_PMD_SOFT_COUNTERS
1563 /* Increment sent packets counter. */
1564 txq->stats.opackets += i;
1566 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1567 mlx5_empw_close(txq, &mpw);
1568 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1569 mlx5_mpw_close(txq, &mpw);
1570 /* Ring QP doorbell. */
1571 mlx5_tx_dbrec(txq, mpw.wqe);
1572 txq->elts_head = elts_head;
1577 * Translate RX completion flags to packet type.
1582 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1585 * Packet type for struct rte_mbuf.
1587 static inline uint32_t
1588 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1591 uint8_t pinfo = cqe->pkt_info;
1592 uint16_t ptype = cqe->hdr_type_etc;
1595 * The index to the array should have:
1596 * bit[1:0] = l3_hdr_type
1597 * bit[4:2] = l4_hdr_type
1600 * bit[7] = outer_l3_type
1602 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1603 return mlx5_ptype_table[idx];
1607 * Get size of the next packet for a given CQE. For compressed CQEs, the
1608 * consumer index is updated only once all packets of the current one have
1612 * Pointer to RX queue.
1615 * @param[out] rss_hash
1616 * Packet RSS Hash result.
1619 * Packet size in bytes (0 if there is none), -1 in case of completion
1623 mlx5_rx_poll_len(struct rxq *rxq, volatile struct mlx5_cqe *cqe,
1624 uint16_t cqe_cnt, uint32_t *rss_hash)
1626 struct rxq_zip *zip = &rxq->zip;
1627 uint16_t cqe_n = cqe_cnt + 1;
1631 /* Process compressed data in the CQE and mini arrays. */
1633 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1634 (volatile struct mlx5_mini_cqe8 (*)[8])
1635 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1637 len = ntohl((*mc)[zip->ai & 7].byte_cnt);
1638 *rss_hash = ntohl((*mc)[zip->ai & 7].rx_hash_result);
1639 if ((++zip->ai & 7) == 0) {
1640 /* Invalidate consumed CQEs */
1643 while (idx != end) {
1644 (*rxq->cqes)[idx & cqe_cnt].op_own =
1645 MLX5_CQE_INVALIDATE;
1649 * Increment consumer index to skip the number of
1650 * CQEs consumed. Hardware leaves holes in the CQ
1651 * ring for software use.
1656 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1657 /* Invalidate the rest */
1661 while (idx != end) {
1662 (*rxq->cqes)[idx & cqe_cnt].op_own =
1663 MLX5_CQE_INVALIDATE;
1666 rxq->cq_ci = zip->cq_ci;
1669 /* No compressed data, get next CQE and verify if it is compressed. */
1674 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1675 if (unlikely(ret == 1))
1678 op_own = cqe->op_own;
1679 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1680 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1681 (volatile struct mlx5_mini_cqe8 (*)[8])
1682 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1685 /* Fix endianness. */
1686 zip->cqe_cnt = ntohl(cqe->byte_cnt);
1688 * Current mini array position is the one returned by
1691 * If completion comprises several mini arrays, as a
1692 * special case the second one is located 7 CQEs after
1693 * the initial CQE instead of 8 for subsequent ones.
1695 zip->ca = rxq->cq_ci;
1696 zip->na = zip->ca + 7;
1697 /* Compute the next non compressed CQE. */
1699 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1700 /* Get packet size to return. */
1701 len = ntohl((*mc)[0].byte_cnt);
1702 *rss_hash = ntohl((*mc)[0].rx_hash_result);
1704 /* Prefetch all the entries to be invalidated */
1707 while (idx != end) {
1708 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1712 len = ntohl(cqe->byte_cnt);
1713 *rss_hash = ntohl(cqe->rx_hash_res);
1715 /* Error while receiving packet. */
1716 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1723 * Translate RX completion flags to offload flags.
1726 * Pointer to RX queue structure.
1731 * Offload flags (ol_flags) for struct rte_mbuf.
1733 static inline uint32_t
1734 rxq_cq_to_ol_flags(struct rxq *rxq, volatile struct mlx5_cqe *cqe)
1736 uint32_t ol_flags = 0;
1737 uint16_t flags = ntohs(cqe->hdr_type_etc);
1741 MLX5_CQE_RX_L3_HDR_VALID,
1742 PKT_RX_IP_CKSUM_GOOD) |
1744 MLX5_CQE_RX_L4_HDR_VALID,
1745 PKT_RX_L4_CKSUM_GOOD);
1746 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1749 MLX5_CQE_RX_L3_HDR_VALID,
1750 PKT_RX_IP_CKSUM_GOOD) |
1752 MLX5_CQE_RX_L4_HDR_VALID,
1753 PKT_RX_L4_CKSUM_GOOD);
1758 * DPDK callback for RX.
1761 * Generic pointer to RX queue structure.
1763 * Array to store received packets.
1765 * Maximum number of packets in array.
1768 * Number of packets successfully received (<= pkts_n).
1771 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1773 struct rxq *rxq = dpdk_rxq;
1774 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1775 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1776 const unsigned int sges_n = rxq->sges_n;
1777 struct rte_mbuf *pkt = NULL;
1778 struct rte_mbuf *seg = NULL;
1779 volatile struct mlx5_cqe *cqe =
1780 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1782 unsigned int rq_ci = rxq->rq_ci << sges_n;
1783 int len = 0; /* keep its value across iterations. */
1786 unsigned int idx = rq_ci & wqe_cnt;
1787 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1788 struct rte_mbuf *rep = (*rxq->elts)[idx];
1789 uint32_t rss_hash_res = 0;
1797 rep = rte_mbuf_raw_alloc(rxq->mp);
1798 if (unlikely(rep == NULL)) {
1799 ++rxq->stats.rx_nombuf;
1802 * no buffers before we even started,
1803 * bail out silently.
1807 while (pkt != seg) {
1808 assert(pkt != (*rxq->elts)[idx]);
1812 rte_mbuf_raw_free(pkt);
1818 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1819 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1822 rte_mbuf_raw_free(rep);
1825 if (unlikely(len == -1)) {
1826 /* RX error, packet is likely too large. */
1827 rte_mbuf_raw_free(rep);
1828 ++rxq->stats.idropped;
1832 assert(len >= (rxq->crc_present << 2));
1833 /* Update packet information. */
1834 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1836 if (rss_hash_res && rxq->rss_hash) {
1837 pkt->hash.rss = rss_hash_res;
1838 pkt->ol_flags = PKT_RX_RSS_HASH;
1841 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1842 pkt->ol_flags |= PKT_RX_FDIR;
1843 if (cqe->sop_drop_qpn !=
1844 htonl(MLX5_FLOW_MARK_DEFAULT)) {
1845 uint32_t mark = cqe->sop_drop_qpn;
1847 pkt->ol_flags |= PKT_RX_FDIR_ID;
1849 mlx5_flow_mark_get(mark);
1852 if (rxq->csum | rxq->csum_l2tun)
1853 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1854 if (rxq->vlan_strip &&
1855 (cqe->hdr_type_etc &
1856 htons(MLX5_CQE_VLAN_STRIPPED))) {
1857 pkt->ol_flags |= PKT_RX_VLAN_PKT |
1858 PKT_RX_VLAN_STRIPPED;
1859 pkt->vlan_tci = ntohs(cqe->vlan_info);
1861 if (rxq->crc_present)
1862 len -= ETHER_CRC_LEN;
1865 DATA_LEN(rep) = DATA_LEN(seg);
1866 PKT_LEN(rep) = PKT_LEN(seg);
1867 SET_DATA_OFF(rep, DATA_OFF(seg));
1868 PORT(rep) = PORT(seg);
1869 (*rxq->elts)[idx] = rep;
1871 * Fill NIC descriptor with the new buffer. The lkey and size
1872 * of the buffers are already known, only the buffer address
1875 wqe->addr = htonll(rte_pktmbuf_mtod(rep, uintptr_t));
1876 if (len > DATA_LEN(seg)) {
1877 len -= DATA_LEN(seg);
1882 DATA_LEN(seg) = len;
1883 #ifdef MLX5_PMD_SOFT_COUNTERS
1884 /* Increment bytes counter. */
1885 rxq->stats.ibytes += PKT_LEN(pkt);
1887 /* Return packet. */
1893 /* Align consumer index to the next stride. */
1898 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1900 /* Update the consumer index. */
1901 rxq->rq_ci = rq_ci >> sges_n;
1903 *rxq->cq_db = htonl(rxq->cq_ci);
1905 *rxq->rq_db = htonl(rxq->rq_ci);
1906 #ifdef MLX5_PMD_SOFT_COUNTERS
1907 /* Increment packets counter. */
1908 rxq->stats.ipackets += i;
1914 * Dummy DPDK callback for TX.
1916 * This function is used to temporarily replace the real callback during
1917 * unsafe control operations on the queue, or in case of error.
1920 * Generic pointer to TX queue structure.
1922 * Packets to transmit.
1924 * Number of packets in array.
1927 * Number of packets successfully transmitted (<= pkts_n).
1930 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1939 * Dummy DPDK callback for RX.
1941 * This function is used to temporarily replace the real callback during
1942 * unsafe control operations on the queue, or in case of error.
1945 * Generic pointer to RX queue structure.
1947 * Array to store received packets.
1949 * Maximum number of packets in array.
1952 * Number of packets successfully received (<= pkts_n).
1955 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1964 * Vectorized Rx/Tx routines are not compiled in when required vector
1965 * instructions are not supported on a target architecture. The following null
1966 * stubs are needed for linkage when those are not included outside of this file
1967 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1970 uint16_t __attribute__((weak))
1971 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1979 uint16_t __attribute__((weak))
1980 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1988 uint16_t __attribute__((weak))
1989 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1997 int __attribute__((weak))
1998 priv_check_raw_vec_tx_support(struct priv *priv)
2004 int __attribute__((weak))
2005 priv_check_vec_tx_support(struct priv *priv)
2011 int __attribute__((weak))
2012 rxq_check_vec_support(struct rxq *rxq)
2018 int __attribute__((weak))
2019 priv_check_vec_rx_support(struct priv *priv)