1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, uint32_t *rss_hash);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
46 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
47 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
51 * Build a table to translate Rx completion flags to packet type.
53 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
56 mlx5_set_ptype_table(void)
59 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
61 /* Last entry must not be overwritten, reserved for errored packet. */
62 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
63 (*p)[i] = RTE_PTYPE_UNKNOWN;
65 * The index to the array should have:
66 * bit[1:0] = l3_hdr_type
67 * bit[4:2] = l4_hdr_type
70 * bit[7] = outer_l3_type
73 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
75 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
77 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
80 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
82 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
85 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
87 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
89 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
91 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
93 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
95 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
98 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
100 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
102 /* Repeat with outer_l3_type being set. Just in case. */
103 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
107 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
109 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
111 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
113 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
115 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
117 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
119 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
121 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
123 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
125 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
128 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
129 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
130 RTE_PTYPE_INNER_L4_NONFRAG;
131 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
132 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
133 RTE_PTYPE_INNER_L4_NONFRAG;
134 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
135 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
136 RTE_PTYPE_INNER_L4_NONFRAG;
137 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
138 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
139 RTE_PTYPE_INNER_L4_NONFRAG;
140 /* Tunneled - Fragmented */
141 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
143 RTE_PTYPE_INNER_L4_FRAG;
144 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
146 RTE_PTYPE_INNER_L4_FRAG;
147 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L4_FRAG;
150 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L4_FRAG;
154 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
156 RTE_PTYPE_INNER_L4_TCP;
157 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L4_TCP;
160 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
162 RTE_PTYPE_INNER_L4_TCP;
163 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L4_TCP;
166 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
191 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
193 RTE_PTYPE_INNER_L4_UDP;
194 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L4_UDP;
197 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
199 RTE_PTYPE_INNER_L4_UDP;
200 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
202 RTE_PTYPE_INNER_L4_UDP;
206 * Return the size of tailroom of WQ.
209 * Pointer to TX queue structure.
211 * Pointer to tail of WQ.
217 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
220 tailroom = (uintptr_t)(txq->wqes) +
221 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
227 * Copy data to tailroom of circular queue.
230 * Pointer to destination.
234 * Number of bytes to copy.
236 * Pointer to head of queue.
238 * Size of tailroom from dst.
241 * Pointer after copied data.
244 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
245 void *base, size_t tailroom)
250 rte_memcpy(dst, src, tailroom);
251 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
253 ret = (uint8_t *)base + n - tailroom;
255 rte_memcpy(dst, src, n);
256 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
262 * DPDK callback to check the status of a tx descriptor.
267 * The index of the descriptor in the ring.
270 * The status of the tx descriptor.
273 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
275 struct mlx5_txq_data *txq = tx_queue;
278 mlx5_tx_complete(txq);
279 used = txq->elts_head - txq->elts_tail;
281 return RTE_ETH_TX_DESC_FULL;
282 return RTE_ETH_TX_DESC_DONE;
286 * DPDK callback to check the status of a rx descriptor.
291 * The index of the descriptor in the ring.
294 * The status of the tx descriptor.
297 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
299 struct mlx5_rxq_data *rxq = rx_queue;
300 struct rxq_zip *zip = &rxq->zip;
301 volatile struct mlx5_cqe *cqe;
302 const unsigned int cqe_n = (1 << rxq->cqe_n);
303 const unsigned int cqe_cnt = cqe_n - 1;
307 /* if we are processing a compressed cqe */
309 used = zip->cqe_cnt - zip->ca;
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
316 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
320 op_own = cqe->op_own;
321 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
322 n = rte_be_to_cpu_32(cqe->byte_cnt);
327 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
329 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
331 return RTE_ETH_RX_DESC_DONE;
332 return RTE_ETH_RX_DESC_AVAIL;
336 * DPDK callback for TX.
339 * Generic pointer to TX queue structure.
341 * Packets to transmit.
343 * Number of packets in array.
346 * Number of packets successfully transmitted (<= pkts_n).
349 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
351 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
352 uint16_t elts_head = txq->elts_head;
353 const uint16_t elts_n = 1 << txq->elts_n;
354 const uint16_t elts_m = elts_n - 1;
361 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
362 unsigned int segs_n = 0;
363 const unsigned int max_inline = txq->max_inline;
365 if (unlikely(!pkts_n))
367 /* Prefetch first packet cacheline. */
368 rte_prefetch0(*pkts);
369 /* Start processing. */
370 mlx5_tx_complete(txq);
371 max_elts = (elts_n - (elts_head - txq->elts_tail));
372 /* A CQE slot must always be available. */
373 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
374 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
375 if (unlikely(!max_wqe))
378 struct rte_mbuf *buf = NULL;
380 volatile struct mlx5_wqe_v *wqe = NULL;
381 volatile rte_v128u32_t *dseg = NULL;
384 unsigned int sg = 0; /* counter of additional segs attached. */
386 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
387 uint16_t tso_header_sz = 0;
391 uint16_t tso_segsz = 0;
392 #ifdef MLX5_PMD_SOFT_COUNTERS
393 uint32_t total_length = 0;
398 segs_n = buf->nb_segs;
400 * Make sure there is enough room to store this packet and
401 * that one ring entry remains unused.
404 if (max_elts < segs_n)
408 if (unlikely(--max_wqe == 0))
410 wqe = (volatile struct mlx5_wqe_v *)
411 tx_mlx5_wqe(txq, txq->wqe_ci);
412 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
414 rte_prefetch0(*(pkts + 1));
415 addr = rte_pktmbuf_mtod(buf, uintptr_t);
416 length = DATA_LEN(buf);
417 ehdr = (((uint8_t *)addr)[1] << 8) |
418 ((uint8_t *)addr)[0];
419 #ifdef MLX5_PMD_SOFT_COUNTERS
420 total_length = length;
422 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
423 txq->stats.oerrors++;
426 /* Update element. */
427 (*txq->elts)[elts_head & elts_m] = buf;
428 /* Prefetch next buffer data. */
431 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
432 cs_flags = txq_ol_cksum_to_cs(txq, buf);
433 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
434 /* Replace the Ethernet type by the VLAN if necessary. */
435 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
436 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
438 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
442 /* Copy Destination and source mac address. */
443 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
445 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
446 /* Copy missing two bytes to end the DSeg. */
447 memcpy((uint8_t *)raw + len + sizeof(vlan),
448 ((uint8_t *)addr) + len, 2);
452 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
453 MLX5_WQE_DWORD_SIZE);
454 length -= pkt_inline_sz;
455 addr += pkt_inline_sz;
457 raw += MLX5_WQE_DWORD_SIZE;
458 tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
461 (uintptr_t)(((uintptr_t)txq->wqes) +
462 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
465 (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
466 const uint64_t is_tunneled =
467 buf->ol_flags & (PKT_TX_TUNNEL_GRE |
468 PKT_TX_TUNNEL_VXLAN);
470 tso_header_sz = buf->l2_len + vlan_sz +
471 buf->l3_len + buf->l4_len;
472 tso_segsz = buf->tso_segsz;
473 if (unlikely(tso_segsz == 0)) {
474 txq->stats.oerrors++;
477 if (is_tunneled && txq->tunnel_en) {
478 tso_header_sz += buf->outer_l2_len +
480 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
482 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
484 if (unlikely(tso_header_sz > MLX5_MAX_TSO_HEADER)) {
485 txq->stats.oerrors++;
488 copy_b = tso_header_sz - pkt_inline_sz;
489 /* First seg must contain all headers. */
490 assert(copy_b <= length);
491 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
492 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
494 if (unlikely(max_wqe < n))
497 rte_memcpy((void *)raw, (void *)addr, copy_b);
500 /* Include padding for TSO header. */
501 copy_b = MLX5_WQE_DS(copy_b) *
503 pkt_inline_sz += copy_b;
507 wqe->ctrl = (rte_v128u32_t){
508 rte_cpu_to_be_32(txq->wqe_ci << 8),
509 rte_cpu_to_be_32(txq->qp_num_8s | 1),
514 #ifdef MLX5_PMD_SOFT_COUNTERS
521 /* Inline if enough room. */
522 if (max_inline || tso) {
524 uintptr_t end = (uintptr_t)
525 (((uintptr_t)txq->wqes) +
526 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
527 unsigned int inline_room = max_inline *
528 RTE_CACHE_LINE_SIZE -
529 (pkt_inline_sz - 2) -
535 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
536 RTE_CACHE_LINE_SIZE);
537 copy_b = (addr_end > addr) ?
538 RTE_MIN((addr_end - addr), length) : 0;
539 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
541 * One Dseg remains in the current WQE. To
542 * keep the computation positive, it is
543 * removed after the bytes to Dseg conversion.
545 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
547 if (unlikely(max_wqe < n))
551 inl = rte_cpu_to_be_32(copy_b |
553 rte_memcpy((void *)raw,
554 (void *)&inl, sizeof(inl));
556 pkt_inline_sz += sizeof(inl);
558 rte_memcpy((void *)raw, (void *)addr, copy_b);
561 pkt_inline_sz += copy_b;
564 * 2 DWORDs consumed by the WQE header + ETH segment +
565 * the size of the inline part of the packet.
567 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
569 if (ds % (MLX5_WQE_SIZE /
570 MLX5_WQE_DWORD_SIZE) == 0) {
571 if (unlikely(--max_wqe == 0))
573 dseg = (volatile rte_v128u32_t *)
574 tx_mlx5_wqe(txq, txq->wqe_ci +
577 dseg = (volatile rte_v128u32_t *)
579 (ds * MLX5_WQE_DWORD_SIZE));
582 } else if (!segs_n) {
586 inline_room -= copy_b;
590 addr = rte_pktmbuf_mtod(buf, uintptr_t);
591 length = DATA_LEN(buf);
592 #ifdef MLX5_PMD_SOFT_COUNTERS
593 total_length += length;
595 (*txq->elts)[++elts_head & elts_m] = buf;
600 * No inline has been done in the packet, only the
601 * Ethernet Header as been stored.
603 dseg = (volatile rte_v128u32_t *)
604 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
607 /* Add the remaining packet as a simple ds. */
608 addr = rte_cpu_to_be_64(addr);
609 *dseg = (rte_v128u32_t){
610 rte_cpu_to_be_32(length),
611 mlx5_tx_mb2mr(txq, buf),
624 * Spill on next WQE when the current one does not have
625 * enough room left. Size of WQE must a be a multiple
626 * of data segment size.
628 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
629 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
630 if (unlikely(--max_wqe == 0))
632 dseg = (volatile rte_v128u32_t *)
633 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
634 rte_prefetch0(tx_mlx5_wqe(txq,
635 txq->wqe_ci + ds / 4 + 1));
642 length = DATA_LEN(buf);
643 #ifdef MLX5_PMD_SOFT_COUNTERS
644 total_length += length;
646 /* Store segment information. */
647 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
648 *dseg = (rte_v128u32_t){
649 rte_cpu_to_be_32(length),
650 mlx5_tx_mb2mr(txq, buf),
654 (*txq->elts)[++elts_head & elts_m] = buf;
658 if (ds > MLX5_DSEG_MAX) {
659 txq->stats.oerrors++;
666 /* Initialize known and common part of the WQE structure. */
668 wqe->ctrl = (rte_v128u32_t){
669 rte_cpu_to_be_32((txq->wqe_ci << 8) |
671 rte_cpu_to_be_32(txq->qp_num_8s | ds),
675 wqe->eseg = (rte_v128u32_t){
677 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
679 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
682 wqe->ctrl = (rte_v128u32_t){
683 rte_cpu_to_be_32((txq->wqe_ci << 8) |
685 rte_cpu_to_be_32(txq->qp_num_8s | ds),
689 wqe->eseg = (rte_v128u32_t){
693 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
697 txq->wqe_ci += (ds + 3) / 4;
698 /* Save the last successful WQE for completion request */
699 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
700 #ifdef MLX5_PMD_SOFT_COUNTERS
701 /* Increment sent bytes counter. */
702 txq->stats.obytes += total_length;
704 } while (i < pkts_n);
705 /* Take a shortcut if nothing must be sent. */
706 if (unlikely((i + k) == 0))
708 txq->elts_head += (i + j);
709 /* Check whether completion threshold has been reached. */
710 comp = txq->elts_comp + i + j + k;
711 if (comp >= MLX5_TX_COMP_THRESH) {
712 /* Request completion on last WQE. */
713 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
714 /* Save elts_head in unused "immediate" field of WQE. */
715 last_wqe->ctrl3 = txq->elts_head;
721 txq->elts_comp = comp;
723 #ifdef MLX5_PMD_SOFT_COUNTERS
724 /* Increment sent packets counter. */
725 txq->stats.opackets += i;
727 /* Ring QP doorbell. */
728 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
733 * Open a MPW session.
736 * Pointer to TX queue structure.
738 * Pointer to MPW session structure.
743 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
745 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
746 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
747 (volatile struct mlx5_wqe_data_seg (*)[])
748 tx_mlx5_wqe(txq, idx + 1);
750 mpw->state = MLX5_MPW_STATE_OPENED;
754 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
755 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
756 mpw->wqe->eseg.inline_hdr_sz = 0;
757 mpw->wqe->eseg.rsvd0 = 0;
758 mpw->wqe->eseg.rsvd1 = 0;
759 mpw->wqe->eseg.rsvd2 = 0;
760 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
763 mpw->wqe->ctrl[2] = 0;
764 mpw->wqe->ctrl[3] = 0;
765 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
766 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
767 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
768 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
769 mpw->data.dseg[2] = &(*dseg)[0];
770 mpw->data.dseg[3] = &(*dseg)[1];
771 mpw->data.dseg[4] = &(*dseg)[2];
775 * Close a MPW session.
778 * Pointer to TX queue structure.
780 * Pointer to MPW session structure.
783 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
785 unsigned int num = mpw->pkts_n;
788 * Store size in multiple of 16 bytes. Control and Ethernet segments
791 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
792 mpw->state = MLX5_MPW_STATE_CLOSED;
797 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
798 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
802 * DPDK callback for TX with MPW support.
805 * Generic pointer to TX queue structure.
807 * Packets to transmit.
809 * Number of packets in array.
812 * Number of packets successfully transmitted (<= pkts_n).
815 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
817 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
818 uint16_t elts_head = txq->elts_head;
819 const uint16_t elts_n = 1 << txq->elts_n;
820 const uint16_t elts_m = elts_n - 1;
826 struct mlx5_mpw mpw = {
827 .state = MLX5_MPW_STATE_CLOSED,
830 if (unlikely(!pkts_n))
832 /* Prefetch first packet cacheline. */
833 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
834 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
835 /* Start processing. */
836 mlx5_tx_complete(txq);
837 max_elts = (elts_n - (elts_head - txq->elts_tail));
838 /* A CQE slot must always be available. */
839 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
840 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
841 if (unlikely(!max_wqe))
844 struct rte_mbuf *buf = *(pkts++);
846 unsigned int segs_n = buf->nb_segs;
850 * Make sure there is enough room to store this packet and
851 * that one ring entry remains unused.
854 if (max_elts < segs_n)
856 /* Do not bother with large packets MPW cannot handle. */
857 if (segs_n > MLX5_MPW_DSEG_MAX) {
858 txq->stats.oerrors++;
863 cs_flags = txq_ol_cksum_to_cs(txq, buf);
864 /* Retrieve packet information. */
865 length = PKT_LEN(buf);
867 /* Start new session if packet differs. */
868 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
869 ((mpw.len != length) ||
871 (mpw.wqe->eseg.cs_flags != cs_flags)))
872 mlx5_mpw_close(txq, &mpw);
873 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
875 * Multi-Packet WQE consumes at most two WQE.
876 * mlx5_mpw_new() expects to be able to use such
879 if (unlikely(max_wqe < 2))
882 mlx5_mpw_new(txq, &mpw, length);
883 mpw.wqe->eseg.cs_flags = cs_flags;
885 /* Multi-segment packets must be alone in their MPW. */
886 assert((segs_n == 1) || (mpw.pkts_n == 0));
887 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
891 volatile struct mlx5_wqe_data_seg *dseg;
895 (*txq->elts)[elts_head++ & elts_m] = buf;
896 dseg = mpw.data.dseg[mpw.pkts_n];
897 addr = rte_pktmbuf_mtod(buf, uintptr_t);
898 *dseg = (struct mlx5_wqe_data_seg){
899 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
900 .lkey = mlx5_tx_mb2mr(txq, buf),
901 .addr = rte_cpu_to_be_64(addr),
903 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
904 length += DATA_LEN(buf);
910 assert(length == mpw.len);
911 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
912 mlx5_mpw_close(txq, &mpw);
913 #ifdef MLX5_PMD_SOFT_COUNTERS
914 /* Increment sent bytes counter. */
915 txq->stats.obytes += length;
919 /* Take a shortcut if nothing must be sent. */
920 if (unlikely(i == 0))
922 /* Check whether completion threshold has been reached. */
923 /* "j" includes both packets and segments. */
924 comp = txq->elts_comp + j;
925 if (comp >= MLX5_TX_COMP_THRESH) {
926 volatile struct mlx5_wqe *wqe = mpw.wqe;
928 /* Request completion on last WQE. */
929 wqe->ctrl[2] = rte_cpu_to_be_32(8);
930 /* Save elts_head in unused "immediate" field of WQE. */
931 wqe->ctrl[3] = elts_head;
937 txq->elts_comp = comp;
939 #ifdef MLX5_PMD_SOFT_COUNTERS
940 /* Increment sent packets counter. */
941 txq->stats.opackets += i;
943 /* Ring QP doorbell. */
944 if (mpw.state == MLX5_MPW_STATE_OPENED)
945 mlx5_mpw_close(txq, &mpw);
946 mlx5_tx_dbrec(txq, mpw.wqe);
947 txq->elts_head = elts_head;
952 * Open a MPW inline session.
955 * Pointer to TX queue structure.
957 * Pointer to MPW session structure.
962 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
965 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
966 struct mlx5_wqe_inl_small *inl;
968 mpw->state = MLX5_MPW_INL_STATE_OPENED;
972 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
973 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
976 mpw->wqe->ctrl[2] = 0;
977 mpw->wqe->ctrl[3] = 0;
978 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
979 mpw->wqe->eseg.inline_hdr_sz = 0;
980 mpw->wqe->eseg.cs_flags = 0;
981 mpw->wqe->eseg.rsvd0 = 0;
982 mpw->wqe->eseg.rsvd1 = 0;
983 mpw->wqe->eseg.rsvd2 = 0;
984 inl = (struct mlx5_wqe_inl_small *)
985 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
986 mpw->data.raw = (uint8_t *)&inl->raw;
990 * Close a MPW inline session.
993 * Pointer to TX queue structure.
995 * Pointer to MPW session structure.
998 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1001 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1002 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1004 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1006 * Store size in multiple of 16 bytes. Control and Ethernet segments
1009 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1011 mpw->state = MLX5_MPW_STATE_CLOSED;
1012 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1013 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1017 * DPDK callback for TX with MPW inline support.
1020 * Generic pointer to TX queue structure.
1022 * Packets to transmit.
1024 * Number of packets in array.
1027 * Number of packets successfully transmitted (<= pkts_n).
1030 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1033 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1034 uint16_t elts_head = txq->elts_head;
1035 const uint16_t elts_n = 1 << txq->elts_n;
1036 const uint16_t elts_m = elts_n - 1;
1042 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1043 struct mlx5_mpw mpw = {
1044 .state = MLX5_MPW_STATE_CLOSED,
1047 * Compute the maximum number of WQE which can be consumed by inline
1050 * - 1 control segment,
1051 * - 1 Ethernet segment,
1052 * - N Dseg from the inline request.
1054 const unsigned int wqe_inl_n =
1055 ((2 * MLX5_WQE_DWORD_SIZE +
1056 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1057 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1059 if (unlikely(!pkts_n))
1061 /* Prefetch first packet cacheline. */
1062 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1063 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1064 /* Start processing. */
1065 mlx5_tx_complete(txq);
1066 max_elts = (elts_n - (elts_head - txq->elts_tail));
1067 /* A CQE slot must always be available. */
1068 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1070 struct rte_mbuf *buf = *(pkts++);
1073 unsigned int segs_n = buf->nb_segs;
1077 * Make sure there is enough room to store this packet and
1078 * that one ring entry remains unused.
1081 if (max_elts < segs_n)
1083 /* Do not bother with large packets MPW cannot handle. */
1084 if (segs_n > MLX5_MPW_DSEG_MAX) {
1085 txq->stats.oerrors++;
1091 * Compute max_wqe in case less WQE were consumed in previous
1094 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1095 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1096 /* Retrieve packet information. */
1097 length = PKT_LEN(buf);
1098 /* Start new session if packet differs. */
1099 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1100 if ((mpw.len != length) ||
1102 (mpw.wqe->eseg.cs_flags != cs_flags))
1103 mlx5_mpw_close(txq, &mpw);
1104 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1105 if ((mpw.len != length) ||
1107 (length > inline_room) ||
1108 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1109 mlx5_mpw_inline_close(txq, &mpw);
1111 txq->max_inline * RTE_CACHE_LINE_SIZE;
1114 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1115 if ((segs_n != 1) ||
1116 (length > inline_room)) {
1118 * Multi-Packet WQE consumes at most two WQE.
1119 * mlx5_mpw_new() expects to be able to use
1122 if (unlikely(max_wqe < 2))
1125 mlx5_mpw_new(txq, &mpw, length);
1126 mpw.wqe->eseg.cs_flags = cs_flags;
1128 if (unlikely(max_wqe < wqe_inl_n))
1130 max_wqe -= wqe_inl_n;
1131 mlx5_mpw_inline_new(txq, &mpw, length);
1132 mpw.wqe->eseg.cs_flags = cs_flags;
1135 /* Multi-segment packets must be alone in their MPW. */
1136 assert((segs_n == 1) || (mpw.pkts_n == 0));
1137 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1138 assert(inline_room ==
1139 txq->max_inline * RTE_CACHE_LINE_SIZE);
1140 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1144 volatile struct mlx5_wqe_data_seg *dseg;
1147 (*txq->elts)[elts_head++ & elts_m] = buf;
1148 dseg = mpw.data.dseg[mpw.pkts_n];
1149 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1150 *dseg = (struct mlx5_wqe_data_seg){
1152 rte_cpu_to_be_32(DATA_LEN(buf)),
1153 .lkey = mlx5_tx_mb2mr(txq, buf),
1154 .addr = rte_cpu_to_be_64(addr),
1156 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1157 length += DATA_LEN(buf);
1163 assert(length == mpw.len);
1164 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1165 mlx5_mpw_close(txq, &mpw);
1169 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1170 assert(length <= inline_room);
1171 assert(length == DATA_LEN(buf));
1172 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1173 (*txq->elts)[elts_head++ & elts_m] = buf;
1174 /* Maximum number of bytes before wrapping. */
1175 max = ((((uintptr_t)(txq->wqes)) +
1178 (uintptr_t)mpw.data.raw);
1180 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1183 mpw.data.raw = (volatile void *)txq->wqes;
1184 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1185 (void *)(addr + max),
1187 mpw.data.raw += length - max;
1189 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1195 (volatile void *)txq->wqes;
1197 mpw.data.raw += length;
1200 mpw.total_len += length;
1202 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1203 mlx5_mpw_inline_close(txq, &mpw);
1205 txq->max_inline * RTE_CACHE_LINE_SIZE;
1207 inline_room -= length;
1210 #ifdef MLX5_PMD_SOFT_COUNTERS
1211 /* Increment sent bytes counter. */
1212 txq->stats.obytes += length;
1216 /* Take a shortcut if nothing must be sent. */
1217 if (unlikely(i == 0))
1219 /* Check whether completion threshold has been reached. */
1220 /* "j" includes both packets and segments. */
1221 comp = txq->elts_comp + j;
1222 if (comp >= MLX5_TX_COMP_THRESH) {
1223 volatile struct mlx5_wqe *wqe = mpw.wqe;
1225 /* Request completion on last WQE. */
1226 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1227 /* Save elts_head in unused "immediate" field of WQE. */
1228 wqe->ctrl[3] = elts_head;
1234 txq->elts_comp = comp;
1236 #ifdef MLX5_PMD_SOFT_COUNTERS
1237 /* Increment sent packets counter. */
1238 txq->stats.opackets += i;
1240 /* Ring QP doorbell. */
1241 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1242 mlx5_mpw_inline_close(txq, &mpw);
1243 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1244 mlx5_mpw_close(txq, &mpw);
1245 mlx5_tx_dbrec(txq, mpw.wqe);
1246 txq->elts_head = elts_head;
1251 * Open an Enhanced MPW session.
1254 * Pointer to TX queue structure.
1256 * Pointer to MPW session structure.
1261 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1263 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1265 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1267 mpw->total_len = sizeof(struct mlx5_wqe);
1268 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1270 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1271 (txq->wqe_ci << 8) |
1272 MLX5_OPCODE_ENHANCED_MPSW);
1273 mpw->wqe->ctrl[2] = 0;
1274 mpw->wqe->ctrl[3] = 0;
1275 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1276 if (unlikely(padding)) {
1277 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1279 /* Pad the first 2 DWORDs with zero-length inline header. */
1280 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1281 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1282 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1283 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1284 /* Start from the next WQEBB. */
1285 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1287 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1292 * Close an Enhanced MPW session.
1295 * Pointer to TX queue structure.
1297 * Pointer to MPW session structure.
1300 * Number of consumed WQEs.
1302 static inline uint16_t
1303 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1307 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1310 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1311 MLX5_WQE_DS(mpw->total_len));
1312 mpw->state = MLX5_MPW_STATE_CLOSED;
1313 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1319 * TX with Enhanced MPW support.
1322 * Pointer to TX queue structure.
1324 * Packets to transmit.
1326 * Number of packets in array.
1329 * Number of packets successfully transmitted (<= pkts_n).
1331 static inline uint16_t
1332 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1335 uint16_t elts_head = txq->elts_head;
1336 const uint16_t elts_n = 1 << txq->elts_n;
1337 const uint16_t elts_m = elts_n - 1;
1342 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1343 unsigned int mpw_room = 0;
1344 unsigned int inl_pad = 0;
1346 struct mlx5_mpw mpw = {
1347 .state = MLX5_MPW_STATE_CLOSED,
1350 if (unlikely(!pkts_n))
1352 /* Start processing. */
1353 mlx5_tx_complete(txq);
1354 max_elts = (elts_n - (elts_head - txq->elts_tail));
1355 /* A CQE slot must always be available. */
1356 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1357 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1358 if (unlikely(!max_wqe))
1361 struct rte_mbuf *buf = *(pkts++);
1364 unsigned int do_inline = 0; /* Whether inline is possible. */
1368 /* Multi-segmented packet is handled in slow-path outside. */
1369 assert(NB_SEGS(buf) == 1);
1370 /* Make sure there is enough room to store this packet. */
1371 if (max_elts - j == 0)
1373 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1374 /* Retrieve packet information. */
1375 length = PKT_LEN(buf);
1376 /* Start new session if:
1377 * - multi-segment packet
1378 * - no space left even for a dseg
1379 * - next packet can be inlined with a new WQE
1382 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1383 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1385 (length <= txq->inline_max_packet_sz &&
1386 inl_pad + sizeof(inl_hdr) + length >
1388 (mpw.wqe->eseg.cs_flags != cs_flags))
1389 max_wqe -= mlx5_empw_close(txq, &mpw);
1391 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1392 /* In Enhanced MPW, inline as much as the budget is
1393 * allowed. The remaining space is to be filled with
1394 * dsegs. If the title WQEBB isn't padded, it will have
1397 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1398 (max_inline ? max_inline :
1399 pkts_n * MLX5_WQE_DWORD_SIZE) +
1401 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1403 /* Don't pad the title WQEBB to not waste WQ. */
1404 mlx5_empw_new(txq, &mpw, 0);
1405 mpw_room -= mpw.total_len;
1407 do_inline = length <= txq->inline_max_packet_sz &&
1408 sizeof(inl_hdr) + length <= mpw_room &&
1410 mpw.wqe->eseg.cs_flags = cs_flags;
1412 /* Evaluate whether the next packet can be inlined.
1413 * Inlininig is possible when:
1414 * - length is less than configured value
1415 * - length fits for remaining space
1416 * - not required to fill the title WQEBB with dsegs
1419 length <= txq->inline_max_packet_sz &&
1420 inl_pad + sizeof(inl_hdr) + length <=
1422 (!txq->mpw_hdr_dseg ||
1423 mpw.total_len >= MLX5_WQE_SIZE);
1425 if (max_inline && do_inline) {
1426 /* Inline packet into WQE. */
1429 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1430 assert(length == DATA_LEN(buf));
1431 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1432 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1433 mpw.data.raw = (volatile void *)
1434 ((uintptr_t)mpw.data.raw + inl_pad);
1435 max = tx_mlx5_wq_tailroom(txq,
1436 (void *)(uintptr_t)mpw.data.raw);
1437 /* Copy inline header. */
1438 mpw.data.raw = (volatile void *)
1440 (void *)(uintptr_t)mpw.data.raw,
1443 (void *)(uintptr_t)txq->wqes,
1445 max = tx_mlx5_wq_tailroom(txq,
1446 (void *)(uintptr_t)mpw.data.raw);
1447 /* Copy packet data. */
1448 mpw.data.raw = (volatile void *)
1450 (void *)(uintptr_t)mpw.data.raw,
1453 (void *)(uintptr_t)txq->wqes,
1456 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1457 /* No need to get completion as the entire packet is
1458 * copied to WQ. Free the buf right away.
1460 rte_pktmbuf_free_seg(buf);
1461 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1462 /* Add pad in the next packet if any. */
1463 inl_pad = (((uintptr_t)mpw.data.raw +
1464 (MLX5_WQE_DWORD_SIZE - 1)) &
1465 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1466 (uintptr_t)mpw.data.raw;
1468 /* No inline. Load a dseg of packet pointer. */
1469 volatile rte_v128u32_t *dseg;
1471 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1472 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1473 assert(length == DATA_LEN(buf));
1474 if (!tx_mlx5_wq_tailroom(txq,
1475 (void *)((uintptr_t)mpw.data.raw
1477 dseg = (volatile void *)txq->wqes;
1479 dseg = (volatile void *)
1480 ((uintptr_t)mpw.data.raw +
1482 (*txq->elts)[elts_head++ & elts_m] = buf;
1483 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1484 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1485 rte_prefetch2((void *)(addr +
1486 n * RTE_CACHE_LINE_SIZE));
1487 addr = rte_cpu_to_be_64(addr);
1488 *dseg = (rte_v128u32_t) {
1489 rte_cpu_to_be_32(length),
1490 mlx5_tx_mb2mr(txq, buf),
1494 mpw.data.raw = (volatile void *)(dseg + 1);
1495 mpw.total_len += (inl_pad + sizeof(*dseg));
1498 mpw_room -= (inl_pad + sizeof(*dseg));
1501 #ifdef MLX5_PMD_SOFT_COUNTERS
1502 /* Increment sent bytes counter. */
1503 txq->stats.obytes += length;
1506 } while (i < pkts_n);
1507 /* Take a shortcut if nothing must be sent. */
1508 if (unlikely(i == 0))
1510 /* Check whether completion threshold has been reached. */
1511 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1512 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1513 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1514 volatile struct mlx5_wqe *wqe = mpw.wqe;
1516 /* Request completion on last WQE. */
1517 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1518 /* Save elts_head in unused "immediate" field of WQE. */
1519 wqe->ctrl[3] = elts_head;
1521 txq->mpw_comp = txq->wqe_ci;
1526 txq->elts_comp += j;
1528 #ifdef MLX5_PMD_SOFT_COUNTERS
1529 /* Increment sent packets counter. */
1530 txq->stats.opackets += i;
1532 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1533 mlx5_empw_close(txq, &mpw);
1534 /* Ring QP doorbell. */
1535 mlx5_tx_dbrec(txq, mpw.wqe);
1536 txq->elts_head = elts_head;
1541 * DPDK callback for TX with Enhanced MPW support.
1544 * Generic pointer to TX queue structure.
1546 * Packets to transmit.
1548 * Number of packets in array.
1551 * Number of packets successfully transmitted (<= pkts_n).
1554 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1556 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1559 while (pkts_n > nb_tx) {
1563 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1565 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1570 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1572 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1582 * Translate RX completion flags to packet type.
1587 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1590 * Packet type for struct rte_mbuf.
1592 static inline uint32_t
1593 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1596 uint8_t pinfo = cqe->pkt_info;
1597 uint16_t ptype = cqe->hdr_type_etc;
1600 * The index to the array should have:
1601 * bit[1:0] = l3_hdr_type
1602 * bit[4:2] = l4_hdr_type
1605 * bit[7] = outer_l3_type
1607 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1608 return mlx5_ptype_table[idx];
1612 * Get size of the next packet for a given CQE. For compressed CQEs, the
1613 * consumer index is updated only once all packets of the current one have
1617 * Pointer to RX queue.
1620 * @param[out] rss_hash
1621 * Packet RSS Hash result.
1624 * Packet size in bytes (0 if there is none), -1 in case of completion
1628 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1629 uint16_t cqe_cnt, uint32_t *rss_hash)
1631 struct rxq_zip *zip = &rxq->zip;
1632 uint16_t cqe_n = cqe_cnt + 1;
1636 /* Process compressed data in the CQE and mini arrays. */
1638 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1639 (volatile struct mlx5_mini_cqe8 (*)[8])
1640 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1642 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1643 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1644 if ((++zip->ai & 7) == 0) {
1645 /* Invalidate consumed CQEs */
1648 while (idx != end) {
1649 (*rxq->cqes)[idx & cqe_cnt].op_own =
1650 MLX5_CQE_INVALIDATE;
1654 * Increment consumer index to skip the number of
1655 * CQEs consumed. Hardware leaves holes in the CQ
1656 * ring for software use.
1661 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1662 /* Invalidate the rest */
1666 while (idx != end) {
1667 (*rxq->cqes)[idx & cqe_cnt].op_own =
1668 MLX5_CQE_INVALIDATE;
1671 rxq->cq_ci = zip->cq_ci;
1674 /* No compressed data, get next CQE and verify if it is compressed. */
1679 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1680 if (unlikely(ret == 1))
1683 op_own = cqe->op_own;
1685 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1686 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1687 (volatile struct mlx5_mini_cqe8 (*)[8])
1688 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1691 /* Fix endianness. */
1692 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1694 * Current mini array position is the one returned by
1697 * If completion comprises several mini arrays, as a
1698 * special case the second one is located 7 CQEs after
1699 * the initial CQE instead of 8 for subsequent ones.
1701 zip->ca = rxq->cq_ci;
1702 zip->na = zip->ca + 7;
1703 /* Compute the next non compressed CQE. */
1705 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1706 /* Get packet size to return. */
1707 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1708 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1710 /* Prefetch all the entries to be invalidated */
1713 while (idx != end) {
1714 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1718 len = rte_be_to_cpu_32(cqe->byte_cnt);
1719 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1721 /* Error while receiving packet. */
1722 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1729 * Translate RX completion flags to offload flags.
1732 * Pointer to RX queue structure.
1737 * Offload flags (ol_flags) for struct rte_mbuf.
1739 static inline uint32_t
1740 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1742 uint32_t ol_flags = 0;
1743 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1747 MLX5_CQE_RX_L3_HDR_VALID,
1748 PKT_RX_IP_CKSUM_GOOD) |
1750 MLX5_CQE_RX_L4_HDR_VALID,
1751 PKT_RX_L4_CKSUM_GOOD);
1752 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1755 MLX5_CQE_RX_L3_HDR_VALID,
1756 PKT_RX_IP_CKSUM_GOOD) |
1758 MLX5_CQE_RX_L4_HDR_VALID,
1759 PKT_RX_L4_CKSUM_GOOD);
1764 * DPDK callback for RX.
1767 * Generic pointer to RX queue structure.
1769 * Array to store received packets.
1771 * Maximum number of packets in array.
1774 * Number of packets successfully received (<= pkts_n).
1777 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1779 struct mlx5_rxq_data *rxq = dpdk_rxq;
1780 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1781 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1782 const unsigned int sges_n = rxq->sges_n;
1783 struct rte_mbuf *pkt = NULL;
1784 struct rte_mbuf *seg = NULL;
1785 volatile struct mlx5_cqe *cqe =
1786 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1788 unsigned int rq_ci = rxq->rq_ci << sges_n;
1789 int len = 0; /* keep its value across iterations. */
1792 unsigned int idx = rq_ci & wqe_cnt;
1793 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1794 struct rte_mbuf *rep = (*rxq->elts)[idx];
1795 uint32_t rss_hash_res = 0;
1803 rep = rte_mbuf_raw_alloc(rxq->mp);
1804 if (unlikely(rep == NULL)) {
1805 ++rxq->stats.rx_nombuf;
1808 * no buffers before we even started,
1809 * bail out silently.
1813 while (pkt != seg) {
1814 assert(pkt != (*rxq->elts)[idx]);
1818 rte_mbuf_raw_free(pkt);
1824 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1825 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1828 rte_mbuf_raw_free(rep);
1831 if (unlikely(len == -1)) {
1832 /* RX error, packet is likely too large. */
1833 rte_mbuf_raw_free(rep);
1834 ++rxq->stats.idropped;
1838 assert(len >= (rxq->crc_present << 2));
1839 /* Update packet information. */
1840 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1842 if (rss_hash_res && rxq->rss_hash) {
1843 pkt->hash.rss = rss_hash_res;
1844 pkt->ol_flags = PKT_RX_RSS_HASH;
1847 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1848 pkt->ol_flags |= PKT_RX_FDIR;
1849 if (cqe->sop_drop_qpn !=
1850 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1851 uint32_t mark = cqe->sop_drop_qpn;
1853 pkt->ol_flags |= PKT_RX_FDIR_ID;
1855 mlx5_flow_mark_get(mark);
1858 if (rxq->csum | rxq->csum_l2tun)
1859 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1860 if (rxq->vlan_strip &&
1861 (cqe->hdr_type_etc &
1862 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1863 pkt->ol_flags |= PKT_RX_VLAN |
1864 PKT_RX_VLAN_STRIPPED;
1866 rte_be_to_cpu_16(cqe->vlan_info);
1868 if (rxq->hw_timestamp) {
1870 rte_be_to_cpu_64(cqe->timestamp);
1871 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1873 if (rxq->crc_present)
1874 len -= ETHER_CRC_LEN;
1877 DATA_LEN(rep) = DATA_LEN(seg);
1878 PKT_LEN(rep) = PKT_LEN(seg);
1879 SET_DATA_OFF(rep, DATA_OFF(seg));
1880 PORT(rep) = PORT(seg);
1881 (*rxq->elts)[idx] = rep;
1883 * Fill NIC descriptor with the new buffer. The lkey and size
1884 * of the buffers are already known, only the buffer address
1887 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1888 if (len > DATA_LEN(seg)) {
1889 len -= DATA_LEN(seg);
1894 DATA_LEN(seg) = len;
1895 #ifdef MLX5_PMD_SOFT_COUNTERS
1896 /* Increment bytes counter. */
1897 rxq->stats.ibytes += PKT_LEN(pkt);
1899 /* Return packet. */
1905 /* Align consumer index to the next stride. */
1910 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1912 /* Update the consumer index. */
1913 rxq->rq_ci = rq_ci >> sges_n;
1915 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1917 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1918 #ifdef MLX5_PMD_SOFT_COUNTERS
1919 /* Increment packets counter. */
1920 rxq->stats.ipackets += i;
1926 * Dummy DPDK callback for TX.
1928 * This function is used to temporarily replace the real callback during
1929 * unsafe control operations on the queue, or in case of error.
1932 * Generic pointer to TX queue structure.
1934 * Packets to transmit.
1936 * Number of packets in array.
1939 * Number of packets successfully transmitted (<= pkts_n).
1942 removed_tx_burst(void *dpdk_txq __rte_unused,
1943 struct rte_mbuf **pkts __rte_unused,
1944 uint16_t pkts_n __rte_unused)
1950 * Dummy DPDK callback for RX.
1952 * This function is used to temporarily replace the real callback during
1953 * unsafe control operations on the queue, or in case of error.
1956 * Generic pointer to RX queue structure.
1958 * Array to store received packets.
1960 * Maximum number of packets in array.
1963 * Number of packets successfully received (<= pkts_n).
1966 removed_rx_burst(void *dpdk_txq __rte_unused,
1967 struct rte_mbuf **pkts __rte_unused,
1968 uint16_t pkts_n __rte_unused)
1974 * Vectorized Rx/Tx routines are not compiled in when required vector
1975 * instructions are not supported on a target architecture. The following null
1976 * stubs are needed for linkage when those are not included outside of this file
1977 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1980 uint16_t __attribute__((weak))
1981 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
1982 struct rte_mbuf **pkts __rte_unused,
1983 uint16_t pkts_n __rte_unused)
1988 uint16_t __attribute__((weak))
1989 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
1990 struct rte_mbuf **pkts __rte_unused,
1991 uint16_t pkts_n __rte_unused)
1996 uint16_t __attribute__((weak))
1997 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1998 struct rte_mbuf **pkts __rte_unused,
1999 uint16_t pkts_n __rte_unused)
2004 int __attribute__((weak))
2005 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2010 int __attribute__((weak))
2011 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2016 int __attribute__((weak))
2017 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2022 int __attribute__((weak))
2023 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)