1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, uint32_t *rss_hash);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
46 static __rte_always_inline void
47 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
48 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
50 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
51 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
54 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
55 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
58 * Build a table to translate Rx completion flags to packet type.
60 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
63 mlx5_set_ptype_table(void)
66 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
68 /* Last entry must not be overwritten, reserved for errored packet. */
69 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
70 (*p)[i] = RTE_PTYPE_UNKNOWN;
72 * The index to the array should have:
73 * bit[1:0] = l3_hdr_type
74 * bit[4:2] = l4_hdr_type
77 * bit[7] = outer_l3_type
80 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
82 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
84 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
87 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
89 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
92 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
94 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
96 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
98 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
100 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
102 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
105 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
107 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
109 /* Repeat with outer_l3_type being set. Just in case. */
110 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
111 RTE_PTYPE_L4_NONFRAG;
112 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 RTE_PTYPE_L4_NONFRAG;
114 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
116 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
128 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
130 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
132 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
136 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
137 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
138 RTE_PTYPE_INNER_L4_NONFRAG;
139 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L4_NONFRAG;
142 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
143 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 /* Tunneled - Fragmented */
150 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L4_FRAG;
153 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
163 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L4_TCP;
166 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
190 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L4_TCP;
193 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L4_TCP;
196 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
197 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L4_TCP;
200 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
202 RTE_PTYPE_INNER_L4_UDP;
203 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_UDP;
206 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_UDP;
209 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_UDP;
215 * Build a table to translate packet to checksum type of Verbs.
218 mlx5_set_cksum_table(void)
224 * The index should have:
225 * bit[0] = PKT_TX_TCP_SEG
226 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
227 * bit[4] = PKT_TX_IP_CKSUM
228 * bit[8] = PKT_TX_OUTER_IP_CKSUM
231 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
234 /* Tunneled packet. */
235 if (i & (1 << 8)) /* Outer IP. */
236 v |= MLX5_ETH_WQE_L3_CSUM;
237 if (i & (1 << 4)) /* Inner IP. */
238 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
239 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
240 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
243 if (i & (1 << 4)) /* IP. */
244 v |= MLX5_ETH_WQE_L3_CSUM;
245 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
246 v |= MLX5_ETH_WQE_L4_CSUM;
248 mlx5_cksum_table[i] = v;
253 * Build a table to translate packet type of mbuf to SWP type of Verbs.
256 mlx5_set_swp_types_table(void)
262 * The index should have:
263 * bit[0:1] = PKT_TX_L4_MASK
264 * bit[4] = PKT_TX_IPV6
265 * bit[8] = PKT_TX_OUTER_IPV6
266 * bit[9] = PKT_TX_OUTER_UDP
268 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
271 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
273 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
275 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
276 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
277 v |= MLX5_ETH_WQE_L4_INNER_UDP;
278 mlx5_swp_types_table[i] = v;
283 * Return the size of tailroom of WQ.
286 * Pointer to TX queue structure.
288 * Pointer to tail of WQ.
294 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
297 tailroom = (uintptr_t)(txq->wqes) +
298 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
304 * Copy data to tailroom of circular queue.
307 * Pointer to destination.
311 * Number of bytes to copy.
313 * Pointer to head of queue.
315 * Size of tailroom from dst.
318 * Pointer after copied data.
321 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
322 void *base, size_t tailroom)
327 rte_memcpy(dst, src, tailroom);
328 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
330 ret = (uint8_t *)base + n - tailroom;
332 rte_memcpy(dst, src, n);
333 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
339 * Inline TSO headers into WQE.
342 * 0 on success, negative errno value on failure.
345 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
348 uint16_t *pkt_inline_sz,
352 uint16_t *tso_header_sz)
354 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
355 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
357 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
358 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
362 *tso_segsz = buf->tso_segsz;
363 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
364 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
365 txq->stats.oerrors++;
369 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
370 /* First seg must contain all TSO headers. */
371 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
372 *tso_header_sz > DATA_LEN(buf)) {
373 txq->stats.oerrors++;
376 copy_b = *tso_header_sz - *pkt_inline_sz;
377 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
379 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
380 if (unlikely(*max_wqe < n_wqe))
383 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
386 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
387 *pkt_inline_sz += copy_b;
393 * DPDK callback to check the status of a tx descriptor.
398 * The index of the descriptor in the ring.
401 * The status of the tx descriptor.
404 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
406 struct mlx5_txq_data *txq = tx_queue;
409 mlx5_tx_complete(txq);
410 used = txq->elts_head - txq->elts_tail;
412 return RTE_ETH_TX_DESC_FULL;
413 return RTE_ETH_TX_DESC_DONE;
417 * DPDK callback to check the status of a rx descriptor.
422 * The index of the descriptor in the ring.
425 * The status of the tx descriptor.
428 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
430 struct mlx5_rxq_data *rxq = rx_queue;
431 struct rxq_zip *zip = &rxq->zip;
432 volatile struct mlx5_cqe *cqe;
433 const unsigned int cqe_n = (1 << rxq->cqe_n);
434 const unsigned int cqe_cnt = cqe_n - 1;
438 /* if we are processing a compressed cqe */
440 used = zip->cqe_cnt - zip->ca;
446 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
447 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
451 op_own = cqe->op_own;
452 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
453 n = rte_be_to_cpu_32(cqe->byte_cnt);
458 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
460 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
462 return RTE_ETH_RX_DESC_DONE;
463 return RTE_ETH_RX_DESC_AVAIL;
467 * DPDK callback for TX.
470 * Generic pointer to TX queue structure.
472 * Packets to transmit.
474 * Number of packets in array.
477 * Number of packets successfully transmitted (<= pkts_n).
480 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
482 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
483 uint16_t elts_head = txq->elts_head;
484 const uint16_t elts_n = 1 << txq->elts_n;
485 const uint16_t elts_m = elts_n - 1;
492 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
493 unsigned int segs_n = 0;
494 const unsigned int max_inline = txq->max_inline;
496 if (unlikely(!pkts_n))
498 /* Prefetch first packet cacheline. */
499 rte_prefetch0(*pkts);
500 /* Start processing. */
501 mlx5_tx_complete(txq);
502 max_elts = (elts_n - (elts_head - txq->elts_tail));
503 /* A CQE slot must always be available. */
504 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
505 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
506 if (unlikely(!max_wqe))
509 struct rte_mbuf *buf = *pkts; /* First_seg. */
511 volatile struct mlx5_wqe_v *wqe = NULL;
512 volatile rte_v128u32_t *dseg = NULL;
515 unsigned int sg = 0; /* counter of additional segs attached. */
517 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
518 uint16_t tso_header_sz = 0;
521 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
522 uint8_t is_vlan = !!(buf->ol_flags & PKT_TX_VLAN_PKT);
523 uint32_t swp_offsets = 0;
524 uint8_t swp_types = 0;
525 uint16_t tso_segsz = 0;
526 #ifdef MLX5_PMD_SOFT_COUNTERS
527 uint32_t total_length = 0;
531 segs_n = buf->nb_segs;
533 * Make sure there is enough room to store this packet and
534 * that one ring entry remains unused.
537 if (max_elts < segs_n)
541 if (unlikely(--max_wqe == 0))
543 wqe = (volatile struct mlx5_wqe_v *)
544 tx_mlx5_wqe(txq, txq->wqe_ci);
545 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
547 rte_prefetch0(*(pkts + 1));
548 addr = rte_pktmbuf_mtod(buf, uintptr_t);
549 length = DATA_LEN(buf);
550 ehdr = (((uint8_t *)addr)[1] << 8) |
551 ((uint8_t *)addr)[0];
552 #ifdef MLX5_PMD_SOFT_COUNTERS
553 total_length = length;
555 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
556 txq->stats.oerrors++;
559 /* Update element. */
560 (*txq->elts)[elts_head & elts_m] = buf;
561 /* Prefetch next buffer data. */
564 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
565 cs_flags = txq_ol_cksum_to_cs(buf);
566 txq_mbuf_to_swp(txq, buf, tso, is_vlan,
567 (uint8_t *)&swp_offsets, &swp_types);
568 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
569 /* Replace the Ethernet type by the VLAN if necessary. */
571 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
573 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
577 /* Copy Destination and source mac address. */
578 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
580 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
581 /* Copy missing two bytes to end the DSeg. */
582 memcpy((uint8_t *)raw + len + sizeof(vlan),
583 ((uint8_t *)addr) + len, 2);
587 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
588 MLX5_WQE_DWORD_SIZE);
589 length -= pkt_inline_sz;
590 addr += pkt_inline_sz;
592 raw += MLX5_WQE_DWORD_SIZE;
594 ret = inline_tso(txq, buf, &length,
595 &addr, &pkt_inline_sz,
597 &tso_segsz, &tso_header_sz);
598 if (ret == -EINVAL) {
600 } else if (ret == -EAGAIN) {
602 wqe->ctrl = (rte_v128u32_t){
603 rte_cpu_to_be_32(txq->wqe_ci << 8),
604 rte_cpu_to_be_32(txq->qp_num_8s | 1),
609 #ifdef MLX5_PMD_SOFT_COUNTERS
616 /* Inline if enough room. */
617 if (max_inline || tso) {
619 uintptr_t end = (uintptr_t)
620 (((uintptr_t)txq->wqes) +
621 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
622 unsigned int inline_room = max_inline *
623 RTE_CACHE_LINE_SIZE -
624 (pkt_inline_sz - 2) -
630 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
631 RTE_CACHE_LINE_SIZE);
632 copy_b = (addr_end > addr) ?
633 RTE_MIN((addr_end - addr), length) : 0;
634 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
636 * One Dseg remains in the current WQE. To
637 * keep the computation positive, it is
638 * removed after the bytes to Dseg conversion.
640 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
642 if (unlikely(max_wqe < n))
646 inl = rte_cpu_to_be_32(copy_b |
648 rte_memcpy((void *)raw,
649 (void *)&inl, sizeof(inl));
651 pkt_inline_sz += sizeof(inl);
653 rte_memcpy((void *)raw, (void *)addr, copy_b);
656 pkt_inline_sz += copy_b;
659 * 2 DWORDs consumed by the WQE header + ETH segment +
660 * the size of the inline part of the packet.
662 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
664 if (ds % (MLX5_WQE_SIZE /
665 MLX5_WQE_DWORD_SIZE) == 0) {
666 if (unlikely(--max_wqe == 0))
668 dseg = (volatile rte_v128u32_t *)
669 tx_mlx5_wqe(txq, txq->wqe_ci +
672 dseg = (volatile rte_v128u32_t *)
674 (ds * MLX5_WQE_DWORD_SIZE));
677 } else if (!segs_n) {
681 inline_room -= copy_b;
685 addr = rte_pktmbuf_mtod(buf, uintptr_t);
686 length = DATA_LEN(buf);
687 #ifdef MLX5_PMD_SOFT_COUNTERS
688 total_length += length;
690 (*txq->elts)[++elts_head & elts_m] = buf;
695 * No inline has been done in the packet, only the
696 * Ethernet Header as been stored.
698 dseg = (volatile rte_v128u32_t *)
699 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
702 /* Add the remaining packet as a simple ds. */
703 addr = rte_cpu_to_be_64(addr);
704 *dseg = (rte_v128u32_t){
705 rte_cpu_to_be_32(length),
706 mlx5_tx_mb2mr(txq, buf),
719 * Spill on next WQE when the current one does not have
720 * enough room left. Size of WQE must a be a multiple
721 * of data segment size.
723 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
724 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
725 if (unlikely(--max_wqe == 0))
727 dseg = (volatile rte_v128u32_t *)
728 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
729 rte_prefetch0(tx_mlx5_wqe(txq,
730 txq->wqe_ci + ds / 4 + 1));
737 length = DATA_LEN(buf);
738 #ifdef MLX5_PMD_SOFT_COUNTERS
739 total_length += length;
741 /* Store segment information. */
742 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
743 *dseg = (rte_v128u32_t){
744 rte_cpu_to_be_32(length),
745 mlx5_tx_mb2mr(txq, buf),
749 (*txq->elts)[++elts_head & elts_m] = buf;
753 if (ds > MLX5_DSEG_MAX) {
754 txq->stats.oerrors++;
761 /* Initialize known and common part of the WQE structure. */
763 wqe->ctrl = (rte_v128u32_t){
764 rte_cpu_to_be_32((txq->wqe_ci << 8) |
766 rte_cpu_to_be_32(txq->qp_num_8s | ds),
770 wqe->eseg = (rte_v128u32_t){
772 cs_flags | (swp_types << 8) |
773 (rte_cpu_to_be_16(tso_segsz) << 16),
775 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
778 wqe->ctrl = (rte_v128u32_t){
779 rte_cpu_to_be_32((txq->wqe_ci << 8) |
781 rte_cpu_to_be_32(txq->qp_num_8s | ds),
785 wqe->eseg = (rte_v128u32_t){
787 cs_flags | (swp_types << 8),
789 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
793 txq->wqe_ci += (ds + 3) / 4;
794 /* Save the last successful WQE for completion request */
795 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
796 #ifdef MLX5_PMD_SOFT_COUNTERS
797 /* Increment sent bytes counter. */
798 txq->stats.obytes += total_length;
800 } while (i < pkts_n);
801 /* Take a shortcut if nothing must be sent. */
802 if (unlikely((i + k) == 0))
804 txq->elts_head += (i + j);
805 /* Check whether completion threshold has been reached. */
806 comp = txq->elts_comp + i + j + k;
807 if (comp >= MLX5_TX_COMP_THRESH) {
808 /* Request completion on last WQE. */
809 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
810 /* Save elts_head in unused "immediate" field of WQE. */
811 last_wqe->ctrl3 = txq->elts_head;
817 txq->elts_comp = comp;
819 #ifdef MLX5_PMD_SOFT_COUNTERS
820 /* Increment sent packets counter. */
821 txq->stats.opackets += i;
823 /* Ring QP doorbell. */
824 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
829 * Open a MPW session.
832 * Pointer to TX queue structure.
834 * Pointer to MPW session structure.
839 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
841 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
842 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
843 (volatile struct mlx5_wqe_data_seg (*)[])
844 tx_mlx5_wqe(txq, idx + 1);
846 mpw->state = MLX5_MPW_STATE_OPENED;
850 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
851 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
852 mpw->wqe->eseg.inline_hdr_sz = 0;
853 mpw->wqe->eseg.rsvd0 = 0;
854 mpw->wqe->eseg.rsvd1 = 0;
855 mpw->wqe->eseg.rsvd2 = 0;
856 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
859 mpw->wqe->ctrl[2] = 0;
860 mpw->wqe->ctrl[3] = 0;
861 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
862 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
863 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
864 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
865 mpw->data.dseg[2] = &(*dseg)[0];
866 mpw->data.dseg[3] = &(*dseg)[1];
867 mpw->data.dseg[4] = &(*dseg)[2];
871 * Close a MPW session.
874 * Pointer to TX queue structure.
876 * Pointer to MPW session structure.
879 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
881 unsigned int num = mpw->pkts_n;
884 * Store size in multiple of 16 bytes. Control and Ethernet segments
887 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
888 mpw->state = MLX5_MPW_STATE_CLOSED;
893 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
894 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
898 * DPDK callback for TX with MPW support.
901 * Generic pointer to TX queue structure.
903 * Packets to transmit.
905 * Number of packets in array.
908 * Number of packets successfully transmitted (<= pkts_n).
911 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
913 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
914 uint16_t elts_head = txq->elts_head;
915 const uint16_t elts_n = 1 << txq->elts_n;
916 const uint16_t elts_m = elts_n - 1;
922 struct mlx5_mpw mpw = {
923 .state = MLX5_MPW_STATE_CLOSED,
926 if (unlikely(!pkts_n))
928 /* Prefetch first packet cacheline. */
929 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
930 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
931 /* Start processing. */
932 mlx5_tx_complete(txq);
933 max_elts = (elts_n - (elts_head - txq->elts_tail));
934 /* A CQE slot must always be available. */
935 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
936 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
937 if (unlikely(!max_wqe))
940 struct rte_mbuf *buf = *(pkts++);
942 unsigned int segs_n = buf->nb_segs;
946 * Make sure there is enough room to store this packet and
947 * that one ring entry remains unused.
950 if (max_elts < segs_n)
952 /* Do not bother with large packets MPW cannot handle. */
953 if (segs_n > MLX5_MPW_DSEG_MAX) {
954 txq->stats.oerrors++;
959 cs_flags = txq_ol_cksum_to_cs(buf);
960 /* Retrieve packet information. */
961 length = PKT_LEN(buf);
963 /* Start new session if packet differs. */
964 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
965 ((mpw.len != length) ||
967 (mpw.wqe->eseg.cs_flags != cs_flags)))
968 mlx5_mpw_close(txq, &mpw);
969 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
971 * Multi-Packet WQE consumes at most two WQE.
972 * mlx5_mpw_new() expects to be able to use such
975 if (unlikely(max_wqe < 2))
978 mlx5_mpw_new(txq, &mpw, length);
979 mpw.wqe->eseg.cs_flags = cs_flags;
981 /* Multi-segment packets must be alone in their MPW. */
982 assert((segs_n == 1) || (mpw.pkts_n == 0));
983 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
987 volatile struct mlx5_wqe_data_seg *dseg;
991 (*txq->elts)[elts_head++ & elts_m] = buf;
992 dseg = mpw.data.dseg[mpw.pkts_n];
993 addr = rte_pktmbuf_mtod(buf, uintptr_t);
994 *dseg = (struct mlx5_wqe_data_seg){
995 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
996 .lkey = mlx5_tx_mb2mr(txq, buf),
997 .addr = rte_cpu_to_be_64(addr),
999 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1000 length += DATA_LEN(buf);
1006 assert(length == mpw.len);
1007 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1008 mlx5_mpw_close(txq, &mpw);
1009 #ifdef MLX5_PMD_SOFT_COUNTERS
1010 /* Increment sent bytes counter. */
1011 txq->stats.obytes += length;
1015 /* Take a shortcut if nothing must be sent. */
1016 if (unlikely(i == 0))
1018 /* Check whether completion threshold has been reached. */
1019 /* "j" includes both packets and segments. */
1020 comp = txq->elts_comp + j;
1021 if (comp >= MLX5_TX_COMP_THRESH) {
1022 volatile struct mlx5_wqe *wqe = mpw.wqe;
1024 /* Request completion on last WQE. */
1025 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1026 /* Save elts_head in unused "immediate" field of WQE. */
1027 wqe->ctrl[3] = elts_head;
1033 txq->elts_comp = comp;
1035 #ifdef MLX5_PMD_SOFT_COUNTERS
1036 /* Increment sent packets counter. */
1037 txq->stats.opackets += i;
1039 /* Ring QP doorbell. */
1040 if (mpw.state == MLX5_MPW_STATE_OPENED)
1041 mlx5_mpw_close(txq, &mpw);
1042 mlx5_tx_dbrec(txq, mpw.wqe);
1043 txq->elts_head = elts_head;
1048 * Open a MPW inline session.
1051 * Pointer to TX queue structure.
1053 * Pointer to MPW session structure.
1058 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1061 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1062 struct mlx5_wqe_inl_small *inl;
1064 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1068 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1069 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1070 (txq->wqe_ci << 8) |
1072 mpw->wqe->ctrl[2] = 0;
1073 mpw->wqe->ctrl[3] = 0;
1074 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1075 mpw->wqe->eseg.inline_hdr_sz = 0;
1076 mpw->wqe->eseg.cs_flags = 0;
1077 mpw->wqe->eseg.rsvd0 = 0;
1078 mpw->wqe->eseg.rsvd1 = 0;
1079 mpw->wqe->eseg.rsvd2 = 0;
1080 inl = (struct mlx5_wqe_inl_small *)
1081 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1082 mpw->data.raw = (uint8_t *)&inl->raw;
1086 * Close a MPW inline session.
1089 * Pointer to TX queue structure.
1091 * Pointer to MPW session structure.
1094 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1097 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1098 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1100 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1102 * Store size in multiple of 16 bytes. Control and Ethernet segments
1105 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1107 mpw->state = MLX5_MPW_STATE_CLOSED;
1108 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1109 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1113 * DPDK callback for TX with MPW inline support.
1116 * Generic pointer to TX queue structure.
1118 * Packets to transmit.
1120 * Number of packets in array.
1123 * Number of packets successfully transmitted (<= pkts_n).
1126 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1129 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1130 uint16_t elts_head = txq->elts_head;
1131 const uint16_t elts_n = 1 << txq->elts_n;
1132 const uint16_t elts_m = elts_n - 1;
1138 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1139 struct mlx5_mpw mpw = {
1140 .state = MLX5_MPW_STATE_CLOSED,
1143 * Compute the maximum number of WQE which can be consumed by inline
1146 * - 1 control segment,
1147 * - 1 Ethernet segment,
1148 * - N Dseg from the inline request.
1150 const unsigned int wqe_inl_n =
1151 ((2 * MLX5_WQE_DWORD_SIZE +
1152 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1153 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1155 if (unlikely(!pkts_n))
1157 /* Prefetch first packet cacheline. */
1158 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1159 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1160 /* Start processing. */
1161 mlx5_tx_complete(txq);
1162 max_elts = (elts_n - (elts_head - txq->elts_tail));
1163 /* A CQE slot must always be available. */
1164 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1166 struct rte_mbuf *buf = *(pkts++);
1169 unsigned int segs_n = buf->nb_segs;
1173 * Make sure there is enough room to store this packet and
1174 * that one ring entry remains unused.
1177 if (max_elts < segs_n)
1179 /* Do not bother with large packets MPW cannot handle. */
1180 if (segs_n > MLX5_MPW_DSEG_MAX) {
1181 txq->stats.oerrors++;
1187 * Compute max_wqe in case less WQE were consumed in previous
1190 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1191 cs_flags = txq_ol_cksum_to_cs(buf);
1192 /* Retrieve packet information. */
1193 length = PKT_LEN(buf);
1194 /* Start new session if packet differs. */
1195 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1196 if ((mpw.len != length) ||
1198 (mpw.wqe->eseg.cs_flags != cs_flags))
1199 mlx5_mpw_close(txq, &mpw);
1200 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1201 if ((mpw.len != length) ||
1203 (length > inline_room) ||
1204 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1205 mlx5_mpw_inline_close(txq, &mpw);
1207 txq->max_inline * RTE_CACHE_LINE_SIZE;
1210 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1211 if ((segs_n != 1) ||
1212 (length > inline_room)) {
1214 * Multi-Packet WQE consumes at most two WQE.
1215 * mlx5_mpw_new() expects to be able to use
1218 if (unlikely(max_wqe < 2))
1221 mlx5_mpw_new(txq, &mpw, length);
1222 mpw.wqe->eseg.cs_flags = cs_flags;
1224 if (unlikely(max_wqe < wqe_inl_n))
1226 max_wqe -= wqe_inl_n;
1227 mlx5_mpw_inline_new(txq, &mpw, length);
1228 mpw.wqe->eseg.cs_flags = cs_flags;
1231 /* Multi-segment packets must be alone in their MPW. */
1232 assert((segs_n == 1) || (mpw.pkts_n == 0));
1233 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1234 assert(inline_room ==
1235 txq->max_inline * RTE_CACHE_LINE_SIZE);
1236 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1240 volatile struct mlx5_wqe_data_seg *dseg;
1243 (*txq->elts)[elts_head++ & elts_m] = buf;
1244 dseg = mpw.data.dseg[mpw.pkts_n];
1245 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1246 *dseg = (struct mlx5_wqe_data_seg){
1248 rte_cpu_to_be_32(DATA_LEN(buf)),
1249 .lkey = mlx5_tx_mb2mr(txq, buf),
1250 .addr = rte_cpu_to_be_64(addr),
1252 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1253 length += DATA_LEN(buf);
1259 assert(length == mpw.len);
1260 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1261 mlx5_mpw_close(txq, &mpw);
1265 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1266 assert(length <= inline_room);
1267 assert(length == DATA_LEN(buf));
1268 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1269 (*txq->elts)[elts_head++ & elts_m] = buf;
1270 /* Maximum number of bytes before wrapping. */
1271 max = ((((uintptr_t)(txq->wqes)) +
1274 (uintptr_t)mpw.data.raw);
1276 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1279 mpw.data.raw = (volatile void *)txq->wqes;
1280 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1281 (void *)(addr + max),
1283 mpw.data.raw += length - max;
1285 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1291 (volatile void *)txq->wqes;
1293 mpw.data.raw += length;
1296 mpw.total_len += length;
1298 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1299 mlx5_mpw_inline_close(txq, &mpw);
1301 txq->max_inline * RTE_CACHE_LINE_SIZE;
1303 inline_room -= length;
1306 #ifdef MLX5_PMD_SOFT_COUNTERS
1307 /* Increment sent bytes counter. */
1308 txq->stats.obytes += length;
1312 /* Take a shortcut if nothing must be sent. */
1313 if (unlikely(i == 0))
1315 /* Check whether completion threshold has been reached. */
1316 /* "j" includes both packets and segments. */
1317 comp = txq->elts_comp + j;
1318 if (comp >= MLX5_TX_COMP_THRESH) {
1319 volatile struct mlx5_wqe *wqe = mpw.wqe;
1321 /* Request completion on last WQE. */
1322 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1323 /* Save elts_head in unused "immediate" field of WQE. */
1324 wqe->ctrl[3] = elts_head;
1330 txq->elts_comp = comp;
1332 #ifdef MLX5_PMD_SOFT_COUNTERS
1333 /* Increment sent packets counter. */
1334 txq->stats.opackets += i;
1336 /* Ring QP doorbell. */
1337 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1338 mlx5_mpw_inline_close(txq, &mpw);
1339 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1340 mlx5_mpw_close(txq, &mpw);
1341 mlx5_tx_dbrec(txq, mpw.wqe);
1342 txq->elts_head = elts_head;
1347 * Open an Enhanced MPW session.
1350 * Pointer to TX queue structure.
1352 * Pointer to MPW session structure.
1357 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1359 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1361 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1363 mpw->total_len = sizeof(struct mlx5_wqe);
1364 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1366 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1367 (txq->wqe_ci << 8) |
1368 MLX5_OPCODE_ENHANCED_MPSW);
1369 mpw->wqe->ctrl[2] = 0;
1370 mpw->wqe->ctrl[3] = 0;
1371 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1372 if (unlikely(padding)) {
1373 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1375 /* Pad the first 2 DWORDs with zero-length inline header. */
1376 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1377 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1378 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1379 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1380 /* Start from the next WQEBB. */
1381 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1383 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1388 * Close an Enhanced MPW session.
1391 * Pointer to TX queue structure.
1393 * Pointer to MPW session structure.
1396 * Number of consumed WQEs.
1398 static inline uint16_t
1399 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1403 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1406 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1407 MLX5_WQE_DS(mpw->total_len));
1408 mpw->state = MLX5_MPW_STATE_CLOSED;
1409 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1415 * TX with Enhanced MPW support.
1418 * Pointer to TX queue structure.
1420 * Packets to transmit.
1422 * Number of packets in array.
1425 * Number of packets successfully transmitted (<= pkts_n).
1427 static inline uint16_t
1428 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1431 uint16_t elts_head = txq->elts_head;
1432 const uint16_t elts_n = 1 << txq->elts_n;
1433 const uint16_t elts_m = elts_n - 1;
1438 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1439 unsigned int mpw_room = 0;
1440 unsigned int inl_pad = 0;
1442 struct mlx5_mpw mpw = {
1443 .state = MLX5_MPW_STATE_CLOSED,
1446 if (unlikely(!pkts_n))
1448 /* Start processing. */
1449 mlx5_tx_complete(txq);
1450 max_elts = (elts_n - (elts_head - txq->elts_tail));
1451 /* A CQE slot must always be available. */
1452 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1453 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1454 if (unlikely(!max_wqe))
1457 struct rte_mbuf *buf = *(pkts++);
1459 unsigned int do_inline = 0; /* Whether inline is possible. */
1463 /* Multi-segmented packet is handled in slow-path outside. */
1464 assert(NB_SEGS(buf) == 1);
1465 /* Make sure there is enough room to store this packet. */
1466 if (max_elts - j == 0)
1468 cs_flags = txq_ol_cksum_to_cs(buf);
1469 /* Retrieve packet information. */
1470 length = PKT_LEN(buf);
1471 /* Start new session if:
1472 * - multi-segment packet
1473 * - no space left even for a dseg
1474 * - next packet can be inlined with a new WQE
1477 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1478 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1480 (length <= txq->inline_max_packet_sz &&
1481 inl_pad + sizeof(inl_hdr) + length >
1483 (mpw.wqe->eseg.cs_flags != cs_flags))
1484 max_wqe -= mlx5_empw_close(txq, &mpw);
1486 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1487 /* In Enhanced MPW, inline as much as the budget is
1488 * allowed. The remaining space is to be filled with
1489 * dsegs. If the title WQEBB isn't padded, it will have
1492 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1493 (max_inline ? max_inline :
1494 pkts_n * MLX5_WQE_DWORD_SIZE) +
1496 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1498 /* Don't pad the title WQEBB to not waste WQ. */
1499 mlx5_empw_new(txq, &mpw, 0);
1500 mpw_room -= mpw.total_len;
1502 do_inline = length <= txq->inline_max_packet_sz &&
1503 sizeof(inl_hdr) + length <= mpw_room &&
1505 mpw.wqe->eseg.cs_flags = cs_flags;
1507 /* Evaluate whether the next packet can be inlined.
1508 * Inlininig is possible when:
1509 * - length is less than configured value
1510 * - length fits for remaining space
1511 * - not required to fill the title WQEBB with dsegs
1514 length <= txq->inline_max_packet_sz &&
1515 inl_pad + sizeof(inl_hdr) + length <=
1517 (!txq->mpw_hdr_dseg ||
1518 mpw.total_len >= MLX5_WQE_SIZE);
1520 if (max_inline && do_inline) {
1521 /* Inline packet into WQE. */
1524 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1525 assert(length == DATA_LEN(buf));
1526 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1527 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1528 mpw.data.raw = (volatile void *)
1529 ((uintptr_t)mpw.data.raw + inl_pad);
1530 max = tx_mlx5_wq_tailroom(txq,
1531 (void *)(uintptr_t)mpw.data.raw);
1532 /* Copy inline header. */
1533 mpw.data.raw = (volatile void *)
1535 (void *)(uintptr_t)mpw.data.raw,
1538 (void *)(uintptr_t)txq->wqes,
1540 max = tx_mlx5_wq_tailroom(txq,
1541 (void *)(uintptr_t)mpw.data.raw);
1542 /* Copy packet data. */
1543 mpw.data.raw = (volatile void *)
1545 (void *)(uintptr_t)mpw.data.raw,
1548 (void *)(uintptr_t)txq->wqes,
1551 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1552 /* No need to get completion as the entire packet is
1553 * copied to WQ. Free the buf right away.
1555 rte_pktmbuf_free_seg(buf);
1556 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1557 /* Add pad in the next packet if any. */
1558 inl_pad = (((uintptr_t)mpw.data.raw +
1559 (MLX5_WQE_DWORD_SIZE - 1)) &
1560 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1561 (uintptr_t)mpw.data.raw;
1563 /* No inline. Load a dseg of packet pointer. */
1564 volatile rte_v128u32_t *dseg;
1566 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1567 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1568 assert(length == DATA_LEN(buf));
1569 if (!tx_mlx5_wq_tailroom(txq,
1570 (void *)((uintptr_t)mpw.data.raw
1572 dseg = (volatile void *)txq->wqes;
1574 dseg = (volatile void *)
1575 ((uintptr_t)mpw.data.raw +
1577 (*txq->elts)[elts_head++ & elts_m] = buf;
1578 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1580 *dseg = (rte_v128u32_t) {
1581 rte_cpu_to_be_32(length),
1582 mlx5_tx_mb2mr(txq, buf),
1586 mpw.data.raw = (volatile void *)(dseg + 1);
1587 mpw.total_len += (inl_pad + sizeof(*dseg));
1590 mpw_room -= (inl_pad + sizeof(*dseg));
1593 #ifdef MLX5_PMD_SOFT_COUNTERS
1594 /* Increment sent bytes counter. */
1595 txq->stats.obytes += length;
1598 } while (i < pkts_n);
1599 /* Take a shortcut if nothing must be sent. */
1600 if (unlikely(i == 0))
1602 /* Check whether completion threshold has been reached. */
1603 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1604 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1605 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1606 volatile struct mlx5_wqe *wqe = mpw.wqe;
1608 /* Request completion on last WQE. */
1609 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1610 /* Save elts_head in unused "immediate" field of WQE. */
1611 wqe->ctrl[3] = elts_head;
1613 txq->mpw_comp = txq->wqe_ci;
1618 txq->elts_comp += j;
1620 #ifdef MLX5_PMD_SOFT_COUNTERS
1621 /* Increment sent packets counter. */
1622 txq->stats.opackets += i;
1624 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1625 mlx5_empw_close(txq, &mpw);
1626 /* Ring QP doorbell. */
1627 mlx5_tx_dbrec(txq, mpw.wqe);
1628 txq->elts_head = elts_head;
1633 * DPDK callback for TX with Enhanced MPW support.
1636 * Generic pointer to TX queue structure.
1638 * Packets to transmit.
1640 * Number of packets in array.
1643 * Number of packets successfully transmitted (<= pkts_n).
1646 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1648 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1651 while (pkts_n > nb_tx) {
1655 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1657 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1662 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1664 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1674 * Translate RX completion flags to packet type.
1677 * Pointer to RX queue structure.
1681 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1684 * Packet type for struct rte_mbuf.
1686 static inline uint32_t
1687 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1690 uint8_t pinfo = cqe->pkt_info;
1691 uint16_t ptype = cqe->hdr_type_etc;
1694 * The index to the array should have:
1695 * bit[1:0] = l3_hdr_type
1696 * bit[4:2] = l4_hdr_type
1699 * bit[7] = outer_l3_type
1701 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1702 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
1706 * Get size of the next packet for a given CQE. For compressed CQEs, the
1707 * consumer index is updated only once all packets of the current one have
1711 * Pointer to RX queue.
1714 * @param[out] rss_hash
1715 * Packet RSS Hash result.
1718 * Packet size in bytes (0 if there is none), -1 in case of completion
1722 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1723 uint16_t cqe_cnt, uint32_t *rss_hash)
1725 struct rxq_zip *zip = &rxq->zip;
1726 uint16_t cqe_n = cqe_cnt + 1;
1730 /* Process compressed data in the CQE and mini arrays. */
1732 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1733 (volatile struct mlx5_mini_cqe8 (*)[8])
1734 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1736 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1737 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1738 if ((++zip->ai & 7) == 0) {
1739 /* Invalidate consumed CQEs */
1742 while (idx != end) {
1743 (*rxq->cqes)[idx & cqe_cnt].op_own =
1744 MLX5_CQE_INVALIDATE;
1748 * Increment consumer index to skip the number of
1749 * CQEs consumed. Hardware leaves holes in the CQ
1750 * ring for software use.
1755 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1756 /* Invalidate the rest */
1760 while (idx != end) {
1761 (*rxq->cqes)[idx & cqe_cnt].op_own =
1762 MLX5_CQE_INVALIDATE;
1765 rxq->cq_ci = zip->cq_ci;
1768 /* No compressed data, get next CQE and verify if it is compressed. */
1773 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1774 if (unlikely(ret == 1))
1777 op_own = cqe->op_own;
1779 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1780 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1781 (volatile struct mlx5_mini_cqe8 (*)[8])
1782 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1785 /* Fix endianness. */
1786 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1788 * Current mini array position is the one returned by
1791 * If completion comprises several mini arrays, as a
1792 * special case the second one is located 7 CQEs after
1793 * the initial CQE instead of 8 for subsequent ones.
1795 zip->ca = rxq->cq_ci;
1796 zip->na = zip->ca + 7;
1797 /* Compute the next non compressed CQE. */
1799 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1800 /* Get packet size to return. */
1801 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1802 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1804 /* Prefetch all the entries to be invalidated */
1807 while (idx != end) {
1808 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1812 len = rte_be_to_cpu_32(cqe->byte_cnt);
1813 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1815 /* Error while receiving packet. */
1816 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1823 * Translate RX completion flags to offload flags.
1829 * Offload flags (ol_flags) for struct rte_mbuf.
1831 static inline uint32_t
1832 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1834 uint32_t ol_flags = 0;
1835 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1839 MLX5_CQE_RX_L3_HDR_VALID,
1840 PKT_RX_IP_CKSUM_GOOD) |
1842 MLX5_CQE_RX_L4_HDR_VALID,
1843 PKT_RX_L4_CKSUM_GOOD);
1848 * Fill in mbuf fields from RX completion flags.
1849 * Note that pkt->ol_flags should be initialized outside of this function.
1852 * Pointer to RX queue.
1857 * @param rss_hash_res
1858 * Packet RSS Hash result.
1861 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1862 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1864 /* Update packet information. */
1865 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1866 if (rss_hash_res && rxq->rss_hash) {
1867 pkt->hash.rss = rss_hash_res;
1868 pkt->ol_flags |= PKT_RX_RSS_HASH;
1870 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1871 pkt->ol_flags |= PKT_RX_FDIR;
1872 if (cqe->sop_drop_qpn !=
1873 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1874 uint32_t mark = cqe->sop_drop_qpn;
1876 pkt->ol_flags |= PKT_RX_FDIR_ID;
1877 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1881 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1882 if (rxq->vlan_strip &&
1883 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1884 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1885 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1887 if (rxq->hw_timestamp) {
1888 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1889 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1894 * DPDK callback for RX.
1897 * Generic pointer to RX queue structure.
1899 * Array to store received packets.
1901 * Maximum number of packets in array.
1904 * Number of packets successfully received (<= pkts_n).
1907 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1909 struct mlx5_rxq_data *rxq = dpdk_rxq;
1910 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1911 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1912 const unsigned int sges_n = rxq->sges_n;
1913 struct rte_mbuf *pkt = NULL;
1914 struct rte_mbuf *seg = NULL;
1915 volatile struct mlx5_cqe *cqe =
1916 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1918 unsigned int rq_ci = rxq->rq_ci << sges_n;
1919 int len = 0; /* keep its value across iterations. */
1922 unsigned int idx = rq_ci & wqe_cnt;
1923 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1924 struct rte_mbuf *rep = (*rxq->elts)[idx];
1925 uint32_t rss_hash_res = 0;
1933 rep = rte_mbuf_raw_alloc(rxq->mp);
1934 if (unlikely(rep == NULL)) {
1935 ++rxq->stats.rx_nombuf;
1938 * no buffers before we even started,
1939 * bail out silently.
1943 while (pkt != seg) {
1944 assert(pkt != (*rxq->elts)[idx]);
1948 rte_mbuf_raw_free(pkt);
1954 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1955 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1958 rte_mbuf_raw_free(rep);
1961 if (unlikely(len == -1)) {
1962 /* RX error, packet is likely too large. */
1963 rte_mbuf_raw_free(rep);
1964 ++rxq->stats.idropped;
1968 assert(len >= (rxq->crc_present << 2));
1970 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1971 if (rxq->crc_present)
1972 len -= ETHER_CRC_LEN;
1975 DATA_LEN(rep) = DATA_LEN(seg);
1976 PKT_LEN(rep) = PKT_LEN(seg);
1977 SET_DATA_OFF(rep, DATA_OFF(seg));
1978 PORT(rep) = PORT(seg);
1979 (*rxq->elts)[idx] = rep;
1981 * Fill NIC descriptor with the new buffer. The lkey and size
1982 * of the buffers are already known, only the buffer address
1985 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1986 /* If there's only one MR, no need to replace LKey in WQE. */
1987 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1988 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1989 if (len > DATA_LEN(seg)) {
1990 len -= DATA_LEN(seg);
1995 DATA_LEN(seg) = len;
1996 #ifdef MLX5_PMD_SOFT_COUNTERS
1997 /* Increment bytes counter. */
1998 rxq->stats.ibytes += PKT_LEN(pkt);
2000 /* Return packet. */
2006 /* Align consumer index to the next stride. */
2011 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
2013 /* Update the consumer index. */
2014 rxq->rq_ci = rq_ci >> sges_n;
2016 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2018 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2019 #ifdef MLX5_PMD_SOFT_COUNTERS
2020 /* Increment packets counter. */
2021 rxq->stats.ipackets += i;
2027 * Dummy DPDK callback for TX.
2029 * This function is used to temporarily replace the real callback during
2030 * unsafe control operations on the queue, or in case of error.
2033 * Generic pointer to TX queue structure.
2035 * Packets to transmit.
2037 * Number of packets in array.
2040 * Number of packets successfully transmitted (<= pkts_n).
2043 removed_tx_burst(void *dpdk_txq __rte_unused,
2044 struct rte_mbuf **pkts __rte_unused,
2045 uint16_t pkts_n __rte_unused)
2051 * Dummy DPDK callback for RX.
2053 * This function is used to temporarily replace the real callback during
2054 * unsafe control operations on the queue, or in case of error.
2057 * Generic pointer to RX queue structure.
2059 * Array to store received packets.
2061 * Maximum number of packets in array.
2064 * Number of packets successfully received (<= pkts_n).
2067 removed_rx_burst(void *dpdk_txq __rte_unused,
2068 struct rte_mbuf **pkts __rte_unused,
2069 uint16_t pkts_n __rte_unused)
2075 * Vectorized Rx/Tx routines are not compiled in when required vector
2076 * instructions are not supported on a target architecture. The following null
2077 * stubs are needed for linkage when those are not included outside of this file
2078 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2081 uint16_t __attribute__((weak))
2082 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2083 struct rte_mbuf **pkts __rte_unused,
2084 uint16_t pkts_n __rte_unused)
2089 uint16_t __attribute__((weak))
2090 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2091 struct rte_mbuf **pkts __rte_unused,
2092 uint16_t pkts_n __rte_unused)
2097 uint16_t __attribute__((weak))
2098 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2099 struct rte_mbuf **pkts __rte_unused,
2100 uint16_t pkts_n __rte_unused)
2105 int __attribute__((weak))
2106 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2111 int __attribute__((weak))
2112 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2117 int __attribute__((weak))
2118 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2123 int __attribute__((weak))
2124 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)