1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
30 #include "mlx5_utils.h"
31 #include "mlx5_rxtx.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 static __rte_always_inline uint32_t
37 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
39 static __rte_always_inline int
40 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
41 uint16_t cqe_cnt, uint32_t *rss_hash);
43 static __rte_always_inline uint32_t
44 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
46 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
47 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
50 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
51 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
54 * Build a table to translate Rx completion flags to packet type.
56 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
59 mlx5_set_ptype_table(void)
62 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
64 /* Last entry must not be overwritten, reserved for errored packet. */
65 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
66 (*p)[i] = RTE_PTYPE_UNKNOWN;
68 * The index to the array should have:
69 * bit[1:0] = l3_hdr_type
70 * bit[4:2] = l4_hdr_type
73 * bit[7] = outer_l3_type
76 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
78 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
80 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
83 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
85 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
88 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
90 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
92 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
94 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
96 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
98 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
101 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
103 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
105 /* Repeat with outer_l3_type being set. Just in case. */
106 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
107 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
109 RTE_PTYPE_L4_NONFRAG;
110 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
112 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
114 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
116 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
128 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
132 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
133 RTE_PTYPE_INNER_L4_NONFRAG;
134 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
136 RTE_PTYPE_INNER_L4_NONFRAG;
137 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
138 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
139 RTE_PTYPE_INNER_L4_NONFRAG;
140 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 /* Tunneled - Fragmented */
144 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
146 RTE_PTYPE_INNER_L4_FRAG;
147 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
149 RTE_PTYPE_INNER_L4_FRAG;
150 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
152 RTE_PTYPE_INNER_L4_FRAG;
153 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
157 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
159 RTE_PTYPE_INNER_L4_TCP;
160 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
162 RTE_PTYPE_INNER_L4_TCP;
163 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
165 RTE_PTYPE_INNER_L4_TCP;
166 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
178 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L4_TCP;
181 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
182 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L4_TCP;
184 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L4_TCP;
187 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L4_TCP;
190 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
191 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
192 RTE_PTYPE_INNER_L4_TCP;
194 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
196 RTE_PTYPE_INNER_L4_UDP;
197 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
198 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
199 RTE_PTYPE_INNER_L4_UDP;
200 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
201 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
202 RTE_PTYPE_INNER_L4_UDP;
203 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
204 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
205 RTE_PTYPE_INNER_L4_UDP;
209 * Build a table to translate packet to checksum type of Verbs.
212 mlx5_set_cksum_table(void)
218 * The index should have:
219 * bit[0] = PKT_TX_TCP_SEG
220 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
221 * bit[4] = PKT_TX_IP_CKSUM
222 * bit[8] = PKT_TX_OUTER_IP_CKSUM
225 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
228 /* Tunneled packet. */
229 if (i & (1 << 8)) /* Outer IP. */
230 v |= MLX5_ETH_WQE_L3_CSUM;
231 if (i & (1 << 4)) /* Inner IP. */
232 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
233 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
234 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
237 if (i & (1 << 4)) /* IP. */
238 v |= MLX5_ETH_WQE_L3_CSUM;
239 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
240 v |= MLX5_ETH_WQE_L4_CSUM;
242 mlx5_cksum_table[i] = v;
247 * Build a table to translate packet type of mbuf to SWP type of Verbs.
250 mlx5_set_swp_types_table(void)
256 * The index should have:
257 * bit[0:1] = PKT_TX_L4_MASK
258 * bit[4] = PKT_TX_IPV6
259 * bit[8] = PKT_TX_OUTER_IPV6
260 * bit[9] = PKT_TX_OUTER_UDP
262 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
265 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
267 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
269 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
270 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
271 v |= MLX5_ETH_WQE_L4_INNER_UDP;
272 mlx5_swp_types_table[i] = v;
277 * Return the size of tailroom of WQ.
280 * Pointer to TX queue structure.
282 * Pointer to tail of WQ.
288 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
291 tailroom = (uintptr_t)(txq->wqes) +
292 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
298 * Copy data to tailroom of circular queue.
301 * Pointer to destination.
305 * Number of bytes to copy.
307 * Pointer to head of queue.
309 * Size of tailroom from dst.
312 * Pointer after copied data.
315 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
316 void *base, size_t tailroom)
321 rte_memcpy(dst, src, tailroom);
322 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
324 ret = (uint8_t *)base + n - tailroom;
326 rte_memcpy(dst, src, n);
327 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
333 * Inline TSO headers into WQE.
336 * 0 on success, negative errno value on failure.
339 inline_tso(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
342 uint16_t *pkt_inline_sz,
346 uint16_t *tso_header_sz)
348 uintptr_t end = (uintptr_t)(((uintptr_t)txq->wqes) +
349 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
351 uint8_t vlan_sz = (buf->ol_flags & PKT_TX_VLAN_PKT) ? 4 : 0;
352 const uint8_t tunneled = txq->tunnel_en && (buf->ol_flags &
356 *tso_segsz = buf->tso_segsz;
357 *tso_header_sz = buf->l2_len + vlan_sz + buf->l3_len + buf->l4_len;
358 if (unlikely(*tso_segsz == 0 || *tso_header_sz == 0)) {
359 txq->stats.oerrors++;
363 *tso_header_sz += buf->outer_l2_len + buf->outer_l3_len;
364 /* First seg must contain all TSO headers. */
365 if (unlikely(*tso_header_sz > MLX5_MAX_TSO_HEADER) ||
366 *tso_header_sz > DATA_LEN(buf)) {
367 txq->stats.oerrors++;
370 copy_b = *tso_header_sz - *pkt_inline_sz;
371 if (!copy_b || ((end - (uintptr_t)*raw) < copy_b))
373 n_wqe = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
374 if (unlikely(*max_wqe < n_wqe))
377 rte_memcpy((void *)*raw, (void *)*addr, copy_b);
380 copy_b = MLX5_WQE_DS(copy_b) * MLX5_WQE_DWORD_SIZE;
381 *pkt_inline_sz += copy_b;
387 * DPDK callback to check the status of a tx descriptor.
392 * The index of the descriptor in the ring.
395 * The status of the tx descriptor.
398 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
400 struct mlx5_txq_data *txq = tx_queue;
403 mlx5_tx_complete(txq);
404 used = txq->elts_head - txq->elts_tail;
406 return RTE_ETH_TX_DESC_FULL;
407 return RTE_ETH_TX_DESC_DONE;
411 * DPDK callback to check the status of a rx descriptor.
416 * The index of the descriptor in the ring.
419 * The status of the tx descriptor.
422 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
424 struct mlx5_rxq_data *rxq = rx_queue;
425 struct rxq_zip *zip = &rxq->zip;
426 volatile struct mlx5_cqe *cqe;
427 const unsigned int cqe_n = (1 << rxq->cqe_n);
428 const unsigned int cqe_cnt = cqe_n - 1;
432 /* if we are processing a compressed cqe */
434 used = zip->cqe_cnt - zip->ca;
440 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
441 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
445 op_own = cqe->op_own;
446 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
447 n = rte_be_to_cpu_32(cqe->byte_cnt);
452 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
454 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
456 return RTE_ETH_RX_DESC_DONE;
457 return RTE_ETH_RX_DESC_AVAIL;
461 * DPDK callback for TX.
464 * Generic pointer to TX queue structure.
466 * Packets to transmit.
468 * Number of packets in array.
471 * Number of packets successfully transmitted (<= pkts_n).
474 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
476 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
477 uint16_t elts_head = txq->elts_head;
478 const uint16_t elts_n = 1 << txq->elts_n;
479 const uint16_t elts_m = elts_n - 1;
486 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
487 unsigned int segs_n = 0;
488 const unsigned int max_inline = txq->max_inline;
490 if (unlikely(!pkts_n))
492 /* Prefetch first packet cacheline. */
493 rte_prefetch0(*pkts);
494 /* Start processing. */
495 mlx5_tx_complete(txq);
496 max_elts = (elts_n - (elts_head - txq->elts_tail));
497 /* A CQE slot must always be available. */
498 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
499 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
500 if (unlikely(!max_wqe))
503 struct rte_mbuf *buf = *pkts; /* First_seg. */
505 volatile struct mlx5_wqe_v *wqe = NULL;
506 volatile rte_v128u32_t *dseg = NULL;
509 unsigned int sg = 0; /* counter of additional segs attached. */
511 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
512 uint16_t tso_header_sz = 0;
515 uint8_t tso = txq->tso_en && (buf->ol_flags & PKT_TX_TCP_SEG);
516 uint8_t is_vlan = !!(buf->ol_flags & PKT_TX_VLAN_PKT);
517 uint32_t swp_offsets = 0;
518 uint8_t swp_types = 0;
519 uint16_t tso_segsz = 0;
520 #ifdef MLX5_PMD_SOFT_COUNTERS
521 uint32_t total_length = 0;
525 segs_n = buf->nb_segs;
527 * Make sure there is enough room to store this packet and
528 * that one ring entry remains unused.
531 if (max_elts < segs_n)
535 if (unlikely(--max_wqe == 0))
537 wqe = (volatile struct mlx5_wqe_v *)
538 tx_mlx5_wqe(txq, txq->wqe_ci);
539 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
541 rte_prefetch0(*(pkts + 1));
542 addr = rte_pktmbuf_mtod(buf, uintptr_t);
543 length = DATA_LEN(buf);
544 ehdr = (((uint8_t *)addr)[1] << 8) |
545 ((uint8_t *)addr)[0];
546 #ifdef MLX5_PMD_SOFT_COUNTERS
547 total_length = length;
549 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
550 txq->stats.oerrors++;
553 /* Update element. */
554 (*txq->elts)[elts_head & elts_m] = buf;
555 /* Prefetch next buffer data. */
558 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
559 cs_flags = txq_ol_cksum_to_cs(buf);
560 txq_mbuf_to_swp(txq, buf, tso, is_vlan,
561 (uint8_t *)&swp_offsets, &swp_types);
562 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
563 /* Replace the Ethernet type by the VLAN if necessary. */
565 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
567 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
571 /* Copy Destination and source mac address. */
572 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
574 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
575 /* Copy missing two bytes to end the DSeg. */
576 memcpy((uint8_t *)raw + len + sizeof(vlan),
577 ((uint8_t *)addr) + len, 2);
581 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
582 MLX5_WQE_DWORD_SIZE);
583 length -= pkt_inline_sz;
584 addr += pkt_inline_sz;
586 raw += MLX5_WQE_DWORD_SIZE;
588 ret = inline_tso(txq, buf, &length,
589 &addr, &pkt_inline_sz,
591 &tso_segsz, &tso_header_sz);
592 if (ret == -EINVAL) {
594 } else if (ret == -EAGAIN) {
596 wqe->ctrl = (rte_v128u32_t){
597 rte_cpu_to_be_32(txq->wqe_ci << 8),
598 rte_cpu_to_be_32(txq->qp_num_8s | 1),
603 #ifdef MLX5_PMD_SOFT_COUNTERS
610 /* Inline if enough room. */
611 if (max_inline || tso) {
613 uintptr_t end = (uintptr_t)
614 (((uintptr_t)txq->wqes) +
615 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
616 unsigned int inline_room = max_inline *
617 RTE_CACHE_LINE_SIZE -
618 (pkt_inline_sz - 2) -
624 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
625 RTE_CACHE_LINE_SIZE);
626 copy_b = (addr_end > addr) ?
627 RTE_MIN((addr_end - addr), length) : 0;
628 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
630 * One Dseg remains in the current WQE. To
631 * keep the computation positive, it is
632 * removed after the bytes to Dseg conversion.
634 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
636 if (unlikely(max_wqe < n))
640 inl = rte_cpu_to_be_32(copy_b |
642 rte_memcpy((void *)raw,
643 (void *)&inl, sizeof(inl));
645 pkt_inline_sz += sizeof(inl);
647 rte_memcpy((void *)raw, (void *)addr, copy_b);
650 pkt_inline_sz += copy_b;
653 * 2 DWORDs consumed by the WQE header + ETH segment +
654 * the size of the inline part of the packet.
656 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
658 if (ds % (MLX5_WQE_SIZE /
659 MLX5_WQE_DWORD_SIZE) == 0) {
660 if (unlikely(--max_wqe == 0))
662 dseg = (volatile rte_v128u32_t *)
663 tx_mlx5_wqe(txq, txq->wqe_ci +
666 dseg = (volatile rte_v128u32_t *)
668 (ds * MLX5_WQE_DWORD_SIZE));
671 } else if (!segs_n) {
675 inline_room -= copy_b;
679 addr = rte_pktmbuf_mtod(buf, uintptr_t);
680 length = DATA_LEN(buf);
681 #ifdef MLX5_PMD_SOFT_COUNTERS
682 total_length += length;
684 (*txq->elts)[++elts_head & elts_m] = buf;
689 * No inline has been done in the packet, only the
690 * Ethernet Header as been stored.
692 dseg = (volatile rte_v128u32_t *)
693 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
696 /* Add the remaining packet as a simple ds. */
697 addr = rte_cpu_to_be_64(addr);
698 *dseg = (rte_v128u32_t){
699 rte_cpu_to_be_32(length),
700 mlx5_tx_mb2mr(txq, buf),
713 * Spill on next WQE when the current one does not have
714 * enough room left. Size of WQE must a be a multiple
715 * of data segment size.
717 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
718 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
719 if (unlikely(--max_wqe == 0))
721 dseg = (volatile rte_v128u32_t *)
722 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
723 rte_prefetch0(tx_mlx5_wqe(txq,
724 txq->wqe_ci + ds / 4 + 1));
731 length = DATA_LEN(buf);
732 #ifdef MLX5_PMD_SOFT_COUNTERS
733 total_length += length;
735 /* Store segment information. */
736 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
737 *dseg = (rte_v128u32_t){
738 rte_cpu_to_be_32(length),
739 mlx5_tx_mb2mr(txq, buf),
743 (*txq->elts)[++elts_head & elts_m] = buf;
747 if (ds > MLX5_DSEG_MAX) {
748 txq->stats.oerrors++;
755 /* Initialize known and common part of the WQE structure. */
757 wqe->ctrl = (rte_v128u32_t){
758 rte_cpu_to_be_32((txq->wqe_ci << 8) |
760 rte_cpu_to_be_32(txq->qp_num_8s | ds),
764 wqe->eseg = (rte_v128u32_t){
766 cs_flags | (swp_types << 8) |
767 (rte_cpu_to_be_16(tso_segsz) << 16),
769 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
772 wqe->ctrl = (rte_v128u32_t){
773 rte_cpu_to_be_32((txq->wqe_ci << 8) |
775 rte_cpu_to_be_32(txq->qp_num_8s | ds),
779 wqe->eseg = (rte_v128u32_t){
781 cs_flags | (swp_types << 8),
783 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
787 txq->wqe_ci += (ds + 3) / 4;
788 /* Save the last successful WQE for completion request */
789 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
790 #ifdef MLX5_PMD_SOFT_COUNTERS
791 /* Increment sent bytes counter. */
792 txq->stats.obytes += total_length;
794 } while (i < pkts_n);
795 /* Take a shortcut if nothing must be sent. */
796 if (unlikely((i + k) == 0))
798 txq->elts_head += (i + j);
799 /* Check whether completion threshold has been reached. */
800 comp = txq->elts_comp + i + j + k;
801 if (comp >= MLX5_TX_COMP_THRESH) {
802 /* Request completion on last WQE. */
803 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
804 /* Save elts_head in unused "immediate" field of WQE. */
805 last_wqe->ctrl3 = txq->elts_head;
811 txq->elts_comp = comp;
813 #ifdef MLX5_PMD_SOFT_COUNTERS
814 /* Increment sent packets counter. */
815 txq->stats.opackets += i;
817 /* Ring QP doorbell. */
818 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
823 * Open a MPW session.
826 * Pointer to TX queue structure.
828 * Pointer to MPW session structure.
833 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
835 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
836 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
837 (volatile struct mlx5_wqe_data_seg (*)[])
838 tx_mlx5_wqe(txq, idx + 1);
840 mpw->state = MLX5_MPW_STATE_OPENED;
844 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
845 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
846 mpw->wqe->eseg.inline_hdr_sz = 0;
847 mpw->wqe->eseg.rsvd0 = 0;
848 mpw->wqe->eseg.rsvd1 = 0;
849 mpw->wqe->eseg.rsvd2 = 0;
850 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
853 mpw->wqe->ctrl[2] = 0;
854 mpw->wqe->ctrl[3] = 0;
855 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
856 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
857 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
858 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
859 mpw->data.dseg[2] = &(*dseg)[0];
860 mpw->data.dseg[3] = &(*dseg)[1];
861 mpw->data.dseg[4] = &(*dseg)[2];
865 * Close a MPW session.
868 * Pointer to TX queue structure.
870 * Pointer to MPW session structure.
873 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
875 unsigned int num = mpw->pkts_n;
878 * Store size in multiple of 16 bytes. Control and Ethernet segments
881 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
882 mpw->state = MLX5_MPW_STATE_CLOSED;
887 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
888 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
892 * DPDK callback for TX with MPW support.
895 * Generic pointer to TX queue structure.
897 * Packets to transmit.
899 * Number of packets in array.
902 * Number of packets successfully transmitted (<= pkts_n).
905 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
907 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
908 uint16_t elts_head = txq->elts_head;
909 const uint16_t elts_n = 1 << txq->elts_n;
910 const uint16_t elts_m = elts_n - 1;
916 struct mlx5_mpw mpw = {
917 .state = MLX5_MPW_STATE_CLOSED,
920 if (unlikely(!pkts_n))
922 /* Prefetch first packet cacheline. */
923 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
924 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
925 /* Start processing. */
926 mlx5_tx_complete(txq);
927 max_elts = (elts_n - (elts_head - txq->elts_tail));
928 /* A CQE slot must always be available. */
929 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
930 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
931 if (unlikely(!max_wqe))
934 struct rte_mbuf *buf = *(pkts++);
936 unsigned int segs_n = buf->nb_segs;
940 * Make sure there is enough room to store this packet and
941 * that one ring entry remains unused.
944 if (max_elts < segs_n)
946 /* Do not bother with large packets MPW cannot handle. */
947 if (segs_n > MLX5_MPW_DSEG_MAX) {
948 txq->stats.oerrors++;
953 cs_flags = txq_ol_cksum_to_cs(buf);
954 /* Retrieve packet information. */
955 length = PKT_LEN(buf);
957 /* Start new session if packet differs. */
958 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
959 ((mpw.len != length) ||
961 (mpw.wqe->eseg.cs_flags != cs_flags)))
962 mlx5_mpw_close(txq, &mpw);
963 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
965 * Multi-Packet WQE consumes at most two WQE.
966 * mlx5_mpw_new() expects to be able to use such
969 if (unlikely(max_wqe < 2))
972 mlx5_mpw_new(txq, &mpw, length);
973 mpw.wqe->eseg.cs_flags = cs_flags;
975 /* Multi-segment packets must be alone in their MPW. */
976 assert((segs_n == 1) || (mpw.pkts_n == 0));
977 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
981 volatile struct mlx5_wqe_data_seg *dseg;
985 (*txq->elts)[elts_head++ & elts_m] = buf;
986 dseg = mpw.data.dseg[mpw.pkts_n];
987 addr = rte_pktmbuf_mtod(buf, uintptr_t);
988 *dseg = (struct mlx5_wqe_data_seg){
989 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
990 .lkey = mlx5_tx_mb2mr(txq, buf),
991 .addr = rte_cpu_to_be_64(addr),
993 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
994 length += DATA_LEN(buf);
1000 assert(length == mpw.len);
1001 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1002 mlx5_mpw_close(txq, &mpw);
1003 #ifdef MLX5_PMD_SOFT_COUNTERS
1004 /* Increment sent bytes counter. */
1005 txq->stats.obytes += length;
1009 /* Take a shortcut if nothing must be sent. */
1010 if (unlikely(i == 0))
1012 /* Check whether completion threshold has been reached. */
1013 /* "j" includes both packets and segments. */
1014 comp = txq->elts_comp + j;
1015 if (comp >= MLX5_TX_COMP_THRESH) {
1016 volatile struct mlx5_wqe *wqe = mpw.wqe;
1018 /* Request completion on last WQE. */
1019 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1020 /* Save elts_head in unused "immediate" field of WQE. */
1021 wqe->ctrl[3] = elts_head;
1027 txq->elts_comp = comp;
1029 #ifdef MLX5_PMD_SOFT_COUNTERS
1030 /* Increment sent packets counter. */
1031 txq->stats.opackets += i;
1033 /* Ring QP doorbell. */
1034 if (mpw.state == MLX5_MPW_STATE_OPENED)
1035 mlx5_mpw_close(txq, &mpw);
1036 mlx5_tx_dbrec(txq, mpw.wqe);
1037 txq->elts_head = elts_head;
1042 * Open a MPW inline session.
1045 * Pointer to TX queue structure.
1047 * Pointer to MPW session structure.
1052 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
1055 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1056 struct mlx5_wqe_inl_small *inl;
1058 mpw->state = MLX5_MPW_INL_STATE_OPENED;
1062 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1063 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
1064 (txq->wqe_ci << 8) |
1066 mpw->wqe->ctrl[2] = 0;
1067 mpw->wqe->ctrl[3] = 0;
1068 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
1069 mpw->wqe->eseg.inline_hdr_sz = 0;
1070 mpw->wqe->eseg.cs_flags = 0;
1071 mpw->wqe->eseg.rsvd0 = 0;
1072 mpw->wqe->eseg.rsvd1 = 0;
1073 mpw->wqe->eseg.rsvd2 = 0;
1074 inl = (struct mlx5_wqe_inl_small *)
1075 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
1076 mpw->data.raw = (uint8_t *)&inl->raw;
1080 * Close a MPW inline session.
1083 * Pointer to TX queue structure.
1085 * Pointer to MPW session structure.
1088 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1091 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
1092 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
1094 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
1096 * Store size in multiple of 16 bytes. Control and Ethernet segments
1099 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1101 mpw->state = MLX5_MPW_STATE_CLOSED;
1102 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1103 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1107 * DPDK callback for TX with MPW inline support.
1110 * Generic pointer to TX queue structure.
1112 * Packets to transmit.
1114 * Number of packets in array.
1117 * Number of packets successfully transmitted (<= pkts_n).
1120 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1123 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1124 uint16_t elts_head = txq->elts_head;
1125 const uint16_t elts_n = 1 << txq->elts_n;
1126 const uint16_t elts_m = elts_n - 1;
1132 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1133 struct mlx5_mpw mpw = {
1134 .state = MLX5_MPW_STATE_CLOSED,
1137 * Compute the maximum number of WQE which can be consumed by inline
1140 * - 1 control segment,
1141 * - 1 Ethernet segment,
1142 * - N Dseg from the inline request.
1144 const unsigned int wqe_inl_n =
1145 ((2 * MLX5_WQE_DWORD_SIZE +
1146 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1147 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1149 if (unlikely(!pkts_n))
1151 /* Prefetch first packet cacheline. */
1152 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1153 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1154 /* Start processing. */
1155 mlx5_tx_complete(txq);
1156 max_elts = (elts_n - (elts_head - txq->elts_tail));
1157 /* A CQE slot must always be available. */
1158 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1160 struct rte_mbuf *buf = *(pkts++);
1163 unsigned int segs_n = buf->nb_segs;
1167 * Make sure there is enough room to store this packet and
1168 * that one ring entry remains unused.
1171 if (max_elts < segs_n)
1173 /* Do not bother with large packets MPW cannot handle. */
1174 if (segs_n > MLX5_MPW_DSEG_MAX) {
1175 txq->stats.oerrors++;
1181 * Compute max_wqe in case less WQE were consumed in previous
1184 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1185 cs_flags = txq_ol_cksum_to_cs(buf);
1186 /* Retrieve packet information. */
1187 length = PKT_LEN(buf);
1188 /* Start new session if packet differs. */
1189 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1190 if ((mpw.len != length) ||
1192 (mpw.wqe->eseg.cs_flags != cs_flags))
1193 mlx5_mpw_close(txq, &mpw);
1194 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1195 if ((mpw.len != length) ||
1197 (length > inline_room) ||
1198 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1199 mlx5_mpw_inline_close(txq, &mpw);
1201 txq->max_inline * RTE_CACHE_LINE_SIZE;
1204 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1205 if ((segs_n != 1) ||
1206 (length > inline_room)) {
1208 * Multi-Packet WQE consumes at most two WQE.
1209 * mlx5_mpw_new() expects to be able to use
1212 if (unlikely(max_wqe < 2))
1215 mlx5_mpw_new(txq, &mpw, length);
1216 mpw.wqe->eseg.cs_flags = cs_flags;
1218 if (unlikely(max_wqe < wqe_inl_n))
1220 max_wqe -= wqe_inl_n;
1221 mlx5_mpw_inline_new(txq, &mpw, length);
1222 mpw.wqe->eseg.cs_flags = cs_flags;
1225 /* Multi-segment packets must be alone in their MPW. */
1226 assert((segs_n == 1) || (mpw.pkts_n == 0));
1227 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1228 assert(inline_room ==
1229 txq->max_inline * RTE_CACHE_LINE_SIZE);
1230 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1234 volatile struct mlx5_wqe_data_seg *dseg;
1237 (*txq->elts)[elts_head++ & elts_m] = buf;
1238 dseg = mpw.data.dseg[mpw.pkts_n];
1239 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1240 *dseg = (struct mlx5_wqe_data_seg){
1242 rte_cpu_to_be_32(DATA_LEN(buf)),
1243 .lkey = mlx5_tx_mb2mr(txq, buf),
1244 .addr = rte_cpu_to_be_64(addr),
1246 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1247 length += DATA_LEN(buf);
1253 assert(length == mpw.len);
1254 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1255 mlx5_mpw_close(txq, &mpw);
1259 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1260 assert(length <= inline_room);
1261 assert(length == DATA_LEN(buf));
1262 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1263 (*txq->elts)[elts_head++ & elts_m] = buf;
1264 /* Maximum number of bytes before wrapping. */
1265 max = ((((uintptr_t)(txq->wqes)) +
1268 (uintptr_t)mpw.data.raw);
1270 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1273 mpw.data.raw = (volatile void *)txq->wqes;
1274 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1275 (void *)(addr + max),
1277 mpw.data.raw += length - max;
1279 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1285 (volatile void *)txq->wqes;
1287 mpw.data.raw += length;
1290 mpw.total_len += length;
1292 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1293 mlx5_mpw_inline_close(txq, &mpw);
1295 txq->max_inline * RTE_CACHE_LINE_SIZE;
1297 inline_room -= length;
1300 #ifdef MLX5_PMD_SOFT_COUNTERS
1301 /* Increment sent bytes counter. */
1302 txq->stats.obytes += length;
1306 /* Take a shortcut if nothing must be sent. */
1307 if (unlikely(i == 0))
1309 /* Check whether completion threshold has been reached. */
1310 /* "j" includes both packets and segments. */
1311 comp = txq->elts_comp + j;
1312 if (comp >= MLX5_TX_COMP_THRESH) {
1313 volatile struct mlx5_wqe *wqe = mpw.wqe;
1315 /* Request completion on last WQE. */
1316 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1317 /* Save elts_head in unused "immediate" field of WQE. */
1318 wqe->ctrl[3] = elts_head;
1324 txq->elts_comp = comp;
1326 #ifdef MLX5_PMD_SOFT_COUNTERS
1327 /* Increment sent packets counter. */
1328 txq->stats.opackets += i;
1330 /* Ring QP doorbell. */
1331 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1332 mlx5_mpw_inline_close(txq, &mpw);
1333 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1334 mlx5_mpw_close(txq, &mpw);
1335 mlx5_tx_dbrec(txq, mpw.wqe);
1336 txq->elts_head = elts_head;
1341 * Open an Enhanced MPW session.
1344 * Pointer to TX queue structure.
1346 * Pointer to MPW session structure.
1351 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1353 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1355 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1357 mpw->total_len = sizeof(struct mlx5_wqe);
1358 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1360 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1361 (txq->wqe_ci << 8) |
1362 MLX5_OPCODE_ENHANCED_MPSW);
1363 mpw->wqe->ctrl[2] = 0;
1364 mpw->wqe->ctrl[3] = 0;
1365 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1366 if (unlikely(padding)) {
1367 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1369 /* Pad the first 2 DWORDs with zero-length inline header. */
1370 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1371 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1372 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1373 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1374 /* Start from the next WQEBB. */
1375 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1377 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1382 * Close an Enhanced MPW session.
1385 * Pointer to TX queue structure.
1387 * Pointer to MPW session structure.
1390 * Number of consumed WQEs.
1392 static inline uint16_t
1393 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1397 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1400 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1401 MLX5_WQE_DS(mpw->total_len));
1402 mpw->state = MLX5_MPW_STATE_CLOSED;
1403 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1409 * TX with Enhanced MPW support.
1412 * Pointer to TX queue structure.
1414 * Packets to transmit.
1416 * Number of packets in array.
1419 * Number of packets successfully transmitted (<= pkts_n).
1421 static inline uint16_t
1422 txq_burst_empw(struct mlx5_txq_data *txq, struct rte_mbuf **pkts,
1425 uint16_t elts_head = txq->elts_head;
1426 const uint16_t elts_n = 1 << txq->elts_n;
1427 const uint16_t elts_m = elts_n - 1;
1432 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1433 unsigned int mpw_room = 0;
1434 unsigned int inl_pad = 0;
1436 struct mlx5_mpw mpw = {
1437 .state = MLX5_MPW_STATE_CLOSED,
1440 if (unlikely(!pkts_n))
1442 /* Start processing. */
1443 mlx5_tx_complete(txq);
1444 max_elts = (elts_n - (elts_head - txq->elts_tail));
1445 /* A CQE slot must always be available. */
1446 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1447 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1448 if (unlikely(!max_wqe))
1451 struct rte_mbuf *buf = *(pkts++);
1453 unsigned int do_inline = 0; /* Whether inline is possible. */
1457 /* Multi-segmented packet is handled in slow-path outside. */
1458 assert(NB_SEGS(buf) == 1);
1459 /* Make sure there is enough room to store this packet. */
1460 if (max_elts - j == 0)
1462 cs_flags = txq_ol_cksum_to_cs(buf);
1463 /* Retrieve packet information. */
1464 length = PKT_LEN(buf);
1465 /* Start new session if:
1466 * - multi-segment packet
1467 * - no space left even for a dseg
1468 * - next packet can be inlined with a new WQE
1471 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1472 if ((inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1474 (length <= txq->inline_max_packet_sz &&
1475 inl_pad + sizeof(inl_hdr) + length >
1477 (mpw.wqe->eseg.cs_flags != cs_flags))
1478 max_wqe -= mlx5_empw_close(txq, &mpw);
1480 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1481 /* In Enhanced MPW, inline as much as the budget is
1482 * allowed. The remaining space is to be filled with
1483 * dsegs. If the title WQEBB isn't padded, it will have
1486 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1487 (max_inline ? max_inline :
1488 pkts_n * MLX5_WQE_DWORD_SIZE) +
1490 if (unlikely(max_wqe * MLX5_WQE_SIZE < mpw_room))
1492 /* Don't pad the title WQEBB to not waste WQ. */
1493 mlx5_empw_new(txq, &mpw, 0);
1494 mpw_room -= mpw.total_len;
1496 do_inline = length <= txq->inline_max_packet_sz &&
1497 sizeof(inl_hdr) + length <= mpw_room &&
1499 mpw.wqe->eseg.cs_flags = cs_flags;
1501 /* Evaluate whether the next packet can be inlined.
1502 * Inlininig is possible when:
1503 * - length is less than configured value
1504 * - length fits for remaining space
1505 * - not required to fill the title WQEBB with dsegs
1508 length <= txq->inline_max_packet_sz &&
1509 inl_pad + sizeof(inl_hdr) + length <=
1511 (!txq->mpw_hdr_dseg ||
1512 mpw.total_len >= MLX5_WQE_SIZE);
1514 if (max_inline && do_inline) {
1515 /* Inline packet into WQE. */
1518 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1519 assert(length == DATA_LEN(buf));
1520 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1521 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1522 mpw.data.raw = (volatile void *)
1523 ((uintptr_t)mpw.data.raw + inl_pad);
1524 max = tx_mlx5_wq_tailroom(txq,
1525 (void *)(uintptr_t)mpw.data.raw);
1526 /* Copy inline header. */
1527 mpw.data.raw = (volatile void *)
1529 (void *)(uintptr_t)mpw.data.raw,
1532 (void *)(uintptr_t)txq->wqes,
1534 max = tx_mlx5_wq_tailroom(txq,
1535 (void *)(uintptr_t)mpw.data.raw);
1536 /* Copy packet data. */
1537 mpw.data.raw = (volatile void *)
1539 (void *)(uintptr_t)mpw.data.raw,
1542 (void *)(uintptr_t)txq->wqes,
1545 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1546 /* No need to get completion as the entire packet is
1547 * copied to WQ. Free the buf right away.
1549 rte_pktmbuf_free_seg(buf);
1550 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1551 /* Add pad in the next packet if any. */
1552 inl_pad = (((uintptr_t)mpw.data.raw +
1553 (MLX5_WQE_DWORD_SIZE - 1)) &
1554 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1555 (uintptr_t)mpw.data.raw;
1557 /* No inline. Load a dseg of packet pointer. */
1558 volatile rte_v128u32_t *dseg;
1560 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1561 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1562 assert(length == DATA_LEN(buf));
1563 if (!tx_mlx5_wq_tailroom(txq,
1564 (void *)((uintptr_t)mpw.data.raw
1566 dseg = (volatile void *)txq->wqes;
1568 dseg = (volatile void *)
1569 ((uintptr_t)mpw.data.raw +
1571 (*txq->elts)[elts_head++ & elts_m] = buf;
1572 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf,
1574 *dseg = (rte_v128u32_t) {
1575 rte_cpu_to_be_32(length),
1576 mlx5_tx_mb2mr(txq, buf),
1580 mpw.data.raw = (volatile void *)(dseg + 1);
1581 mpw.total_len += (inl_pad + sizeof(*dseg));
1584 mpw_room -= (inl_pad + sizeof(*dseg));
1587 #ifdef MLX5_PMD_SOFT_COUNTERS
1588 /* Increment sent bytes counter. */
1589 txq->stats.obytes += length;
1592 } while (i < pkts_n);
1593 /* Take a shortcut if nothing must be sent. */
1594 if (unlikely(i == 0))
1596 /* Check whether completion threshold has been reached. */
1597 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1598 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1599 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1600 volatile struct mlx5_wqe *wqe = mpw.wqe;
1602 /* Request completion on last WQE. */
1603 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1604 /* Save elts_head in unused "immediate" field of WQE. */
1605 wqe->ctrl[3] = elts_head;
1607 txq->mpw_comp = txq->wqe_ci;
1612 txq->elts_comp += j;
1614 #ifdef MLX5_PMD_SOFT_COUNTERS
1615 /* Increment sent packets counter. */
1616 txq->stats.opackets += i;
1618 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1619 mlx5_empw_close(txq, &mpw);
1620 /* Ring QP doorbell. */
1621 mlx5_tx_dbrec(txq, mpw.wqe);
1622 txq->elts_head = elts_head;
1627 * DPDK callback for TX with Enhanced MPW support.
1630 * Generic pointer to TX queue structure.
1632 * Packets to transmit.
1634 * Number of packets in array.
1637 * Number of packets successfully transmitted (<= pkts_n).
1640 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1642 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1645 while (pkts_n > nb_tx) {
1649 n = txq_count_contig_multi_seg(&pkts[nb_tx], pkts_n - nb_tx);
1651 ret = mlx5_tx_burst(dpdk_txq, &pkts[nb_tx], n);
1656 n = txq_count_contig_single_seg(&pkts[nb_tx], pkts_n - nb_tx);
1658 ret = txq_burst_empw(txq, &pkts[nb_tx], n);
1668 * Translate RX completion flags to packet type.
1673 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1676 * Packet type for struct rte_mbuf.
1678 static inline uint32_t
1679 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1682 uint8_t pinfo = cqe->pkt_info;
1683 uint16_t ptype = cqe->hdr_type_etc;
1686 * The index to the array should have:
1687 * bit[1:0] = l3_hdr_type
1688 * bit[4:2] = l4_hdr_type
1691 * bit[7] = outer_l3_type
1693 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1694 return mlx5_ptype_table[idx];
1698 * Get size of the next packet for a given CQE. For compressed CQEs, the
1699 * consumer index is updated only once all packets of the current one have
1703 * Pointer to RX queue.
1706 * @param[out] rss_hash
1707 * Packet RSS Hash result.
1710 * Packet size in bytes (0 if there is none), -1 in case of completion
1714 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1715 uint16_t cqe_cnt, uint32_t *rss_hash)
1717 struct rxq_zip *zip = &rxq->zip;
1718 uint16_t cqe_n = cqe_cnt + 1;
1722 /* Process compressed data in the CQE and mini arrays. */
1724 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1725 (volatile struct mlx5_mini_cqe8 (*)[8])
1726 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1728 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1729 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1730 if ((++zip->ai & 7) == 0) {
1731 /* Invalidate consumed CQEs */
1734 while (idx != end) {
1735 (*rxq->cqes)[idx & cqe_cnt].op_own =
1736 MLX5_CQE_INVALIDATE;
1740 * Increment consumer index to skip the number of
1741 * CQEs consumed. Hardware leaves holes in the CQ
1742 * ring for software use.
1747 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1748 /* Invalidate the rest */
1752 while (idx != end) {
1753 (*rxq->cqes)[idx & cqe_cnt].op_own =
1754 MLX5_CQE_INVALIDATE;
1757 rxq->cq_ci = zip->cq_ci;
1760 /* No compressed data, get next CQE and verify if it is compressed. */
1765 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1766 if (unlikely(ret == 1))
1769 op_own = cqe->op_own;
1771 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1772 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1773 (volatile struct mlx5_mini_cqe8 (*)[8])
1774 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1777 /* Fix endianness. */
1778 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1780 * Current mini array position is the one returned by
1783 * If completion comprises several mini arrays, as a
1784 * special case the second one is located 7 CQEs after
1785 * the initial CQE instead of 8 for subsequent ones.
1787 zip->ca = rxq->cq_ci;
1788 zip->na = zip->ca + 7;
1789 /* Compute the next non compressed CQE. */
1791 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1792 /* Get packet size to return. */
1793 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1794 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1796 /* Prefetch all the entries to be invalidated */
1799 while (idx != end) {
1800 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1804 len = rte_be_to_cpu_32(cqe->byte_cnt);
1805 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1807 /* Error while receiving packet. */
1808 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1815 * Translate RX completion flags to offload flags.
1818 * Pointer to RX queue structure.
1823 * Offload flags (ol_flags) for struct rte_mbuf.
1825 static inline uint32_t
1826 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1828 uint32_t ol_flags = 0;
1829 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1833 MLX5_CQE_RX_L3_HDR_VALID,
1834 PKT_RX_IP_CKSUM_GOOD) |
1836 MLX5_CQE_RX_L4_HDR_VALID,
1837 PKT_RX_L4_CKSUM_GOOD);
1838 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1841 MLX5_CQE_RX_L3_HDR_VALID,
1842 PKT_RX_IP_CKSUM_GOOD) |
1844 MLX5_CQE_RX_L4_HDR_VALID,
1845 PKT_RX_L4_CKSUM_GOOD);
1850 * DPDK callback for RX.
1853 * Generic pointer to RX queue structure.
1855 * Array to store received packets.
1857 * Maximum number of packets in array.
1860 * Number of packets successfully received (<= pkts_n).
1863 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1865 struct mlx5_rxq_data *rxq = dpdk_rxq;
1866 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1867 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1868 const unsigned int sges_n = rxq->sges_n;
1869 struct rte_mbuf *pkt = NULL;
1870 struct rte_mbuf *seg = NULL;
1871 volatile struct mlx5_cqe *cqe =
1872 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1874 unsigned int rq_ci = rxq->rq_ci << sges_n;
1875 int len = 0; /* keep its value across iterations. */
1878 unsigned int idx = rq_ci & wqe_cnt;
1879 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1880 struct rte_mbuf *rep = (*rxq->elts)[idx];
1881 uint32_t rss_hash_res = 0;
1889 rep = rte_mbuf_raw_alloc(rxq->mp);
1890 if (unlikely(rep == NULL)) {
1891 ++rxq->stats.rx_nombuf;
1894 * no buffers before we even started,
1895 * bail out silently.
1899 while (pkt != seg) {
1900 assert(pkt != (*rxq->elts)[idx]);
1904 rte_mbuf_raw_free(pkt);
1910 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1911 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1914 rte_mbuf_raw_free(rep);
1917 if (unlikely(len == -1)) {
1918 /* RX error, packet is likely too large. */
1919 rte_mbuf_raw_free(rep);
1920 ++rxq->stats.idropped;
1924 assert(len >= (rxq->crc_present << 2));
1925 /* Update packet information. */
1926 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1928 if (rss_hash_res && rxq->rss_hash) {
1929 pkt->hash.rss = rss_hash_res;
1930 pkt->ol_flags = PKT_RX_RSS_HASH;
1933 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1934 pkt->ol_flags |= PKT_RX_FDIR;
1935 if (cqe->sop_drop_qpn !=
1936 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1937 uint32_t mark = cqe->sop_drop_qpn;
1939 pkt->ol_flags |= PKT_RX_FDIR_ID;
1941 mlx5_flow_mark_get(mark);
1944 if (rxq->csum | rxq->csum_l2tun)
1945 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1946 if (rxq->vlan_strip &&
1947 (cqe->hdr_type_etc &
1948 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1949 pkt->ol_flags |= PKT_RX_VLAN |
1950 PKT_RX_VLAN_STRIPPED;
1952 rte_be_to_cpu_16(cqe->vlan_info);
1954 if (rxq->hw_timestamp) {
1956 rte_be_to_cpu_64(cqe->timestamp);
1957 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1959 if (rxq->crc_present)
1960 len -= ETHER_CRC_LEN;
1963 DATA_LEN(rep) = DATA_LEN(seg);
1964 PKT_LEN(rep) = PKT_LEN(seg);
1965 SET_DATA_OFF(rep, DATA_OFF(seg));
1966 PORT(rep) = PORT(seg);
1967 (*rxq->elts)[idx] = rep;
1969 * Fill NIC descriptor with the new buffer. The lkey and size
1970 * of the buffers are already known, only the buffer address
1973 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1974 if (len > DATA_LEN(seg)) {
1975 len -= DATA_LEN(seg);
1980 DATA_LEN(seg) = len;
1981 #ifdef MLX5_PMD_SOFT_COUNTERS
1982 /* Increment bytes counter. */
1983 rxq->stats.ibytes += PKT_LEN(pkt);
1985 /* Return packet. */
1991 /* Align consumer index to the next stride. */
1996 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1998 /* Update the consumer index. */
1999 rxq->rq_ci = rq_ci >> sges_n;
2001 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
2003 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
2004 #ifdef MLX5_PMD_SOFT_COUNTERS
2005 /* Increment packets counter. */
2006 rxq->stats.ipackets += i;
2012 * Dummy DPDK callback for TX.
2014 * This function is used to temporarily replace the real callback during
2015 * unsafe control operations on the queue, or in case of error.
2018 * Generic pointer to TX queue structure.
2020 * Packets to transmit.
2022 * Number of packets in array.
2025 * Number of packets successfully transmitted (<= pkts_n).
2028 removed_tx_burst(void *dpdk_txq __rte_unused,
2029 struct rte_mbuf **pkts __rte_unused,
2030 uint16_t pkts_n __rte_unused)
2036 * Dummy DPDK callback for RX.
2038 * This function is used to temporarily replace the real callback during
2039 * unsafe control operations on the queue, or in case of error.
2042 * Generic pointer to RX queue structure.
2044 * Array to store received packets.
2046 * Maximum number of packets in array.
2049 * Number of packets successfully received (<= pkts_n).
2052 removed_rx_burst(void *dpdk_txq __rte_unused,
2053 struct rte_mbuf **pkts __rte_unused,
2054 uint16_t pkts_n __rte_unused)
2060 * Vectorized Rx/Tx routines are not compiled in when required vector
2061 * instructions are not supported on a target architecture. The following null
2062 * stubs are needed for linkage when those are not included outside of this file
2063 * (e.g. mlx5_rxtx_vec_sse.c for x86).
2066 uint16_t __attribute__((weak))
2067 mlx5_tx_burst_raw_vec(void *dpdk_txq __rte_unused,
2068 struct rte_mbuf **pkts __rte_unused,
2069 uint16_t pkts_n __rte_unused)
2074 uint16_t __attribute__((weak))
2075 mlx5_tx_burst_vec(void *dpdk_txq __rte_unused,
2076 struct rte_mbuf **pkts __rte_unused,
2077 uint16_t pkts_n __rte_unused)
2082 uint16_t __attribute__((weak))
2083 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
2084 struct rte_mbuf **pkts __rte_unused,
2085 uint16_t pkts_n __rte_unused)
2090 int __attribute__((weak))
2091 mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2096 int __attribute__((weak))
2097 mlx5_check_vec_tx_support(struct rte_eth_dev *dev __rte_unused)
2102 int __attribute__((weak))
2103 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
2108 int __attribute__((weak))
2109 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)