1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #pragma GCC diagnostic ignored "-Wpedantic"
15 #include <infiniband/verbs.h>
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_mempool.h>
23 #include <rte_prefetch.h>
24 #include <rte_common.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_ether.h>
27 #include <rte_cycles.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_common.h>
34 #include "mlx5_defs.h"
36 #include "mlx5_utils.h"
37 #include "mlx5_rxtx.h"
38 #include "mlx5_autoconf.h"
40 /* TX burst subroutines return codes. */
41 enum mlx5_txcmp_code {
42 MLX5_TXCMP_CODE_EXIT = 0,
43 MLX5_TXCMP_CODE_ERROR,
44 MLX5_TXCMP_CODE_SINGLE,
45 MLX5_TXCMP_CODE_MULTI,
51 * These defines are used to configure Tx burst routine option set
52 * supported at compile time. The not specified options are optimized out
53 * out due to if conditions can be explicitly calculated at compile time.
54 * The offloads with bigger runtime check (require more CPU cycles to
55 * skip) overhead should have the bigger index - this is needed to
56 * select the better matching routine function if no exact match and
57 * some offloads are not actually requested.
59 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
60 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
61 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
62 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
63 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
64 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
65 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
66 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
67 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
69 /* The most common offloads groups. */
70 #define MLX5_TXOFF_CONFIG_NONE 0
71 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
72 MLX5_TXOFF_CONFIG_TSO | \
73 MLX5_TXOFF_CONFIG_SWP | \
74 MLX5_TXOFF_CONFIG_CSUM | \
75 MLX5_TXOFF_CONFIG_INLINE | \
76 MLX5_TXOFF_CONFIG_VLAN | \
77 MLX5_TXOFF_CONFIG_METADATA)
79 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
81 #define MLX5_TXOFF_DECL(func, olx) \
82 static uint16_t mlx5_tx_burst_##func(void *txq, \
83 struct rte_mbuf **pkts, \
86 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
87 pkts, pkts_n, (olx)); \
90 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
92 static __rte_always_inline uint32_t
93 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
95 static __rte_always_inline int
96 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
97 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
99 static __rte_always_inline uint32_t
100 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
102 static __rte_always_inline void
103 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
104 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
106 static __rte_always_inline void
107 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
108 const unsigned int strd_n);
111 mlx5_queue_state_modify(struct rte_eth_dev *dev,
112 struct mlx5_mp_arg_queue_state_modify *sm);
115 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
116 volatile struct mlx5_cqe *restrict cqe,
120 mlx5_lro_update_hdr(uint8_t *restrict padd,
121 volatile struct mlx5_cqe *restrict cqe,
124 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
125 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
128 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
129 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
131 uint64_t rte_net_mlx5_dynf_inline_mask;
132 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
135 * Build a table to translate Rx completion flags to packet type.
137 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
140 mlx5_set_ptype_table(void)
143 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
145 /* Last entry must not be overwritten, reserved for errored packet. */
146 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
147 (*p)[i] = RTE_PTYPE_UNKNOWN;
149 * The index to the array should have:
150 * bit[1:0] = l3_hdr_type
151 * bit[4:2] = l4_hdr_type
154 * bit[7] = outer_l3_type
157 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
159 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_L4_NONFRAG;
161 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 RTE_PTYPE_L4_NONFRAG;
164 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
166 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
169 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
171 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
173 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
175 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
177 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
179 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
182 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
184 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
186 /* Repeat with outer_l3_type being set. Just in case. */
187 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
188 RTE_PTYPE_L4_NONFRAG;
189 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_L4_NONFRAG;
191 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
193 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
195 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
197 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
199 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
201 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
203 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
205 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
209 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
212 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
213 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_NONFRAG;
216 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_NONFRAG;
219 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
220 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_NONFRAG;
223 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_NONFRAG;
226 /* Tunneled - Fragmented */
227 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
229 RTE_PTYPE_INNER_L4_FRAG;
230 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
232 RTE_PTYPE_INNER_L4_FRAG;
233 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_FRAG;
236 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L4_FRAG;
240 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L4_TCP;
243 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L4_TCP;
246 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
247 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L4_TCP;
249 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L4_TCP;
252 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L4_TCP;
255 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L4_TCP;
258 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
259 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L4_TCP;
261 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L4_TCP;
264 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
266 RTE_PTYPE_INNER_L4_TCP;
267 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
269 RTE_PTYPE_INNER_L4_TCP;
270 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_TCP;
273 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L4_TCP;
277 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
278 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
279 RTE_PTYPE_INNER_L4_UDP;
280 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
282 RTE_PTYPE_INNER_L4_UDP;
283 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
284 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
285 RTE_PTYPE_INNER_L4_UDP;
286 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
287 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
288 RTE_PTYPE_INNER_L4_UDP;
292 * Build a table to translate packet to checksum type of Verbs.
295 mlx5_set_cksum_table(void)
301 * The index should have:
302 * bit[0] = PKT_TX_TCP_SEG
303 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
304 * bit[4] = PKT_TX_IP_CKSUM
305 * bit[8] = PKT_TX_OUTER_IP_CKSUM
308 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
311 /* Tunneled packet. */
312 if (i & (1 << 8)) /* Outer IP. */
313 v |= MLX5_ETH_WQE_L3_CSUM;
314 if (i & (1 << 4)) /* Inner IP. */
315 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
316 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
317 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
320 if (i & (1 << 4)) /* IP. */
321 v |= MLX5_ETH_WQE_L3_CSUM;
322 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
323 v |= MLX5_ETH_WQE_L4_CSUM;
325 mlx5_cksum_table[i] = v;
330 * Build a table to translate packet type of mbuf to SWP type of Verbs.
333 mlx5_set_swp_types_table(void)
339 * The index should have:
340 * bit[0:1] = PKT_TX_L4_MASK
341 * bit[4] = PKT_TX_IPV6
342 * bit[8] = PKT_TX_OUTER_IPV6
343 * bit[9] = PKT_TX_OUTER_UDP
345 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
348 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
350 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
352 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
353 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
354 v |= MLX5_ETH_WQE_L4_INNER_UDP;
355 mlx5_swp_types_table[i] = v;
360 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
361 * Flags must be preliminary initialized to zero.
364 * Pointer to burst routine local context.
366 * Pointer to store Software Parser flags
368 * Configured Tx offloads mask. It is fully defined at
369 * compile time and may be used for optimization.
372 * Software Parser offsets packed in dword.
373 * Software Parser flags are set by pointer.
375 static __rte_always_inline uint32_t
376 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
381 unsigned int idx, off;
384 if (!MLX5_TXOFF_CONFIG(SWP))
386 ol = loc->mbuf->ol_flags;
387 tunnel = ol & PKT_TX_TUNNEL_MASK;
389 * Check whether Software Parser is required.
390 * Only customized tunnels may ask for.
392 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
395 * The index should have:
396 * bit[0:1] = PKT_TX_L4_MASK
397 * bit[4] = PKT_TX_IPV6
398 * bit[8] = PKT_TX_OUTER_IPV6
399 * bit[9] = PKT_TX_OUTER_UDP
401 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
402 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
403 *swp_flags = mlx5_swp_types_table[idx];
405 * Set offsets for SW parser. Since ConnectX-5, SW parser just
406 * complements HW parser. SW parser starts to engage only if HW parser
407 * can't reach a header. For the older devices, HW parser will not kick
408 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
409 * should be set regardless of HW offload.
411 off = loc->mbuf->outer_l2_len;
412 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
413 off += sizeof(struct rte_vlan_hdr);
414 set = (off >> 1) << 8; /* Outer L3 offset. */
415 off += loc->mbuf->outer_l3_len;
416 if (tunnel == PKT_TX_TUNNEL_UDP)
417 set |= off >> 1; /* Outer L4 offset. */
418 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
419 const uint64_t csum = ol & PKT_TX_L4_MASK;
420 off += loc->mbuf->l2_len;
421 set |= (off >> 1) << 24; /* Inner L3 offset. */
422 if (csum == PKT_TX_TCP_CKSUM ||
423 csum == PKT_TX_UDP_CKSUM ||
424 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
425 off += loc->mbuf->l3_len;
426 set |= (off >> 1) << 16; /* Inner L4 offset. */
429 set = rte_cpu_to_le_32(set);
434 * Convert the Checksum offloads to Verbs.
437 * Pointer to the mbuf.
440 * Converted checksum flags.
442 static __rte_always_inline uint8_t
443 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
446 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
447 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
448 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
451 * The index should have:
452 * bit[0] = PKT_TX_TCP_SEG
453 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
454 * bit[4] = PKT_TX_IP_CKSUM
455 * bit[8] = PKT_TX_OUTER_IP_CKSUM
458 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
459 return mlx5_cksum_table[idx];
463 * Internal function to compute the number of used descriptors in an RX queue
469 * The number of used rx descriptor.
472 rx_queue_count(struct mlx5_rxq_data *rxq)
474 struct rxq_zip *zip = &rxq->zip;
475 volatile struct mlx5_cqe *cqe;
476 const unsigned int cqe_n = (1 << rxq->cqe_n);
477 const unsigned int cqe_cnt = cqe_n - 1;
481 /* if we are processing a compressed cqe */
483 used = zip->cqe_cnt - zip->ca;
489 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
490 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
494 op_own = cqe->op_own;
495 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
496 n = rte_be_to_cpu_32(cqe->byte_cnt);
501 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
503 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
508 * DPDK callback to check the status of a rx descriptor.
513 * The index of the descriptor in the ring.
516 * The status of the tx descriptor.
519 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
521 struct mlx5_rxq_data *rxq = rx_queue;
522 struct mlx5_rxq_ctrl *rxq_ctrl =
523 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
524 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
526 if (dev->rx_pkt_burst != mlx5_rx_burst) {
530 if (offset >= (1 << rxq->elts_n)) {
534 if (offset < rx_queue_count(rxq))
535 return RTE_ETH_RX_DESC_DONE;
536 return RTE_ETH_RX_DESC_AVAIL;
540 * DPDK callback to get the number of used descriptors in a RX queue
543 * Pointer to the device structure.
549 * The number of used rx descriptor.
550 * -EINVAL if the queue is invalid
553 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
555 struct mlx5_priv *priv = dev->data->dev_private;
556 struct mlx5_rxq_data *rxq;
558 if (dev->rx_pkt_burst != mlx5_rx_burst) {
562 rxq = (*priv->rxqs)[rx_queue_id];
567 return rx_queue_count(rxq);
570 #define MLX5_SYSTEM_LOG_DIR "/var/log"
572 * Dump debug information to log file.
577 * If not NULL this string is printed as a header to the output
578 * and the output will be in hexadecimal view.
580 * This is the buffer address to print out.
582 * The number of bytes to dump out.
585 mlx5_dump_debug_information(const char *fname, const char *hex_title,
586 const void *buf, unsigned int hex_len)
590 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
591 fd = fopen(path, "a+");
593 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
594 MKSTR(path2, "./%s", fname);
595 fd = fopen(path2, "a+");
597 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
600 DRV_LOG(INFO, "New debug dump in file %s", path2);
602 DRV_LOG(INFO, "New debug dump in file %s", path);
605 rte_hexdump(fd, hex_title, buf, hex_len);
607 fprintf(fd, "%s", (const char *)buf);
608 fprintf(fd, "\n\n\n");
613 * Move QP from error state to running state and initialize indexes.
616 * Pointer to TX queue control structure.
619 * 0 on success, else -1.
622 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
624 struct mlx5_mp_arg_queue_state_modify sm = {
626 .queue_id = txq_ctrl->txq.idx,
629 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
631 txq_ctrl->txq.wqe_ci = 0;
632 txq_ctrl->txq.wqe_pi = 0;
633 txq_ctrl->txq.elts_comp = 0;
637 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
639 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
641 static const uint8_t magic[] = "seen";
645 for (i = 0; i < sizeof(magic); ++i)
646 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
648 err_cqe->rsvd1[i] = magic[i];
657 * Pointer to TX queue structure.
659 * Pointer to the error CQE.
662 * Negative value if queue recovery failed, otherwise
663 * the error completion entry is handled successfully.
666 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
667 volatile struct mlx5_err_cqe *err_cqe)
669 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
670 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
671 struct mlx5_txq_ctrl *txq_ctrl =
672 container_of(txq, struct mlx5_txq_ctrl, txq);
673 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
674 int seen = check_err_cqe_seen(err_cqe);
676 if (!seen && txq_ctrl->dump_file_n <
677 txq_ctrl->priv->config.max_dump_files_num) {
678 MKSTR(err_str, "Unexpected CQE error syndrome "
679 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
680 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
681 txq->cqe_s, txq->qp_num_8s >> 8,
682 rte_be_to_cpu_16(err_cqe->wqe_counter),
683 txq->wqe_ci, txq->cq_ci);
684 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
685 PORT_ID(txq_ctrl->priv), txq->idx,
686 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
687 mlx5_dump_debug_information(name, NULL, err_str, 0);
688 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
689 (const void *)((uintptr_t)
693 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
694 (const void *)((uintptr_t)
698 txq_ctrl->dump_file_n++;
702 * Count errors in WQEs units.
703 * Later it can be improved to count error packets,
704 * for example, by SQ parsing to find how much packets
705 * should be counted for each WQE.
707 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
709 if (tx_recover_qp(txq_ctrl)) {
710 /* Recovering failed - retry later on the same WQE. */
713 /* Release all the remaining buffers. */
714 txq_free_elts(txq_ctrl);
720 * Translate RX completion flags to packet type.
723 * Pointer to RX queue structure.
727 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
730 * Packet type for struct rte_mbuf.
732 static inline uint32_t
733 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
736 uint8_t pinfo = cqe->pkt_info;
737 uint16_t ptype = cqe->hdr_type_etc;
740 * The index to the array should have:
741 * bit[1:0] = l3_hdr_type
742 * bit[4:2] = l4_hdr_type
745 * bit[7] = outer_l3_type
747 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
748 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
752 * Initialize Rx WQ and indexes.
755 * Pointer to RX queue structure.
758 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
760 const unsigned int wqe_n = 1 << rxq->elts_n;
763 for (i = 0; (i != wqe_n); ++i) {
764 volatile struct mlx5_wqe_data_seg *scat;
768 if (mlx5_rxq_mprq_enabled(rxq)) {
769 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
771 scat = &((volatile struct mlx5_wqe_mprq *)
773 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
774 1 << rxq->strd_num_n);
775 byte_count = (1 << rxq->strd_sz_n) *
776 (1 << rxq->strd_num_n);
778 struct rte_mbuf *buf = (*rxq->elts)[i];
780 scat = &((volatile struct mlx5_wqe_data_seg *)
782 addr = rte_pktmbuf_mtod(buf, uintptr_t);
783 byte_count = DATA_LEN(buf);
785 /* scat->addr must be able to store a pointer. */
786 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
787 *scat = (struct mlx5_wqe_data_seg){
788 .addr = rte_cpu_to_be_64(addr),
789 .byte_count = rte_cpu_to_be_32(byte_count),
790 .lkey = mlx5_rx_addr2mr(rxq, addr),
793 rxq->consumed_strd = 0;
794 rxq->decompressed = 0;
796 rxq->zip = (struct rxq_zip){
799 /* Update doorbell counter. */
800 rxq->rq_ci = wqe_n >> rxq->sges_n;
802 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
806 * Modify a Verbs/DevX queue state.
807 * This must be called from the primary process.
810 * Pointer to Ethernet device.
812 * State modify request parameters.
815 * 0 in case of success else non-zero value and rte_errno is set.
818 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
819 const struct mlx5_mp_arg_queue_state_modify *sm)
822 struct mlx5_priv *priv = dev->data->dev_private;
825 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
826 struct mlx5_rxq_ctrl *rxq_ctrl =
827 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
829 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
830 struct ibv_wq_attr mod = {
831 .attr_mask = IBV_WQ_ATTR_STATE,
832 .wq_state = sm->state,
835 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
836 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
837 struct mlx5_devx_modify_rq_attr rq_attr;
839 memset(&rq_attr, 0, sizeof(rq_attr));
840 if (sm->state == IBV_WQS_RESET) {
841 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
842 rq_attr.state = MLX5_RQC_STATE_RST;
843 } else if (sm->state == IBV_WQS_RDY) {
844 rq_attr.rq_state = MLX5_RQC_STATE_RST;
845 rq_attr.state = MLX5_RQC_STATE_RDY;
846 } else if (sm->state == IBV_WQS_ERR) {
847 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
848 rq_attr.state = MLX5_RQC_STATE_ERR;
850 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
854 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
855 sm->state, strerror(errno));
860 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
861 struct mlx5_txq_ctrl *txq_ctrl =
862 container_of(txq, struct mlx5_txq_ctrl, txq);
863 struct ibv_qp_attr mod = {
864 .qp_state = IBV_QPS_RESET,
865 .port_num = (uint8_t)priv->ibv_port,
867 struct ibv_qp *qp = txq_ctrl->obj->qp;
869 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
871 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
872 "%s", strerror(errno));
876 mod.qp_state = IBV_QPS_INIT;
877 ret = mlx5_glue->modify_qp(qp, &mod,
878 (IBV_QP_STATE | IBV_QP_PORT));
880 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
885 mod.qp_state = IBV_QPS_RTR;
886 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
888 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
893 mod.qp_state = IBV_QPS_RTS;
894 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
896 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
906 * Modify a Verbs queue state.
909 * Pointer to Ethernet device.
911 * State modify request parameters.
914 * 0 in case of success else non-zero value.
917 mlx5_queue_state_modify(struct rte_eth_dev *dev,
918 struct mlx5_mp_arg_queue_state_modify *sm)
922 switch (rte_eal_process_type()) {
923 case RTE_PROC_PRIMARY:
924 ret = mlx5_queue_state_modify_primary(dev, sm);
926 case RTE_PROC_SECONDARY:
927 ret = mlx5_mp_req_queue_state_modify(dev, sm);
937 * The function inserts the RQ state to reset when the first error CQE is
938 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
939 * it moves the RQ state to ready and initializes the RQ.
940 * Next CQE identification and error counting are in the caller responsibility.
943 * Pointer to RX queue structure.
945 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
946 * 0 when called from non-vectorized Rx burst.
949 * -1 in case of recovery error, otherwise the CQE status.
952 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
954 const uint16_t cqe_n = 1 << rxq->cqe_n;
955 const uint16_t cqe_mask = cqe_n - 1;
956 const unsigned int wqe_n = 1 << rxq->elts_n;
957 struct mlx5_rxq_ctrl *rxq_ctrl =
958 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
960 volatile struct mlx5_cqe *cqe;
961 volatile struct mlx5_err_cqe *err_cqe;
963 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
965 struct mlx5_mp_arg_queue_state_modify sm;
968 switch (rxq->err_state) {
969 case MLX5_RXQ_ERR_STATE_NO_ERROR:
970 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
972 case MLX5_RXQ_ERR_STATE_NEED_RESET:
974 sm.queue_id = rxq->idx;
975 sm.state = IBV_WQS_RESET;
976 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
978 if (rxq_ctrl->dump_file_n <
979 rxq_ctrl->priv->config.max_dump_files_num) {
980 MKSTR(err_str, "Unexpected CQE error syndrome "
981 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
982 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
983 rxq->cqn, rxq_ctrl->wqn,
984 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
985 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
986 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
987 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
988 mlx5_dump_debug_information(name, NULL, err_str, 0);
989 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
990 (const void *)((uintptr_t)
992 sizeof(*u.cqe) * cqe_n);
993 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
994 (const void *)((uintptr_t)
997 rxq_ctrl->dump_file_n++;
999 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1001 case MLX5_RXQ_ERR_STATE_NEED_READY:
1002 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1003 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1005 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1008 * The RQ consumer index must be zeroed while moving
1009 * from RESET state to RDY state.
1011 *rxq->rq_db = rte_cpu_to_be_32(0);
1014 sm.queue_id = rxq->idx;
1015 sm.state = IBV_WQS_RDY;
1016 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1020 const uint16_t q_mask = wqe_n - 1;
1022 struct rte_mbuf **elt;
1024 unsigned int n = wqe_n - (rxq->rq_ci -
1027 for (i = 0; i < (int)n; ++i) {
1028 elt_idx = (rxq->rq_ci + i) & q_mask;
1029 elt = &(*rxq->elts)[elt_idx];
1030 *elt = rte_mbuf_raw_alloc(rxq->mp);
1032 for (i--; i >= 0; --i) {
1033 elt_idx = (rxq->rq_ci +
1037 rte_pktmbuf_free_seg
1043 for (i = 0; i < (int)wqe_n; ++i) {
1044 elt = &(*rxq->elts)[i];
1046 (uint16_t)((*elt)->buf_len -
1047 rte_pktmbuf_headroom(*elt));
1049 /* Padding with a fake mbuf for vec Rx. */
1050 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1051 (*rxq->elts)[wqe_n + i] =
1054 mlx5_rxq_initialize(rxq);
1055 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1064 * Get size of the next packet for a given CQE. For compressed CQEs, the
1065 * consumer index is updated only once all packets of the current one have
1069 * Pointer to RX queue.
1073 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1077 * 0 in case of empty CQE, otherwise the packet size in bytes.
1080 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1081 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1083 struct rxq_zip *zip = &rxq->zip;
1084 uint16_t cqe_n = cqe_cnt + 1;
1090 /* Process compressed data in the CQE and mini arrays. */
1092 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1093 (volatile struct mlx5_mini_cqe8 (*)[8])
1094 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1097 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1098 *mcqe = &(*mc)[zip->ai & 7];
1099 if ((++zip->ai & 7) == 0) {
1100 /* Invalidate consumed CQEs */
1103 while (idx != end) {
1104 (*rxq->cqes)[idx & cqe_cnt].op_own =
1105 MLX5_CQE_INVALIDATE;
1109 * Increment consumer index to skip the number
1110 * of CQEs consumed. Hardware leaves holes in
1111 * the CQ ring for software use.
1116 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1117 /* Invalidate the rest */
1121 while (idx != end) {
1122 (*rxq->cqes)[idx & cqe_cnt].op_own =
1123 MLX5_CQE_INVALIDATE;
1126 rxq->cq_ci = zip->cq_ci;
1130 * No compressed data, get next CQE and verify if it is
1137 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1138 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1139 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1141 ret = mlx5_rx_err_handle(rxq, 0);
1142 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1150 op_own = cqe->op_own;
1151 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1152 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1153 (volatile struct mlx5_mini_cqe8 (*)[8])
1154 (uintptr_t)(&(*rxq->cqes)
1158 /* Fix endianness. */
1159 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1161 * Current mini array position is the one
1162 * returned by check_cqe64().
1164 * If completion comprises several mini arrays,
1165 * as a special case the second one is located
1166 * 7 CQEs after the initial CQE instead of 8
1167 * for subsequent ones.
1169 zip->ca = rxq->cq_ci;
1170 zip->na = zip->ca + 7;
1171 /* Compute the next non compressed CQE. */
1173 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1174 /* Get packet size to return. */
1175 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1178 /* Prefetch all to be invalidated */
1181 while (idx != end) {
1182 rte_prefetch0(&(*rxq->cqes)[(idx) &
1187 len = rte_be_to_cpu_32(cqe->byte_cnt);
1190 if (unlikely(rxq->err_state)) {
1191 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1192 ++rxq->stats.idropped;
1200 * Translate RX completion flags to offload flags.
1206 * Offload flags (ol_flags) for struct rte_mbuf.
1208 static inline uint32_t
1209 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1211 uint32_t ol_flags = 0;
1212 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1216 MLX5_CQE_RX_L3_HDR_VALID,
1217 PKT_RX_IP_CKSUM_GOOD) |
1219 MLX5_CQE_RX_L4_HDR_VALID,
1220 PKT_RX_L4_CKSUM_GOOD);
1225 * Fill in mbuf fields from RX completion flags.
1226 * Note that pkt->ol_flags should be initialized outside of this function.
1229 * Pointer to RX queue.
1234 * @param rss_hash_res
1235 * Packet RSS Hash result.
1238 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1239 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1241 /* Update packet information. */
1242 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1243 if (rss_hash_res && rxq->rss_hash) {
1244 pkt->hash.rss = rss_hash_res;
1245 pkt->ol_flags |= PKT_RX_RSS_HASH;
1247 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1248 pkt->ol_flags |= PKT_RX_FDIR;
1249 if (cqe->sop_drop_qpn !=
1250 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1251 uint32_t mark = cqe->sop_drop_qpn;
1253 pkt->ol_flags |= PKT_RX_FDIR_ID;
1254 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1257 if (rte_flow_dynf_metadata_avail() && cqe->flow_table_metadata) {
1258 pkt->ol_flags |= PKT_RX_DYNF_METADATA;
1259 *RTE_FLOW_DYNF_METADATA(pkt) = cqe->flow_table_metadata;
1262 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1263 if (rxq->vlan_strip &&
1264 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1265 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1266 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1268 if (rxq->hw_timestamp) {
1269 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1270 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1275 * DPDK callback for RX.
1278 * Generic pointer to RX queue structure.
1280 * Array to store received packets.
1282 * Maximum number of packets in array.
1285 * Number of packets successfully received (<= pkts_n).
1288 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1290 struct mlx5_rxq_data *rxq = dpdk_rxq;
1291 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1292 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1293 const unsigned int sges_n = rxq->sges_n;
1294 struct rte_mbuf *pkt = NULL;
1295 struct rte_mbuf *seg = NULL;
1296 volatile struct mlx5_cqe *cqe =
1297 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1299 unsigned int rq_ci = rxq->rq_ci << sges_n;
1300 int len = 0; /* keep its value across iterations. */
1303 unsigned int idx = rq_ci & wqe_cnt;
1304 volatile struct mlx5_wqe_data_seg *wqe =
1305 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1306 struct rte_mbuf *rep = (*rxq->elts)[idx];
1307 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1308 uint32_t rss_hash_res;
1316 rep = rte_mbuf_raw_alloc(rxq->mp);
1317 if (unlikely(rep == NULL)) {
1318 ++rxq->stats.rx_nombuf;
1321 * no buffers before we even started,
1322 * bail out silently.
1326 while (pkt != seg) {
1327 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1331 rte_mbuf_raw_free(pkt);
1337 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1338 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1340 rte_mbuf_raw_free(rep);
1344 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1345 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1346 /* If compressed, take hash result from mini-CQE. */
1347 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1349 mcqe->rx_hash_result);
1350 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1351 if (rxq->crc_present)
1352 len -= RTE_ETHER_CRC_LEN;
1354 if (cqe->lro_num_seg > 1) {
1356 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1358 pkt->ol_flags |= PKT_RX_LRO;
1359 pkt->tso_segsz = len / cqe->lro_num_seg;
1362 DATA_LEN(rep) = DATA_LEN(seg);
1363 PKT_LEN(rep) = PKT_LEN(seg);
1364 SET_DATA_OFF(rep, DATA_OFF(seg));
1365 PORT(rep) = PORT(seg);
1366 (*rxq->elts)[idx] = rep;
1368 * Fill NIC descriptor with the new buffer. The lkey and size
1369 * of the buffers are already known, only the buffer address
1372 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1373 /* If there's only one MR, no need to replace LKey in WQE. */
1374 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1375 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1376 if (len > DATA_LEN(seg)) {
1377 len -= DATA_LEN(seg);
1382 DATA_LEN(seg) = len;
1383 #ifdef MLX5_PMD_SOFT_COUNTERS
1384 /* Increment bytes counter. */
1385 rxq->stats.ibytes += PKT_LEN(pkt);
1387 /* Return packet. */
1392 /* Align consumer index to the next stride. */
1397 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1399 /* Update the consumer index. */
1400 rxq->rq_ci = rq_ci >> sges_n;
1402 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1404 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1405 #ifdef MLX5_PMD_SOFT_COUNTERS
1406 /* Increment packets counter. */
1407 rxq->stats.ipackets += i;
1413 * Update LRO packet TCP header.
1414 * The HW LRO feature doesn't update the TCP header after coalescing the
1415 * TCP segments but supplies information in CQE to fill it by SW.
1418 * Pointer to the TCP header.
1420 * Pointer to the completion entry..
1422 * The L3 pseudo-header checksum.
1425 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1426 volatile struct mlx5_cqe *restrict cqe,
1429 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1430 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1432 * The HW calculates only the TCP payload checksum, need to complete
1433 * the TCP header checksum and the L3 pseudo-header checksum.
1435 uint32_t csum = phcsum + cqe->csum;
1437 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1438 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1439 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1440 tcp->recv_ack = cqe->lro_ack_seq_num;
1441 tcp->rx_win = cqe->lro_tcp_win;
1443 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1444 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1446 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1447 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1448 csum = (~csum) & 0xffff;
1455 * Update LRO packet headers.
1456 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1457 * TCP segments but supply information in CQE to fill it by SW.
1460 * The packet address.
1462 * Pointer to the completion entry..
1464 * The packet length.
1467 mlx5_lro_update_hdr(uint8_t *restrict padd,
1468 volatile struct mlx5_cqe *restrict cqe,
1472 struct rte_ether_hdr *eth;
1473 struct rte_vlan_hdr *vlan;
1474 struct rte_ipv4_hdr *ipv4;
1475 struct rte_ipv6_hdr *ipv6;
1476 struct rte_tcp_hdr *tcp;
1481 uint16_t proto = h.eth->ether_type;
1485 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1486 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1487 proto = h.vlan->eth_proto;
1490 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1491 h.ipv4->time_to_live = cqe->lro_min_ttl;
1492 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1493 h.ipv4->hdr_checksum = 0;
1494 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1495 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1498 h.ipv6->hop_limits = cqe->lro_min_ttl;
1499 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1501 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1504 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1508 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1510 struct mlx5_mprq_buf *buf = opaque;
1512 if (rte_atomic16_read(&buf->refcnt) == 1) {
1513 rte_mempool_put(buf->mp, buf);
1514 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1515 rte_atomic16_set(&buf->refcnt, 1);
1516 rte_mempool_put(buf->mp, buf);
1521 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1523 mlx5_mprq_buf_free_cb(NULL, buf);
1527 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1528 const unsigned int strd_n)
1530 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1531 volatile struct mlx5_wqe_data_seg *wqe =
1532 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1535 MLX5_ASSERT(rep != NULL);
1536 /* Replace MPRQ buf. */
1537 (*rxq->mprq_bufs)[rq_idx] = rep;
1539 addr = mlx5_mprq_buf_addr(rep, strd_n);
1540 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1541 /* If there's only one MR, no need to replace LKey in WQE. */
1542 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1543 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1544 /* Stash a mbuf for next replacement. */
1545 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1546 rxq->mprq_repl = rep;
1548 rxq->mprq_repl = NULL;
1552 * DPDK callback for RX with Multi-Packet RQ support.
1555 * Generic pointer to RX queue structure.
1557 * Array to store received packets.
1559 * Maximum number of packets in array.
1562 * Number of packets successfully received (<= pkts_n).
1565 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1567 struct mlx5_rxq_data *rxq = dpdk_rxq;
1568 const unsigned int strd_n = 1 << rxq->strd_num_n;
1569 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1570 const unsigned int strd_shift =
1571 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1572 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1573 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1574 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1576 uint32_t rq_ci = rxq->rq_ci;
1577 uint16_t consumed_strd = rxq->consumed_strd;
1578 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1579 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1581 while (i < pkts_n) {
1582 struct rte_mbuf *pkt;
1590 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1591 uint32_t rss_hash_res = 0;
1592 uint8_t lro_num_seg;
1594 if (consumed_strd == strd_n) {
1595 /* Replace WQE only if the buffer is still in use. */
1596 if (rte_atomic16_read(&buf->refcnt) > 1) {
1597 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1598 /* Release the old buffer. */
1599 mlx5_mprq_buf_free(buf);
1600 } else if (unlikely(rxq->mprq_repl == NULL)) {
1601 struct mlx5_mprq_buf *rep;
1604 * Currently, the MPRQ mempool is out of buffer
1605 * and doing memcpy regardless of the size of Rx
1606 * packet. Retry allocation to get back to
1609 if (!rte_mempool_get(rxq->mprq_mp,
1611 rxq->mprq_repl = rep;
1613 /* Advance to the next WQE. */
1616 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1618 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1619 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1623 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1624 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1625 MLX5_ASSERT(strd_cnt);
1626 consumed_strd += strd_cnt;
1627 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1630 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1631 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1633 /* mini-CQE for MPRQ doesn't have hash result. */
1634 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1636 MLX5_ASSERT(strd_idx < strd_n);
1637 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1639 lro_num_seg = cqe->lro_num_seg;
1641 * Currently configured to receive a packet per a stride. But if
1642 * MTU is adjusted through kernel interface, device could
1643 * consume multiple strides without raising an error. In this
1644 * case, the packet should be dropped because it is bigger than
1645 * the max_rx_pkt_len.
1647 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1648 ++rxq->stats.idropped;
1651 pkt = rte_pktmbuf_alloc(rxq->mp);
1652 if (unlikely(pkt == NULL)) {
1653 ++rxq->stats.rx_nombuf;
1656 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1657 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1658 if (rxq->crc_present)
1659 len -= RTE_ETHER_CRC_LEN;
1660 offset = strd_idx * strd_sz + strd_shift;
1661 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1663 * Memcpy packets to the target mbuf if:
1664 * - The size of packet is smaller than mprq_max_memcpy_len.
1665 * - Out of buffer in the Mempool for Multi-Packet RQ.
1667 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1669 * When memcpy'ing packet due to out-of-buffer, the
1670 * packet must be smaller than the target mbuf.
1672 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1673 rte_pktmbuf_free_seg(pkt);
1674 ++rxq->stats.idropped;
1677 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1678 DATA_LEN(pkt) = len;
1680 rte_iova_t buf_iova;
1681 struct rte_mbuf_ext_shared_info *shinfo;
1682 uint16_t buf_len = strd_cnt * strd_sz;
1685 /* Increment the refcnt of the whole chunk. */
1686 rte_atomic16_add_return(&buf->refcnt, 1);
1687 MLX5_ASSERT((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1689 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1691 * MLX5 device doesn't use iova but it is necessary in a
1692 * case where the Rx packet is transmitted via a
1695 buf_iova = rte_mempool_virt2iova(buf) +
1696 RTE_PTR_DIFF(buf_addr, buf);
1697 shinfo = &buf->shinfos[strd_idx];
1698 rte_mbuf_ext_refcnt_set(shinfo, 1);
1700 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1701 * attaching the stride to mbuf and more offload flags
1702 * will be added below by calling rxq_cq_to_mbuf().
1703 * Other fields will be overwritten.
1705 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1707 /* Set mbuf head-room. */
1708 pkt->data_off = headroom_sz;
1709 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
1711 * Prevent potential overflow due to MTU change through
1714 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1715 rte_pktmbuf_free_seg(pkt);
1716 ++rxq->stats.idropped;
1719 DATA_LEN(pkt) = len;
1721 * LRO packet may consume all the stride memory, in this
1722 * case packet head-room space is not guaranteed so must
1723 * to add an empty mbuf for the head-room.
1725 if (!rxq->strd_headroom_en) {
1726 struct rte_mbuf *headroom_mbuf =
1727 rte_pktmbuf_alloc(rxq->mp);
1729 if (unlikely(headroom_mbuf == NULL)) {
1730 rte_pktmbuf_free_seg(pkt);
1731 ++rxq->stats.rx_nombuf;
1734 PORT(pkt) = rxq->port_id;
1735 NEXT(headroom_mbuf) = pkt;
1736 pkt = headroom_mbuf;
1740 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1741 if (lro_num_seg > 1) {
1742 mlx5_lro_update_hdr(addr, cqe, len);
1743 pkt->ol_flags |= PKT_RX_LRO;
1744 pkt->tso_segsz = strd_sz;
1747 PORT(pkt) = rxq->port_id;
1748 #ifdef MLX5_PMD_SOFT_COUNTERS
1749 /* Increment bytes counter. */
1750 rxq->stats.ibytes += PKT_LEN(pkt);
1752 /* Return packet. */
1756 /* Update the consumer indexes. */
1757 rxq->consumed_strd = consumed_strd;
1759 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1760 if (rq_ci != rxq->rq_ci) {
1763 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1765 #ifdef MLX5_PMD_SOFT_COUNTERS
1766 /* Increment packets counter. */
1767 rxq->stats.ipackets += i;
1773 * Dummy DPDK callback for TX.
1775 * This function is used to temporarily replace the real callback during
1776 * unsafe control operations on the queue, or in case of error.
1779 * Generic pointer to TX queue structure.
1781 * Packets to transmit.
1783 * Number of packets in array.
1786 * Number of packets successfully transmitted (<= pkts_n).
1789 removed_tx_burst(void *dpdk_txq __rte_unused,
1790 struct rte_mbuf **pkts __rte_unused,
1791 uint16_t pkts_n __rte_unused)
1798 * Dummy DPDK callback for RX.
1800 * This function is used to temporarily replace the real callback during
1801 * unsafe control operations on the queue, or in case of error.
1804 * Generic pointer to RX queue structure.
1806 * Array to store received packets.
1808 * Maximum number of packets in array.
1811 * Number of packets successfully received (<= pkts_n).
1814 removed_rx_burst(void *dpdk_txq __rte_unused,
1815 struct rte_mbuf **pkts __rte_unused,
1816 uint16_t pkts_n __rte_unused)
1823 * Vectorized Rx/Tx routines are not compiled in when required vector
1824 * instructions are not supported on a target architecture. The following null
1825 * stubs are needed for linkage when those are not included outside of this file
1826 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1830 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1831 struct rte_mbuf **pkts __rte_unused,
1832 uint16_t pkts_n __rte_unused)
1838 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1844 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1850 * Free the mbufs from the linear array of pointers.
1853 * Pointer to array of packets to be free.
1855 * Number of packets to be freed.
1857 * Configured Tx offloads mask. It is fully defined at
1858 * compile time and may be used for optimization.
1860 static __rte_always_inline void
1861 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1862 unsigned int pkts_n,
1863 unsigned int olx __rte_unused)
1865 struct rte_mempool *pool = NULL;
1866 struct rte_mbuf **p_free = NULL;
1867 struct rte_mbuf *mbuf;
1868 unsigned int n_free = 0;
1871 * The implemented algorithm eliminates
1872 * copying pointers to temporary array
1873 * for rte_mempool_put_bulk() calls.
1876 MLX5_ASSERT(pkts_n);
1880 * Decrement mbuf reference counter, detach
1881 * indirect and external buffers if needed.
1883 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1884 if (likely(mbuf != NULL)) {
1885 MLX5_ASSERT(mbuf == *pkts);
1886 if (likely(n_free != 0)) {
1887 if (unlikely(pool != mbuf->pool))
1888 /* From different pool. */
1891 /* Start new scan array. */
1898 if (unlikely(pkts_n == 0)) {
1904 * This happens if mbuf is still referenced.
1905 * We can't put it back to the pool, skip.
1909 if (unlikely(n_free != 0))
1910 /* There is some array to free.*/
1912 if (unlikely(pkts_n == 0))
1913 /* Last mbuf, nothing to free. */
1919 * This loop is implemented to avoid multiple
1920 * inlining of rte_mempool_put_bulk().
1923 MLX5_ASSERT(p_free);
1924 MLX5_ASSERT(n_free);
1926 * Free the array of pre-freed mbufs
1927 * belonging to the same memory pool.
1929 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1930 if (unlikely(mbuf != NULL)) {
1931 /* There is the request to start new scan. */
1936 if (likely(pkts_n != 0))
1939 * This is the last mbuf to be freed.
1940 * Do one more loop iteration to complete.
1941 * This is rare case of the last unique mbuf.
1946 if (likely(pkts_n == 0))
1955 * Free the mbuf from the elts ring buffer till new tail.
1958 * Pointer to Tx queue structure.
1960 * Index in elts to free up to, becomes new elts tail.
1962 * Configured Tx offloads mask. It is fully defined at
1963 * compile time and may be used for optimization.
1965 static __rte_always_inline void
1966 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1968 unsigned int olx __rte_unused)
1970 uint16_t n_elts = tail - txq->elts_tail;
1972 MLX5_ASSERT(n_elts);
1973 MLX5_ASSERT(n_elts <= txq->elts_s);
1975 * Implement a loop to support ring buffer wraparound
1976 * with single inlining of mlx5_tx_free_mbuf().
1981 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1982 part = RTE_MIN(part, n_elts);
1984 MLX5_ASSERT(part <= txq->elts_s);
1985 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1987 txq->elts_tail += part;
1993 * Store the mbuf being sent into elts ring buffer.
1994 * On Tx completion these mbufs will be freed.
1997 * Pointer to Tx queue structure.
1999 * Pointer to array of packets to be stored.
2001 * Number of packets to be stored.
2003 * Configured Tx offloads mask. It is fully defined at
2004 * compile time and may be used for optimization.
2006 static __rte_always_inline void
2007 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
2008 struct rte_mbuf **restrict pkts,
2009 unsigned int pkts_n,
2010 unsigned int olx __rte_unused)
2013 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2016 MLX5_ASSERT(pkts_n);
2017 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2019 MLX5_ASSERT(part <= txq->elts_s);
2020 /* This code is a good candidate for vectorizing with SIMD. */
2021 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2023 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2024 txq->elts_head += pkts_n;
2025 if (unlikely(part < pkts_n))
2026 /* The copy is wrapping around the elts array. */
2027 rte_memcpy((void *)elts, (void *)(pkts + part),
2028 (pkts_n - part) * sizeof(struct rte_mbuf *));
2032 * Update completion queue consuming index via doorbell
2033 * and flush the completed data buffers.
2036 * Pointer to TX queue structure.
2037 * @param valid CQE pointer
2038 * if not NULL update txq->wqe_pi and flush the buffers
2040 * Configured Tx offloads mask. It is fully defined at
2041 * compile time and may be used for optimization.
2043 static __rte_always_inline void
2044 mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
2045 volatile struct mlx5_cqe *last_cqe,
2046 unsigned int olx __rte_unused)
2048 if (likely(last_cqe != NULL)) {
2051 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2052 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2053 if (likely(tail != txq->elts_tail)) {
2054 mlx5_tx_free_elts(txq, tail, olx);
2055 MLX5_ASSERT(tail == txq->elts_tail);
2061 * Manage TX completions. This routine checks the CQ for
2062 * arrived CQEs, deduces the last accomplished WQE in SQ,
2063 * updates SQ producing index and frees all completed mbufs.
2066 * Pointer to TX queue structure.
2068 * Configured Tx offloads mask. It is fully defined at
2069 * compile time and may be used for optimization.
2071 * NOTE: not inlined intentionally, it makes tx_burst
2072 * routine smaller, simple and faster - from experiments.
2075 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2076 unsigned int olx __rte_unused)
2078 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2079 volatile struct mlx5_cqe *last_cqe = NULL;
2080 uint16_t ci = txq->cq_ci;
2083 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2084 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2086 volatile struct mlx5_cqe *cqe;
2088 cqe = &txq->cqes[ci & txq->cqe_m];
2089 ret = check_cqe(cqe, txq->cqe_s, ci);
2090 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2091 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2092 /* No new CQEs in completion queue. */
2093 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2097 * Some error occurred, try to restart.
2098 * We have no barrier after WQE related Doorbell
2099 * written, make sure all writes are completed
2100 * here, before we might perform SQ reset.
2104 ret = mlx5_tx_error_cqe_handle
2105 (txq, (volatile struct mlx5_err_cqe *)cqe);
2106 if (unlikely(ret < 0)) {
2108 * Some error occurred on queue error
2109 * handling, we do not advance the index
2110 * here, allowing to retry on next call.
2115 * We are going to fetch all entries with
2116 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2117 * The send queue is supposed to be empty.
2124 /* Normal transmit completion. */
2125 MLX5_ASSERT(ci != txq->cq_pi);
2126 MLX5_ASSERT((txq->fcqs[ci & txq->cqe_m] >> 16) ==
2131 * We have to restrict the amount of processed CQEs
2132 * in one tx_burst routine call. The CQ may be large
2133 * and many CQEs may be updated by the NIC in one
2134 * transaction. Buffers freeing is time consuming,
2135 * multiple iterations may introduce significant
2138 if (likely(--count == 0))
2141 if (likely(ci != txq->cq_ci)) {
2143 * Update completion queue consuming index
2144 * and ring doorbell to notify hardware.
2146 rte_compiler_barrier();
2148 *txq->cq_db = rte_cpu_to_be_32(ci);
2149 mlx5_tx_comp_flush(txq, last_cqe, olx);
2154 * Check if the completion request flag should be set in the last WQE.
2155 * Both pushed mbufs and WQEs are monitored and the completion request
2156 * flag is set if any of thresholds is reached.
2159 * Pointer to TX queue structure.
2161 * Pointer to burst routine local context.
2163 * Configured Tx offloads mask. It is fully defined at
2164 * compile time and may be used for optimization.
2166 static __rte_always_inline void
2167 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2168 struct mlx5_txq_local *restrict loc,
2171 uint16_t head = txq->elts_head;
2174 part = MLX5_TXOFF_CONFIG(INLINE) ?
2175 0 : loc->pkts_sent - loc->pkts_copy;
2177 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2178 (MLX5_TXOFF_CONFIG(INLINE) &&
2179 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2180 volatile struct mlx5_wqe *last = loc->wqe_last;
2182 txq->elts_comp = head;
2183 if (MLX5_TXOFF_CONFIG(INLINE))
2184 txq->wqe_comp = txq->wqe_ci;
2185 /* Request unconditional completion on last WQE. */
2186 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2187 MLX5_COMP_MODE_OFFSET);
2188 /* Save elts_head in dedicated free on completion queue. */
2189 #ifdef RTE_LIBRTE_MLX5_DEBUG
2190 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2191 (last->cseg.opcode >> 8) << 16;
2193 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2195 /* A CQE slot must always be available. */
2196 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2201 * DPDK callback to check the status of a tx descriptor.
2206 * The index of the descriptor in the ring.
2209 * The status of the tx descriptor.
2212 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2214 struct mlx5_txq_data *restrict txq = tx_queue;
2217 mlx5_tx_handle_completion(txq, 0);
2218 used = txq->elts_head - txq->elts_tail;
2220 return RTE_ETH_TX_DESC_FULL;
2221 return RTE_ETH_TX_DESC_DONE;
2225 * Build the Control Segment with specified opcode:
2226 * - MLX5_OPCODE_SEND
2227 * - MLX5_OPCODE_ENHANCED_MPSW
2231 * Pointer to TX queue structure.
2233 * Pointer to burst routine local context.
2235 * Pointer to WQE to fill with built Control Segment.
2237 * Supposed length of WQE in segments.
2239 * SQ WQE opcode to put into Control Segment.
2241 * Configured Tx offloads mask. It is fully defined at
2242 * compile time and may be used for optimization.
2244 static __rte_always_inline void
2245 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2246 struct mlx5_txq_local *restrict loc __rte_unused,
2247 struct mlx5_wqe *restrict wqe,
2249 unsigned int opcode,
2250 unsigned int olx __rte_unused)
2252 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2254 /* For legacy MPW replace the EMPW by TSO with modifier. */
2255 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2256 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2257 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2258 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2259 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2260 MLX5_COMP_MODE_OFFSET);
2261 cs->misc = RTE_BE32(0);
2265 * Build the Ethernet Segment without inlined data.
2266 * Supports Software Parser, Checksums and VLAN
2267 * insertion Tx offload features.
2270 * Pointer to TX queue structure.
2272 * Pointer to burst routine local context.
2274 * Pointer to WQE to fill with built Ethernet Segment.
2276 * Configured Tx offloads mask. It is fully defined at
2277 * compile time and may be used for optimization.
2279 static __rte_always_inline void
2280 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2281 struct mlx5_txq_local *restrict loc,
2282 struct mlx5_wqe *restrict wqe,
2285 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2289 * Calculate and set check sum flags first, dword field
2290 * in segment may be shared with Software Parser flags.
2292 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2293 es->flags = rte_cpu_to_le_32(csum);
2295 * Calculate and set Software Parser offsets and flags.
2296 * These flags a set for custom UDP and IP tunnel packets.
2298 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2299 /* Fill metadata field if needed. */
2300 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2301 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2302 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2303 /* Engage VLAN tag insertion feature if requested. */
2304 if (MLX5_TXOFF_CONFIG(VLAN) &&
2305 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2307 * We should get here only if device support
2308 * this feature correctly.
2310 MLX5_ASSERT(txq->vlan_en);
2311 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2312 loc->mbuf->vlan_tci);
2314 es->inline_hdr = RTE_BE32(0);
2319 * Build the Ethernet Segment with minimal inlined data
2320 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2321 * used to fill the gap in single WQEBB WQEs.
2322 * Supports Software Parser, Checksums and VLAN
2323 * insertion Tx offload features.
2326 * Pointer to TX queue structure.
2328 * Pointer to burst routine local context.
2330 * Pointer to WQE to fill with built Ethernet Segment.
2332 * Length of VLAN tag insertion if any.
2334 * Configured Tx offloads mask. It is fully defined at
2335 * compile time and may be used for optimization.
2337 static __rte_always_inline void
2338 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2339 struct mlx5_txq_local *restrict loc,
2340 struct mlx5_wqe *restrict wqe,
2344 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2346 uint8_t *psrc, *pdst;
2349 * Calculate and set check sum flags first, dword field
2350 * in segment may be shared with Software Parser flags.
2352 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2353 es->flags = rte_cpu_to_le_32(csum);
2355 * Calculate and set Software Parser offsets and flags.
2356 * These flags a set for custom UDP and IP tunnel packets.
2358 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2359 /* Fill metadata field if needed. */
2360 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2361 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2362 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2363 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2365 sizeof(rte_v128u32_t)),
2366 "invalid Ethernet Segment data size");
2367 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2369 sizeof(struct rte_vlan_hdr) +
2370 2 * RTE_ETHER_ADDR_LEN),
2371 "invalid Ethernet Segment data size");
2372 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2373 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2374 es->inline_data = *(unaligned_uint16_t *)psrc;
2375 psrc += sizeof(uint16_t);
2376 pdst = (uint8_t *)(es + 1);
2377 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2378 /* Implement VLAN tag insertion as part inline data. */
2379 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2380 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2381 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2382 /* Insert VLAN ethertype + VLAN tag. */
2383 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2384 ((RTE_ETHER_TYPE_VLAN << 16) |
2385 loc->mbuf->vlan_tci);
2386 pdst += sizeof(struct rte_vlan_hdr);
2387 /* Copy the rest two bytes from packet data. */
2388 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2389 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2391 /* Fill the gap in the title WQEBB with inline data. */
2392 rte_mov16(pdst, psrc);
2397 * Build the Ethernet Segment with entire packet
2398 * data inlining. Checks the boundary of WQEBB and
2399 * ring buffer wrapping, supports Software Parser,
2400 * Checksums and VLAN insertion Tx offload features.
2403 * Pointer to TX queue structure.
2405 * Pointer to burst routine local context.
2407 * Pointer to WQE to fill with built Ethernet Segment.
2409 * Length of VLAN tag insertion if any.
2411 * Length of data to inline (VLAN included, if any).
2413 * TSO flag, set mss field from the packet.
2415 * Configured Tx offloads mask. It is fully defined at
2416 * compile time and may be used for optimization.
2419 * Pointer to the next Data Segment (aligned and wrapped around).
2421 static __rte_always_inline struct mlx5_wqe_dseg *
2422 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2423 struct mlx5_txq_local *restrict loc,
2424 struct mlx5_wqe *restrict wqe,
2430 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2432 uint8_t *psrc, *pdst;
2436 * Calculate and set check sum flags first, dword field
2437 * in segment may be shared with Software Parser flags.
2439 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2442 csum |= loc->mbuf->tso_segsz;
2443 es->flags = rte_cpu_to_be_32(csum);
2445 es->flags = rte_cpu_to_le_32(csum);
2448 * Calculate and set Software Parser offsets and flags.
2449 * These flags a set for custom UDP and IP tunnel packets.
2451 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2452 /* Fill metadata field if needed. */
2453 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2454 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2455 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2456 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2458 sizeof(rte_v128u32_t)),
2459 "invalid Ethernet Segment data size");
2460 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2462 sizeof(struct rte_vlan_hdr) +
2463 2 * RTE_ETHER_ADDR_LEN),
2464 "invalid Ethernet Segment data size");
2465 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2466 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2467 es->inline_data = *(unaligned_uint16_t *)psrc;
2468 psrc += sizeof(uint16_t);
2469 pdst = (uint8_t *)(es + 1);
2470 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2471 /* Implement VLAN tag insertion as part inline data. */
2472 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2473 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2474 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2475 /* Insert VLAN ethertype + VLAN tag. */
2476 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2477 ((RTE_ETHER_TYPE_VLAN << 16) |
2478 loc->mbuf->vlan_tci);
2479 pdst += sizeof(struct rte_vlan_hdr);
2480 /* Copy the rest two bytes from packet data. */
2481 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2482 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2483 psrc += sizeof(uint16_t);
2485 /* Fill the gap in the title WQEBB with inline data. */
2486 rte_mov16(pdst, psrc);
2487 psrc += sizeof(rte_v128u32_t);
2489 pdst = (uint8_t *)(es + 2);
2490 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2491 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2492 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2494 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2495 return (struct mlx5_wqe_dseg *)pdst;
2498 * The WQEBB space availability is checked by caller.
2499 * Here we should be aware of WQE ring buffer wraparound only.
2501 part = (uint8_t *)txq->wqes_end - pdst;
2502 part = RTE_MIN(part, inlen);
2504 rte_memcpy(pdst, psrc, part);
2506 if (likely(!inlen)) {
2508 * If return value is not used by the caller
2509 * the code below will be optimized out.
2512 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2513 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2514 pdst = (uint8_t *)txq->wqes;
2515 return (struct mlx5_wqe_dseg *)pdst;
2517 pdst = (uint8_t *)txq->wqes;
2524 * Copy data from chain of mbuf to the specified linear buffer.
2525 * Checksums and VLAN insertion Tx offload features. If data
2526 * from some mbuf copied completely this mbuf is freed. Local
2527 * structure is used to keep the byte stream state.
2530 * Pointer to the destination linear buffer.
2532 * Pointer to burst routine local context.
2534 * Length of data to be copied.
2536 * Length of data to be copied ignoring no inline hint.
2538 * Configured Tx offloads mask. It is fully defined at
2539 * compile time and may be used for optimization.
2542 * Number of actual copied data bytes. This is always greater than or
2543 * equal to must parameter and might be lesser than len in no inline
2544 * hint flag is encountered.
2546 static __rte_always_inline unsigned int
2547 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2548 struct mlx5_txq_local *restrict loc,
2551 unsigned int olx __rte_unused)
2553 struct rte_mbuf *mbuf;
2554 unsigned int part, dlen, copy = 0;
2558 MLX5_ASSERT(must <= len);
2560 /* Allow zero length packets, must check first. */
2561 dlen = rte_pktmbuf_data_len(loc->mbuf);
2562 if (dlen <= loc->mbuf_off) {
2563 /* Exhausted packet, just free. */
2565 loc->mbuf = mbuf->next;
2566 rte_pktmbuf_free_seg(mbuf);
2568 MLX5_ASSERT(loc->mbuf_nseg > 1);
2569 MLX5_ASSERT(loc->mbuf);
2571 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2576 * We already copied the minimal
2577 * requested amount of data.
2582 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2584 * Copy only the minimal required
2585 * part of the data buffer.
2592 dlen -= loc->mbuf_off;
2593 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2595 part = RTE_MIN(len, dlen);
2596 rte_memcpy(pdst, psrc, part);
2598 loc->mbuf_off += part;
2601 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2603 /* Exhausted packet, just free. */
2605 loc->mbuf = mbuf->next;
2606 rte_pktmbuf_free_seg(mbuf);
2608 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2618 * Build the Ethernet Segment with inlined data from
2619 * multi-segment packet. Checks the boundary of WQEBB
2620 * and ring buffer wrapping, supports Software Parser,
2621 * Checksums and VLAN insertion Tx offload features.
2624 * Pointer to TX queue structure.
2626 * Pointer to burst routine local context.
2628 * Pointer to WQE to fill with built Ethernet Segment.
2630 * Length of VLAN tag insertion if any.
2632 * Length of data to inline (VLAN included, if any).
2634 * TSO flag, set mss field from the packet.
2636 * Configured Tx offloads mask. It is fully defined at
2637 * compile time and may be used for optimization.
2640 * Pointer to the next Data Segment (aligned and
2641 * possible NOT wrapped around - caller should do
2642 * wrapping check on its own).
2644 static __rte_always_inline struct mlx5_wqe_dseg *
2645 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2646 struct mlx5_txq_local *restrict loc,
2647 struct mlx5_wqe *restrict wqe,
2653 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2656 unsigned int part, tlen = 0;
2659 * Calculate and set check sum flags first, uint32_t field
2660 * in segment may be shared with Software Parser flags.
2662 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2665 csum |= loc->mbuf->tso_segsz;
2666 es->flags = rte_cpu_to_be_32(csum);
2668 es->flags = rte_cpu_to_le_32(csum);
2671 * Calculate and set Software Parser offsets and flags.
2672 * These flags a set for custom UDP and IP tunnel packets.
2674 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2675 /* Fill metadata field if needed. */
2676 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2677 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2678 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2679 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2681 sizeof(rte_v128u32_t)),
2682 "invalid Ethernet Segment data size");
2683 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2685 sizeof(struct rte_vlan_hdr) +
2686 2 * RTE_ETHER_ADDR_LEN),
2687 "invalid Ethernet Segment data size");
2688 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2689 pdst = (uint8_t *)&es->inline_data;
2690 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2691 /* Implement VLAN tag insertion as part inline data. */
2692 mlx5_tx_mseg_memcpy(pdst, loc,
2693 2 * RTE_ETHER_ADDR_LEN,
2694 2 * RTE_ETHER_ADDR_LEN, olx);
2695 pdst += 2 * RTE_ETHER_ADDR_LEN;
2696 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2697 ((RTE_ETHER_TYPE_VLAN << 16) |
2698 loc->mbuf->vlan_tci);
2699 pdst += sizeof(struct rte_vlan_hdr);
2700 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2702 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2704 * The WQEBB space availability is checked by caller.
2705 * Here we should be aware of WQE ring buffer wraparound only.
2707 part = (uint8_t *)txq->wqes_end - pdst;
2708 part = RTE_MIN(part, inlen - tlen);
2714 * Copying may be interrupted inside the routine
2715 * if run into no inline hint flag.
2717 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2718 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2720 if (likely(inlen <= tlen) || copy < part) {
2721 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2723 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2724 return (struct mlx5_wqe_dseg *)pdst;
2726 pdst = (uint8_t *)txq->wqes;
2727 part = inlen - tlen;
2732 * Build the Data Segment of pointer type.
2735 * Pointer to TX queue structure.
2737 * Pointer to burst routine local context.
2739 * Pointer to WQE to fill with built Data Segment.
2741 * Data buffer to point.
2743 * Data buffer length.
2745 * Configured Tx offloads mask. It is fully defined at
2746 * compile time and may be used for optimization.
2748 static __rte_always_inline void
2749 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2750 struct mlx5_txq_local *restrict loc,
2751 struct mlx5_wqe_dseg *restrict dseg,
2754 unsigned int olx __rte_unused)
2758 dseg->bcount = rte_cpu_to_be_32(len);
2759 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2760 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2764 * Build the Data Segment of pointer type or inline
2765 * if data length is less than buffer in minimal
2766 * Data Segment size.
2769 * Pointer to TX queue structure.
2771 * Pointer to burst routine local context.
2773 * Pointer to WQE to fill with built Data Segment.
2775 * Data buffer to point.
2777 * Data buffer length.
2779 * Configured Tx offloads mask. It is fully defined at
2780 * compile time and may be used for optimization.
2782 static __rte_always_inline void
2783 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2784 struct mlx5_txq_local *restrict loc,
2785 struct mlx5_wqe_dseg *restrict dseg,
2788 unsigned int olx __rte_unused)
2794 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2795 dseg->bcount = rte_cpu_to_be_32(len);
2796 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2797 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2801 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2802 /* Unrolled implementation of generic rte_memcpy. */
2803 dst = (uintptr_t)&dseg->inline_data[0];
2804 src = (uintptr_t)buf;
2806 #ifdef RTE_ARCH_STRICT_ALIGN
2807 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2808 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2809 dst += sizeof(uint32_t);
2810 src += sizeof(uint32_t);
2811 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2812 dst += sizeof(uint32_t);
2813 src += sizeof(uint32_t);
2815 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2816 dst += sizeof(uint64_t);
2817 src += sizeof(uint64_t);
2821 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2822 dst += sizeof(uint32_t);
2823 src += sizeof(uint32_t);
2826 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2827 dst += sizeof(uint16_t);
2828 src += sizeof(uint16_t);
2831 *(uint8_t *)dst = *(uint8_t *)src;
2835 * Build the Data Segment of inlined data from single
2836 * segment packet, no VLAN insertion.
2839 * Pointer to TX queue structure.
2841 * Pointer to burst routine local context.
2843 * Pointer to WQE to fill with built Data Segment.
2845 * Data buffer to point.
2847 * Data buffer length.
2849 * Configured Tx offloads mask. It is fully defined at
2850 * compile time and may be used for optimization.
2853 * Pointer to the next Data Segment after inlined data.
2854 * Ring buffer wraparound check is needed. We do not
2855 * do it here because it may not be needed for the
2856 * last packet in the eMPW session.
2858 static __rte_always_inline struct mlx5_wqe_dseg *
2859 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2860 struct mlx5_txq_local *restrict loc __rte_unused,
2861 struct mlx5_wqe_dseg *restrict dseg,
2864 unsigned int olx __rte_unused)
2869 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2870 pdst = &dseg->inline_data[0];
2872 * The WQEBB space availability is checked by caller.
2873 * Here we should be aware of WQE ring buffer wraparound only.
2875 part = (uint8_t *)txq->wqes_end - pdst;
2876 part = RTE_MIN(part, len);
2878 rte_memcpy(pdst, buf, part);
2882 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2883 /* Note: no final wraparound check here. */
2884 return (struct mlx5_wqe_dseg *)pdst;
2886 pdst = (uint8_t *)txq->wqes;
2893 * Build the Data Segment of inlined data from single
2894 * segment packet with VLAN insertion.
2897 * Pointer to TX queue structure.
2899 * Pointer to burst routine local context.
2901 * Pointer to the dseg fill with built Data Segment.
2903 * Data buffer to point.
2905 * Data buffer length.
2907 * Configured Tx offloads mask. It is fully defined at
2908 * compile time and may be used for optimization.
2911 * Pointer to the next Data Segment after inlined data.
2912 * Ring buffer wraparound check is needed.
2914 static __rte_always_inline struct mlx5_wqe_dseg *
2915 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2916 struct mlx5_txq_local *restrict loc __rte_unused,
2917 struct mlx5_wqe_dseg *restrict dseg,
2920 unsigned int olx __rte_unused)
2926 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
2927 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2928 (2 * RTE_ETHER_ADDR_LEN),
2929 "invalid Data Segment data size");
2930 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2931 MLX5_ETH_WQE_DATA_INLINE);
2932 pdst = &dseg->inline_data[0];
2933 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2934 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2935 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2936 len -= MLX5_DSEG_MIN_INLINE_SIZE;
2937 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2938 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2939 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2940 pdst = (uint8_t *)txq->wqes;
2941 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2942 loc->mbuf->vlan_tci);
2943 pdst += sizeof(struct rte_vlan_hdr);
2945 * The WQEBB space availability is checked by caller.
2946 * Here we should be aware of WQE ring buffer wraparound only.
2948 part = (uint8_t *)txq->wqes_end - pdst;
2949 part = RTE_MIN(part, len);
2951 rte_memcpy(pdst, buf, part);
2955 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2956 /* Note: no final wraparound check here. */
2957 return (struct mlx5_wqe_dseg *)pdst;
2959 pdst = (uint8_t *)txq->wqes;
2966 * Build the Ethernet Segment with optionally inlined data with
2967 * VLAN insertion and following Data Segments (if any) from
2968 * multi-segment packet. Used by ordinary send and TSO.
2971 * Pointer to TX queue structure.
2973 * Pointer to burst routine local context.
2975 * Pointer to WQE to fill with built Ethernet/Data Segments.
2977 * Length of VLAN header to insert, 0 means no VLAN insertion.
2979 * Data length to inline. For TSO this parameter specifies
2980 * exact value, for ordinary send routine can be aligned by
2981 * caller to provide better WQE space saving and data buffer
2982 * start address alignment. This length includes VLAN header
2985 * Zero means ordinary send, inlined data can be extended,
2986 * otherwise this is TSO, inlined data length is fixed.
2988 * Configured Tx offloads mask. It is fully defined at
2989 * compile time and may be used for optimization.
2992 * Actual size of built WQE in segments.
2994 static __rte_always_inline unsigned int
2995 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2996 struct mlx5_txq_local *restrict loc,
2997 struct mlx5_wqe *restrict wqe,
3001 unsigned int olx __rte_unused)
3003 struct mlx5_wqe_dseg *restrict dseg;
3006 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3007 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3010 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3011 if (!loc->mbuf_nseg)
3014 * There are still some mbuf remaining, not inlined.
3015 * The first mbuf may be partially inlined and we
3016 * must process the possible non-zero data offset.
3018 if (loc->mbuf_off) {
3023 * Exhausted packets must be dropped before.
3024 * Non-zero offset means there are some data
3025 * remained in the packet.
3027 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3028 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3029 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3031 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3033 * Build the pointer/minimal data Data Segment.
3034 * Do ring buffer wrapping check in advance.
3036 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3037 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3038 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3039 /* Store the mbuf to be freed on completion. */
3040 MLX5_ASSERT(loc->elts_free);
3041 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3044 if (--loc->mbuf_nseg == 0)
3046 loc->mbuf = loc->mbuf->next;
3050 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3051 struct rte_mbuf *mbuf;
3053 /* Zero length segment found, just skip. */
3055 loc->mbuf = loc->mbuf->next;
3056 rte_pktmbuf_free_seg(mbuf);
3057 if (--loc->mbuf_nseg == 0)
3060 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3061 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3064 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3065 rte_pktmbuf_data_len(loc->mbuf), olx);
3066 MLX5_ASSERT(loc->elts_free);
3067 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3070 if (--loc->mbuf_nseg == 0)
3072 loc->mbuf = loc->mbuf->next;
3077 /* Calculate actual segments used from the dseg pointer. */
3078 if ((uintptr_t)wqe < (uintptr_t)dseg)
3079 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3081 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3082 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3087 * Tx one packet function for multi-segment TSO. Supports all
3088 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3089 * sends one packet per WQE.
3091 * This routine is responsible for storing processed mbuf
3092 * into elts ring buffer and update elts_head.
3095 * Pointer to TX queue structure.
3097 * Pointer to burst routine local context.
3099 * Configured Tx offloads mask. It is fully defined at
3100 * compile time and may be used for optimization.
3103 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3104 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3105 * Local context variables partially updated.
3107 static __rte_always_inline enum mlx5_txcmp_code
3108 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3109 struct mlx5_txq_local *restrict loc,
3112 struct mlx5_wqe *restrict wqe;
3113 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3116 * Calculate data length to be inlined to estimate
3117 * the required space in WQE ring buffer.
3119 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3120 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3121 vlan = sizeof(struct rte_vlan_hdr);
3122 inlen = loc->mbuf->l2_len + vlan +
3123 loc->mbuf->l3_len + loc->mbuf->l4_len;
3124 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3125 return MLX5_TXCMP_CODE_ERROR;
3126 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3127 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3128 /* Packet must contain all TSO headers. */
3129 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3130 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3131 inlen > (dlen + vlan)))
3132 return MLX5_TXCMP_CODE_ERROR;
3133 MLX5_ASSERT(inlen >= txq->inlen_mode);
3135 * Check whether there are enough free WQEBBs:
3137 * - Ethernet Segment
3138 * - First Segment of inlined Ethernet data
3139 * - ... data continued ...
3140 * - Data Segments of pointer/min inline type
3142 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3143 MLX5_ESEG_MIN_INLINE_SIZE +
3145 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3146 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3147 return MLX5_TXCMP_CODE_EXIT;
3148 /* Check for maximal WQE size. */
3149 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3150 return MLX5_TXCMP_CODE_ERROR;
3151 #ifdef MLX5_PMD_SOFT_COUNTERS
3152 /* Update sent data bytes/packets counters. */
3153 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3154 loc->mbuf->tso_segsz;
3156 * One will be added for mbuf itself
3157 * at the end of the mlx5_tx_burst from
3158 * loc->pkts_sent field.
3161 txq->stats.opackets += ntcp;
3162 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3164 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3165 loc->wqe_last = wqe;
3166 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3167 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3168 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3169 txq->wqe_ci += (ds + 3) / 4;
3170 loc->wqe_free -= (ds + 3) / 4;
3171 return MLX5_TXCMP_CODE_MULTI;
3175 * Tx one packet function for multi-segment SEND. Supports all
3176 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3177 * sends one packet per WQE, without any data inlining in
3180 * This routine is responsible for storing processed mbuf
3181 * into elts ring buffer and update elts_head.
3184 * Pointer to TX queue structure.
3186 * Pointer to burst routine local context.
3188 * Configured Tx offloads mask. It is fully defined at
3189 * compile time and may be used for optimization.
3192 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3193 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3194 * Local context variables partially updated.
3196 static __rte_always_inline enum mlx5_txcmp_code
3197 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3198 struct mlx5_txq_local *restrict loc,
3201 struct mlx5_wqe_dseg *restrict dseg;
3202 struct mlx5_wqe *restrict wqe;
3203 unsigned int ds, nseg;
3205 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3207 * No inline at all, it means the CPU cycles saving
3208 * is prioritized at configuration, we should not
3209 * copy any packet data to WQE.
3211 nseg = NB_SEGS(loc->mbuf);
3213 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3214 return MLX5_TXCMP_CODE_EXIT;
3215 /* Check for maximal WQE size. */
3216 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3217 return MLX5_TXCMP_CODE_ERROR;
3219 * Some Tx offloads may cause an error if
3220 * packet is not long enough, check against
3221 * assumed minimal length.
3223 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3224 return MLX5_TXCMP_CODE_ERROR;
3225 #ifdef MLX5_PMD_SOFT_COUNTERS
3226 /* Update sent data bytes counter. */
3227 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3228 if (MLX5_TXOFF_CONFIG(VLAN) &&
3229 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3230 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3233 * SEND WQE, one WQEBB:
3234 * - Control Segment, SEND opcode
3235 * - Ethernet Segment, optional VLAN, no inline
3236 * - Data Segments, pointer only type
3238 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3239 loc->wqe_last = wqe;
3240 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3241 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3242 dseg = &wqe->dseg[0];
3244 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3245 struct rte_mbuf *mbuf;
3248 * Zero length segment found, have to
3249 * correct total size of WQE in segments.
3250 * It is supposed to be rare occasion, so
3251 * in normal case (no zero length segments)
3252 * we avoid extra writing to the Control
3256 wqe->cseg.sq_ds -= RTE_BE32(1);
3258 loc->mbuf = mbuf->next;
3259 rte_pktmbuf_free_seg(mbuf);
3265 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3266 rte_pktmbuf_data_len(loc->mbuf), olx);
3267 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3272 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3273 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3274 loc->mbuf = loc->mbuf->next;
3277 txq->wqe_ci += (ds + 3) / 4;
3278 loc->wqe_free -= (ds + 3) / 4;
3279 return MLX5_TXCMP_CODE_MULTI;
3283 * Tx one packet function for multi-segment SEND. Supports all
3284 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3285 * sends one packet per WQE, with data inlining in
3286 * Ethernet Segment and minimal Data Segments.
3288 * This routine is responsible for storing processed mbuf
3289 * into elts ring buffer and update elts_head.
3292 * Pointer to TX queue structure.
3294 * Pointer to burst routine local context.
3296 * Configured Tx offloads mask. It is fully defined at
3297 * compile time and may be used for optimization.
3300 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3301 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3302 * Local context variables partially updated.
3304 static __rte_always_inline enum mlx5_txcmp_code
3305 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3306 struct mlx5_txq_local *restrict loc,
3309 struct mlx5_wqe *restrict wqe;
3310 unsigned int ds, inlen, dlen, vlan = 0;
3312 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3313 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3315 * First calculate data length to be inlined
3316 * to estimate the required space for WQE.
3318 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3319 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3320 vlan = sizeof(struct rte_vlan_hdr);
3321 inlen = dlen + vlan;
3322 /* Check against minimal length. */
3323 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3324 return MLX5_TXCMP_CODE_ERROR;
3325 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3326 if (inlen > txq->inlen_send ||
3327 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3328 struct rte_mbuf *mbuf;
3333 * Packet length exceeds the allowed inline
3334 * data length, check whether the minimal
3335 * inlining is required.
3337 if (txq->inlen_mode) {
3338 MLX5_ASSERT(txq->inlen_mode >=
3339 MLX5_ESEG_MIN_INLINE_SIZE);
3340 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3341 inlen = txq->inlen_mode;
3343 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3344 !vlan || txq->vlan_en) {
3346 * VLAN insertion will be done inside by HW.
3347 * It is not utmost effective - VLAN flag is
3348 * checked twice, but we should proceed the
3349 * inlining length correctly and take into
3350 * account the VLAN header being inserted.
3352 return mlx5_tx_packet_multi_send
3355 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3358 * Now we know the minimal amount of data is requested
3359 * to inline. Check whether we should inline the buffers
3360 * from the chain beginning to eliminate some mbufs.
3363 nxlen = rte_pktmbuf_data_len(mbuf);
3364 if (unlikely(nxlen <= txq->inlen_send)) {
3365 /* We can inline first mbuf at least. */
3366 if (nxlen < inlen) {
3369 /* Scan mbufs till inlen filled. */
3374 nxlen = rte_pktmbuf_data_len(mbuf);
3376 } while (unlikely(nxlen < inlen));
3377 if (unlikely(nxlen > txq->inlen_send)) {
3378 /* We cannot inline entire mbuf. */
3379 smlen = inlen - smlen;
3380 start = rte_pktmbuf_mtod_offset
3381 (mbuf, uintptr_t, smlen);
3388 /* There should be not end of packet. */
3390 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3391 } while (unlikely(nxlen < txq->inlen_send));
3393 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3395 * Check whether we can do inline to align start
3396 * address of data buffer to cacheline.
3399 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3400 if (unlikely(start)) {
3402 if (start <= txq->inlen_send)
3407 * Check whether there are enough free WQEBBs:
3409 * - Ethernet Segment
3410 * - First Segment of inlined Ethernet data
3411 * - ... data continued ...
3412 * - Data Segments of pointer/min inline type
3414 * Estimate the number of Data Segments conservatively,
3415 * supposing no any mbufs is being freed during inlining.
3417 MLX5_ASSERT(inlen <= txq->inlen_send);
3418 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3419 MLX5_ESEG_MIN_INLINE_SIZE +
3421 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3422 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3423 return MLX5_TXCMP_CODE_EXIT;
3424 /* Check for maximal WQE size. */
3425 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3426 return MLX5_TXCMP_CODE_ERROR;
3427 #ifdef MLX5_PMD_SOFT_COUNTERS
3428 /* Update sent data bytes/packets counters. */
3429 txq->stats.obytes += dlen + vlan;
3431 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3432 loc->wqe_last = wqe;
3433 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3434 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3435 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3436 txq->wqe_ci += (ds + 3) / 4;
3437 loc->wqe_free -= (ds + 3) / 4;
3438 return MLX5_TXCMP_CODE_MULTI;
3442 * Tx burst function for multi-segment packets. Supports all
3443 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3444 * sends one packet per WQE. Function stops sending if it
3445 * encounters the single-segment packet.
3447 * This routine is responsible for storing processed mbuf
3448 * into elts ring buffer and update elts_head.
3451 * Pointer to TX queue structure.
3453 * Packets to transmit.
3455 * Number of packets in array.
3457 * Pointer to burst routine local context.
3459 * Configured Tx offloads mask. It is fully defined at
3460 * compile time and may be used for optimization.
3463 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3464 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3465 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3466 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3467 * Local context variables updated.
3469 static __rte_always_inline enum mlx5_txcmp_code
3470 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3471 struct rte_mbuf **restrict pkts,
3472 unsigned int pkts_n,
3473 struct mlx5_txq_local *restrict loc,
3476 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3477 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3478 pkts += loc->pkts_sent + 1;
3479 pkts_n -= loc->pkts_sent;
3481 enum mlx5_txcmp_code ret;
3483 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3485 * Estimate the number of free elts quickly but
3486 * conservatively. Some segment may be fully inlined
3487 * and freed, ignore this here - precise estimation
3490 if (loc->elts_free < NB_SEGS(loc->mbuf))
3491 return MLX5_TXCMP_CODE_EXIT;
3492 if (MLX5_TXOFF_CONFIG(TSO) &&
3493 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3494 /* Proceed with multi-segment TSO. */
3495 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3496 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3497 /* Proceed with multi-segment SEND with inlining. */
3498 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3500 /* Proceed with multi-segment SEND w/o inlining. */
3501 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3503 if (ret == MLX5_TXCMP_CODE_EXIT)
3504 return MLX5_TXCMP_CODE_EXIT;
3505 if (ret == MLX5_TXCMP_CODE_ERROR)
3506 return MLX5_TXCMP_CODE_ERROR;
3507 /* WQE is built, go to the next packet. */
3510 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3511 return MLX5_TXCMP_CODE_EXIT;
3512 loc->mbuf = *pkts++;
3514 rte_prefetch0(*pkts);
3515 if (likely(NB_SEGS(loc->mbuf) > 1))
3517 /* Here ends the series of multi-segment packets. */
3518 if (MLX5_TXOFF_CONFIG(TSO) &&
3519 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3520 return MLX5_TXCMP_CODE_TSO;
3521 return MLX5_TXCMP_CODE_SINGLE;
3527 * Tx burst function for single-segment packets with TSO.
3528 * Supports all types of Tx offloads, except multi-packets.
3529 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3530 * Function stops sending if it encounters the multi-segment
3531 * packet or packet without TSO requested.
3533 * The routine is responsible for storing processed mbuf
3534 * into elts ring buffer and update elts_head if inline
3535 * offloads is requested due to possible early freeing
3536 * of the inlined mbufs (can not store pkts array in elts
3540 * Pointer to TX queue structure.
3542 * Packets to transmit.
3544 * Number of packets in array.
3546 * Pointer to burst routine local context.
3548 * Configured Tx offloads mask. It is fully defined at
3549 * compile time and may be used for optimization.
3552 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3553 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3554 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3555 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3556 * Local context variables updated.
3558 static __rte_always_inline enum mlx5_txcmp_code
3559 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3560 struct rte_mbuf **restrict pkts,
3561 unsigned int pkts_n,
3562 struct mlx5_txq_local *restrict loc,
3565 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3566 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3567 pkts += loc->pkts_sent + 1;
3568 pkts_n -= loc->pkts_sent;
3570 struct mlx5_wqe_dseg *restrict dseg;
3571 struct mlx5_wqe *restrict wqe;
3572 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3575 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3576 dlen = rte_pktmbuf_data_len(loc->mbuf);
3577 if (MLX5_TXOFF_CONFIG(VLAN) &&
3578 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3579 vlan = sizeof(struct rte_vlan_hdr);
3582 * First calculate the WQE size to check
3583 * whether we have enough space in ring buffer.
3585 hlen = loc->mbuf->l2_len + vlan +
3586 loc->mbuf->l3_len + loc->mbuf->l4_len;
3587 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3588 return MLX5_TXCMP_CODE_ERROR;
3589 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3590 hlen += loc->mbuf->outer_l2_len +
3591 loc->mbuf->outer_l3_len;
3592 /* Segment must contain all TSO headers. */
3593 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3594 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3595 hlen > (dlen + vlan)))
3596 return MLX5_TXCMP_CODE_ERROR;
3598 * Check whether there are enough free WQEBBs:
3600 * - Ethernet Segment
3601 * - First Segment of inlined Ethernet data
3602 * - ... data continued ...
3603 * - Finishing Data Segment of pointer type
3605 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3606 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3607 if (loc->wqe_free < ((ds + 3) / 4))
3608 return MLX5_TXCMP_CODE_EXIT;
3609 #ifdef MLX5_PMD_SOFT_COUNTERS
3610 /* Update sent data bytes/packets counters. */
3611 ntcp = (dlen + vlan - hlen +
3612 loc->mbuf->tso_segsz - 1) /
3613 loc->mbuf->tso_segsz;
3615 * One will be added for mbuf itself at the end
3616 * of the mlx5_tx_burst from loc->pkts_sent field.
3619 txq->stats.opackets += ntcp;
3620 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3623 * Build the TSO WQE:
3625 * - Ethernet Segment with hlen bytes inlined
3626 * - Data Segment of pointer type
3628 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3629 loc->wqe_last = wqe;
3630 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3631 MLX5_OPCODE_TSO, olx);
3632 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3633 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3634 dlen -= hlen - vlan;
3635 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3637 * WQE is built, update the loop parameters
3638 * and go to the next packet.
3640 txq->wqe_ci += (ds + 3) / 4;
3641 loc->wqe_free -= (ds + 3) / 4;
3642 if (MLX5_TXOFF_CONFIG(INLINE))
3643 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3647 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3648 return MLX5_TXCMP_CODE_EXIT;
3649 loc->mbuf = *pkts++;
3651 rte_prefetch0(*pkts);
3652 if (MLX5_TXOFF_CONFIG(MULTI) &&
3653 unlikely(NB_SEGS(loc->mbuf) > 1))
3654 return MLX5_TXCMP_CODE_MULTI;
3655 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3656 return MLX5_TXCMP_CODE_SINGLE;
3657 /* Continue with the next TSO packet. */
3663 * Analyze the packet and select the best method to send.
3666 * Pointer to TX queue structure.
3668 * Pointer to burst routine local context.
3670 * Configured Tx offloads mask. It is fully defined at
3671 * compile time and may be used for optimization.
3673 * The predefined flag whether do complete check for
3674 * multi-segment packets and TSO.
3677 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3678 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3679 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3680 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3682 static __rte_always_inline enum mlx5_txcmp_code
3683 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3684 struct mlx5_txq_local *restrict loc,
3688 /* Check for multi-segment packet. */
3690 MLX5_TXOFF_CONFIG(MULTI) &&
3691 unlikely(NB_SEGS(loc->mbuf) > 1))
3692 return MLX5_TXCMP_CODE_MULTI;
3693 /* Check for TSO packet. */
3695 MLX5_TXOFF_CONFIG(TSO) &&
3696 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3697 return MLX5_TXCMP_CODE_TSO;
3698 /* Check if eMPW is enabled at all. */
3699 if (!MLX5_TXOFF_CONFIG(EMPW))
3700 return MLX5_TXCMP_CODE_SINGLE;
3701 /* Check if eMPW can be engaged. */
3702 if (MLX5_TXOFF_CONFIG(VLAN) &&
3703 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3704 (!MLX5_TXOFF_CONFIG(INLINE) ||
3705 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3706 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3708 * eMPW does not support VLAN insertion offload,
3709 * we have to inline the entire packet but
3710 * packet is too long for inlining.
3712 return MLX5_TXCMP_CODE_SINGLE;
3714 return MLX5_TXCMP_CODE_EMPW;
3718 * Check the next packet attributes to match with the eMPW batch ones.
3719 * In addition, for legacy MPW the packet length is checked either.
3722 * Pointer to TX queue structure.
3724 * Pointer to Ethernet Segment of eMPW batch.
3726 * Pointer to burst routine local context.
3728 * Length of previous packet in MPW descriptor.
3730 * Configured Tx offloads mask. It is fully defined at
3731 * compile time and may be used for optimization.
3734 * true - packet match with eMPW batch attributes.
3735 * false - no match, eMPW should be restarted.
3737 static __rte_always_inline bool
3738 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3739 struct mlx5_wqe_eseg *restrict es,
3740 struct mlx5_txq_local *restrict loc,
3744 uint8_t swp_flags = 0;
3746 /* Compare the checksum flags, if any. */
3747 if (MLX5_TXOFF_CONFIG(CSUM) &&
3748 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3750 /* Compare the Software Parser offsets and flags. */
3751 if (MLX5_TXOFF_CONFIG(SWP) &&
3752 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3753 es->swp_flags != swp_flags))
3755 /* Fill metadata field if needed. */
3756 if (MLX5_TXOFF_CONFIG(METADATA) &&
3757 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3758 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3760 /* Legacy MPW can send packets with the same lengt only. */
3761 if (MLX5_TXOFF_CONFIG(MPW) &&
3762 dlen != rte_pktmbuf_data_len(loc->mbuf))
3764 /* There must be no VLAN packets in eMPW loop. */
3765 if (MLX5_TXOFF_CONFIG(VLAN))
3766 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3771 * Update send loop variables and WQE for eMPW loop
3772 * without data inlining. Number of Data Segments is
3773 * equal to the number of sent packets.
3776 * Pointer to TX queue structure.
3778 * Pointer to burst routine local context.
3780 * Number of packets/Data Segments/Packets.
3782 * Accumulated statistics, bytes sent
3784 * Configured Tx offloads mask. It is fully defined at
3785 * compile time and may be used for optimization.
3788 * true - packet match with eMPW batch attributes.
3789 * false - no match, eMPW should be restarted.
3791 static __rte_always_inline void
3792 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3793 struct mlx5_txq_local *restrict loc,
3796 unsigned int olx __rte_unused)
3798 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3799 #ifdef MLX5_PMD_SOFT_COUNTERS
3800 /* Update sent data bytes counter. */
3801 txq->stats.obytes += slen;
3805 loc->elts_free -= ds;
3806 loc->pkts_sent += ds;
3808 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3809 txq->wqe_ci += (ds + 3) / 4;
3810 loc->wqe_free -= (ds + 3) / 4;
3814 * Update send loop variables and WQE for eMPW loop
3815 * with data inlining. Gets the size of pushed descriptors
3816 * and data to the WQE.
3819 * Pointer to TX queue structure.
3821 * Pointer to burst routine local context.
3823 * Total size of descriptor/data in bytes.
3825 * Accumulated statistics, data bytes sent.
3827 * Configured Tx offloads mask. It is fully defined at
3828 * compile time and may be used for optimization.
3831 * true - packet match with eMPW batch attributes.
3832 * false - no match, eMPW should be restarted.
3834 static __rte_always_inline void
3835 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3836 struct mlx5_txq_local *restrict loc,
3839 unsigned int olx __rte_unused)
3841 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3842 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
3843 #ifdef MLX5_PMD_SOFT_COUNTERS
3844 /* Update sent data bytes counter. */
3845 txq->stats.obytes += slen;
3849 len = len / MLX5_WSEG_SIZE + 2;
3850 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3851 txq->wqe_ci += (len + 3) / 4;
3852 loc->wqe_free -= (len + 3) / 4;
3856 * The set of Tx burst functions for single-segment packets
3857 * without TSO and with Multi-Packet Writing feature support.
3858 * Supports all types of Tx offloads, except multi-packets
3861 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3862 * as many packet per WQE as it can. If eMPW is not configured
3863 * or packet can not be sent with eMPW (VLAN insertion) the
3864 * ordinary SEND opcode is used and only one packet placed
3867 * Functions stop sending if it encounters the multi-segment
3868 * packet or packet with TSO requested.
3870 * The routines are responsible for storing processed mbuf
3871 * into elts ring buffer and update elts_head if inlining
3872 * offload is requested. Otherwise the copying mbufs to elts
3873 * can be postponed and completed at the end of burst routine.
3876 * Pointer to TX queue structure.
3878 * Packets to transmit.
3880 * Number of packets in array.
3882 * Pointer to burst routine local context.
3884 * Configured Tx offloads mask. It is fully defined at
3885 * compile time and may be used for optimization.
3888 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3889 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3890 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3891 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3892 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3893 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3895 * Local context variables updated.
3898 * The routine sends packets with MLX5_OPCODE_EMPW
3899 * without inlining, this is dedicated optimized branch.
3900 * No VLAN insertion is supported.
3902 static __rte_always_inline enum mlx5_txcmp_code
3903 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3904 struct rte_mbuf **restrict pkts,
3905 unsigned int pkts_n,
3906 struct mlx5_txq_local *restrict loc,
3910 * Subroutine is the part of mlx5_tx_burst_single()
3911 * and sends single-segment packet with eMPW opcode
3912 * without data inlining.
3914 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3915 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
3916 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3917 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3918 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3919 pkts += loc->pkts_sent + 1;
3920 pkts_n -= loc->pkts_sent;
3922 struct mlx5_wqe_dseg *restrict dseg;
3923 struct mlx5_wqe_eseg *restrict eseg;
3924 enum mlx5_txcmp_code ret;
3925 unsigned int part, loop;
3926 unsigned int slen = 0;
3929 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3930 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
3931 MLX5_MPW_MAX_PACKETS :
3932 MLX5_EMPW_MAX_PACKETS);
3933 if (unlikely(loc->elts_free < part)) {
3934 /* We have no enough elts to save all mbufs. */
3935 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3936 return MLX5_TXCMP_CODE_EXIT;
3937 /* But we still able to send at least minimal eMPW. */
3938 part = loc->elts_free;
3940 /* Check whether we have enough WQEs */
3941 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3942 if (unlikely(loc->wqe_free <
3943 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3944 return MLX5_TXCMP_CODE_EXIT;
3945 part = (loc->wqe_free * 4) - 2;
3947 if (likely(part > 1))
3948 rte_prefetch0(*pkts);
3949 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3951 * Build eMPW title WQEBB:
3952 * - Control Segment, eMPW opcode
3953 * - Ethernet Segment, no inline
3955 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3956 MLX5_OPCODE_ENHANCED_MPSW, olx);
3957 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3958 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3959 eseg = &loc->wqe_last->eseg;
3960 dseg = &loc->wqe_last->dseg[0];
3962 /* Store the packet length for legacy MPW. */
3963 if (MLX5_TXOFF_CONFIG(MPW))
3964 eseg->mss = rte_cpu_to_be_16
3965 (rte_pktmbuf_data_len(loc->mbuf));
3967 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3968 #ifdef MLX5_PMD_SOFT_COUNTERS
3969 /* Update sent data bytes counter. */
3974 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3976 if (unlikely(--loop == 0))
3978 loc->mbuf = *pkts++;
3979 if (likely(loop > 1))
3980 rte_prefetch0(*pkts);
3981 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3983 * Unroll the completion code to avoid
3984 * returning variable value - it results in
3985 * unoptimized sequent checking in caller.
3987 if (ret == MLX5_TXCMP_CODE_MULTI) {
3989 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3990 if (unlikely(!loc->elts_free ||
3992 return MLX5_TXCMP_CODE_EXIT;
3993 return MLX5_TXCMP_CODE_MULTI;
3995 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3996 if (ret == MLX5_TXCMP_CODE_TSO) {
3998 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3999 if (unlikely(!loc->elts_free ||
4001 return MLX5_TXCMP_CODE_EXIT;
4002 return MLX5_TXCMP_CODE_TSO;
4004 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4006 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4007 if (unlikely(!loc->elts_free ||
4009 return MLX5_TXCMP_CODE_EXIT;
4010 return MLX5_TXCMP_CODE_SINGLE;
4012 if (ret != MLX5_TXCMP_CODE_EMPW) {
4015 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4016 return MLX5_TXCMP_CODE_ERROR;
4019 * Check whether packet parameters coincide
4020 * within assumed eMPW batch:
4021 * - check sum settings
4023 * - software parser settings
4024 * - packets length (legacy MPW only)
4026 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4029 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4030 if (unlikely(!loc->elts_free ||
4032 return MLX5_TXCMP_CODE_EXIT;
4036 /* Packet attributes match, continue the same eMPW. */
4038 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4039 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4041 /* eMPW is built successfully, update loop parameters. */
4043 MLX5_ASSERT(pkts_n >= part);
4044 #ifdef MLX5_PMD_SOFT_COUNTERS
4045 /* Update sent data bytes counter. */
4046 txq->stats.obytes += slen;
4048 loc->elts_free -= part;
4049 loc->pkts_sent += part;
4050 txq->wqe_ci += (2 + part + 3) / 4;
4051 loc->wqe_free -= (2 + part + 3) / 4;
4053 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4054 return MLX5_TXCMP_CODE_EXIT;
4055 loc->mbuf = *pkts++;
4056 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4057 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4059 /* Continue sending eMPW batches. */
4065 * The routine sends packets with MLX5_OPCODE_EMPW
4066 * with inlining, optionally supports VLAN insertion.
4068 static __rte_always_inline enum mlx5_txcmp_code
4069 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
4070 struct rte_mbuf **restrict pkts,
4071 unsigned int pkts_n,
4072 struct mlx5_txq_local *restrict loc,
4076 * Subroutine is the part of mlx5_tx_burst_single()
4077 * and sends single-segment packet with eMPW opcode
4078 * with data inlining.
4080 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4081 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4082 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4083 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4084 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4085 pkts += loc->pkts_sent + 1;
4086 pkts_n -= loc->pkts_sent;
4088 struct mlx5_wqe_dseg *restrict dseg;
4089 struct mlx5_wqe_eseg *restrict eseg;
4090 enum mlx5_txcmp_code ret;
4091 unsigned int room, part, nlim;
4092 unsigned int slen = 0;
4094 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4096 * Limits the amount of packets in one WQE
4097 * to improve CQE latency generation.
4099 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4100 MLX5_MPW_INLINE_MAX_PACKETS :
4101 MLX5_EMPW_MAX_PACKETS);
4102 /* Check whether we have minimal amount WQEs */
4103 if (unlikely(loc->wqe_free <
4104 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4105 return MLX5_TXCMP_CODE_EXIT;
4106 if (likely(pkts_n > 1))
4107 rte_prefetch0(*pkts);
4108 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4110 * Build eMPW title WQEBB:
4111 * - Control Segment, eMPW opcode, zero DS
4112 * - Ethernet Segment, no inline
4114 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
4115 MLX5_OPCODE_ENHANCED_MPSW, olx);
4116 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4117 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4118 eseg = &loc->wqe_last->eseg;
4119 dseg = &loc->wqe_last->dseg[0];
4120 /* Store the packet length for legacy MPW. */
4121 if (MLX5_TXOFF_CONFIG(MPW))
4122 eseg->mss = rte_cpu_to_be_16
4123 (rte_pktmbuf_data_len(loc->mbuf));
4124 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4125 loc->wqe_free) * MLX5_WQE_SIZE -
4126 MLX5_WQE_CSEG_SIZE -
4128 /* Build WQE till we have space, packets and resources. */
4131 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4132 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4135 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4136 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4137 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4139 * Some Tx offloads may cause an error if
4140 * packet is not long enough, check against
4141 * assumed minimal length.
4143 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4145 if (unlikely(!part))
4146 return MLX5_TXCMP_CODE_ERROR;
4148 * We have some successfully built
4149 * packet Data Segments to send.
4151 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4152 return MLX5_TXCMP_CODE_ERROR;
4154 /* Inline or not inline - that's the Question. */
4155 if (dlen > txq->inlen_empw ||
4156 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4158 /* Inline entire packet, optional VLAN insertion. */
4159 tlen = sizeof(dseg->bcount) + dlen;
4160 if (MLX5_TXOFF_CONFIG(VLAN) &&
4161 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4163 * The packet length must be checked in
4164 * mlx5_tx_able_to_empw() and packet
4165 * fits into inline length guaranteed.
4168 sizeof(struct rte_vlan_hdr)) <=
4170 tlen += sizeof(struct rte_vlan_hdr);
4173 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4175 #ifdef MLX5_PMD_SOFT_COUNTERS
4176 /* Update sent data bytes counter. */
4177 slen += sizeof(struct rte_vlan_hdr);
4182 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4185 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4186 MLX5_ASSERT(room >= tlen);
4189 * Packet data are completely inlined,
4190 * free the packet immediately.
4192 rte_pktmbuf_free_seg(loc->mbuf);
4196 * Not inlinable VLAN packets are
4197 * proceeded outside of this routine.
4199 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4200 if (MLX5_TXOFF_CONFIG(VLAN))
4201 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4203 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4204 /* We have to store mbuf in elts.*/
4205 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4206 room -= MLX5_WQE_DSEG_SIZE;
4207 /* Ring buffer wraparound is checked at the loop end.*/
4210 #ifdef MLX5_PMD_SOFT_COUNTERS
4211 /* Update sent data bytes counter. */
4217 if (unlikely(!pkts_n || !loc->elts_free)) {
4219 * We have no resources/packets to
4220 * continue build descriptors.
4223 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4224 return MLX5_TXCMP_CODE_EXIT;
4226 loc->mbuf = *pkts++;
4227 if (likely(pkts_n > 1))
4228 rte_prefetch0(*pkts);
4229 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4231 * Unroll the completion code to avoid
4232 * returning variable value - it results in
4233 * unoptimized sequent checking in caller.
4235 if (ret == MLX5_TXCMP_CODE_MULTI) {
4237 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4238 if (unlikely(!loc->elts_free ||
4240 return MLX5_TXCMP_CODE_EXIT;
4241 return MLX5_TXCMP_CODE_MULTI;
4243 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4244 if (ret == MLX5_TXCMP_CODE_TSO) {
4246 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4247 if (unlikely(!loc->elts_free ||
4249 return MLX5_TXCMP_CODE_EXIT;
4250 return MLX5_TXCMP_CODE_TSO;
4252 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4254 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4255 if (unlikely(!loc->elts_free ||
4257 return MLX5_TXCMP_CODE_EXIT;
4258 return MLX5_TXCMP_CODE_SINGLE;
4260 if (ret != MLX5_TXCMP_CODE_EMPW) {
4263 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4264 return MLX5_TXCMP_CODE_ERROR;
4266 /* Check if we have minimal room left. */
4268 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4271 * Check whether packet parameters coincide
4272 * within assumed eMPW batch:
4273 * - check sum settings
4275 * - software parser settings
4276 * - packets length (legacy MPW only)
4278 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx))
4280 /* Packet attributes match, continue the same eMPW. */
4281 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4282 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4285 * We get here to close an existing eMPW
4286 * session and start the new one.
4288 MLX5_ASSERT(pkts_n);
4290 if (unlikely(!part))
4291 return MLX5_TXCMP_CODE_EXIT;
4292 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4293 if (unlikely(!loc->elts_free ||
4295 return MLX5_TXCMP_CODE_EXIT;
4296 /* Continue the loop with new eMPW session. */
4302 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4303 * Data inlining and VLAN insertion are supported.
4305 static __rte_always_inline enum mlx5_txcmp_code
4306 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4307 struct rte_mbuf **restrict pkts,
4308 unsigned int pkts_n,
4309 struct mlx5_txq_local *restrict loc,
4313 * Subroutine is the part of mlx5_tx_burst_single()
4314 * and sends single-segment packet with SEND opcode.
4316 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4317 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4318 pkts += loc->pkts_sent + 1;
4319 pkts_n -= loc->pkts_sent;
4321 struct mlx5_wqe *restrict wqe;
4322 enum mlx5_txcmp_code ret;
4324 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4325 if (MLX5_TXOFF_CONFIG(INLINE)) {
4326 unsigned int inlen, vlan = 0;
4328 inlen = rte_pktmbuf_data_len(loc->mbuf);
4329 if (MLX5_TXOFF_CONFIG(VLAN) &&
4330 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4331 vlan = sizeof(struct rte_vlan_hdr);
4333 static_assert((sizeof(struct rte_vlan_hdr) +
4334 sizeof(struct rte_ether_hdr)) ==
4335 MLX5_ESEG_MIN_INLINE_SIZE,
4336 "invalid min inline data size");
4339 * If inlining is enabled at configuration time
4340 * the limit must be not less than minimal size.
4341 * Otherwise we would do extra check for data
4342 * size to avoid crashes due to length overflow.
4344 MLX5_ASSERT(txq->inlen_send >=
4345 MLX5_ESEG_MIN_INLINE_SIZE);
4346 if (inlen <= txq->inlen_send) {
4347 unsigned int seg_n, wqe_n;
4349 rte_prefetch0(rte_pktmbuf_mtod
4350 (loc->mbuf, uint8_t *));
4351 /* Check against minimal length. */
4352 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4353 return MLX5_TXCMP_CODE_ERROR;
4354 if (loc->mbuf->ol_flags &
4355 PKT_TX_DYNF_NOINLINE) {
4357 * The hint flag not to inline packet
4358 * data is set. Check whether we can
4361 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4363 (MLX5_TXOFF_CONFIG(MPW) &&
4366 * The hardware requires the
4367 * minimal inline data header.
4369 goto single_min_inline;
4371 if (MLX5_TXOFF_CONFIG(VLAN) &&
4372 vlan && !txq->vlan_en) {
4374 * We must insert VLAN tag
4375 * by software means.
4377 goto single_part_inline;
4379 goto single_no_inline;
4382 * Completely inlined packet data WQE:
4383 * - Control Segment, SEND opcode
4384 * - Ethernet Segment, no VLAN insertion
4385 * - Data inlined, VLAN optionally inserted
4386 * - Alignment to MLX5_WSEG_SIZE
4387 * Have to estimate amount of WQEBBs
4389 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4390 MLX5_ESEG_MIN_INLINE_SIZE +
4391 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4392 /* Check if there are enough WQEBBs. */
4393 wqe_n = (seg_n + 3) / 4;
4394 if (wqe_n > loc->wqe_free)
4395 return MLX5_TXCMP_CODE_EXIT;
4396 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4397 loc->wqe_last = wqe;
4398 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4399 MLX5_OPCODE_SEND, olx);
4400 mlx5_tx_eseg_data(txq, loc, wqe,
4401 vlan, inlen, 0, olx);
4402 txq->wqe_ci += wqe_n;
4403 loc->wqe_free -= wqe_n;
4405 * Packet data are completely inlined,
4406 * free the packet immediately.
4408 rte_pktmbuf_free_seg(loc->mbuf);
4409 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4410 MLX5_TXOFF_CONFIG(MPW)) &&
4413 * If minimal inlining is requested the eMPW
4414 * feature should be disabled due to data is
4415 * inlined into Ethernet Segment, which can
4416 * not contain inlined data for eMPW due to
4417 * segment shared for all packets.
4419 struct mlx5_wqe_dseg *restrict dseg;
4424 * The inline-mode settings require
4425 * to inline the specified amount of
4426 * data bytes to the Ethernet Segment.
4427 * We should check the free space in
4428 * WQE ring buffer to inline partially.
4431 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4432 MLX5_ASSERT(inlen > txq->inlen_mode);
4433 MLX5_ASSERT(txq->inlen_mode >=
4434 MLX5_ESEG_MIN_INLINE_SIZE);
4436 * Check whether there are enough free WQEBBs:
4438 * - Ethernet Segment
4439 * - First Segment of inlined Ethernet data
4440 * - ... data continued ...
4441 * - Finishing Data Segment of pointer type
4443 ds = (MLX5_WQE_CSEG_SIZE +
4444 MLX5_WQE_ESEG_SIZE +
4445 MLX5_WQE_DSEG_SIZE +
4447 MLX5_ESEG_MIN_INLINE_SIZE +
4448 MLX5_WQE_DSEG_SIZE +
4449 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4450 if (loc->wqe_free < ((ds + 3) / 4))
4451 return MLX5_TXCMP_CODE_EXIT;
4453 * Build the ordinary SEND WQE:
4455 * - Ethernet Segment, inline inlen_mode bytes
4456 * - Data Segment of pointer type
4458 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4459 loc->wqe_last = wqe;
4460 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4461 MLX5_OPCODE_SEND, olx);
4462 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4465 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4466 txq->inlen_mode - vlan;
4467 inlen -= txq->inlen_mode;
4468 mlx5_tx_dseg_ptr(txq, loc, dseg,
4471 * WQE is built, update the loop parameters
4472 * and got to the next packet.
4474 txq->wqe_ci += (ds + 3) / 4;
4475 loc->wqe_free -= (ds + 3) / 4;
4476 /* We have to store mbuf in elts.*/
4477 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4478 txq->elts[txq->elts_head++ & txq->elts_m] =
4486 * Partially inlined packet data WQE, we have
4487 * some space in title WQEBB, we can fill it
4488 * with some packet data. It takes one WQEBB,
4489 * it is available, no extra space check:
4490 * - Control Segment, SEND opcode
4491 * - Ethernet Segment, no VLAN insertion
4492 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4493 * - Data Segment, pointer type
4495 * We also get here if VLAN insertion is not
4496 * supported by HW, the inline is enabled.
4499 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4500 loc->wqe_last = wqe;
4501 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4502 MLX5_OPCODE_SEND, olx);
4503 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4504 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4505 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4507 * The length check is performed above, by
4508 * comparing with txq->inlen_send. We should
4509 * not get overflow here.
4511 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4512 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4513 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4517 /* We have to store mbuf in elts.*/
4518 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4519 txq->elts[txq->elts_head++ & txq->elts_m] =
4523 #ifdef MLX5_PMD_SOFT_COUNTERS
4524 /* Update sent data bytes counter. */
4525 txq->stats.obytes += vlan +
4526 rte_pktmbuf_data_len(loc->mbuf);
4530 * No inline at all, it means the CPU cycles saving
4531 * is prioritized at configuration, we should not
4532 * copy any packet data to WQE.
4534 * SEND WQE, one WQEBB:
4535 * - Control Segment, SEND opcode
4536 * - Ethernet Segment, optional VLAN, no inline
4537 * - Data Segment, pointer type
4540 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4541 loc->wqe_last = wqe;
4542 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4543 MLX5_OPCODE_SEND, olx);
4544 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4546 (txq, loc, &wqe->dseg[0],
4547 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4548 rte_pktmbuf_data_len(loc->mbuf), olx);
4552 * We should not store mbuf pointer in elts
4553 * if no inlining is configured, this is done
4554 * by calling routine in a batch copy.
4556 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4558 #ifdef MLX5_PMD_SOFT_COUNTERS
4559 /* Update sent data bytes counter. */
4560 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4561 if (MLX5_TXOFF_CONFIG(VLAN) &&
4562 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4563 txq->stats.obytes +=
4564 sizeof(struct rte_vlan_hdr);
4569 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4570 return MLX5_TXCMP_CODE_EXIT;
4571 loc->mbuf = *pkts++;
4573 rte_prefetch0(*pkts);
4574 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4575 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4581 static __rte_always_inline enum mlx5_txcmp_code
4582 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4583 struct rte_mbuf **restrict pkts,
4584 unsigned int pkts_n,
4585 struct mlx5_txq_local *restrict loc,
4588 enum mlx5_txcmp_code ret;
4590 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4591 if (ret == MLX5_TXCMP_CODE_SINGLE)
4593 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4595 /* Optimize for inline/no inline eMPW send. */
4596 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4597 mlx5_tx_burst_empw_inline
4598 (txq, pkts, pkts_n, loc, olx) :
4599 mlx5_tx_burst_empw_simple
4600 (txq, pkts, pkts_n, loc, olx);
4601 if (ret != MLX5_TXCMP_CODE_SINGLE)
4603 /* The resources to send one packet should remain. */
4604 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4606 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4607 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4608 if (ret != MLX5_TXCMP_CODE_EMPW)
4610 /* The resources to send one packet should remain. */
4611 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4616 * DPDK Tx callback template. This is configured template
4617 * used to generate routines optimized for specified offload setup.
4618 * One of this generated functions is chosen at SQ configuration
4622 * Generic pointer to TX queue structure.
4624 * Packets to transmit.
4626 * Number of packets in array.
4628 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4629 * values. Should be static to take compile time static configuration
4633 * Number of packets successfully transmitted (<= pkts_n).
4635 static __rte_always_inline uint16_t
4636 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4637 struct rte_mbuf **restrict pkts,
4641 struct mlx5_txq_local loc;
4642 enum mlx5_txcmp_code ret;
4645 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4646 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4647 if (unlikely(!pkts_n))
4651 loc.wqe_last = NULL;
4654 loc.pkts_loop = loc.pkts_sent;
4656 * Check if there are some CQEs, if any:
4657 * - process an encountered errors
4658 * - process the completed WQEs
4659 * - free related mbufs
4660 * - doorbell the NIC about processed CQEs
4662 rte_prefetch0(*(pkts + loc.pkts_sent));
4663 mlx5_tx_handle_completion(txq, olx);
4665 * Calculate the number of available resources - elts and WQEs.
4666 * There are two possible different scenarios:
4667 * - no data inlining into WQEs, one WQEBB may contains upto
4668 * four packets, in this case elts become scarce resource
4669 * - data inlining into WQEs, one packet may require multiple
4670 * WQEBBs, the WQEs become the limiting factor.
4672 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4673 loc.elts_free = txq->elts_s -
4674 (uint16_t)(txq->elts_head - txq->elts_tail);
4675 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4676 loc.wqe_free = txq->wqe_s -
4677 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4678 if (unlikely(!loc.elts_free || !loc.wqe_free))
4682 * Fetch the packet from array. Usually this is
4683 * the first packet in series of multi/single
4686 loc.mbuf = *(pkts + loc.pkts_sent);
4687 /* Dedicated branch for multi-segment packets. */
4688 if (MLX5_TXOFF_CONFIG(MULTI) &&
4689 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4691 * Multi-segment packet encountered.
4692 * Hardware is able to process it only
4693 * with SEND/TSO opcodes, one packet
4694 * per WQE, do it in dedicated routine.
4697 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4698 part = loc.pkts_sent - loc.pkts_copy;
4699 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4701 * There are some single-segment mbufs not
4702 * stored in elts. The mbufs must be in the
4703 * same order as WQEs, so we must copy the
4704 * mbufs to elts here, before the coming
4705 * multi-segment packet mbufs is appended.
4707 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4709 loc.pkts_copy = loc.pkts_sent;
4711 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4712 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4713 if (!MLX5_TXOFF_CONFIG(INLINE))
4714 loc.pkts_copy = loc.pkts_sent;
4716 * These returned code checks are supposed
4717 * to be optimized out due to routine inlining.
4719 if (ret == MLX5_TXCMP_CODE_EXIT) {
4721 * The routine returns this code when
4722 * all packets are sent or there is no
4723 * enough resources to complete request.
4727 if (ret == MLX5_TXCMP_CODE_ERROR) {
4729 * The routine returns this code when
4730 * some error in the incoming packets
4733 txq->stats.oerrors++;
4736 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4738 * The single-segment packet was encountered
4739 * in the array, try to send it with the
4740 * best optimized way, possible engaging eMPW.
4742 goto enter_send_single;
4744 if (MLX5_TXOFF_CONFIG(TSO) &&
4745 ret == MLX5_TXCMP_CODE_TSO) {
4747 * The single-segment TSO packet was
4748 * encountered in the array.
4750 goto enter_send_tso;
4752 /* We must not get here. Something is going wrong. */
4754 txq->stats.oerrors++;
4757 /* Dedicated branch for single-segment TSO packets. */
4758 if (MLX5_TXOFF_CONFIG(TSO) &&
4759 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4761 * TSO might require special way for inlining
4762 * (dedicated parameters) and is sent with
4763 * MLX5_OPCODE_TSO opcode only, provide this
4764 * in dedicated branch.
4767 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
4768 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4769 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4771 * These returned code checks are supposed
4772 * to be optimized out due to routine inlining.
4774 if (ret == MLX5_TXCMP_CODE_EXIT)
4776 if (ret == MLX5_TXCMP_CODE_ERROR) {
4777 txq->stats.oerrors++;
4780 if (ret == MLX5_TXCMP_CODE_SINGLE)
4781 goto enter_send_single;
4782 if (MLX5_TXOFF_CONFIG(MULTI) &&
4783 ret == MLX5_TXCMP_CODE_MULTI) {
4785 * The multi-segment packet was
4786 * encountered in the array.
4788 goto enter_send_multi;
4790 /* We must not get here. Something is going wrong. */
4792 txq->stats.oerrors++;
4796 * The dedicated branch for the single-segment packets
4797 * without TSO. Often these ones can be sent using
4798 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4799 * The routine builds the WQEs till it encounters
4800 * the TSO or multi-segment packet (in case if these
4801 * offloads are requested at SQ configuration time).
4804 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4805 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4807 * These returned code checks are supposed
4808 * to be optimized out due to routine inlining.
4810 if (ret == MLX5_TXCMP_CODE_EXIT)
4812 if (ret == MLX5_TXCMP_CODE_ERROR) {
4813 txq->stats.oerrors++;
4816 if (MLX5_TXOFF_CONFIG(MULTI) &&
4817 ret == MLX5_TXCMP_CODE_MULTI) {
4819 * The multi-segment packet was
4820 * encountered in the array.
4822 goto enter_send_multi;
4824 if (MLX5_TXOFF_CONFIG(TSO) &&
4825 ret == MLX5_TXCMP_CODE_TSO) {
4827 * The single-segment TSO packet was
4828 * encountered in the array.
4830 goto enter_send_tso;
4832 /* We must not get here. Something is going wrong. */
4834 txq->stats.oerrors++;
4838 * Main Tx loop is completed, do the rest:
4839 * - set completion request if thresholds are reached
4840 * - doorbell the hardware
4841 * - copy the rest of mbufs to elts (if any)
4843 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
4844 loc.pkts_sent >= loc.pkts_copy);
4845 /* Take a shortcut if nothing is sent. */
4846 if (unlikely(loc.pkts_sent == loc.pkts_loop))
4848 /* Request CQE generation if limits are reached. */
4849 mlx5_tx_request_completion(txq, &loc, olx);
4851 * Ring QP doorbell immediately after WQE building completion
4852 * to improve latencies. The pure software related data treatment
4853 * can be completed after doorbell. Tx CQEs for this SQ are
4854 * processed in this thread only by the polling.
4856 * The rdma core library can map doorbell register in two ways,
4857 * depending on the environment variable "MLX5_SHUT_UP_BF":
4859 * - as regular cached memory, the variable is either missing or
4860 * set to zero. This type of mapping may cause the significant
4861 * doorbell register writing latency and requires explicit
4862 * memory write barrier to mitigate this issue and prevent
4865 * - as non-cached memory, the variable is present and set to
4866 * not "0" value. This type of mapping may cause performance
4867 * impact under heavy loading conditions but the explicit write
4868 * memory barrier is not required and it may improve core
4871 * - the legacy behaviour (prior 19.08 release) was to use some
4872 * heuristics to decide whether write memory barrier should
4873 * be performed. This behavior is supported with specifying
4874 * tx_db_nc=2, write barrier is skipped if application
4875 * provides the full recommended burst of packets, it
4876 * supposes the next packets are coming and the write barrier
4877 * will be issued on the next burst (after descriptor writing,
4880 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
4881 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
4882 /* Not all of the mbufs may be stored into elts yet. */
4883 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4884 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4886 * There are some single-segment mbufs not stored in elts.
4887 * It can be only if the last packet was single-segment.
4888 * The copying is gathered into one place due to it is
4889 * a good opportunity to optimize that with SIMD.
4890 * Unfortunately if inlining is enabled the gaps in
4891 * pointer array may happen due to early freeing of the
4894 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4895 loc.pkts_copy = loc.pkts_sent;
4897 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4898 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4899 if (pkts_n > loc.pkts_sent) {
4901 * If burst size is large there might be no enough CQE
4902 * fetched from completion queue and no enough resources
4903 * freed to send all the packets.
4908 #ifdef MLX5_PMD_SOFT_COUNTERS
4909 /* Increment sent packets counter. */
4910 txq->stats.opackets += loc.pkts_sent;
4912 return loc.pkts_sent;
4915 /* Generate routines with Enhanced Multi-Packet Write support. */
4916 MLX5_TXOFF_DECL(full_empw,
4917 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4919 MLX5_TXOFF_DECL(none_empw,
4920 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4922 MLX5_TXOFF_DECL(md_empw,
4923 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4925 MLX5_TXOFF_DECL(mt_empw,
4926 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4927 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4929 MLX5_TXOFF_DECL(mtsc_empw,
4930 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4931 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4932 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4934 MLX5_TXOFF_DECL(mti_empw,
4935 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4936 MLX5_TXOFF_CONFIG_INLINE |
4937 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4939 MLX5_TXOFF_DECL(mtv_empw,
4940 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4941 MLX5_TXOFF_CONFIG_VLAN |
4942 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4944 MLX5_TXOFF_DECL(mtiv_empw,
4945 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4946 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4947 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4949 MLX5_TXOFF_DECL(sc_empw,
4950 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4951 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4953 MLX5_TXOFF_DECL(sci_empw,
4954 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4955 MLX5_TXOFF_CONFIG_INLINE |
4956 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4958 MLX5_TXOFF_DECL(scv_empw,
4959 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4960 MLX5_TXOFF_CONFIG_VLAN |
4961 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4963 MLX5_TXOFF_DECL(sciv_empw,
4964 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4965 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4966 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4968 MLX5_TXOFF_DECL(i_empw,
4969 MLX5_TXOFF_CONFIG_INLINE |
4970 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4972 MLX5_TXOFF_DECL(v_empw,
4973 MLX5_TXOFF_CONFIG_VLAN |
4974 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4976 MLX5_TXOFF_DECL(iv_empw,
4977 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4978 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4980 /* Generate routines without Enhanced Multi-Packet Write support. */
4981 MLX5_TXOFF_DECL(full,
4982 MLX5_TXOFF_CONFIG_FULL)
4984 MLX5_TXOFF_DECL(none,
4985 MLX5_TXOFF_CONFIG_NONE)
4988 MLX5_TXOFF_CONFIG_METADATA)
4991 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4992 MLX5_TXOFF_CONFIG_METADATA)
4994 MLX5_TXOFF_DECL(mtsc,
4995 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4996 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4997 MLX5_TXOFF_CONFIG_METADATA)
4999 MLX5_TXOFF_DECL(mti,
5000 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5001 MLX5_TXOFF_CONFIG_INLINE |
5002 MLX5_TXOFF_CONFIG_METADATA)
5005 MLX5_TXOFF_DECL(mtv,
5006 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5007 MLX5_TXOFF_CONFIG_VLAN |
5008 MLX5_TXOFF_CONFIG_METADATA)
5011 MLX5_TXOFF_DECL(mtiv,
5012 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5013 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5014 MLX5_TXOFF_CONFIG_METADATA)
5017 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5018 MLX5_TXOFF_CONFIG_METADATA)
5020 MLX5_TXOFF_DECL(sci,
5021 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5022 MLX5_TXOFF_CONFIG_INLINE |
5023 MLX5_TXOFF_CONFIG_METADATA)
5026 MLX5_TXOFF_DECL(scv,
5027 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5028 MLX5_TXOFF_CONFIG_VLAN |
5029 MLX5_TXOFF_CONFIG_METADATA)
5032 MLX5_TXOFF_DECL(sciv,
5033 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5034 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5035 MLX5_TXOFF_CONFIG_METADATA)
5038 MLX5_TXOFF_CONFIG_INLINE |
5039 MLX5_TXOFF_CONFIG_METADATA)
5042 MLX5_TXOFF_CONFIG_VLAN |
5043 MLX5_TXOFF_CONFIG_METADATA)
5046 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5047 MLX5_TXOFF_CONFIG_METADATA)
5050 * Generate routines with Legacy Multi-Packet Write support.
5051 * This mode is supported by ConnectX-4LX only and imposes
5052 * offload limitations, not supported:
5053 * - ACL/Flows (metadata are becoming meaningless)
5054 * - WQE Inline headers
5055 * - SRIOV (E-Switch offloads)
5057 * - tunnel encapsulation/decapsulation
5060 MLX5_TXOFF_DECL(none_mpw,
5061 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5062 MLX5_TXOFF_CONFIG_MPW)
5064 MLX5_TXOFF_DECL(mci_mpw,
5065 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5066 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5067 MLX5_TXOFF_CONFIG_MPW)
5069 MLX5_TXOFF_DECL(mc_mpw,
5070 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5071 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5073 MLX5_TXOFF_DECL(i_mpw,
5074 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5075 MLX5_TXOFF_CONFIG_MPW)
5078 * Array of declared and compiled Tx burst function and corresponding
5079 * supported offloads set. The array is used to select the Tx burst
5080 * function for specified offloads set at Tx queue configuration time.
5083 eth_tx_burst_t func;
5086 MLX5_TXOFF_INFO(full_empw,
5087 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5088 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5089 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5090 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5092 MLX5_TXOFF_INFO(none_empw,
5093 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5095 MLX5_TXOFF_INFO(md_empw,
5096 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5098 MLX5_TXOFF_INFO(mt_empw,
5099 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5100 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5102 MLX5_TXOFF_INFO(mtsc_empw,
5103 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5104 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5105 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5107 MLX5_TXOFF_INFO(mti_empw,
5108 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5109 MLX5_TXOFF_CONFIG_INLINE |
5110 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5112 MLX5_TXOFF_INFO(mtv_empw,
5113 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5114 MLX5_TXOFF_CONFIG_VLAN |
5115 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5117 MLX5_TXOFF_INFO(mtiv_empw,
5118 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5119 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5120 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5122 MLX5_TXOFF_INFO(sc_empw,
5123 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5124 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5126 MLX5_TXOFF_INFO(sci_empw,
5127 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5128 MLX5_TXOFF_CONFIG_INLINE |
5129 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5131 MLX5_TXOFF_INFO(scv_empw,
5132 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5133 MLX5_TXOFF_CONFIG_VLAN |
5134 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5136 MLX5_TXOFF_INFO(sciv_empw,
5137 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5138 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5139 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5141 MLX5_TXOFF_INFO(i_empw,
5142 MLX5_TXOFF_CONFIG_INLINE |
5143 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5145 MLX5_TXOFF_INFO(v_empw,
5146 MLX5_TXOFF_CONFIG_VLAN |
5147 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5149 MLX5_TXOFF_INFO(iv_empw,
5150 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5151 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5153 MLX5_TXOFF_INFO(full,
5154 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5155 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5156 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5157 MLX5_TXOFF_CONFIG_METADATA)
5159 MLX5_TXOFF_INFO(none,
5160 MLX5_TXOFF_CONFIG_NONE)
5163 MLX5_TXOFF_CONFIG_METADATA)
5166 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5167 MLX5_TXOFF_CONFIG_METADATA)
5169 MLX5_TXOFF_INFO(mtsc,
5170 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5171 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5172 MLX5_TXOFF_CONFIG_METADATA)
5174 MLX5_TXOFF_INFO(mti,
5175 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5176 MLX5_TXOFF_CONFIG_INLINE |
5177 MLX5_TXOFF_CONFIG_METADATA)
5179 MLX5_TXOFF_INFO(mtv,
5180 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5181 MLX5_TXOFF_CONFIG_VLAN |
5182 MLX5_TXOFF_CONFIG_METADATA)
5184 MLX5_TXOFF_INFO(mtiv,
5185 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5186 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5187 MLX5_TXOFF_CONFIG_METADATA)
5190 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5191 MLX5_TXOFF_CONFIG_METADATA)
5193 MLX5_TXOFF_INFO(sci,
5194 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5195 MLX5_TXOFF_CONFIG_INLINE |
5196 MLX5_TXOFF_CONFIG_METADATA)
5198 MLX5_TXOFF_INFO(scv,
5199 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5200 MLX5_TXOFF_CONFIG_VLAN |
5201 MLX5_TXOFF_CONFIG_METADATA)
5203 MLX5_TXOFF_INFO(sciv,
5204 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5205 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5206 MLX5_TXOFF_CONFIG_METADATA)
5209 MLX5_TXOFF_CONFIG_INLINE |
5210 MLX5_TXOFF_CONFIG_METADATA)
5213 MLX5_TXOFF_CONFIG_VLAN |
5214 MLX5_TXOFF_CONFIG_METADATA)
5217 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5218 MLX5_TXOFF_CONFIG_METADATA)
5220 MLX5_TXOFF_INFO(none_mpw,
5221 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5222 MLX5_TXOFF_CONFIG_MPW)
5224 MLX5_TXOFF_INFO(mci_mpw,
5225 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5226 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5227 MLX5_TXOFF_CONFIG_MPW)
5229 MLX5_TXOFF_INFO(mc_mpw,
5230 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5231 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5233 MLX5_TXOFF_INFO(i_mpw,
5234 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5235 MLX5_TXOFF_CONFIG_MPW)
5239 * Configure the Tx function to use. The routine checks configured
5240 * Tx offloads for the device and selects appropriate Tx burst
5241 * routine. There are multiple Tx burst routines compiled from
5242 * the same template in the most optimal way for the dedicated
5246 * Pointer to private data structure.
5249 * Pointer to selected Tx burst function.
5252 mlx5_select_tx_function(struct rte_eth_dev *dev)
5254 struct mlx5_priv *priv = dev->data->dev_private;
5255 struct mlx5_dev_config *config = &priv->config;
5256 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5257 unsigned int diff = 0, olx = 0, i, m;
5259 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5260 MLX5_DSEG_MAX, "invalid WQE max size");
5261 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5262 "invalid WQE Control Segment size");
5263 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5264 "invalid WQE Ethernet Segment size");
5265 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5266 "invalid WQE Data Segment size");
5267 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5268 "invalid WQE size");
5270 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5271 /* We should support Multi-Segment Packets. */
5272 olx |= MLX5_TXOFF_CONFIG_MULTI;
5274 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5275 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5276 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5277 DEV_TX_OFFLOAD_IP_TNL_TSO |
5278 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5279 /* We should support TCP Send Offload. */
5280 olx |= MLX5_TXOFF_CONFIG_TSO;
5282 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5283 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5284 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5285 /* We should support Software Parser for Tunnels. */
5286 olx |= MLX5_TXOFF_CONFIG_SWP;
5288 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5289 DEV_TX_OFFLOAD_UDP_CKSUM |
5290 DEV_TX_OFFLOAD_TCP_CKSUM |
5291 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5292 /* We should support IP/TCP/UDP Checksums. */
5293 olx |= MLX5_TXOFF_CONFIG_CSUM;
5295 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5296 /* We should support VLAN insertion. */
5297 olx |= MLX5_TXOFF_CONFIG_VLAN;
5299 if (priv->txqs_n && (*priv->txqs)[0]) {
5300 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5302 if (txd->inlen_send) {
5304 * Check the data inline requirements. Data inline
5305 * is enabled on per device basis, we can check
5306 * the first Tx queue only.
5308 * If device does not support VLAN insertion in WQE
5309 * and some queues are requested to perform VLAN
5310 * insertion offload than inline must be enabled.
5312 olx |= MLX5_TXOFF_CONFIG_INLINE;
5315 if (config->mps == MLX5_MPW_ENHANCED &&
5316 config->txq_inline_min <= 0) {
5318 * The NIC supports Enhanced Multi-Packet Write
5319 * and does not require minimal inline data.
5321 olx |= MLX5_TXOFF_CONFIG_EMPW;
5323 if (rte_flow_dynf_metadata_avail()) {
5324 /* We should support Flow metadata. */
5325 olx |= MLX5_TXOFF_CONFIG_METADATA;
5327 if (config->mps == MLX5_MPW) {
5329 * The NIC supports Legacy Multi-Packet Write.
5330 * The MLX5_TXOFF_CONFIG_MPW controls the
5331 * descriptor building method in combination
5332 * with MLX5_TXOFF_CONFIG_EMPW.
5334 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5335 MLX5_TXOFF_CONFIG_SWP |
5336 MLX5_TXOFF_CONFIG_VLAN |
5337 MLX5_TXOFF_CONFIG_METADATA)))
5338 olx |= MLX5_TXOFF_CONFIG_EMPW |
5339 MLX5_TXOFF_CONFIG_MPW;
5342 * Scan the routines table to find the minimal
5343 * satisfying routine with requested offloads.
5345 m = RTE_DIM(txoff_func);
5346 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5349 tmp = txoff_func[i].olx;
5351 /* Meets requested offloads exactly.*/
5355 if ((tmp & olx) != olx) {
5356 /* Does not meet requested offloads at all. */
5359 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5360 /* Do not enable eMPW if not configured. */
5362 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5363 /* Do not enable inlining if not configured. */
5366 * Some routine meets the requirements.
5367 * Check whether it has minimal amount
5368 * of not requested offloads.
5370 tmp = __builtin_popcountl(tmp & ~olx);
5371 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5372 /* First or better match, save and continue. */
5378 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5379 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5380 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5381 /* Lighter not requested offload. */
5386 if (m >= RTE_DIM(txoff_func)) {
5387 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5388 " for requested offloads %04X",
5389 dev->data->port_id, olx);
5392 DRV_LOG(DEBUG, "port %u has selected Tx function"
5393 " supporting offloads %04X/%04X",
5394 dev->data->port_id, olx, txoff_func[m].olx);
5395 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5396 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5397 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5398 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5399 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5400 DRV_LOG(DEBUG, "\tSWP (software parser)");
5401 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5402 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5403 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5404 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5405 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5406 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5407 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5408 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5409 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5410 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5411 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5413 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5415 return txoff_func[m].func;