1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
11 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
13 #pragma GCC diagnostic ignored "-Wpedantic"
15 #include <infiniband/verbs.h>
16 #include <infiniband/mlx5dv.h>
18 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_mempool.h>
23 #include <rte_prefetch.h>
24 #include <rte_common.h>
25 #include <rte_branch_prediction.h>
26 #include <rte_ether.h>
27 #include <rte_cycles.h>
30 #include <mlx5_devx_cmds.h>
32 #include <mlx5_common.h>
34 #include "mlx5_defs.h"
37 #include "mlx5_utils.h"
38 #include "mlx5_rxtx.h"
39 #include "mlx5_autoconf.h"
41 /* TX burst subroutines return codes. */
42 enum mlx5_txcmp_code {
43 MLX5_TXCMP_CODE_EXIT = 0,
44 MLX5_TXCMP_CODE_ERROR,
45 MLX5_TXCMP_CODE_SINGLE,
46 MLX5_TXCMP_CODE_MULTI,
52 * These defines are used to configure Tx burst routine option set
53 * supported at compile time. The not specified options are optimized out
54 * out due to if conditions can be explicitly calculated at compile time.
55 * The offloads with bigger runtime check (require more CPU cycles to
56 * skip) overhead should have the bigger index - this is needed to
57 * select the better matching routine function if no exact match and
58 * some offloads are not actually requested.
60 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
61 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
62 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
63 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
64 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
65 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
66 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
67 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
68 #define MLX5_TXOFF_CONFIG_MPW (1u << 9) /* Legacy MPW supported.*/
70 /* The most common offloads groups. */
71 #define MLX5_TXOFF_CONFIG_NONE 0
72 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
73 MLX5_TXOFF_CONFIG_TSO | \
74 MLX5_TXOFF_CONFIG_SWP | \
75 MLX5_TXOFF_CONFIG_CSUM | \
76 MLX5_TXOFF_CONFIG_INLINE | \
77 MLX5_TXOFF_CONFIG_VLAN | \
78 MLX5_TXOFF_CONFIG_METADATA)
80 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
82 #define MLX5_TXOFF_DECL(func, olx) \
83 static uint16_t mlx5_tx_burst_##func(void *txq, \
84 struct rte_mbuf **pkts, \
87 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
88 pkts, pkts_n, (olx)); \
91 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
93 static __rte_always_inline uint32_t
94 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
96 static __rte_always_inline int
97 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
98 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
100 static __rte_always_inline uint32_t
101 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
103 static __rte_always_inline void
104 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
105 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
107 static __rte_always_inline void
108 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
109 const unsigned int strd_n);
112 mlx5_queue_state_modify(struct rte_eth_dev *dev,
113 struct mlx5_mp_arg_queue_state_modify *sm);
116 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
117 volatile struct mlx5_cqe *restrict cqe,
121 mlx5_lro_update_hdr(uint8_t *restrict padd,
122 volatile struct mlx5_cqe *restrict cqe,
125 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
126 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
129 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
130 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
132 uint64_t rte_net_mlx5_dynf_inline_mask;
133 #define PKT_TX_DYNF_NOINLINE rte_net_mlx5_dynf_inline_mask
136 * Build a table to translate Rx completion flags to packet type.
138 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
141 mlx5_set_ptype_table(void)
144 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
146 /* Last entry must not be overwritten, reserved for errored packet. */
147 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
148 (*p)[i] = RTE_PTYPE_UNKNOWN;
150 * The index to the array should have:
151 * bit[1:0] = l3_hdr_type
152 * bit[4:2] = l4_hdr_type
155 * bit[7] = outer_l3_type
158 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
160 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_L4_NONFRAG;
162 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
163 RTE_PTYPE_L4_NONFRAG;
165 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
167 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
172 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
174 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
178 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
180 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
185 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
187 /* Repeat with outer_l3_type being set. Just in case. */
188 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_L4_NONFRAG;
190 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
191 RTE_PTYPE_L4_NONFRAG;
192 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
202 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
204 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
206 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
208 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
210 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
213 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
214 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
216 RTE_PTYPE_INNER_L4_NONFRAG;
217 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
219 RTE_PTYPE_INNER_L4_NONFRAG;
220 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
221 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
223 RTE_PTYPE_INNER_L4_NONFRAG;
224 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
226 RTE_PTYPE_INNER_L4_NONFRAG;
227 /* Tunneled - Fragmented */
228 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
229 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L4_FRAG;
231 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
232 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
233 RTE_PTYPE_INNER_L4_FRAG;
234 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
236 RTE_PTYPE_INNER_L4_FRAG;
237 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
239 RTE_PTYPE_INNER_L4_FRAG;
241 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
242 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L4_TCP;
244 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
245 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L4_TCP;
247 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
248 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L4_TCP;
250 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
251 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L4_TCP;
253 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
254 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L4_TCP;
256 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
257 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L4_TCP;
259 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
260 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L4_TCP;
262 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
263 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L4_TCP;
265 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
266 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L4_TCP;
268 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
269 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
270 RTE_PTYPE_INNER_L4_TCP;
271 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
273 RTE_PTYPE_INNER_L4_TCP;
274 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
276 RTE_PTYPE_INNER_L4_TCP;
278 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
279 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L4_UDP;
281 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
282 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
283 RTE_PTYPE_INNER_L4_UDP;
284 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
285 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
286 RTE_PTYPE_INNER_L4_UDP;
287 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
288 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
289 RTE_PTYPE_INNER_L4_UDP;
293 * Build a table to translate packet to checksum type of Verbs.
296 mlx5_set_cksum_table(void)
302 * The index should have:
303 * bit[0] = PKT_TX_TCP_SEG
304 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
305 * bit[4] = PKT_TX_IP_CKSUM
306 * bit[8] = PKT_TX_OUTER_IP_CKSUM
309 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
312 /* Tunneled packet. */
313 if (i & (1 << 8)) /* Outer IP. */
314 v |= MLX5_ETH_WQE_L3_CSUM;
315 if (i & (1 << 4)) /* Inner IP. */
316 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
317 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
318 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
321 if (i & (1 << 4)) /* IP. */
322 v |= MLX5_ETH_WQE_L3_CSUM;
323 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
324 v |= MLX5_ETH_WQE_L4_CSUM;
326 mlx5_cksum_table[i] = v;
331 * Build a table to translate packet type of mbuf to SWP type of Verbs.
334 mlx5_set_swp_types_table(void)
340 * The index should have:
341 * bit[0:1] = PKT_TX_L4_MASK
342 * bit[4] = PKT_TX_IPV6
343 * bit[8] = PKT_TX_OUTER_IPV6
344 * bit[9] = PKT_TX_OUTER_UDP
346 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
349 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
351 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
353 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
354 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
355 v |= MLX5_ETH_WQE_L4_INNER_UDP;
356 mlx5_swp_types_table[i] = v;
361 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
362 * Flags must be preliminary initialized to zero.
365 * Pointer to burst routine local context.
367 * Pointer to store Software Parser flags
369 * Configured Tx offloads mask. It is fully defined at
370 * compile time and may be used for optimization.
373 * Software Parser offsets packed in dword.
374 * Software Parser flags are set by pointer.
376 static __rte_always_inline uint32_t
377 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
382 unsigned int idx, off;
385 if (!MLX5_TXOFF_CONFIG(SWP))
387 ol = loc->mbuf->ol_flags;
388 tunnel = ol & PKT_TX_TUNNEL_MASK;
390 * Check whether Software Parser is required.
391 * Only customized tunnels may ask for.
393 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
396 * The index should have:
397 * bit[0:1] = PKT_TX_L4_MASK
398 * bit[4] = PKT_TX_IPV6
399 * bit[8] = PKT_TX_OUTER_IPV6
400 * bit[9] = PKT_TX_OUTER_UDP
402 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
403 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
404 *swp_flags = mlx5_swp_types_table[idx];
406 * Set offsets for SW parser. Since ConnectX-5, SW parser just
407 * complements HW parser. SW parser starts to engage only if HW parser
408 * can't reach a header. For the older devices, HW parser will not kick
409 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
410 * should be set regardless of HW offload.
412 off = loc->mbuf->outer_l2_len;
413 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
414 off += sizeof(struct rte_vlan_hdr);
415 set = (off >> 1) << 8; /* Outer L3 offset. */
416 off += loc->mbuf->outer_l3_len;
417 if (tunnel == PKT_TX_TUNNEL_UDP)
418 set |= off >> 1; /* Outer L4 offset. */
419 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
420 const uint64_t csum = ol & PKT_TX_L4_MASK;
421 off += loc->mbuf->l2_len;
422 set |= (off >> 1) << 24; /* Inner L3 offset. */
423 if (csum == PKT_TX_TCP_CKSUM ||
424 csum == PKT_TX_UDP_CKSUM ||
425 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
426 off += loc->mbuf->l3_len;
427 set |= (off >> 1) << 16; /* Inner L4 offset. */
430 set = rte_cpu_to_le_32(set);
435 * Convert the Checksum offloads to Verbs.
438 * Pointer to the mbuf.
441 * Converted checksum flags.
443 static __rte_always_inline uint8_t
444 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
447 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
448 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
449 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
452 * The index should have:
453 * bit[0] = PKT_TX_TCP_SEG
454 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
455 * bit[4] = PKT_TX_IP_CKSUM
456 * bit[8] = PKT_TX_OUTER_IP_CKSUM
459 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
460 return mlx5_cksum_table[idx];
464 * Internal function to compute the number of used descriptors in an RX queue
470 * The number of used rx descriptor.
473 rx_queue_count(struct mlx5_rxq_data *rxq)
475 struct rxq_zip *zip = &rxq->zip;
476 volatile struct mlx5_cqe *cqe;
477 const unsigned int cqe_n = (1 << rxq->cqe_n);
478 const unsigned int cqe_cnt = cqe_n - 1;
482 /* if we are processing a compressed cqe */
484 used = zip->cqe_cnt - zip->ca;
490 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
491 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
495 op_own = cqe->op_own;
496 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
497 n = rte_be_to_cpu_32(cqe->byte_cnt);
502 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
504 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
509 * DPDK callback to check the status of a rx descriptor.
514 * The index of the descriptor in the ring.
517 * The status of the tx descriptor.
520 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
522 struct mlx5_rxq_data *rxq = rx_queue;
523 struct mlx5_rxq_ctrl *rxq_ctrl =
524 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
525 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
527 if (dev->rx_pkt_burst != mlx5_rx_burst) {
531 if (offset >= (1 << rxq->elts_n)) {
535 if (offset < rx_queue_count(rxq))
536 return RTE_ETH_RX_DESC_DONE;
537 return RTE_ETH_RX_DESC_AVAIL;
541 * DPDK callback to get the RX queue information
544 * Pointer to the device structure.
547 * Rx queue identificator.
550 * Pointer to the RX queue information structure.
557 mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
558 struct rte_eth_rxq_info *qinfo)
560 struct mlx5_priv *priv = dev->data->dev_private;
561 struct mlx5_rxq_data *rxq = (*priv->rxqs)[rx_queue_id];
562 struct mlx5_rxq_ctrl *rxq_ctrl =
563 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
567 qinfo->mp = mlx5_rxq_mprq_enabled(&rxq_ctrl->rxq) ?
568 rxq->mprq_mp : rxq->mp;
569 qinfo->conf.rx_thresh.pthresh = 0;
570 qinfo->conf.rx_thresh.hthresh = 0;
571 qinfo->conf.rx_thresh.wthresh = 0;
572 qinfo->conf.rx_free_thresh = rxq->rq_repl_thresh;
573 qinfo->conf.rx_drop_en = 1;
574 qinfo->conf.rx_deferred_start = rxq_ctrl ? 0 : 1;
575 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads;
576 qinfo->scattered_rx = dev->data->scattered_rx;
577 qinfo->nb_desc = 1 << rxq->elts_n;
581 * DPDK callback to get the RX packet burst mode information
584 * Pointer to the device structure.
587 * Rx queue identificatior.
590 * Pointer to the burts mode information.
593 * 0 as success, -EINVAL as failure.
597 mlx5_rx_burst_mode_get(struct rte_eth_dev *dev,
598 uint16_t rx_queue_id __rte_unused,
599 struct rte_eth_burst_mode *mode)
601 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst;
603 if (pkt_burst == mlx5_rx_burst) {
604 snprintf(mode->info, sizeof(mode->info), "%s", "Scalar");
605 } else if (pkt_burst == mlx5_rx_burst_mprq) {
606 snprintf(mode->info, sizeof(mode->info), "%s", "Multi-Packet RQ");
607 } else if (pkt_burst == mlx5_rx_burst_vec) {
608 #if defined RTE_ARCH_X86_64
609 snprintf(mode->info, sizeof(mode->info), "%s", "Vector SSE");
610 #elif defined RTE_ARCH_ARM64
611 snprintf(mode->info, sizeof(mode->info), "%s", "Vector Neon");
612 #elif defined RTE_ARCH_PPC_64
613 snprintf(mode->info, sizeof(mode->info), "%s", "Vector AltiVec");
624 * DPDK callback to get the number of used descriptors in a RX queue
627 * Pointer to the device structure.
633 * The number of used rx descriptor.
634 * -EINVAL if the queue is invalid
637 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
639 struct mlx5_priv *priv = dev->data->dev_private;
640 struct mlx5_rxq_data *rxq;
642 if (dev->rx_pkt_burst != mlx5_rx_burst) {
646 rxq = (*priv->rxqs)[rx_queue_id];
651 return rx_queue_count(rxq);
654 #define MLX5_SYSTEM_LOG_DIR "/var/log"
656 * Dump debug information to log file.
661 * If not NULL this string is printed as a header to the output
662 * and the output will be in hexadecimal view.
664 * This is the buffer address to print out.
666 * The number of bytes to dump out.
669 mlx5_dump_debug_information(const char *fname, const char *hex_title,
670 const void *buf, unsigned int hex_len)
674 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
675 fd = fopen(path, "a+");
677 DRV_LOG(WARNING, "cannot open %s for debug dump", path);
678 MKSTR(path2, "./%s", fname);
679 fd = fopen(path2, "a+");
681 DRV_LOG(ERR, "cannot open %s for debug dump", path2);
684 DRV_LOG(INFO, "New debug dump in file %s", path2);
686 DRV_LOG(INFO, "New debug dump in file %s", path);
689 rte_hexdump(fd, hex_title, buf, hex_len);
691 fprintf(fd, "%s", (const char *)buf);
692 fprintf(fd, "\n\n\n");
697 * Move QP from error state to running state and initialize indexes.
700 * Pointer to TX queue control structure.
703 * 0 on success, else -1.
706 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
708 struct mlx5_mp_arg_queue_state_modify sm = {
710 .queue_id = txq_ctrl->txq.idx,
713 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
715 txq_ctrl->txq.wqe_ci = 0;
716 txq_ctrl->txq.wqe_pi = 0;
717 txq_ctrl->txq.elts_comp = 0;
721 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
723 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
725 static const uint8_t magic[] = "seen";
729 for (i = 0; i < sizeof(magic); ++i)
730 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
732 err_cqe->rsvd1[i] = magic[i];
741 * Pointer to TX queue structure.
743 * Pointer to the error CQE.
746 * Negative value if queue recovery failed, otherwise
747 * the error completion entry is handled successfully.
750 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
751 volatile struct mlx5_err_cqe *err_cqe)
753 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
754 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
755 struct mlx5_txq_ctrl *txq_ctrl =
756 container_of(txq, struct mlx5_txq_ctrl, txq);
757 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
758 int seen = check_err_cqe_seen(err_cqe);
760 if (!seen && txq_ctrl->dump_file_n <
761 txq_ctrl->priv->config.max_dump_files_num) {
762 MKSTR(err_str, "Unexpected CQE error syndrome "
763 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
764 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
765 txq->cqe_s, txq->qp_num_8s >> 8,
766 rte_be_to_cpu_16(err_cqe->wqe_counter),
767 txq->wqe_ci, txq->cq_ci);
768 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
769 PORT_ID(txq_ctrl->priv), txq->idx,
770 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
771 mlx5_dump_debug_information(name, NULL, err_str, 0);
772 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
773 (const void *)((uintptr_t)
777 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
778 (const void *)((uintptr_t)
782 txq_ctrl->dump_file_n++;
786 * Count errors in WQEs units.
787 * Later it can be improved to count error packets,
788 * for example, by SQ parsing to find how much packets
789 * should be counted for each WQE.
791 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
793 if (tx_recover_qp(txq_ctrl)) {
794 /* Recovering failed - retry later on the same WQE. */
797 /* Release all the remaining buffers. */
798 txq_free_elts(txq_ctrl);
804 * Translate RX completion flags to packet type.
807 * Pointer to RX queue structure.
811 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
814 * Packet type for struct rte_mbuf.
816 static inline uint32_t
817 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
820 uint8_t pinfo = cqe->pkt_info;
821 uint16_t ptype = cqe->hdr_type_etc;
824 * The index to the array should have:
825 * bit[1:0] = l3_hdr_type
826 * bit[4:2] = l4_hdr_type
829 * bit[7] = outer_l3_type
831 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
832 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
836 * Initialize Rx WQ and indexes.
839 * Pointer to RX queue structure.
842 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
844 const unsigned int wqe_n = 1 << rxq->elts_n;
847 for (i = 0; (i != wqe_n); ++i) {
848 volatile struct mlx5_wqe_data_seg *scat;
852 if (mlx5_rxq_mprq_enabled(rxq)) {
853 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
855 scat = &((volatile struct mlx5_wqe_mprq *)
857 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
858 1 << rxq->strd_num_n);
859 byte_count = (1 << rxq->strd_sz_n) *
860 (1 << rxq->strd_num_n);
862 struct rte_mbuf *buf = (*rxq->elts)[i];
864 scat = &((volatile struct mlx5_wqe_data_seg *)
866 addr = rte_pktmbuf_mtod(buf, uintptr_t);
867 byte_count = DATA_LEN(buf);
869 /* scat->addr must be able to store a pointer. */
870 MLX5_ASSERT(sizeof(scat->addr) >= sizeof(uintptr_t));
871 *scat = (struct mlx5_wqe_data_seg){
872 .addr = rte_cpu_to_be_64(addr),
873 .byte_count = rte_cpu_to_be_32(byte_count),
874 .lkey = mlx5_rx_addr2mr(rxq, addr),
877 rxq->consumed_strd = 0;
878 rxq->decompressed = 0;
880 rxq->zip = (struct rxq_zip){
883 /* Update doorbell counter. */
884 rxq->rq_ci = wqe_n >> rxq->sges_n;
886 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
890 * Modify a Verbs/DevX queue state.
891 * This must be called from the primary process.
894 * Pointer to Ethernet device.
896 * State modify request parameters.
899 * 0 in case of success else non-zero value and rte_errno is set.
902 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
903 const struct mlx5_mp_arg_queue_state_modify *sm)
906 struct mlx5_priv *priv = dev->data->dev_private;
909 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
910 struct mlx5_rxq_ctrl *rxq_ctrl =
911 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
913 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
914 struct ibv_wq_attr mod = {
915 .attr_mask = IBV_WQ_ATTR_STATE,
916 .wq_state = sm->state,
919 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
920 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
921 struct mlx5_devx_modify_rq_attr rq_attr;
923 memset(&rq_attr, 0, sizeof(rq_attr));
924 if (sm->state == IBV_WQS_RESET) {
925 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
926 rq_attr.state = MLX5_RQC_STATE_RST;
927 } else if (sm->state == IBV_WQS_RDY) {
928 rq_attr.rq_state = MLX5_RQC_STATE_RST;
929 rq_attr.state = MLX5_RQC_STATE_RDY;
930 } else if (sm->state == IBV_WQS_ERR) {
931 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
932 rq_attr.state = MLX5_RQC_STATE_ERR;
934 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
938 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s",
939 sm->state, strerror(errno));
944 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
945 struct mlx5_txq_ctrl *txq_ctrl =
946 container_of(txq, struct mlx5_txq_ctrl, txq);
947 struct ibv_qp_attr mod = {
948 .qp_state = IBV_QPS_RESET,
949 .port_num = (uint8_t)priv->ibv_port,
951 struct ibv_qp *qp = txq_ctrl->obj->qp;
953 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
955 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
956 "%s", strerror(errno));
960 mod.qp_state = IBV_QPS_INIT;
961 ret = mlx5_glue->modify_qp(qp, &mod,
962 (IBV_QP_STATE | IBV_QP_PORT));
964 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s",
969 mod.qp_state = IBV_QPS_RTR;
970 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
972 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s",
977 mod.qp_state = IBV_QPS_RTS;
978 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
980 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s",
990 * Modify a Verbs queue state.
993 * Pointer to Ethernet device.
995 * State modify request parameters.
998 * 0 in case of success else non-zero value.
1001 mlx5_queue_state_modify(struct rte_eth_dev *dev,
1002 struct mlx5_mp_arg_queue_state_modify *sm)
1004 struct mlx5_priv *priv = dev->data->dev_private;
1007 switch (rte_eal_process_type()) {
1008 case RTE_PROC_PRIMARY:
1009 ret = mlx5_queue_state_modify_primary(dev, sm);
1011 case RTE_PROC_SECONDARY:
1012 ret = mlx5_mp_req_queue_state_modify(&priv->mp_id, sm);
1021 * Handle a Rx error.
1022 * The function inserts the RQ state to reset when the first error CQE is
1023 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
1024 * it moves the RQ state to ready and initializes the RQ.
1025 * Next CQE identification and error counting are in the caller responsibility.
1028 * Pointer to RX queue structure.
1030 * 1 when called from vectorized Rx burst, need to prepare mbufs for the RQ.
1031 * 0 when called from non-vectorized Rx burst.
1034 * -1 in case of recovery error, otherwise the CQE status.
1037 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec)
1039 const uint16_t cqe_n = 1 << rxq->cqe_n;
1040 const uint16_t cqe_mask = cqe_n - 1;
1041 const unsigned int wqe_n = 1 << rxq->elts_n;
1042 struct mlx5_rxq_ctrl *rxq_ctrl =
1043 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
1045 volatile struct mlx5_cqe *cqe;
1046 volatile struct mlx5_err_cqe *err_cqe;
1048 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
1050 struct mlx5_mp_arg_queue_state_modify sm;
1053 switch (rxq->err_state) {
1054 case MLX5_RXQ_ERR_STATE_NO_ERROR:
1055 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
1057 case MLX5_RXQ_ERR_STATE_NEED_RESET:
1059 sm.queue_id = rxq->idx;
1060 sm.state = IBV_WQS_RESET;
1061 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
1063 if (rxq_ctrl->dump_file_n <
1064 rxq_ctrl->priv->config.max_dump_files_num) {
1065 MKSTR(err_str, "Unexpected CQE error syndrome "
1066 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
1067 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
1068 rxq->cqn, rxq_ctrl->wqn,
1069 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
1070 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
1071 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
1072 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
1073 mlx5_dump_debug_information(name, NULL, err_str, 0);
1074 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
1075 (const void *)((uintptr_t)
1077 sizeof(*u.cqe) * cqe_n);
1078 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
1079 (const void *)((uintptr_t)
1082 rxq_ctrl->dump_file_n++;
1084 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
1086 case MLX5_RXQ_ERR_STATE_NEED_READY:
1087 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1088 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1090 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1093 * The RQ consumer index must be zeroed while moving
1094 * from RESET state to RDY state.
1096 *rxq->rq_db = rte_cpu_to_be_32(0);
1099 sm.queue_id = rxq->idx;
1100 sm.state = IBV_WQS_RDY;
1101 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1105 const uint16_t q_mask = wqe_n - 1;
1107 struct rte_mbuf **elt;
1109 unsigned int n = wqe_n - (rxq->rq_ci -
1112 for (i = 0; i < (int)n; ++i) {
1113 elt_idx = (rxq->rq_ci + i) & q_mask;
1114 elt = &(*rxq->elts)[elt_idx];
1115 *elt = rte_mbuf_raw_alloc(rxq->mp);
1117 for (i--; i >= 0; --i) {
1118 elt_idx = (rxq->rq_ci +
1122 rte_pktmbuf_free_seg
1128 for (i = 0; i < (int)wqe_n; ++i) {
1129 elt = &(*rxq->elts)[i];
1131 (uint16_t)((*elt)->buf_len -
1132 rte_pktmbuf_headroom(*elt));
1134 /* Padding with a fake mbuf for vec Rx. */
1135 for (i = 0; i < MLX5_VPMD_DESCS_PER_LOOP; ++i)
1136 (*rxq->elts)[wqe_n + i] =
1139 mlx5_rxq_initialize(rxq);
1140 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1149 * Get size of the next packet for a given CQE. For compressed CQEs, the
1150 * consumer index is updated only once all packets of the current one have
1154 * Pointer to RX queue.
1158 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1162 * 0 in case of empty CQE, otherwise the packet size in bytes.
1165 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1166 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1168 struct rxq_zip *zip = &rxq->zip;
1169 uint16_t cqe_n = cqe_cnt + 1;
1175 /* Process compressed data in the CQE and mini arrays. */
1177 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1178 (volatile struct mlx5_mini_cqe8 (*)[8])
1179 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1182 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1183 *mcqe = &(*mc)[zip->ai & 7];
1184 if ((++zip->ai & 7) == 0) {
1185 /* Invalidate consumed CQEs */
1188 while (idx != end) {
1189 (*rxq->cqes)[idx & cqe_cnt].op_own =
1190 MLX5_CQE_INVALIDATE;
1194 * Increment consumer index to skip the number
1195 * of CQEs consumed. Hardware leaves holes in
1196 * the CQ ring for software use.
1201 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1202 /* Invalidate the rest */
1206 while (idx != end) {
1207 (*rxq->cqes)[idx & cqe_cnt].op_own =
1208 MLX5_CQE_INVALIDATE;
1211 rxq->cq_ci = zip->cq_ci;
1215 * No compressed data, get next CQE and verify if it is
1222 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1223 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1224 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1226 ret = mlx5_rx_err_handle(rxq, 0);
1227 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1235 op_own = cqe->op_own;
1236 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1237 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1238 (volatile struct mlx5_mini_cqe8 (*)[8])
1239 (uintptr_t)(&(*rxq->cqes)
1243 /* Fix endianness. */
1244 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1246 * Current mini array position is the one
1247 * returned by check_cqe64().
1249 * If completion comprises several mini arrays,
1250 * as a special case the second one is located
1251 * 7 CQEs after the initial CQE instead of 8
1252 * for subsequent ones.
1254 zip->ca = rxq->cq_ci;
1255 zip->na = zip->ca + 7;
1256 /* Compute the next non compressed CQE. */
1258 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1259 /* Get packet size to return. */
1260 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1263 /* Prefetch all to be invalidated */
1266 while (idx != end) {
1267 rte_prefetch0(&(*rxq->cqes)[(idx) &
1272 len = rte_be_to_cpu_32(cqe->byte_cnt);
1275 if (unlikely(rxq->err_state)) {
1276 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1277 ++rxq->stats.idropped;
1285 * Translate RX completion flags to offload flags.
1291 * Offload flags (ol_flags) for struct rte_mbuf.
1293 static inline uint32_t
1294 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1296 uint32_t ol_flags = 0;
1297 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1301 MLX5_CQE_RX_L3_HDR_VALID,
1302 PKT_RX_IP_CKSUM_GOOD) |
1304 MLX5_CQE_RX_L4_HDR_VALID,
1305 PKT_RX_L4_CKSUM_GOOD);
1310 * Fill in mbuf fields from RX completion flags.
1311 * Note that pkt->ol_flags should be initialized outside of this function.
1314 * Pointer to RX queue.
1319 * @param rss_hash_res
1320 * Packet RSS Hash result.
1323 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1324 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1326 /* Update packet information. */
1327 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1328 if (rss_hash_res && rxq->rss_hash) {
1329 pkt->hash.rss = rss_hash_res;
1330 pkt->ol_flags |= PKT_RX_RSS_HASH;
1332 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1333 pkt->ol_flags |= PKT_RX_FDIR;
1334 if (cqe->sop_drop_qpn !=
1335 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1336 uint32_t mark = cqe->sop_drop_qpn;
1338 pkt->ol_flags |= PKT_RX_FDIR_ID;
1339 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1342 if (rte_flow_dynf_metadata_avail() && cqe->flow_table_metadata) {
1343 pkt->ol_flags |= PKT_RX_DYNF_METADATA;
1344 *RTE_FLOW_DYNF_METADATA(pkt) = cqe->flow_table_metadata;
1347 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1348 if (rxq->vlan_strip &&
1349 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1350 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1351 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1353 if (rxq->hw_timestamp) {
1354 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1355 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1360 * DPDK callback for RX.
1363 * Generic pointer to RX queue structure.
1365 * Array to store received packets.
1367 * Maximum number of packets in array.
1370 * Number of packets successfully received (<= pkts_n).
1373 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1375 struct mlx5_rxq_data *rxq = dpdk_rxq;
1376 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1377 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1378 const unsigned int sges_n = rxq->sges_n;
1379 struct rte_mbuf *pkt = NULL;
1380 struct rte_mbuf *seg = NULL;
1381 volatile struct mlx5_cqe *cqe =
1382 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1384 unsigned int rq_ci = rxq->rq_ci << sges_n;
1385 int len = 0; /* keep its value across iterations. */
1388 unsigned int idx = rq_ci & wqe_cnt;
1389 volatile struct mlx5_wqe_data_seg *wqe =
1390 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1391 struct rte_mbuf *rep = (*rxq->elts)[idx];
1392 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1393 uint32_t rss_hash_res;
1401 rep = rte_mbuf_raw_alloc(rxq->mp);
1402 if (unlikely(rep == NULL)) {
1403 ++rxq->stats.rx_nombuf;
1406 * no buffers before we even started,
1407 * bail out silently.
1411 while (pkt != seg) {
1412 MLX5_ASSERT(pkt != (*rxq->elts)[idx]);
1416 rte_mbuf_raw_free(pkt);
1422 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1423 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1425 rte_mbuf_raw_free(rep);
1429 MLX5_ASSERT(len >= (rxq->crc_present << 2));
1430 pkt->ol_flags &= EXT_ATTACHED_MBUF;
1431 /* If compressed, take hash result from mini-CQE. */
1432 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1434 mcqe->rx_hash_result);
1435 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1436 if (rxq->crc_present)
1437 len -= RTE_ETHER_CRC_LEN;
1439 if (cqe->lro_num_seg > 1) {
1441 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1443 pkt->ol_flags |= PKT_RX_LRO;
1444 pkt->tso_segsz = len / cqe->lro_num_seg;
1447 DATA_LEN(rep) = DATA_LEN(seg);
1448 PKT_LEN(rep) = PKT_LEN(seg);
1449 SET_DATA_OFF(rep, DATA_OFF(seg));
1450 PORT(rep) = PORT(seg);
1451 (*rxq->elts)[idx] = rep;
1453 * Fill NIC descriptor with the new buffer. The lkey and size
1454 * of the buffers are already known, only the buffer address
1457 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1458 /* If there's only one MR, no need to replace LKey in WQE. */
1459 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1460 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1461 if (len > DATA_LEN(seg)) {
1462 len -= DATA_LEN(seg);
1467 DATA_LEN(seg) = len;
1468 #ifdef MLX5_PMD_SOFT_COUNTERS
1469 /* Increment bytes counter. */
1470 rxq->stats.ibytes += PKT_LEN(pkt);
1472 /* Return packet. */
1477 /* Align consumer index to the next stride. */
1482 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1484 /* Update the consumer index. */
1485 rxq->rq_ci = rq_ci >> sges_n;
1487 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1489 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1490 #ifdef MLX5_PMD_SOFT_COUNTERS
1491 /* Increment packets counter. */
1492 rxq->stats.ipackets += i;
1498 * Update LRO packet TCP header.
1499 * The HW LRO feature doesn't update the TCP header after coalescing the
1500 * TCP segments but supplies information in CQE to fill it by SW.
1503 * Pointer to the TCP header.
1505 * Pointer to the completion entry..
1507 * The L3 pseudo-header checksum.
1510 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1511 volatile struct mlx5_cqe *restrict cqe,
1514 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1515 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1517 * The HW calculates only the TCP payload checksum, need to complete
1518 * the TCP header checksum and the L3 pseudo-header checksum.
1520 uint32_t csum = phcsum + cqe->csum;
1522 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1523 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1524 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1525 tcp->recv_ack = cqe->lro_ack_seq_num;
1526 tcp->rx_win = cqe->lro_tcp_win;
1528 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1529 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1531 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1532 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1533 csum = (~csum) & 0xffff;
1540 * Update LRO packet headers.
1541 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1542 * TCP segments but supply information in CQE to fill it by SW.
1545 * The packet address.
1547 * Pointer to the completion entry..
1549 * The packet length.
1552 mlx5_lro_update_hdr(uint8_t *restrict padd,
1553 volatile struct mlx5_cqe *restrict cqe,
1557 struct rte_ether_hdr *eth;
1558 struct rte_vlan_hdr *vlan;
1559 struct rte_ipv4_hdr *ipv4;
1560 struct rte_ipv6_hdr *ipv6;
1561 struct rte_tcp_hdr *tcp;
1566 uint16_t proto = h.eth->ether_type;
1570 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1571 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1572 proto = h.vlan->eth_proto;
1575 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1576 h.ipv4->time_to_live = cqe->lro_min_ttl;
1577 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1578 h.ipv4->hdr_checksum = 0;
1579 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1580 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1583 h.ipv6->hop_limits = cqe->lro_min_ttl;
1584 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1586 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1589 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1593 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1595 struct mlx5_mprq_buf *buf = opaque;
1597 if (rte_atomic16_read(&buf->refcnt) == 1) {
1598 rte_mempool_put(buf->mp, buf);
1599 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1600 rte_atomic16_set(&buf->refcnt, 1);
1601 rte_mempool_put(buf->mp, buf);
1606 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1608 mlx5_mprq_buf_free_cb(NULL, buf);
1612 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1613 const unsigned int strd_n)
1615 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1616 volatile struct mlx5_wqe_data_seg *wqe =
1617 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1620 MLX5_ASSERT(rep != NULL);
1621 /* Replace MPRQ buf. */
1622 (*rxq->mprq_bufs)[rq_idx] = rep;
1624 addr = mlx5_mprq_buf_addr(rep, strd_n);
1625 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1626 /* If there's only one MR, no need to replace LKey in WQE. */
1627 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1628 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1629 /* Stash a mbuf for next replacement. */
1630 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1631 rxq->mprq_repl = rep;
1633 rxq->mprq_repl = NULL;
1637 * DPDK callback for RX with Multi-Packet RQ support.
1640 * Generic pointer to RX queue structure.
1642 * Array to store received packets.
1644 * Maximum number of packets in array.
1647 * Number of packets successfully received (<= pkts_n).
1650 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1652 struct mlx5_rxq_data *rxq = dpdk_rxq;
1653 const unsigned int strd_n = 1 << rxq->strd_num_n;
1654 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1655 const unsigned int strd_shift =
1656 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1657 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1658 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1659 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1661 uint32_t rq_ci = rxq->rq_ci;
1662 uint16_t consumed_strd = rxq->consumed_strd;
1663 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1665 while (i < pkts_n) {
1666 struct rte_mbuf *pkt;
1674 int32_t hdrm_overlap;
1675 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1676 uint32_t rss_hash_res = 0;
1678 if (consumed_strd == strd_n) {
1679 /* Replace WQE only if the buffer is still in use. */
1680 if (rte_atomic16_read(&buf->refcnt) > 1) {
1681 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1682 /* Release the old buffer. */
1683 mlx5_mprq_buf_free(buf);
1684 } else if (unlikely(rxq->mprq_repl == NULL)) {
1685 struct mlx5_mprq_buf *rep;
1688 * Currently, the MPRQ mempool is out of buffer
1689 * and doing memcpy regardless of the size of Rx
1690 * packet. Retry allocation to get back to
1693 if (!rte_mempool_get(rxq->mprq_mp,
1695 rxq->mprq_repl = rep;
1697 /* Advance to the next WQE. */
1700 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1702 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1703 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1707 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1708 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1709 MLX5_ASSERT(strd_cnt);
1710 consumed_strd += strd_cnt;
1711 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1714 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1715 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1717 /* mini-CQE for MPRQ doesn't have hash result. */
1718 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1720 MLX5_ASSERT(strd_idx < strd_n);
1721 MLX5_ASSERT(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) &
1723 pkt = rte_pktmbuf_alloc(rxq->mp);
1724 if (unlikely(pkt == NULL)) {
1725 ++rxq->stats.rx_nombuf;
1728 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1729 MLX5_ASSERT((int)len >= (rxq->crc_present << 2));
1730 if (rxq->crc_present)
1731 len -= RTE_ETHER_CRC_LEN;
1732 offset = strd_idx * strd_sz + strd_shift;
1733 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1734 hdrm_overlap = len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
1736 * Memcpy packets to the target mbuf if:
1737 * - The size of packet is smaller than mprq_max_memcpy_len.
1738 * - Out of buffer in the Mempool for Multi-Packet RQ.
1739 * - The packet's stride overlaps a headroom and scatter is off.
1741 if (len <= rxq->mprq_max_memcpy_len ||
1742 rxq->mprq_repl == NULL ||
1743 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
1744 if (likely(rte_pktmbuf_tailroom(pkt) >= len)) {
1745 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
1747 DATA_LEN(pkt) = len;
1748 } else if (rxq->strd_scatter_en) {
1749 struct rte_mbuf *prev = pkt;
1751 RTE_MIN(rte_pktmbuf_tailroom(pkt), len);
1752 uint32_t rem_len = len - seg_len;
1754 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
1756 DATA_LEN(pkt) = seg_len;
1758 struct rte_mbuf *next =
1759 rte_pktmbuf_alloc(rxq->mp);
1761 if (unlikely(next == NULL)) {
1762 rte_pktmbuf_free(pkt);
1763 ++rxq->stats.rx_nombuf;
1767 SET_DATA_OFF(next, 0);
1768 addr = RTE_PTR_ADD(addr, seg_len);
1770 (rte_pktmbuf_tailroom(next),
1773 (rte_pktmbuf_mtod(next, void *),
1775 DATA_LEN(next) = seg_len;
1781 rte_pktmbuf_free_seg(pkt);
1782 ++rxq->stats.idropped;
1786 rte_iova_t buf_iova;
1787 struct rte_mbuf_ext_shared_info *shinfo;
1788 uint16_t buf_len = strd_cnt * strd_sz;
1791 /* Increment the refcnt of the whole chunk. */
1792 rte_atomic16_add_return(&buf->refcnt, 1);
1793 MLX5_ASSERT((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1795 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
1797 * MLX5 device doesn't use iova but it is necessary in a
1798 * case where the Rx packet is transmitted via a
1801 buf_iova = rte_mempool_virt2iova(buf) +
1802 RTE_PTR_DIFF(buf_addr, buf);
1803 shinfo = &buf->shinfos[strd_idx];
1804 rte_mbuf_ext_refcnt_set(shinfo, 1);
1806 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1807 * attaching the stride to mbuf and more offload flags
1808 * will be added below by calling rxq_cq_to_mbuf().
1809 * Other fields will be overwritten.
1811 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1813 /* Set mbuf head-room. */
1814 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
1815 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
1816 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) <
1817 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
1818 DATA_LEN(pkt) = len;
1820 * Copy the last fragment of a packet (up to headroom
1821 * size bytes) in case there is a stride overlap with
1822 * a next packet's headroom. Allocate a separate mbuf
1823 * to store this fragment and link it. Scatter is on.
1825 if (hdrm_overlap > 0) {
1826 MLX5_ASSERT(rxq->strd_scatter_en);
1827 struct rte_mbuf *seg =
1828 rte_pktmbuf_alloc(rxq->mp);
1830 if (unlikely(seg == NULL)) {
1831 rte_pktmbuf_free_seg(pkt);
1832 ++rxq->stats.rx_nombuf;
1835 SET_DATA_OFF(seg, 0);
1836 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
1837 RTE_PTR_ADD(addr, len - hdrm_overlap),
1839 DATA_LEN(seg) = hdrm_overlap;
1840 DATA_LEN(pkt) = len - hdrm_overlap;
1845 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1846 if (cqe->lro_num_seg > 1) {
1847 mlx5_lro_update_hdr(addr, cqe, len);
1848 pkt->ol_flags |= PKT_RX_LRO;
1849 pkt->tso_segsz = len / cqe->lro_num_seg;
1852 PORT(pkt) = rxq->port_id;
1853 #ifdef MLX5_PMD_SOFT_COUNTERS
1854 /* Increment bytes counter. */
1855 rxq->stats.ibytes += PKT_LEN(pkt);
1857 /* Return packet. */
1862 /* Update the consumer indexes. */
1863 rxq->consumed_strd = consumed_strd;
1865 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1866 if (rq_ci != rxq->rq_ci) {
1869 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1871 #ifdef MLX5_PMD_SOFT_COUNTERS
1872 /* Increment packets counter. */
1873 rxq->stats.ipackets += i;
1879 * Dummy DPDK callback for TX.
1881 * This function is used to temporarily replace the real callback during
1882 * unsafe control operations on the queue, or in case of error.
1885 * Generic pointer to TX queue structure.
1887 * Packets to transmit.
1889 * Number of packets in array.
1892 * Number of packets successfully transmitted (<= pkts_n).
1895 removed_tx_burst(void *dpdk_txq __rte_unused,
1896 struct rte_mbuf **pkts __rte_unused,
1897 uint16_t pkts_n __rte_unused)
1904 * Dummy DPDK callback for RX.
1906 * This function is used to temporarily replace the real callback during
1907 * unsafe control operations on the queue, or in case of error.
1910 * Generic pointer to RX queue structure.
1912 * Array to store received packets.
1914 * Maximum number of packets in array.
1917 * Number of packets successfully received (<= pkts_n).
1920 removed_rx_burst(void *dpdk_txq __rte_unused,
1921 struct rte_mbuf **pkts __rte_unused,
1922 uint16_t pkts_n __rte_unused)
1929 * Vectorized Rx/Tx routines are not compiled in when required vector
1930 * instructions are not supported on a target architecture. The following null
1931 * stubs are needed for linkage when those are not included outside of this file
1932 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1936 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1937 struct rte_mbuf **pkts __rte_unused,
1938 uint16_t pkts_n __rte_unused)
1944 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1950 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1956 * Free the mbufs from the linear array of pointers.
1959 * Pointer to array of packets to be free.
1961 * Number of packets to be freed.
1963 * Configured Tx offloads mask. It is fully defined at
1964 * compile time and may be used for optimization.
1966 static __rte_always_inline void
1967 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1968 unsigned int pkts_n,
1969 unsigned int olx __rte_unused)
1971 struct rte_mempool *pool = NULL;
1972 struct rte_mbuf **p_free = NULL;
1973 struct rte_mbuf *mbuf;
1974 unsigned int n_free = 0;
1977 * The implemented algorithm eliminates
1978 * copying pointers to temporary array
1979 * for rte_mempool_put_bulk() calls.
1982 MLX5_ASSERT(pkts_n);
1986 * Decrement mbuf reference counter, detach
1987 * indirect and external buffers if needed.
1989 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1990 if (likely(mbuf != NULL)) {
1991 MLX5_ASSERT(mbuf == *pkts);
1992 if (likely(n_free != 0)) {
1993 if (unlikely(pool != mbuf->pool))
1994 /* From different pool. */
1997 /* Start new scan array. */
2004 if (unlikely(pkts_n == 0)) {
2010 * This happens if mbuf is still referenced.
2011 * We can't put it back to the pool, skip.
2015 if (unlikely(n_free != 0))
2016 /* There is some array to free.*/
2018 if (unlikely(pkts_n == 0))
2019 /* Last mbuf, nothing to free. */
2025 * This loop is implemented to avoid multiple
2026 * inlining of rte_mempool_put_bulk().
2029 MLX5_ASSERT(p_free);
2030 MLX5_ASSERT(n_free);
2032 * Free the array of pre-freed mbufs
2033 * belonging to the same memory pool.
2035 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
2036 if (unlikely(mbuf != NULL)) {
2037 /* There is the request to start new scan. */
2042 if (likely(pkts_n != 0))
2045 * This is the last mbuf to be freed.
2046 * Do one more loop iteration to complete.
2047 * This is rare case of the last unique mbuf.
2052 if (likely(pkts_n == 0))
2061 * Free the mbuf from the elts ring buffer till new tail.
2064 * Pointer to Tx queue structure.
2066 * Index in elts to free up to, becomes new elts tail.
2068 * Configured Tx offloads mask. It is fully defined at
2069 * compile time and may be used for optimization.
2071 static __rte_always_inline void
2072 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
2074 unsigned int olx __rte_unused)
2076 uint16_t n_elts = tail - txq->elts_tail;
2078 MLX5_ASSERT(n_elts);
2079 MLX5_ASSERT(n_elts <= txq->elts_s);
2081 * Implement a loop to support ring buffer wraparound
2082 * with single inlining of mlx5_tx_free_mbuf().
2087 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
2088 part = RTE_MIN(part, n_elts);
2090 MLX5_ASSERT(part <= txq->elts_s);
2091 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
2093 txq->elts_tail += part;
2099 * Store the mbuf being sent into elts ring buffer.
2100 * On Tx completion these mbufs will be freed.
2103 * Pointer to Tx queue structure.
2105 * Pointer to array of packets to be stored.
2107 * Number of packets to be stored.
2109 * Configured Tx offloads mask. It is fully defined at
2110 * compile time and may be used for optimization.
2112 static __rte_always_inline void
2113 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
2114 struct rte_mbuf **restrict pkts,
2115 unsigned int pkts_n,
2116 unsigned int olx __rte_unused)
2119 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2122 MLX5_ASSERT(pkts_n);
2123 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2125 MLX5_ASSERT(part <= txq->elts_s);
2126 /* This code is a good candidate for vectorizing with SIMD. */
2127 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2129 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2130 txq->elts_head += pkts_n;
2131 if (unlikely(part < pkts_n))
2132 /* The copy is wrapping around the elts array. */
2133 rte_memcpy((void *)elts, (void *)(pkts + part),
2134 (pkts_n - part) * sizeof(struct rte_mbuf *));
2138 * Update completion queue consuming index via doorbell
2139 * and flush the completed data buffers.
2142 * Pointer to TX queue structure.
2143 * @param valid CQE pointer
2144 * if not NULL update txq->wqe_pi and flush the buffers
2146 * Configured Tx offloads mask. It is fully defined at
2147 * compile time and may be used for optimization.
2149 static __rte_always_inline void
2150 mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
2151 volatile struct mlx5_cqe *last_cqe,
2152 unsigned int olx __rte_unused)
2154 if (likely(last_cqe != NULL)) {
2157 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2158 tail = txq->fcqs[(txq->cq_ci - 1) & txq->cqe_m];
2159 if (likely(tail != txq->elts_tail)) {
2160 mlx5_tx_free_elts(txq, tail, olx);
2161 MLX5_ASSERT(tail == txq->elts_tail);
2167 * Manage TX completions. This routine checks the CQ for
2168 * arrived CQEs, deduces the last accomplished WQE in SQ,
2169 * updates SQ producing index and frees all completed mbufs.
2172 * Pointer to TX queue structure.
2174 * Configured Tx offloads mask. It is fully defined at
2175 * compile time and may be used for optimization.
2177 * NOTE: not inlined intentionally, it makes tx_burst
2178 * routine smaller, simple and faster - from experiments.
2181 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2182 unsigned int olx __rte_unused)
2184 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2185 volatile struct mlx5_cqe *last_cqe = NULL;
2186 bool ring_doorbell = false;
2189 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2190 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2192 volatile struct mlx5_cqe *cqe;
2194 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2195 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2196 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2197 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2198 /* No new CQEs in completion queue. */
2199 MLX5_ASSERT(ret == MLX5_CQE_STATUS_HW_OWN);
2203 * Some error occurred, try to restart.
2204 * We have no barrier after WQE related Doorbell
2205 * written, make sure all writes are completed
2206 * here, before we might perform SQ reset.
2209 ret = mlx5_tx_error_cqe_handle
2210 (txq, (volatile struct mlx5_err_cqe *)cqe);
2211 if (unlikely(ret < 0)) {
2213 * Some error occurred on queue error
2214 * handling, we do not advance the index
2215 * here, allowing to retry on next call.
2220 * We are going to fetch all entries with
2221 * MLX5_CQE_SYNDROME_WR_FLUSH_ERR status.
2222 * The send queue is supposed to be empty.
2224 ring_doorbell = true;
2226 txq->cq_pi = txq->cq_ci;
2230 /* Normal transmit completion. */
2231 MLX5_ASSERT(txq->cq_ci != txq->cq_pi);
2232 MLX5_ASSERT((txq->fcqs[txq->cq_ci & txq->cqe_m] >> 16) ==
2234 ring_doorbell = true;
2238 * We have to restrict the amount of processed CQEs
2239 * in one tx_burst routine call. The CQ may be large
2240 * and many CQEs may be updated by the NIC in one
2241 * transaction. Buffers freeing is time consuming,
2242 * multiple iterations may introduce significant
2245 if (likely(--count == 0))
2248 if (likely(ring_doorbell)) {
2249 /* Ring doorbell to notify hardware. */
2250 rte_compiler_barrier();
2251 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2252 mlx5_tx_comp_flush(txq, last_cqe, olx);
2257 * Check if the completion request flag should be set in the last WQE.
2258 * Both pushed mbufs and WQEs are monitored and the completion request
2259 * flag is set if any of thresholds is reached.
2262 * Pointer to TX queue structure.
2264 * Pointer to burst routine local context.
2266 * Configured Tx offloads mask. It is fully defined at
2267 * compile time and may be used for optimization.
2269 static __rte_always_inline void
2270 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2271 struct mlx5_txq_local *restrict loc,
2274 uint16_t head = txq->elts_head;
2277 part = MLX5_TXOFF_CONFIG(INLINE) ?
2278 0 : loc->pkts_sent - loc->pkts_copy;
2280 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2281 (MLX5_TXOFF_CONFIG(INLINE) &&
2282 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2283 volatile struct mlx5_wqe *last = loc->wqe_last;
2286 txq->elts_comp = head;
2287 if (MLX5_TXOFF_CONFIG(INLINE))
2288 txq->wqe_comp = txq->wqe_ci;
2289 /* Request unconditional completion on last WQE. */
2290 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2291 MLX5_COMP_MODE_OFFSET);
2292 /* Save elts_head in dedicated free on completion queue. */
2293 #ifdef RTE_LIBRTE_MLX5_DEBUG
2294 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head |
2295 (last->cseg.opcode >> 8) << 16;
2297 txq->fcqs[txq->cq_pi++ & txq->cqe_m] = head;
2299 /* A CQE slot must always be available. */
2300 MLX5_ASSERT((txq->cq_pi - txq->cq_ci) <= txq->cqe_s);
2305 * DPDK callback to check the status of a tx descriptor.
2310 * The index of the descriptor in the ring.
2313 * The status of the tx descriptor.
2316 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2318 struct mlx5_txq_data *restrict txq = tx_queue;
2321 mlx5_tx_handle_completion(txq, 0);
2322 used = txq->elts_head - txq->elts_tail;
2324 return RTE_ETH_TX_DESC_FULL;
2325 return RTE_ETH_TX_DESC_DONE;
2329 * Build the Control Segment with specified opcode:
2330 * - MLX5_OPCODE_SEND
2331 * - MLX5_OPCODE_ENHANCED_MPSW
2335 * Pointer to TX queue structure.
2337 * Pointer to burst routine local context.
2339 * Pointer to WQE to fill with built Control Segment.
2341 * Supposed length of WQE in segments.
2343 * SQ WQE opcode to put into Control Segment.
2345 * Configured Tx offloads mask. It is fully defined at
2346 * compile time and may be used for optimization.
2348 static __rte_always_inline void
2349 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2350 struct mlx5_txq_local *restrict loc __rte_unused,
2351 struct mlx5_wqe *restrict wqe,
2353 unsigned int opcode,
2354 unsigned int olx __rte_unused)
2356 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2358 /* For legacy MPW replace the EMPW by TSO with modifier. */
2359 if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW)
2360 opcode = MLX5_OPCODE_TSO | MLX5_OPC_MOD_MPW << 24;
2361 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2362 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2363 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2364 MLX5_COMP_MODE_OFFSET);
2365 cs->misc = RTE_BE32(0);
2369 * Build the Ethernet Segment without inlined data.
2370 * Supports Software Parser, Checksums and VLAN
2371 * insertion Tx offload features.
2374 * Pointer to TX queue structure.
2376 * Pointer to burst routine local context.
2378 * Pointer to WQE to fill with built Ethernet Segment.
2380 * Configured Tx offloads mask. It is fully defined at
2381 * compile time and may be used for optimization.
2383 static __rte_always_inline void
2384 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2385 struct mlx5_txq_local *restrict loc,
2386 struct mlx5_wqe *restrict wqe,
2389 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2393 * Calculate and set check sum flags first, dword field
2394 * in segment may be shared with Software Parser flags.
2396 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2397 es->flags = rte_cpu_to_le_32(csum);
2399 * Calculate and set Software Parser offsets and flags.
2400 * These flags a set for custom UDP and IP tunnel packets.
2402 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2403 /* Fill metadata field if needed. */
2404 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2405 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2406 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2407 /* Engage VLAN tag insertion feature if requested. */
2408 if (MLX5_TXOFF_CONFIG(VLAN) &&
2409 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2411 * We should get here only if device support
2412 * this feature correctly.
2414 MLX5_ASSERT(txq->vlan_en);
2415 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2416 loc->mbuf->vlan_tci);
2418 es->inline_hdr = RTE_BE32(0);
2423 * Build the Ethernet Segment with minimal inlined data
2424 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2425 * used to fill the gap in single WQEBB WQEs.
2426 * Supports Software Parser, Checksums and VLAN
2427 * insertion Tx offload features.
2430 * Pointer to TX queue structure.
2432 * Pointer to burst routine local context.
2434 * Pointer to WQE to fill with built Ethernet Segment.
2436 * Length of VLAN tag insertion if any.
2438 * Configured Tx offloads mask. It is fully defined at
2439 * compile time and may be used for optimization.
2441 static __rte_always_inline void
2442 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2443 struct mlx5_txq_local *restrict loc,
2444 struct mlx5_wqe *restrict wqe,
2448 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2450 uint8_t *psrc, *pdst;
2453 * Calculate and set check sum flags first, dword field
2454 * in segment may be shared with Software Parser flags.
2456 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2457 es->flags = rte_cpu_to_le_32(csum);
2459 * Calculate and set Software Parser offsets and flags.
2460 * These flags a set for custom UDP and IP tunnel packets.
2462 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2463 /* Fill metadata field if needed. */
2464 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2465 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2466 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2467 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2469 sizeof(rte_v128u32_t)),
2470 "invalid Ethernet Segment data size");
2471 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2473 sizeof(struct rte_vlan_hdr) +
2474 2 * RTE_ETHER_ADDR_LEN),
2475 "invalid Ethernet Segment data size");
2476 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2477 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2478 es->inline_data = *(unaligned_uint16_t *)psrc;
2479 psrc += sizeof(uint16_t);
2480 pdst = (uint8_t *)(es + 1);
2481 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2482 /* Implement VLAN tag insertion as part inline data. */
2483 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2484 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2485 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2486 /* Insert VLAN ethertype + VLAN tag. */
2487 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2488 ((RTE_ETHER_TYPE_VLAN << 16) |
2489 loc->mbuf->vlan_tci);
2490 pdst += sizeof(struct rte_vlan_hdr);
2491 /* Copy the rest two bytes from packet data. */
2492 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2493 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2495 /* Fill the gap in the title WQEBB with inline data. */
2496 rte_mov16(pdst, psrc);
2501 * Build the Ethernet Segment with entire packet
2502 * data inlining. Checks the boundary of WQEBB and
2503 * ring buffer wrapping, supports Software Parser,
2504 * Checksums and VLAN insertion Tx offload features.
2507 * Pointer to TX queue structure.
2509 * Pointer to burst routine local context.
2511 * Pointer to WQE to fill with built Ethernet Segment.
2513 * Length of VLAN tag insertion if any.
2515 * Length of data to inline (VLAN included, if any).
2517 * TSO flag, set mss field from the packet.
2519 * Configured Tx offloads mask. It is fully defined at
2520 * compile time and may be used for optimization.
2523 * Pointer to the next Data Segment (aligned and wrapped around).
2525 static __rte_always_inline struct mlx5_wqe_dseg *
2526 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2527 struct mlx5_txq_local *restrict loc,
2528 struct mlx5_wqe *restrict wqe,
2534 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2536 uint8_t *psrc, *pdst;
2540 * Calculate and set check sum flags first, dword field
2541 * in segment may be shared with Software Parser flags.
2543 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2546 csum |= loc->mbuf->tso_segsz;
2547 es->flags = rte_cpu_to_be_32(csum);
2549 es->flags = rte_cpu_to_le_32(csum);
2552 * Calculate and set Software Parser offsets and flags.
2553 * These flags a set for custom UDP and IP tunnel packets.
2555 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2556 /* Fill metadata field if needed. */
2557 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2558 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2559 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2560 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2562 sizeof(rte_v128u32_t)),
2563 "invalid Ethernet Segment data size");
2564 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2566 sizeof(struct rte_vlan_hdr) +
2567 2 * RTE_ETHER_ADDR_LEN),
2568 "invalid Ethernet Segment data size");
2569 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2570 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2571 es->inline_data = *(unaligned_uint16_t *)psrc;
2572 psrc += sizeof(uint16_t);
2573 pdst = (uint8_t *)(es + 1);
2574 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2575 /* Implement VLAN tag insertion as part inline data. */
2576 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2577 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2578 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2579 /* Insert VLAN ethertype + VLAN tag. */
2580 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2581 ((RTE_ETHER_TYPE_VLAN << 16) |
2582 loc->mbuf->vlan_tci);
2583 pdst += sizeof(struct rte_vlan_hdr);
2584 /* Copy the rest two bytes from packet data. */
2585 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2586 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2587 psrc += sizeof(uint16_t);
2589 /* Fill the gap in the title WQEBB with inline data. */
2590 rte_mov16(pdst, psrc);
2591 psrc += sizeof(rte_v128u32_t);
2593 pdst = (uint8_t *)(es + 2);
2594 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2595 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2596 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2598 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2599 return (struct mlx5_wqe_dseg *)pdst;
2602 * The WQEBB space availability is checked by caller.
2603 * Here we should be aware of WQE ring buffer wraparound only.
2605 part = (uint8_t *)txq->wqes_end - pdst;
2606 part = RTE_MIN(part, inlen);
2608 rte_memcpy(pdst, psrc, part);
2610 if (likely(!inlen)) {
2612 * If return value is not used by the caller
2613 * the code below will be optimized out.
2616 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2617 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2618 pdst = (uint8_t *)txq->wqes;
2619 return (struct mlx5_wqe_dseg *)pdst;
2621 pdst = (uint8_t *)txq->wqes;
2628 * Copy data from chain of mbuf to the specified linear buffer.
2629 * Checksums and VLAN insertion Tx offload features. If data
2630 * from some mbuf copied completely this mbuf is freed. Local
2631 * structure is used to keep the byte stream state.
2634 * Pointer to the destination linear buffer.
2636 * Pointer to burst routine local context.
2638 * Length of data to be copied.
2640 * Length of data to be copied ignoring no inline hint.
2642 * Configured Tx offloads mask. It is fully defined at
2643 * compile time and may be used for optimization.
2646 * Number of actual copied data bytes. This is always greater than or
2647 * equal to must parameter and might be lesser than len in no inline
2648 * hint flag is encountered.
2650 static __rte_always_inline unsigned int
2651 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2652 struct mlx5_txq_local *restrict loc,
2655 unsigned int olx __rte_unused)
2657 struct rte_mbuf *mbuf;
2658 unsigned int part, dlen, copy = 0;
2662 MLX5_ASSERT(must <= len);
2664 /* Allow zero length packets, must check first. */
2665 dlen = rte_pktmbuf_data_len(loc->mbuf);
2666 if (dlen <= loc->mbuf_off) {
2667 /* Exhausted packet, just free. */
2669 loc->mbuf = mbuf->next;
2670 rte_pktmbuf_free_seg(mbuf);
2672 MLX5_ASSERT(loc->mbuf_nseg > 1);
2673 MLX5_ASSERT(loc->mbuf);
2675 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
2680 * We already copied the minimal
2681 * requested amount of data.
2686 if (diff <= rte_pktmbuf_data_len(loc->mbuf)) {
2688 * Copy only the minimal required
2689 * part of the data buffer.
2696 dlen -= loc->mbuf_off;
2697 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2699 part = RTE_MIN(len, dlen);
2700 rte_memcpy(pdst, psrc, part);
2702 loc->mbuf_off += part;
2705 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2707 /* Exhausted packet, just free. */
2709 loc->mbuf = mbuf->next;
2710 rte_pktmbuf_free_seg(mbuf);
2712 MLX5_ASSERT(loc->mbuf_nseg >= 1);
2722 * Build the Ethernet Segment with inlined data from
2723 * multi-segment packet. Checks the boundary of WQEBB
2724 * and ring buffer wrapping, supports Software Parser,
2725 * Checksums and VLAN insertion Tx offload features.
2728 * Pointer to TX queue structure.
2730 * Pointer to burst routine local context.
2732 * Pointer to WQE to fill with built Ethernet Segment.
2734 * Length of VLAN tag insertion if any.
2736 * Length of data to inline (VLAN included, if any).
2738 * TSO flag, set mss field from the packet.
2740 * Configured Tx offloads mask. It is fully defined at
2741 * compile time and may be used for optimization.
2744 * Pointer to the next Data Segment (aligned and
2745 * possible NOT wrapped around - caller should do
2746 * wrapping check on its own).
2748 static __rte_always_inline struct mlx5_wqe_dseg *
2749 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2750 struct mlx5_txq_local *restrict loc,
2751 struct mlx5_wqe *restrict wqe,
2757 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2760 unsigned int part, tlen = 0;
2763 * Calculate and set check sum flags first, uint32_t field
2764 * in segment may be shared with Software Parser flags.
2766 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2769 csum |= loc->mbuf->tso_segsz;
2770 es->flags = rte_cpu_to_be_32(csum);
2772 es->flags = rte_cpu_to_le_32(csum);
2775 * Calculate and set Software Parser offsets and flags.
2776 * These flags a set for custom UDP and IP tunnel packets.
2778 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2779 /* Fill metadata field if needed. */
2780 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2781 loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
2782 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0 : 0;
2783 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2785 sizeof(rte_v128u32_t)),
2786 "invalid Ethernet Segment data size");
2787 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2789 sizeof(struct rte_vlan_hdr) +
2790 2 * RTE_ETHER_ADDR_LEN),
2791 "invalid Ethernet Segment data size");
2792 MLX5_ASSERT(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2793 pdst = (uint8_t *)&es->inline_data;
2794 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2795 /* Implement VLAN tag insertion as part inline data. */
2796 mlx5_tx_mseg_memcpy(pdst, loc,
2797 2 * RTE_ETHER_ADDR_LEN,
2798 2 * RTE_ETHER_ADDR_LEN, olx);
2799 pdst += 2 * RTE_ETHER_ADDR_LEN;
2800 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2801 ((RTE_ETHER_TYPE_VLAN << 16) |
2802 loc->mbuf->vlan_tci);
2803 pdst += sizeof(struct rte_vlan_hdr);
2804 tlen += 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2806 MLX5_ASSERT(pdst < (uint8_t *)txq->wqes_end);
2808 * The WQEBB space availability is checked by caller.
2809 * Here we should be aware of WQE ring buffer wraparound only.
2811 part = (uint8_t *)txq->wqes_end - pdst;
2812 part = RTE_MIN(part, inlen - tlen);
2818 * Copying may be interrupted inside the routine
2819 * if run into no inline hint flag.
2821 copy = tlen >= txq->inlen_mode ? 0 : (txq->inlen_mode - tlen);
2822 copy = mlx5_tx_mseg_memcpy(pdst, loc, part, copy, olx);
2824 if (likely(inlen <= tlen) || copy < part) {
2825 es->inline_hdr_sz = rte_cpu_to_be_16(tlen);
2827 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2828 return (struct mlx5_wqe_dseg *)pdst;
2830 pdst = (uint8_t *)txq->wqes;
2831 part = inlen - tlen;
2836 * Build the Data Segment of pointer type.
2839 * Pointer to TX queue structure.
2841 * Pointer to burst routine local context.
2843 * Pointer to WQE to fill with built Data Segment.
2845 * Data buffer to point.
2847 * Data buffer length.
2849 * Configured Tx offloads mask. It is fully defined at
2850 * compile time and may be used for optimization.
2852 static __rte_always_inline void
2853 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2854 struct mlx5_txq_local *restrict loc,
2855 struct mlx5_wqe_dseg *restrict dseg,
2858 unsigned int olx __rte_unused)
2862 dseg->bcount = rte_cpu_to_be_32(len);
2863 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2864 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2868 * Build the Data Segment of pointer type or inline
2869 * if data length is less than buffer in minimal
2870 * Data Segment size.
2873 * Pointer to TX queue structure.
2875 * Pointer to burst routine local context.
2877 * Pointer to WQE to fill with built Data Segment.
2879 * Data buffer to point.
2881 * Data buffer length.
2883 * Configured Tx offloads mask. It is fully defined at
2884 * compile time and may be used for optimization.
2886 static __rte_always_inline void
2887 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2888 struct mlx5_txq_local *restrict loc,
2889 struct mlx5_wqe_dseg *restrict dseg,
2892 unsigned int olx __rte_unused)
2898 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2899 dseg->bcount = rte_cpu_to_be_32(len);
2900 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2901 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2905 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2906 /* Unrolled implementation of generic rte_memcpy. */
2907 dst = (uintptr_t)&dseg->inline_data[0];
2908 src = (uintptr_t)buf;
2910 #ifdef RTE_ARCH_STRICT_ALIGN
2911 MLX5_ASSERT(dst == RTE_PTR_ALIGN(dst, sizeof(uint32_t)));
2912 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2913 dst += sizeof(uint32_t);
2914 src += sizeof(uint32_t);
2915 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2916 dst += sizeof(uint32_t);
2917 src += sizeof(uint32_t);
2919 *(uint64_t *)dst = *(unaligned_uint64_t *)src;
2920 dst += sizeof(uint64_t);
2921 src += sizeof(uint64_t);
2925 *(uint32_t *)dst = *(unaligned_uint32_t *)src;
2926 dst += sizeof(uint32_t);
2927 src += sizeof(uint32_t);
2930 *(uint16_t *)dst = *(unaligned_uint16_t *)src;
2931 dst += sizeof(uint16_t);
2932 src += sizeof(uint16_t);
2935 *(uint8_t *)dst = *(uint8_t *)src;
2939 * Build the Data Segment of inlined data from single
2940 * segment packet, no VLAN insertion.
2943 * Pointer to TX queue structure.
2945 * Pointer to burst routine local context.
2947 * Pointer to WQE to fill with built Data Segment.
2949 * Data buffer to point.
2951 * Data buffer length.
2953 * Configured Tx offloads mask. It is fully defined at
2954 * compile time and may be used for optimization.
2957 * Pointer to the next Data Segment after inlined data.
2958 * Ring buffer wraparound check is needed. We do not
2959 * do it here because it may not be needed for the
2960 * last packet in the eMPW session.
2962 static __rte_always_inline struct mlx5_wqe_dseg *
2963 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2964 struct mlx5_txq_local *restrict loc __rte_unused,
2965 struct mlx5_wqe_dseg *restrict dseg,
2968 unsigned int olx __rte_unused)
2973 if (!MLX5_TXOFF_CONFIG(MPW)) {
2974 /* Store the descriptor byte counter for eMPW sessions. */
2975 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2976 pdst = &dseg->inline_data[0];
2978 /* The entire legacy MPW session counter is stored on close. */
2979 pdst = (uint8_t *)dseg;
2982 * The WQEBB space availability is checked by caller.
2983 * Here we should be aware of WQE ring buffer wraparound only.
2985 part = (uint8_t *)txq->wqes_end - pdst;
2986 part = RTE_MIN(part, len);
2988 rte_memcpy(pdst, buf, part);
2992 if (!MLX5_TXOFF_CONFIG(MPW))
2993 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2994 /* Note: no final wraparound check here. */
2995 return (struct mlx5_wqe_dseg *)pdst;
2997 pdst = (uint8_t *)txq->wqes;
3004 * Build the Data Segment of inlined data from single
3005 * segment packet with VLAN insertion.
3008 * Pointer to TX queue structure.
3010 * Pointer to burst routine local context.
3012 * Pointer to the dseg fill with built Data Segment.
3014 * Data buffer to point.
3016 * Data buffer length.
3018 * Configured Tx offloads mask. It is fully defined at
3019 * compile time and may be used for optimization.
3022 * Pointer to the next Data Segment after inlined data.
3023 * Ring buffer wraparound check is needed.
3025 static __rte_always_inline struct mlx5_wqe_dseg *
3026 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
3027 struct mlx5_txq_local *restrict loc __rte_unused,
3028 struct mlx5_wqe_dseg *restrict dseg,
3031 unsigned int olx __rte_unused)
3037 MLX5_ASSERT(len > MLX5_ESEG_MIN_INLINE_SIZE);
3038 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
3039 (2 * RTE_ETHER_ADDR_LEN),
3040 "invalid Data Segment data size");
3041 if (!MLX5_TXOFF_CONFIG(MPW)) {
3042 /* Store the descriptor byte counter for eMPW sessions. */
3043 dseg->bcount = rte_cpu_to_be_32
3044 ((len + sizeof(struct rte_vlan_hdr)) |
3045 MLX5_ETH_WQE_DATA_INLINE);
3046 pdst = &dseg->inline_data[0];
3048 /* The entire legacy MPW session counter is stored on close. */
3049 pdst = (uint8_t *)dseg;
3051 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
3052 buf += MLX5_DSEG_MIN_INLINE_SIZE;
3053 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
3054 len -= MLX5_DSEG_MIN_INLINE_SIZE;
3055 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
3056 MLX5_ASSERT(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
3057 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
3058 pdst = (uint8_t *)txq->wqes;
3059 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
3060 loc->mbuf->vlan_tci);
3061 pdst += sizeof(struct rte_vlan_hdr);
3063 * The WQEBB space availability is checked by caller.
3064 * Here we should be aware of WQE ring buffer wraparound only.
3066 part = (uint8_t *)txq->wqes_end - pdst;
3067 part = RTE_MIN(part, len);
3069 rte_memcpy(pdst, buf, part);
3073 if (!MLX5_TXOFF_CONFIG(MPW))
3074 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
3075 /* Note: no final wraparound check here. */
3076 return (struct mlx5_wqe_dseg *)pdst;
3078 pdst = (uint8_t *)txq->wqes;
3085 * Build the Ethernet Segment with optionally inlined data with
3086 * VLAN insertion and following Data Segments (if any) from
3087 * multi-segment packet. Used by ordinary send and TSO.
3090 * Pointer to TX queue structure.
3092 * Pointer to burst routine local context.
3094 * Pointer to WQE to fill with built Ethernet/Data Segments.
3096 * Length of VLAN header to insert, 0 means no VLAN insertion.
3098 * Data length to inline. For TSO this parameter specifies
3099 * exact value, for ordinary send routine can be aligned by
3100 * caller to provide better WQE space saving and data buffer
3101 * start address alignment. This length includes VLAN header
3104 * Zero means ordinary send, inlined data can be extended,
3105 * otherwise this is TSO, inlined data length is fixed.
3107 * Configured Tx offloads mask. It is fully defined at
3108 * compile time and may be used for optimization.
3111 * Actual size of built WQE in segments.
3113 static __rte_always_inline unsigned int
3114 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
3115 struct mlx5_txq_local *restrict loc,
3116 struct mlx5_wqe *restrict wqe,
3120 unsigned int olx __rte_unused)
3122 struct mlx5_wqe_dseg *restrict dseg;
3125 MLX5_ASSERT((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
3126 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
3129 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
3130 if (!loc->mbuf_nseg)
3133 * There are still some mbuf remaining, not inlined.
3134 * The first mbuf may be partially inlined and we
3135 * must process the possible non-zero data offset.
3137 if (loc->mbuf_off) {
3142 * Exhausted packets must be dropped before.
3143 * Non-zero offset means there are some data
3144 * remained in the packet.
3146 MLX5_ASSERT(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
3147 MLX5_ASSERT(rte_pktmbuf_data_len(loc->mbuf));
3148 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
3150 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
3152 * Build the pointer/minimal data Data Segment.
3153 * Do ring buffer wrapping check in advance.
3155 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3156 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3157 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
3158 /* Store the mbuf to be freed on completion. */
3159 MLX5_ASSERT(loc->elts_free);
3160 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3163 if (--loc->mbuf_nseg == 0)
3165 loc->mbuf = loc->mbuf->next;
3169 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3170 struct rte_mbuf *mbuf;
3172 /* Zero length segment found, just skip. */
3174 loc->mbuf = loc->mbuf->next;
3175 rte_pktmbuf_free_seg(mbuf);
3176 if (--loc->mbuf_nseg == 0)
3179 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3180 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3183 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3184 rte_pktmbuf_data_len(loc->mbuf), olx);
3185 MLX5_ASSERT(loc->elts_free);
3186 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3189 if (--loc->mbuf_nseg == 0)
3191 loc->mbuf = loc->mbuf->next;
3196 /* Calculate actual segments used from the dseg pointer. */
3197 if ((uintptr_t)wqe < (uintptr_t)dseg)
3198 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3200 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3201 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3206 * Tx one packet function for multi-segment TSO. Supports all
3207 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3208 * sends one packet per WQE.
3210 * This routine is responsible for storing processed mbuf
3211 * into elts ring buffer and update elts_head.
3214 * Pointer to TX queue structure.
3216 * Pointer to burst routine local context.
3218 * Configured Tx offloads mask. It is fully defined at
3219 * compile time and may be used for optimization.
3222 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3223 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3224 * Local context variables partially updated.
3226 static __rte_always_inline enum mlx5_txcmp_code
3227 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3228 struct mlx5_txq_local *restrict loc,
3231 struct mlx5_wqe *restrict wqe;
3232 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3235 * Calculate data length to be inlined to estimate
3236 * the required space in WQE ring buffer.
3238 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3239 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3240 vlan = sizeof(struct rte_vlan_hdr);
3241 inlen = loc->mbuf->l2_len + vlan +
3242 loc->mbuf->l3_len + loc->mbuf->l4_len;
3243 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3244 return MLX5_TXCMP_CODE_ERROR;
3245 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3246 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3247 /* Packet must contain all TSO headers. */
3248 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3249 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3250 inlen > (dlen + vlan)))
3251 return MLX5_TXCMP_CODE_ERROR;
3252 MLX5_ASSERT(inlen >= txq->inlen_mode);
3254 * Check whether there are enough free WQEBBs:
3256 * - Ethernet Segment
3257 * - First Segment of inlined Ethernet data
3258 * - ... data continued ...
3259 * - Data Segments of pointer/min inline type
3261 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3262 MLX5_ESEG_MIN_INLINE_SIZE +
3264 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3265 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3266 return MLX5_TXCMP_CODE_EXIT;
3267 /* Check for maximal WQE size. */
3268 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3269 return MLX5_TXCMP_CODE_ERROR;
3270 #ifdef MLX5_PMD_SOFT_COUNTERS
3271 /* Update sent data bytes/packets counters. */
3272 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3273 loc->mbuf->tso_segsz;
3275 * One will be added for mbuf itself
3276 * at the end of the mlx5_tx_burst from
3277 * loc->pkts_sent field.
3280 txq->stats.opackets += ntcp;
3281 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3283 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3284 loc->wqe_last = wqe;
3285 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3286 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3287 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3288 txq->wqe_ci += (ds + 3) / 4;
3289 loc->wqe_free -= (ds + 3) / 4;
3290 return MLX5_TXCMP_CODE_MULTI;
3294 * Tx one packet function for multi-segment SEND. Supports all
3295 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3296 * sends one packet per WQE, without any data inlining in
3299 * This routine is responsible for storing processed mbuf
3300 * into elts ring buffer and update elts_head.
3303 * Pointer to TX queue structure.
3305 * Pointer to burst routine local context.
3307 * Configured Tx offloads mask. It is fully defined at
3308 * compile time and may be used for optimization.
3311 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3312 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3313 * Local context variables partially updated.
3315 static __rte_always_inline enum mlx5_txcmp_code
3316 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3317 struct mlx5_txq_local *restrict loc,
3320 struct mlx5_wqe_dseg *restrict dseg;
3321 struct mlx5_wqe *restrict wqe;
3322 unsigned int ds, nseg;
3324 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3326 * No inline at all, it means the CPU cycles saving
3327 * is prioritized at configuration, we should not
3328 * copy any packet data to WQE.
3330 nseg = NB_SEGS(loc->mbuf);
3332 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3333 return MLX5_TXCMP_CODE_EXIT;
3334 /* Check for maximal WQE size. */
3335 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3336 return MLX5_TXCMP_CODE_ERROR;
3338 * Some Tx offloads may cause an error if
3339 * packet is not long enough, check against
3340 * assumed minimal length.
3342 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3343 return MLX5_TXCMP_CODE_ERROR;
3344 #ifdef MLX5_PMD_SOFT_COUNTERS
3345 /* Update sent data bytes counter. */
3346 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3347 if (MLX5_TXOFF_CONFIG(VLAN) &&
3348 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3349 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3352 * SEND WQE, one WQEBB:
3353 * - Control Segment, SEND opcode
3354 * - Ethernet Segment, optional VLAN, no inline
3355 * - Data Segments, pointer only type
3357 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3358 loc->wqe_last = wqe;
3359 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3360 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3361 dseg = &wqe->dseg[0];
3363 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3364 struct rte_mbuf *mbuf;
3367 * Zero length segment found, have to
3368 * correct total size of WQE in segments.
3369 * It is supposed to be rare occasion, so
3370 * in normal case (no zero length segments)
3371 * we avoid extra writing to the Control
3375 wqe->cseg.sq_ds -= RTE_BE32(1);
3377 loc->mbuf = mbuf->next;
3378 rte_pktmbuf_free_seg(mbuf);
3384 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3385 rte_pktmbuf_data_len(loc->mbuf), olx);
3386 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3391 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3392 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3393 loc->mbuf = loc->mbuf->next;
3396 txq->wqe_ci += (ds + 3) / 4;
3397 loc->wqe_free -= (ds + 3) / 4;
3398 return MLX5_TXCMP_CODE_MULTI;
3402 * Tx one packet function for multi-segment SEND. Supports all
3403 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3404 * sends one packet per WQE, with data inlining in
3405 * Ethernet Segment and minimal Data Segments.
3407 * This routine is responsible for storing processed mbuf
3408 * into elts ring buffer and update elts_head.
3411 * Pointer to TX queue structure.
3413 * Pointer to burst routine local context.
3415 * Configured Tx offloads mask. It is fully defined at
3416 * compile time and may be used for optimization.
3419 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3420 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3421 * Local context variables partially updated.
3423 static __rte_always_inline enum mlx5_txcmp_code
3424 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3425 struct mlx5_txq_local *restrict loc,
3428 struct mlx5_wqe *restrict wqe;
3429 unsigned int ds, inlen, dlen, vlan = 0;
3431 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3432 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3434 * First calculate data length to be inlined
3435 * to estimate the required space for WQE.
3437 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3438 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3439 vlan = sizeof(struct rte_vlan_hdr);
3440 inlen = dlen + vlan;
3441 /* Check against minimal length. */
3442 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3443 return MLX5_TXCMP_CODE_ERROR;
3444 MLX5_ASSERT(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3445 if (inlen > txq->inlen_send ||
3446 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE) {
3447 struct rte_mbuf *mbuf;
3452 * Packet length exceeds the allowed inline
3453 * data length, check whether the minimal
3454 * inlining is required.
3456 if (txq->inlen_mode) {
3457 MLX5_ASSERT(txq->inlen_mode >=
3458 MLX5_ESEG_MIN_INLINE_SIZE);
3459 MLX5_ASSERT(txq->inlen_mode <= txq->inlen_send);
3460 inlen = txq->inlen_mode;
3462 if (loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE ||
3463 !vlan || txq->vlan_en) {
3465 * VLAN insertion will be done inside by HW.
3466 * It is not utmost effective - VLAN flag is
3467 * checked twice, but we should proceed the
3468 * inlining length correctly and take into
3469 * account the VLAN header being inserted.
3471 return mlx5_tx_packet_multi_send
3474 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3477 * Now we know the minimal amount of data is requested
3478 * to inline. Check whether we should inline the buffers
3479 * from the chain beginning to eliminate some mbufs.
3482 nxlen = rte_pktmbuf_data_len(mbuf);
3483 if (unlikely(nxlen <= txq->inlen_send)) {
3484 /* We can inline first mbuf at least. */
3485 if (nxlen < inlen) {
3488 /* Scan mbufs till inlen filled. */
3493 nxlen = rte_pktmbuf_data_len(mbuf);
3495 } while (unlikely(nxlen < inlen));
3496 if (unlikely(nxlen > txq->inlen_send)) {
3497 /* We cannot inline entire mbuf. */
3498 smlen = inlen - smlen;
3499 start = rte_pktmbuf_mtod_offset
3500 (mbuf, uintptr_t, smlen);
3507 /* There should be not end of packet. */
3509 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3510 } while (unlikely(nxlen < txq->inlen_send));
3512 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3514 * Check whether we can do inline to align start
3515 * address of data buffer to cacheline.
3518 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3519 if (unlikely(start)) {
3521 if (start <= txq->inlen_send)
3526 * Check whether there are enough free WQEBBs:
3528 * - Ethernet Segment
3529 * - First Segment of inlined Ethernet data
3530 * - ... data continued ...
3531 * - Data Segments of pointer/min inline type
3533 * Estimate the number of Data Segments conservatively,
3534 * supposing no any mbufs is being freed during inlining.
3536 MLX5_ASSERT(inlen <= txq->inlen_send);
3537 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3538 MLX5_ESEG_MIN_INLINE_SIZE +
3540 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3541 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3542 return MLX5_TXCMP_CODE_EXIT;
3543 /* Check for maximal WQE size. */
3544 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3545 return MLX5_TXCMP_CODE_ERROR;
3546 #ifdef MLX5_PMD_SOFT_COUNTERS
3547 /* Update sent data bytes/packets counters. */
3548 txq->stats.obytes += dlen + vlan;
3550 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3551 loc->wqe_last = wqe;
3552 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3553 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3554 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3555 txq->wqe_ci += (ds + 3) / 4;
3556 loc->wqe_free -= (ds + 3) / 4;
3557 return MLX5_TXCMP_CODE_MULTI;
3561 * Tx burst function for multi-segment packets. Supports all
3562 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3563 * sends one packet per WQE. Function stops sending if it
3564 * encounters the single-segment packet.
3566 * This routine is responsible for storing processed mbuf
3567 * into elts ring buffer and update elts_head.
3570 * Pointer to TX queue structure.
3572 * Packets to transmit.
3574 * Number of packets in array.
3576 * Pointer to burst routine local context.
3578 * Configured Tx offloads mask. It is fully defined at
3579 * compile time and may be used for optimization.
3582 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3583 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3584 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3585 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3586 * Local context variables updated.
3588 static __rte_always_inline enum mlx5_txcmp_code
3589 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3590 struct rte_mbuf **restrict pkts,
3591 unsigned int pkts_n,
3592 struct mlx5_txq_local *restrict loc,
3595 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3596 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3597 pkts += loc->pkts_sent + 1;
3598 pkts_n -= loc->pkts_sent;
3600 enum mlx5_txcmp_code ret;
3602 MLX5_ASSERT(NB_SEGS(loc->mbuf) > 1);
3604 * Estimate the number of free elts quickly but
3605 * conservatively. Some segment may be fully inlined
3606 * and freed, ignore this here - precise estimation
3609 if (loc->elts_free < NB_SEGS(loc->mbuf))
3610 return MLX5_TXCMP_CODE_EXIT;
3611 if (MLX5_TXOFF_CONFIG(TSO) &&
3612 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3613 /* Proceed with multi-segment TSO. */
3614 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3615 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3616 /* Proceed with multi-segment SEND with inlining. */
3617 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3619 /* Proceed with multi-segment SEND w/o inlining. */
3620 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3622 if (ret == MLX5_TXCMP_CODE_EXIT)
3623 return MLX5_TXCMP_CODE_EXIT;
3624 if (ret == MLX5_TXCMP_CODE_ERROR)
3625 return MLX5_TXCMP_CODE_ERROR;
3626 /* WQE is built, go to the next packet. */
3629 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3630 return MLX5_TXCMP_CODE_EXIT;
3631 loc->mbuf = *pkts++;
3633 rte_prefetch0(*pkts);
3634 if (likely(NB_SEGS(loc->mbuf) > 1))
3636 /* Here ends the series of multi-segment packets. */
3637 if (MLX5_TXOFF_CONFIG(TSO) &&
3638 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3639 return MLX5_TXCMP_CODE_TSO;
3640 return MLX5_TXCMP_CODE_SINGLE;
3646 * Tx burst function for single-segment packets with TSO.
3647 * Supports all types of Tx offloads, except multi-packets.
3648 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3649 * Function stops sending if it encounters the multi-segment
3650 * packet or packet without TSO requested.
3652 * The routine is responsible for storing processed mbuf
3653 * into elts ring buffer and update elts_head if inline
3654 * offloads is requested due to possible early freeing
3655 * of the inlined mbufs (can not store pkts array in elts
3659 * Pointer to TX queue structure.
3661 * Packets to transmit.
3663 * Number of packets in array.
3665 * Pointer to burst routine local context.
3667 * Configured Tx offloads mask. It is fully defined at
3668 * compile time and may be used for optimization.
3671 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3672 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3673 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3674 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3675 * Local context variables updated.
3677 static __rte_always_inline enum mlx5_txcmp_code
3678 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3679 struct rte_mbuf **restrict pkts,
3680 unsigned int pkts_n,
3681 struct mlx5_txq_local *restrict loc,
3684 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
3685 MLX5_ASSERT(pkts_n > loc->pkts_sent);
3686 pkts += loc->pkts_sent + 1;
3687 pkts_n -= loc->pkts_sent;
3689 struct mlx5_wqe_dseg *restrict dseg;
3690 struct mlx5_wqe *restrict wqe;
3691 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3694 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
3695 dlen = rte_pktmbuf_data_len(loc->mbuf);
3696 if (MLX5_TXOFF_CONFIG(VLAN) &&
3697 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3698 vlan = sizeof(struct rte_vlan_hdr);
3701 * First calculate the WQE size to check
3702 * whether we have enough space in ring buffer.
3704 hlen = loc->mbuf->l2_len + vlan +
3705 loc->mbuf->l3_len + loc->mbuf->l4_len;
3706 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3707 return MLX5_TXCMP_CODE_ERROR;
3708 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3709 hlen += loc->mbuf->outer_l2_len +
3710 loc->mbuf->outer_l3_len;
3711 /* Segment must contain all TSO headers. */
3712 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3713 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3714 hlen > (dlen + vlan)))
3715 return MLX5_TXCMP_CODE_ERROR;
3717 * Check whether there are enough free WQEBBs:
3719 * - Ethernet Segment
3720 * - First Segment of inlined Ethernet data
3721 * - ... data continued ...
3722 * - Finishing Data Segment of pointer type
3724 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3725 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3726 if (loc->wqe_free < ((ds + 3) / 4))
3727 return MLX5_TXCMP_CODE_EXIT;
3728 #ifdef MLX5_PMD_SOFT_COUNTERS
3729 /* Update sent data bytes/packets counters. */
3730 ntcp = (dlen + vlan - hlen +
3731 loc->mbuf->tso_segsz - 1) /
3732 loc->mbuf->tso_segsz;
3734 * One will be added for mbuf itself at the end
3735 * of the mlx5_tx_burst from loc->pkts_sent field.
3738 txq->stats.opackets += ntcp;
3739 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3742 * Build the TSO WQE:
3744 * - Ethernet Segment with hlen bytes inlined
3745 * - Data Segment of pointer type
3747 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3748 loc->wqe_last = wqe;
3749 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3750 MLX5_OPCODE_TSO, olx);
3751 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3752 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3753 dlen -= hlen - vlan;
3754 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3756 * WQE is built, update the loop parameters
3757 * and go to the next packet.
3759 txq->wqe_ci += (ds + 3) / 4;
3760 loc->wqe_free -= (ds + 3) / 4;
3761 if (MLX5_TXOFF_CONFIG(INLINE))
3762 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3766 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3767 return MLX5_TXCMP_CODE_EXIT;
3768 loc->mbuf = *pkts++;
3770 rte_prefetch0(*pkts);
3771 if (MLX5_TXOFF_CONFIG(MULTI) &&
3772 unlikely(NB_SEGS(loc->mbuf) > 1))
3773 return MLX5_TXCMP_CODE_MULTI;
3774 if (likely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3775 return MLX5_TXCMP_CODE_SINGLE;
3776 /* Continue with the next TSO packet. */
3782 * Analyze the packet and select the best method to send.
3785 * Pointer to TX queue structure.
3787 * Pointer to burst routine local context.
3789 * Configured Tx offloads mask. It is fully defined at
3790 * compile time and may be used for optimization.
3792 * The predefined flag whether do complete check for
3793 * multi-segment packets and TSO.
3796 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3797 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3798 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3799 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3801 static __rte_always_inline enum mlx5_txcmp_code
3802 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3803 struct mlx5_txq_local *restrict loc,
3807 /* Check for multi-segment packet. */
3809 MLX5_TXOFF_CONFIG(MULTI) &&
3810 unlikely(NB_SEGS(loc->mbuf) > 1))
3811 return MLX5_TXCMP_CODE_MULTI;
3812 /* Check for TSO packet. */
3814 MLX5_TXOFF_CONFIG(TSO) &&
3815 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3816 return MLX5_TXCMP_CODE_TSO;
3817 /* Check if eMPW is enabled at all. */
3818 if (!MLX5_TXOFF_CONFIG(EMPW))
3819 return MLX5_TXCMP_CODE_SINGLE;
3820 /* Check if eMPW can be engaged. */
3821 if (MLX5_TXOFF_CONFIG(VLAN) &&
3822 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3823 (!MLX5_TXOFF_CONFIG(INLINE) ||
3824 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3825 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3827 * eMPW does not support VLAN insertion offload,
3828 * we have to inline the entire packet but
3829 * packet is too long for inlining.
3831 return MLX5_TXCMP_CODE_SINGLE;
3833 return MLX5_TXCMP_CODE_EMPW;
3837 * Check the next packet attributes to match with the eMPW batch ones.
3838 * In addition, for legacy MPW the packet length is checked either.
3841 * Pointer to TX queue structure.
3843 * Pointer to Ethernet Segment of eMPW batch.
3845 * Pointer to burst routine local context.
3847 * Length of previous packet in MPW descriptor.
3849 * Configured Tx offloads mask. It is fully defined at
3850 * compile time and may be used for optimization.
3853 * true - packet match with eMPW batch attributes.
3854 * false - no match, eMPW should be restarted.
3856 static __rte_always_inline bool
3857 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3858 struct mlx5_wqe_eseg *restrict es,
3859 struct mlx5_txq_local *restrict loc,
3863 uint8_t swp_flags = 0;
3865 /* Compare the checksum flags, if any. */
3866 if (MLX5_TXOFF_CONFIG(CSUM) &&
3867 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3869 /* Compare the Software Parser offsets and flags. */
3870 if (MLX5_TXOFF_CONFIG(SWP) &&
3871 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3872 es->swp_flags != swp_flags))
3874 /* Fill metadata field if needed. */
3875 if (MLX5_TXOFF_CONFIG(METADATA) &&
3876 es->metadata != (loc->mbuf->ol_flags & PKT_TX_DYNF_METADATA ?
3877 *RTE_FLOW_DYNF_METADATA(loc->mbuf) : 0))
3879 /* Legacy MPW can send packets with the same lengt only. */
3880 if (MLX5_TXOFF_CONFIG(MPW) &&
3881 dlen != rte_pktmbuf_data_len(loc->mbuf))
3883 /* There must be no VLAN packets in eMPW loop. */
3884 if (MLX5_TXOFF_CONFIG(VLAN))
3885 MLX5_ASSERT(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3890 * Update send loop variables and WQE for eMPW loop
3891 * without data inlining. Number of Data Segments is
3892 * equal to the number of sent packets.
3895 * Pointer to TX queue structure.
3897 * Pointer to burst routine local context.
3899 * Number of packets/Data Segments/Packets.
3901 * Accumulated statistics, bytes sent
3903 * Configured Tx offloads mask. It is fully defined at
3904 * compile time and may be used for optimization.
3907 * true - packet match with eMPW batch attributes.
3908 * false - no match, eMPW should be restarted.
3910 static __rte_always_inline void
3911 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3912 struct mlx5_txq_local *restrict loc,
3915 unsigned int olx __rte_unused)
3917 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
3918 #ifdef MLX5_PMD_SOFT_COUNTERS
3919 /* Update sent data bytes counter. */
3920 txq->stats.obytes += slen;
3924 loc->elts_free -= ds;
3925 loc->pkts_sent += ds;
3927 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3928 txq->wqe_ci += (ds + 3) / 4;
3929 loc->wqe_free -= (ds + 3) / 4;
3933 * Update send loop variables and WQE for eMPW loop
3934 * with data inlining. Gets the size of pushed descriptors
3935 * and data to the WQE.
3938 * Pointer to TX queue structure.
3940 * Pointer to burst routine local context.
3942 * Total size of descriptor/data in bytes.
3944 * Accumulated statistics, data bytes sent.
3946 * The base WQE for the eMPW/MPW descriptor.
3948 * Configured Tx offloads mask. It is fully defined at
3949 * compile time and may be used for optimization.
3952 * true - packet match with eMPW batch attributes.
3953 * false - no match, eMPW should be restarted.
3955 static __rte_always_inline void
3956 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3957 struct mlx5_txq_local *restrict loc,
3960 struct mlx5_wqe *restrict wqem,
3961 unsigned int olx __rte_unused)
3963 struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
3965 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
3966 #ifdef MLX5_PMD_SOFT_COUNTERS
3967 /* Update sent data bytes counter. */
3968 txq->stats.obytes += slen;
3972 if (MLX5_TXOFF_CONFIG(MPW) && dseg->bcount == RTE_BE32(0)) {
3974 * If the legacy MPW session contains the inline packets
3975 * we should set the only inline data segment length
3976 * and align the total length to the segment size.
3978 MLX5_ASSERT(len > sizeof(dseg->bcount));
3979 dseg->bcount = rte_cpu_to_be_32((len - sizeof(dseg->bcount)) |
3980 MLX5_ETH_WQE_DATA_INLINE);
3981 len = (len + MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE + 2;
3984 * The session is not legacy MPW or contains the
3985 * data buffer pointer segments.
3987 MLX5_ASSERT((len % MLX5_WSEG_SIZE) == 0);
3988 len = len / MLX5_WSEG_SIZE + 2;
3990 wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3991 txq->wqe_ci += (len + 3) / 4;
3992 loc->wqe_free -= (len + 3) / 4;
3993 loc->wqe_last = wqem;
3997 * The set of Tx burst functions for single-segment packets
3998 * without TSO and with Multi-Packet Writing feature support.
3999 * Supports all types of Tx offloads, except multi-packets
4002 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
4003 * as many packet per WQE as it can. If eMPW is not configured
4004 * or packet can not be sent with eMPW (VLAN insertion) the
4005 * ordinary SEND opcode is used and only one packet placed
4008 * Functions stop sending if it encounters the multi-segment
4009 * packet or packet with TSO requested.
4011 * The routines are responsible for storing processed mbuf
4012 * into elts ring buffer and update elts_head if inlining
4013 * offload is requested. Otherwise the copying mbufs to elts
4014 * can be postponed and completed at the end of burst routine.
4017 * Pointer to TX queue structure.
4019 * Packets to transmit.
4021 * Number of packets in array.
4023 * Pointer to burst routine local context.
4025 * Configured Tx offloads mask. It is fully defined at
4026 * compile time and may be used for optimization.
4029 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
4030 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
4031 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
4032 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
4033 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
4034 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
4036 * Local context variables updated.
4039 * The routine sends packets with MLX5_OPCODE_EMPW
4040 * without inlining, this is dedicated optimized branch.
4041 * No VLAN insertion is supported.
4043 static __rte_always_inline enum mlx5_txcmp_code
4044 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
4045 struct rte_mbuf **restrict pkts,
4046 unsigned int pkts_n,
4047 struct mlx5_txq_local *restrict loc,
4051 * Subroutine is the part of mlx5_tx_burst_single()
4052 * and sends single-segment packet with eMPW opcode
4053 * without data inlining.
4055 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4056 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4057 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4058 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4059 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4060 pkts += loc->pkts_sent + 1;
4061 pkts_n -= loc->pkts_sent;
4063 struct mlx5_wqe_dseg *restrict dseg;
4064 struct mlx5_wqe_eseg *restrict eseg;
4065 enum mlx5_txcmp_code ret;
4066 unsigned int part, loop;
4067 unsigned int slen = 0;
4070 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4071 part = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4072 MLX5_MPW_MAX_PACKETS :
4073 MLX5_EMPW_MAX_PACKETS);
4074 if (unlikely(loc->elts_free < part)) {
4075 /* We have no enough elts to save all mbufs. */
4076 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
4077 return MLX5_TXCMP_CODE_EXIT;
4078 /* But we still able to send at least minimal eMPW. */
4079 part = loc->elts_free;
4081 /* Check whether we have enough WQEs */
4082 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
4083 if (unlikely(loc->wqe_free <
4084 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4085 return MLX5_TXCMP_CODE_EXIT;
4086 part = (loc->wqe_free * 4) - 2;
4088 if (likely(part > 1))
4089 rte_prefetch0(*pkts);
4090 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4092 * Build eMPW title WQEBB:
4093 * - Control Segment, eMPW opcode
4094 * - Ethernet Segment, no inline
4096 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
4097 MLX5_OPCODE_ENHANCED_MPSW, olx);
4098 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4099 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4100 eseg = &loc->wqe_last->eseg;
4101 dseg = &loc->wqe_last->dseg[0];
4103 /* Store the packet length for legacy MPW. */
4104 if (MLX5_TXOFF_CONFIG(MPW))
4105 eseg->mss = rte_cpu_to_be_16
4106 (rte_pktmbuf_data_len(loc->mbuf));
4108 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4109 #ifdef MLX5_PMD_SOFT_COUNTERS
4110 /* Update sent data bytes counter. */
4115 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4117 if (unlikely(--loop == 0))
4119 loc->mbuf = *pkts++;
4120 if (likely(loop > 1))
4121 rte_prefetch0(*pkts);
4122 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4124 * Unroll the completion code to avoid
4125 * returning variable value - it results in
4126 * unoptimized sequent checking in caller.
4128 if (ret == MLX5_TXCMP_CODE_MULTI) {
4130 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4131 if (unlikely(!loc->elts_free ||
4133 return MLX5_TXCMP_CODE_EXIT;
4134 return MLX5_TXCMP_CODE_MULTI;
4136 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4137 if (ret == MLX5_TXCMP_CODE_TSO) {
4139 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4140 if (unlikely(!loc->elts_free ||
4142 return MLX5_TXCMP_CODE_EXIT;
4143 return MLX5_TXCMP_CODE_TSO;
4145 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4147 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4148 if (unlikely(!loc->elts_free ||
4150 return MLX5_TXCMP_CODE_EXIT;
4151 return MLX5_TXCMP_CODE_SINGLE;
4153 if (ret != MLX5_TXCMP_CODE_EMPW) {
4156 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4157 return MLX5_TXCMP_CODE_ERROR;
4160 * Check whether packet parameters coincide
4161 * within assumed eMPW batch:
4162 * - check sum settings
4164 * - software parser settings
4165 * - packets length (legacy MPW only)
4167 if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx)) {
4170 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
4171 if (unlikely(!loc->elts_free ||
4173 return MLX5_TXCMP_CODE_EXIT;
4177 /* Packet attributes match, continue the same eMPW. */
4179 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4180 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4182 /* eMPW is built successfully, update loop parameters. */
4184 MLX5_ASSERT(pkts_n >= part);
4185 #ifdef MLX5_PMD_SOFT_COUNTERS
4186 /* Update sent data bytes counter. */
4187 txq->stats.obytes += slen;
4189 loc->elts_free -= part;
4190 loc->pkts_sent += part;
4191 txq->wqe_ci += (2 + part + 3) / 4;
4192 loc->wqe_free -= (2 + part + 3) / 4;
4194 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4195 return MLX5_TXCMP_CODE_EXIT;
4196 loc->mbuf = *pkts++;
4197 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4198 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
4200 /* Continue sending eMPW batches. */
4206 * The routine sends packets with MLX5_OPCODE_EMPW
4207 * with inlining, optionally supports VLAN insertion.
4209 static __rte_always_inline enum mlx5_txcmp_code
4210 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
4211 struct rte_mbuf **restrict pkts,
4212 unsigned int pkts_n,
4213 struct mlx5_txq_local *restrict loc,
4217 * Subroutine is the part of mlx5_tx_burst_single()
4218 * and sends single-segment packet with eMPW opcode
4219 * with data inlining.
4221 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4222 MLX5_ASSERT(MLX5_TXOFF_CONFIG(EMPW));
4223 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4224 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4225 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4226 pkts += loc->pkts_sent + 1;
4227 pkts_n -= loc->pkts_sent;
4229 struct mlx5_wqe_dseg *restrict dseg;
4230 struct mlx5_wqe *restrict wqem;
4231 enum mlx5_txcmp_code ret;
4232 unsigned int room, part, nlim;
4233 unsigned int slen = 0;
4235 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4237 * Limits the amount of packets in one WQE
4238 * to improve CQE latency generation.
4240 nlim = RTE_MIN(pkts_n, MLX5_TXOFF_CONFIG(MPW) ?
4241 MLX5_MPW_INLINE_MAX_PACKETS :
4242 MLX5_EMPW_MAX_PACKETS);
4243 /* Check whether we have minimal amount WQEs */
4244 if (unlikely(loc->wqe_free <
4245 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4246 return MLX5_TXCMP_CODE_EXIT;
4247 if (likely(pkts_n > 1))
4248 rte_prefetch0(*pkts);
4249 wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4251 * Build eMPW title WQEBB:
4252 * - Control Segment, eMPW opcode, zero DS
4253 * - Ethernet Segment, no inline
4255 mlx5_tx_cseg_init(txq, loc, wqem, 0,
4256 MLX5_OPCODE_ENHANCED_MPSW, olx);
4257 mlx5_tx_eseg_none(txq, loc, wqem,
4258 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4259 dseg = &wqem->dseg[0];
4260 /* Store the packet length for legacy MPW. */
4261 if (MLX5_TXOFF_CONFIG(MPW))
4262 wqem->eseg.mss = rte_cpu_to_be_16
4263 (rte_pktmbuf_data_len(loc->mbuf));
4264 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4265 loc->wqe_free) * MLX5_WQE_SIZE -
4266 MLX5_WQE_CSEG_SIZE -
4268 /* Limit the room for legacy MPW sessions for performance. */
4269 if (MLX5_TXOFF_CONFIG(MPW))
4270 room = RTE_MIN(room,
4271 RTE_MAX(txq->inlen_empw +
4272 sizeof(dseg->bcount) +
4273 (MLX5_TXOFF_CONFIG(VLAN) ?
4274 sizeof(struct rte_vlan_hdr) : 0),
4275 MLX5_MPW_INLINE_MAX_PACKETS *
4276 MLX5_WQE_DSEG_SIZE));
4277 /* Build WQE till we have space, packets and resources. */
4280 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4281 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4284 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4285 MLX5_ASSERT((room % MLX5_WQE_DSEG_SIZE) == 0);
4286 MLX5_ASSERT((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4288 * Some Tx offloads may cause an error if
4289 * packet is not long enough, check against
4290 * assumed minimal length.
4292 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4294 if (unlikely(!part))
4295 return MLX5_TXCMP_CODE_ERROR;
4297 * We have some successfully built
4298 * packet Data Segments to send.
4300 mlx5_tx_idone_empw(txq, loc, part,
4302 return MLX5_TXCMP_CODE_ERROR;
4304 /* Inline or not inline - that's the Question. */
4305 if (dlen > txq->inlen_empw ||
4306 loc->mbuf->ol_flags & PKT_TX_DYNF_NOINLINE)
4308 if (MLX5_TXOFF_CONFIG(MPW)) {
4309 if (dlen > txq->inlen_send)
4313 /* Open new inline MPW session. */
4314 tlen += sizeof(dseg->bcount);
4315 dseg->bcount = RTE_BE32(0);
4317 (dseg, sizeof(dseg->bcount));
4320 * No pointer and inline descriptor
4321 * intermix for legacy MPW sessions.
4323 if (wqem->dseg[0].bcount)
4327 tlen = sizeof(dseg->bcount) + dlen;
4329 /* Inline entire packet, optional VLAN insertion. */
4330 if (MLX5_TXOFF_CONFIG(VLAN) &&
4331 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4333 * The packet length must be checked in
4334 * mlx5_tx_able_to_empw() and packet
4335 * fits into inline length guaranteed.
4338 sizeof(struct rte_vlan_hdr)) <=
4340 tlen += sizeof(struct rte_vlan_hdr);
4343 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4345 #ifdef MLX5_PMD_SOFT_COUNTERS
4346 /* Update sent data bytes counter. */
4347 slen += sizeof(struct rte_vlan_hdr);
4352 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4355 if (!MLX5_TXOFF_CONFIG(MPW))
4356 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4357 MLX5_ASSERT(room >= tlen);
4360 * Packet data are completely inlined,
4361 * free the packet immediately.
4363 rte_pktmbuf_free_seg(loc->mbuf);
4367 * No pointer and inline descriptor
4368 * intermix for legacy MPW sessions.
4370 if (MLX5_TXOFF_CONFIG(MPW) &&
4372 wqem->dseg[0].bcount == RTE_BE32(0))
4375 * Not inlinable VLAN packets are
4376 * proceeded outside of this routine.
4378 MLX5_ASSERT(room >= MLX5_WQE_DSEG_SIZE);
4379 if (MLX5_TXOFF_CONFIG(VLAN))
4380 MLX5_ASSERT(!(loc->mbuf->ol_flags &
4382 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4383 /* We have to store mbuf in elts.*/
4384 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4385 room -= MLX5_WQE_DSEG_SIZE;
4386 /* Ring buffer wraparound is checked at the loop end.*/
4389 #ifdef MLX5_PMD_SOFT_COUNTERS
4390 /* Update sent data bytes counter. */
4396 if (unlikely(!pkts_n || !loc->elts_free)) {
4398 * We have no resources/packets to
4399 * continue build descriptors.
4402 mlx5_tx_idone_empw(txq, loc, part,
4404 return MLX5_TXCMP_CODE_EXIT;
4406 loc->mbuf = *pkts++;
4407 if (likely(pkts_n > 1))
4408 rte_prefetch0(*pkts);
4409 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4411 * Unroll the completion code to avoid
4412 * returning variable value - it results in
4413 * unoptimized sequent checking in caller.
4415 if (ret == MLX5_TXCMP_CODE_MULTI) {
4417 mlx5_tx_idone_empw(txq, loc, part,
4419 if (unlikely(!loc->elts_free ||
4421 return MLX5_TXCMP_CODE_EXIT;
4422 return MLX5_TXCMP_CODE_MULTI;
4424 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4425 if (ret == MLX5_TXCMP_CODE_TSO) {
4427 mlx5_tx_idone_empw(txq, loc, part,
4429 if (unlikely(!loc->elts_free ||
4431 return MLX5_TXCMP_CODE_EXIT;
4432 return MLX5_TXCMP_CODE_TSO;
4434 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4436 mlx5_tx_idone_empw(txq, loc, part,
4438 if (unlikely(!loc->elts_free ||
4440 return MLX5_TXCMP_CODE_EXIT;
4441 return MLX5_TXCMP_CODE_SINGLE;
4443 if (ret != MLX5_TXCMP_CODE_EMPW) {
4446 mlx5_tx_idone_empw(txq, loc, part,
4448 return MLX5_TXCMP_CODE_ERROR;
4450 /* Check if we have minimal room left. */
4452 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4455 * Check whether packet parameters coincide
4456 * within assumed eMPW batch:
4457 * - check sum settings
4459 * - software parser settings
4460 * - packets length (legacy MPW only)
4462 if (!mlx5_tx_match_empw(txq, &wqem->eseg,
4465 /* Packet attributes match, continue the same eMPW. */
4466 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4467 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4470 * We get here to close an existing eMPW
4471 * session and start the new one.
4473 MLX5_ASSERT(pkts_n);
4475 if (unlikely(!part))
4476 return MLX5_TXCMP_CODE_EXIT;
4477 mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
4478 if (unlikely(!loc->elts_free ||
4480 return MLX5_TXCMP_CODE_EXIT;
4481 /* Continue the loop with new eMPW session. */
4487 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4488 * Data inlining and VLAN insertion are supported.
4490 static __rte_always_inline enum mlx5_txcmp_code
4491 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4492 struct rte_mbuf **restrict pkts,
4493 unsigned int pkts_n,
4494 struct mlx5_txq_local *restrict loc,
4498 * Subroutine is the part of mlx5_tx_burst_single()
4499 * and sends single-segment packet with SEND opcode.
4501 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4502 MLX5_ASSERT(pkts_n > loc->pkts_sent);
4503 pkts += loc->pkts_sent + 1;
4504 pkts_n -= loc->pkts_sent;
4506 struct mlx5_wqe *restrict wqe;
4507 enum mlx5_txcmp_code ret;
4509 MLX5_ASSERT(NB_SEGS(loc->mbuf) == 1);
4510 if (MLX5_TXOFF_CONFIG(INLINE)) {
4511 unsigned int inlen, vlan = 0;
4513 inlen = rte_pktmbuf_data_len(loc->mbuf);
4514 if (MLX5_TXOFF_CONFIG(VLAN) &&
4515 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4516 vlan = sizeof(struct rte_vlan_hdr);
4518 static_assert((sizeof(struct rte_vlan_hdr) +
4519 sizeof(struct rte_ether_hdr)) ==
4520 MLX5_ESEG_MIN_INLINE_SIZE,
4521 "invalid min inline data size");
4524 * If inlining is enabled at configuration time
4525 * the limit must be not less than minimal size.
4526 * Otherwise we would do extra check for data
4527 * size to avoid crashes due to length overflow.
4529 MLX5_ASSERT(txq->inlen_send >=
4530 MLX5_ESEG_MIN_INLINE_SIZE);
4531 if (inlen <= txq->inlen_send) {
4532 unsigned int seg_n, wqe_n;
4534 rte_prefetch0(rte_pktmbuf_mtod
4535 (loc->mbuf, uint8_t *));
4536 /* Check against minimal length. */
4537 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4538 return MLX5_TXCMP_CODE_ERROR;
4539 if (loc->mbuf->ol_flags &
4540 PKT_TX_DYNF_NOINLINE) {
4542 * The hint flag not to inline packet
4543 * data is set. Check whether we can
4546 if ((!MLX5_TXOFF_CONFIG(EMPW) &&
4548 (MLX5_TXOFF_CONFIG(MPW) &&
4551 * The hardware requires the
4552 * minimal inline data header.
4554 goto single_min_inline;
4556 if (MLX5_TXOFF_CONFIG(VLAN) &&
4557 vlan && !txq->vlan_en) {
4559 * We must insert VLAN tag
4560 * by software means.
4562 goto single_part_inline;
4564 goto single_no_inline;
4567 * Completely inlined packet data WQE:
4568 * - Control Segment, SEND opcode
4569 * - Ethernet Segment, no VLAN insertion
4570 * - Data inlined, VLAN optionally inserted
4571 * - Alignment to MLX5_WSEG_SIZE
4572 * Have to estimate amount of WQEBBs
4574 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4575 MLX5_ESEG_MIN_INLINE_SIZE +
4576 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4577 /* Check if there are enough WQEBBs. */
4578 wqe_n = (seg_n + 3) / 4;
4579 if (wqe_n > loc->wqe_free)
4580 return MLX5_TXCMP_CODE_EXIT;
4581 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4582 loc->wqe_last = wqe;
4583 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4584 MLX5_OPCODE_SEND, olx);
4585 mlx5_tx_eseg_data(txq, loc, wqe,
4586 vlan, inlen, 0, olx);
4587 txq->wqe_ci += wqe_n;
4588 loc->wqe_free -= wqe_n;
4590 * Packet data are completely inlined,
4591 * free the packet immediately.
4593 rte_pktmbuf_free_seg(loc->mbuf);
4594 } else if ((!MLX5_TXOFF_CONFIG(EMPW) ||
4595 MLX5_TXOFF_CONFIG(MPW)) &&
4598 * If minimal inlining is requested the eMPW
4599 * feature should be disabled due to data is
4600 * inlined into Ethernet Segment, which can
4601 * not contain inlined data for eMPW due to
4602 * segment shared for all packets.
4604 struct mlx5_wqe_dseg *restrict dseg;
4609 * The inline-mode settings require
4610 * to inline the specified amount of
4611 * data bytes to the Ethernet Segment.
4612 * We should check the free space in
4613 * WQE ring buffer to inline partially.
4616 MLX5_ASSERT(txq->inlen_send >= txq->inlen_mode);
4617 MLX5_ASSERT(inlen > txq->inlen_mode);
4618 MLX5_ASSERT(txq->inlen_mode >=
4619 MLX5_ESEG_MIN_INLINE_SIZE);
4621 * Check whether there are enough free WQEBBs:
4623 * - Ethernet Segment
4624 * - First Segment of inlined Ethernet data
4625 * - ... data continued ...
4626 * - Finishing Data Segment of pointer type
4628 ds = (MLX5_WQE_CSEG_SIZE +
4629 MLX5_WQE_ESEG_SIZE +
4630 MLX5_WQE_DSEG_SIZE +
4632 MLX5_ESEG_MIN_INLINE_SIZE +
4633 MLX5_WQE_DSEG_SIZE +
4634 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4635 if (loc->wqe_free < ((ds + 3) / 4))
4636 return MLX5_TXCMP_CODE_EXIT;
4638 * Build the ordinary SEND WQE:
4640 * - Ethernet Segment, inline inlen_mode bytes
4641 * - Data Segment of pointer type
4643 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4644 loc->wqe_last = wqe;
4645 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4646 MLX5_OPCODE_SEND, olx);
4647 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4650 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4651 txq->inlen_mode - vlan;
4652 inlen -= txq->inlen_mode;
4653 mlx5_tx_dseg_ptr(txq, loc, dseg,
4656 * WQE is built, update the loop parameters
4657 * and got to the next packet.
4659 txq->wqe_ci += (ds + 3) / 4;
4660 loc->wqe_free -= (ds + 3) / 4;
4661 /* We have to store mbuf in elts.*/
4662 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4663 txq->elts[txq->elts_head++ & txq->elts_m] =
4671 * Partially inlined packet data WQE, we have
4672 * some space in title WQEBB, we can fill it
4673 * with some packet data. It takes one WQEBB,
4674 * it is available, no extra space check:
4675 * - Control Segment, SEND opcode
4676 * - Ethernet Segment, no VLAN insertion
4677 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4678 * - Data Segment, pointer type
4680 * We also get here if VLAN insertion is not
4681 * supported by HW, the inline is enabled.
4684 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4685 loc->wqe_last = wqe;
4686 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4687 MLX5_OPCODE_SEND, olx);
4688 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4689 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4690 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4692 * The length check is performed above, by
4693 * comparing with txq->inlen_send. We should
4694 * not get overflow here.
4696 MLX5_ASSERT(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4697 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4698 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4702 /* We have to store mbuf in elts.*/
4703 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE));
4704 txq->elts[txq->elts_head++ & txq->elts_m] =
4708 #ifdef MLX5_PMD_SOFT_COUNTERS
4709 /* Update sent data bytes counter. */
4710 txq->stats.obytes += vlan +
4711 rte_pktmbuf_data_len(loc->mbuf);
4715 * No inline at all, it means the CPU cycles saving
4716 * is prioritized at configuration, we should not
4717 * copy any packet data to WQE.
4719 * SEND WQE, one WQEBB:
4720 * - Control Segment, SEND opcode
4721 * - Ethernet Segment, optional VLAN, no inline
4722 * - Data Segment, pointer type
4725 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4726 loc->wqe_last = wqe;
4727 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4728 MLX5_OPCODE_SEND, olx);
4729 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4731 (txq, loc, &wqe->dseg[0],
4732 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4733 rte_pktmbuf_data_len(loc->mbuf), olx);
4737 * We should not store mbuf pointer in elts
4738 * if no inlining is configured, this is done
4739 * by calling routine in a batch copy.
4741 MLX5_ASSERT(!MLX5_TXOFF_CONFIG(INLINE));
4743 #ifdef MLX5_PMD_SOFT_COUNTERS
4744 /* Update sent data bytes counter. */
4745 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4746 if (MLX5_TXOFF_CONFIG(VLAN) &&
4747 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4748 txq->stats.obytes +=
4749 sizeof(struct rte_vlan_hdr);
4754 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4755 return MLX5_TXCMP_CODE_EXIT;
4756 loc->mbuf = *pkts++;
4758 rte_prefetch0(*pkts);
4759 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4760 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4766 static __rte_always_inline enum mlx5_txcmp_code
4767 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4768 struct rte_mbuf **restrict pkts,
4769 unsigned int pkts_n,
4770 struct mlx5_txq_local *restrict loc,
4773 enum mlx5_txcmp_code ret;
4775 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4776 if (ret == MLX5_TXCMP_CODE_SINGLE)
4778 MLX5_ASSERT(ret == MLX5_TXCMP_CODE_EMPW);
4780 /* Optimize for inline/no inline eMPW send. */
4781 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4782 mlx5_tx_burst_empw_inline
4783 (txq, pkts, pkts_n, loc, olx) :
4784 mlx5_tx_burst_empw_simple
4785 (txq, pkts, pkts_n, loc, olx);
4786 if (ret != MLX5_TXCMP_CODE_SINGLE)
4788 /* The resources to send one packet should remain. */
4789 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4791 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4792 MLX5_ASSERT(ret != MLX5_TXCMP_CODE_SINGLE);
4793 if (ret != MLX5_TXCMP_CODE_EMPW)
4795 /* The resources to send one packet should remain. */
4796 MLX5_ASSERT(loc->elts_free && loc->wqe_free);
4801 * DPDK Tx callback template. This is configured template
4802 * used to generate routines optimized for specified offload setup.
4803 * One of this generated functions is chosen at SQ configuration
4807 * Generic pointer to TX queue structure.
4809 * Packets to transmit.
4811 * Number of packets in array.
4813 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4814 * values. Should be static to take compile time static configuration
4818 * Number of packets successfully transmitted (<= pkts_n).
4820 static __rte_always_inline uint16_t
4821 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4822 struct rte_mbuf **restrict pkts,
4826 struct mlx5_txq_local loc;
4827 enum mlx5_txcmp_code ret;
4830 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4831 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4832 if (unlikely(!pkts_n))
4836 loc.wqe_last = NULL;
4839 loc.pkts_loop = loc.pkts_sent;
4841 * Check if there are some CQEs, if any:
4842 * - process an encountered errors
4843 * - process the completed WQEs
4844 * - free related mbufs
4845 * - doorbell the NIC about processed CQEs
4847 rte_prefetch0(*(pkts + loc.pkts_sent));
4848 mlx5_tx_handle_completion(txq, olx);
4850 * Calculate the number of available resources - elts and WQEs.
4851 * There are two possible different scenarios:
4852 * - no data inlining into WQEs, one WQEBB may contains upto
4853 * four packets, in this case elts become scarce resource
4854 * - data inlining into WQEs, one packet may require multiple
4855 * WQEBBs, the WQEs become the limiting factor.
4857 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4858 loc.elts_free = txq->elts_s -
4859 (uint16_t)(txq->elts_head - txq->elts_tail);
4860 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4861 loc.wqe_free = txq->wqe_s -
4862 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4863 if (unlikely(!loc.elts_free || !loc.wqe_free))
4867 * Fetch the packet from array. Usually this is
4868 * the first packet in series of multi/single
4871 loc.mbuf = *(pkts + loc.pkts_sent);
4872 /* Dedicated branch for multi-segment packets. */
4873 if (MLX5_TXOFF_CONFIG(MULTI) &&
4874 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4876 * Multi-segment packet encountered.
4877 * Hardware is able to process it only
4878 * with SEND/TSO opcodes, one packet
4879 * per WQE, do it in dedicated routine.
4882 MLX5_ASSERT(loc.pkts_sent >= loc.pkts_copy);
4883 part = loc.pkts_sent - loc.pkts_copy;
4884 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4886 * There are some single-segment mbufs not
4887 * stored in elts. The mbufs must be in the
4888 * same order as WQEs, so we must copy the
4889 * mbufs to elts here, before the coming
4890 * multi-segment packet mbufs is appended.
4892 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4894 loc.pkts_copy = loc.pkts_sent;
4896 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4897 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4898 if (!MLX5_TXOFF_CONFIG(INLINE))
4899 loc.pkts_copy = loc.pkts_sent;
4901 * These returned code checks are supposed
4902 * to be optimized out due to routine inlining.
4904 if (ret == MLX5_TXCMP_CODE_EXIT) {
4906 * The routine returns this code when
4907 * all packets are sent or there is no
4908 * enough resources to complete request.
4912 if (ret == MLX5_TXCMP_CODE_ERROR) {
4914 * The routine returns this code when
4915 * some error in the incoming packets
4918 txq->stats.oerrors++;
4921 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4923 * The single-segment packet was encountered
4924 * in the array, try to send it with the
4925 * best optimized way, possible engaging eMPW.
4927 goto enter_send_single;
4929 if (MLX5_TXOFF_CONFIG(TSO) &&
4930 ret == MLX5_TXCMP_CODE_TSO) {
4932 * The single-segment TSO packet was
4933 * encountered in the array.
4935 goto enter_send_tso;
4937 /* We must not get here. Something is going wrong. */
4939 txq->stats.oerrors++;
4942 /* Dedicated branch for single-segment TSO packets. */
4943 if (MLX5_TXOFF_CONFIG(TSO) &&
4944 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4946 * TSO might require special way for inlining
4947 * (dedicated parameters) and is sent with
4948 * MLX5_OPCODE_TSO opcode only, provide this
4949 * in dedicated branch.
4952 MLX5_ASSERT(NB_SEGS(loc.mbuf) == 1);
4953 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4954 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4956 * These returned code checks are supposed
4957 * to be optimized out due to routine inlining.
4959 if (ret == MLX5_TXCMP_CODE_EXIT)
4961 if (ret == MLX5_TXCMP_CODE_ERROR) {
4962 txq->stats.oerrors++;
4965 if (ret == MLX5_TXCMP_CODE_SINGLE)
4966 goto enter_send_single;
4967 if (MLX5_TXOFF_CONFIG(MULTI) &&
4968 ret == MLX5_TXCMP_CODE_MULTI) {
4970 * The multi-segment packet was
4971 * encountered in the array.
4973 goto enter_send_multi;
4975 /* We must not get here. Something is going wrong. */
4977 txq->stats.oerrors++;
4981 * The dedicated branch for the single-segment packets
4982 * without TSO. Often these ones can be sent using
4983 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4984 * The routine builds the WQEs till it encounters
4985 * the TSO or multi-segment packet (in case if these
4986 * offloads are requested at SQ configuration time).
4989 MLX5_ASSERT(pkts_n > loc.pkts_sent);
4990 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4992 * These returned code checks are supposed
4993 * to be optimized out due to routine inlining.
4995 if (ret == MLX5_TXCMP_CODE_EXIT)
4997 if (ret == MLX5_TXCMP_CODE_ERROR) {
4998 txq->stats.oerrors++;
5001 if (MLX5_TXOFF_CONFIG(MULTI) &&
5002 ret == MLX5_TXCMP_CODE_MULTI) {
5004 * The multi-segment packet was
5005 * encountered in the array.
5007 goto enter_send_multi;
5009 if (MLX5_TXOFF_CONFIG(TSO) &&
5010 ret == MLX5_TXCMP_CODE_TSO) {
5012 * The single-segment TSO packet was
5013 * encountered in the array.
5015 goto enter_send_tso;
5017 /* We must not get here. Something is going wrong. */
5019 txq->stats.oerrors++;
5023 * Main Tx loop is completed, do the rest:
5024 * - set completion request if thresholds are reached
5025 * - doorbell the hardware
5026 * - copy the rest of mbufs to elts (if any)
5028 MLX5_ASSERT(MLX5_TXOFF_CONFIG(INLINE) ||
5029 loc.pkts_sent >= loc.pkts_copy);
5030 /* Take a shortcut if nothing is sent. */
5031 if (unlikely(loc.pkts_sent == loc.pkts_loop))
5033 /* Request CQE generation if limits are reached. */
5034 mlx5_tx_request_completion(txq, &loc, olx);
5036 * Ring QP doorbell immediately after WQE building completion
5037 * to improve latencies. The pure software related data treatment
5038 * can be completed after doorbell. Tx CQEs for this SQ are
5039 * processed in this thread only by the polling.
5041 * The rdma core library can map doorbell register in two ways,
5042 * depending on the environment variable "MLX5_SHUT_UP_BF":
5044 * - as regular cached memory, the variable is either missing or
5045 * set to zero. This type of mapping may cause the significant
5046 * doorbell register writing latency and requires explicit
5047 * memory write barrier to mitigate this issue and prevent
5050 * - as non-cached memory, the variable is present and set to
5051 * not "0" value. This type of mapping may cause performance
5052 * impact under heavy loading conditions but the explicit write
5053 * memory barrier is not required and it may improve core
5056 * - the legacy behaviour (prior 19.08 release) was to use some
5057 * heuristics to decide whether write memory barrier should
5058 * be performed. This behavior is supported with specifying
5059 * tx_db_nc=2, write barrier is skipped if application
5060 * provides the full recommended burst of packets, it
5061 * supposes the next packets are coming and the write barrier
5062 * will be issued on the next burst (after descriptor writing,
5065 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, !txq->db_nc &&
5066 (!txq->db_heu || pkts_n % MLX5_TX_DEFAULT_BURST));
5067 /* Not all of the mbufs may be stored into elts yet. */
5068 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
5069 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
5071 * There are some single-segment mbufs not stored in elts.
5072 * It can be only if the last packet was single-segment.
5073 * The copying is gathered into one place due to it is
5074 * a good opportunity to optimize that with SIMD.
5075 * Unfortunately if inlining is enabled the gaps in
5076 * pointer array may happen due to early freeing of the
5079 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
5080 loc.pkts_copy = loc.pkts_sent;
5082 MLX5_ASSERT(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
5083 MLX5_ASSERT(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
5084 if (pkts_n > loc.pkts_sent) {
5086 * If burst size is large there might be no enough CQE
5087 * fetched from completion queue and no enough resources
5088 * freed to send all the packets.
5093 #ifdef MLX5_PMD_SOFT_COUNTERS
5094 /* Increment sent packets counter. */
5095 txq->stats.opackets += loc.pkts_sent;
5097 return loc.pkts_sent;
5100 /* Generate routines with Enhanced Multi-Packet Write support. */
5101 MLX5_TXOFF_DECL(full_empw,
5102 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
5104 MLX5_TXOFF_DECL(none_empw,
5105 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5107 MLX5_TXOFF_DECL(md_empw,
5108 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5110 MLX5_TXOFF_DECL(mt_empw,
5111 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5112 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5114 MLX5_TXOFF_DECL(mtsc_empw,
5115 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5116 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5117 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5119 MLX5_TXOFF_DECL(mti_empw,
5120 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5121 MLX5_TXOFF_CONFIG_INLINE |
5122 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5124 MLX5_TXOFF_DECL(mtv_empw,
5125 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5126 MLX5_TXOFF_CONFIG_VLAN |
5127 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5129 MLX5_TXOFF_DECL(mtiv_empw,
5130 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5131 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5132 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5134 MLX5_TXOFF_DECL(sc_empw,
5135 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5136 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5138 MLX5_TXOFF_DECL(sci_empw,
5139 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5140 MLX5_TXOFF_CONFIG_INLINE |
5141 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5143 MLX5_TXOFF_DECL(scv_empw,
5144 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5145 MLX5_TXOFF_CONFIG_VLAN |
5146 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5148 MLX5_TXOFF_DECL(sciv_empw,
5149 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5150 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5151 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5153 MLX5_TXOFF_DECL(i_empw,
5154 MLX5_TXOFF_CONFIG_INLINE |
5155 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5157 MLX5_TXOFF_DECL(v_empw,
5158 MLX5_TXOFF_CONFIG_VLAN |
5159 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5161 MLX5_TXOFF_DECL(iv_empw,
5162 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5163 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5165 /* Generate routines without Enhanced Multi-Packet Write support. */
5166 MLX5_TXOFF_DECL(full,
5167 MLX5_TXOFF_CONFIG_FULL)
5169 MLX5_TXOFF_DECL(none,
5170 MLX5_TXOFF_CONFIG_NONE)
5173 MLX5_TXOFF_CONFIG_METADATA)
5176 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5177 MLX5_TXOFF_CONFIG_METADATA)
5179 MLX5_TXOFF_DECL(mtsc,
5180 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5181 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5182 MLX5_TXOFF_CONFIG_METADATA)
5184 MLX5_TXOFF_DECL(mti,
5185 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5186 MLX5_TXOFF_CONFIG_INLINE |
5187 MLX5_TXOFF_CONFIG_METADATA)
5190 MLX5_TXOFF_DECL(mtv,
5191 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5192 MLX5_TXOFF_CONFIG_VLAN |
5193 MLX5_TXOFF_CONFIG_METADATA)
5196 MLX5_TXOFF_DECL(mtiv,
5197 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5198 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5199 MLX5_TXOFF_CONFIG_METADATA)
5202 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5203 MLX5_TXOFF_CONFIG_METADATA)
5205 MLX5_TXOFF_DECL(sci,
5206 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5207 MLX5_TXOFF_CONFIG_INLINE |
5208 MLX5_TXOFF_CONFIG_METADATA)
5211 MLX5_TXOFF_DECL(scv,
5212 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5213 MLX5_TXOFF_CONFIG_VLAN |
5214 MLX5_TXOFF_CONFIG_METADATA)
5217 MLX5_TXOFF_DECL(sciv,
5218 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5219 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5220 MLX5_TXOFF_CONFIG_METADATA)
5223 MLX5_TXOFF_CONFIG_INLINE |
5224 MLX5_TXOFF_CONFIG_METADATA)
5227 MLX5_TXOFF_CONFIG_VLAN |
5228 MLX5_TXOFF_CONFIG_METADATA)
5231 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5232 MLX5_TXOFF_CONFIG_METADATA)
5235 * Generate routines with Legacy Multi-Packet Write support.
5236 * This mode is supported by ConnectX-4 Lx only and imposes
5237 * offload limitations, not supported:
5238 * - ACL/Flows (metadata are becoming meaningless)
5239 * - WQE Inline headers
5240 * - SRIOV (E-Switch offloads)
5242 * - tunnel encapsulation/decapsulation
5245 MLX5_TXOFF_DECL(none_mpw,
5246 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5247 MLX5_TXOFF_CONFIG_MPW)
5249 MLX5_TXOFF_DECL(mci_mpw,
5250 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5251 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5252 MLX5_TXOFF_CONFIG_MPW)
5254 MLX5_TXOFF_DECL(mc_mpw,
5255 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5256 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5258 MLX5_TXOFF_DECL(i_mpw,
5259 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5260 MLX5_TXOFF_CONFIG_MPW)
5263 * Array of declared and compiled Tx burst function and corresponding
5264 * supported offloads set. The array is used to select the Tx burst
5265 * function for specified offloads set at Tx queue configuration time.
5268 eth_tx_burst_t func;
5271 MLX5_TXOFF_INFO(full_empw,
5272 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5273 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5274 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5275 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5277 MLX5_TXOFF_INFO(none_empw,
5278 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
5280 MLX5_TXOFF_INFO(md_empw,
5281 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5283 MLX5_TXOFF_INFO(mt_empw,
5284 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5285 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5287 MLX5_TXOFF_INFO(mtsc_empw,
5288 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5289 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5290 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5292 MLX5_TXOFF_INFO(mti_empw,
5293 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5294 MLX5_TXOFF_CONFIG_INLINE |
5295 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5297 MLX5_TXOFF_INFO(mtv_empw,
5298 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5299 MLX5_TXOFF_CONFIG_VLAN |
5300 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5302 MLX5_TXOFF_INFO(mtiv_empw,
5303 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5304 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5305 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5307 MLX5_TXOFF_INFO(sc_empw,
5308 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5309 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5311 MLX5_TXOFF_INFO(sci_empw,
5312 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5313 MLX5_TXOFF_CONFIG_INLINE |
5314 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5316 MLX5_TXOFF_INFO(scv_empw,
5317 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5318 MLX5_TXOFF_CONFIG_VLAN |
5319 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5321 MLX5_TXOFF_INFO(sciv_empw,
5322 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5323 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5324 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5326 MLX5_TXOFF_INFO(i_empw,
5327 MLX5_TXOFF_CONFIG_INLINE |
5328 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5330 MLX5_TXOFF_INFO(v_empw,
5331 MLX5_TXOFF_CONFIG_VLAN |
5332 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5334 MLX5_TXOFF_INFO(iv_empw,
5335 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5336 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
5338 MLX5_TXOFF_INFO(full,
5339 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5340 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5341 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5342 MLX5_TXOFF_CONFIG_METADATA)
5344 MLX5_TXOFF_INFO(none,
5345 MLX5_TXOFF_CONFIG_NONE)
5348 MLX5_TXOFF_CONFIG_METADATA)
5351 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5352 MLX5_TXOFF_CONFIG_METADATA)
5354 MLX5_TXOFF_INFO(mtsc,
5355 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5356 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5357 MLX5_TXOFF_CONFIG_METADATA)
5359 MLX5_TXOFF_INFO(mti,
5360 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5361 MLX5_TXOFF_CONFIG_INLINE |
5362 MLX5_TXOFF_CONFIG_METADATA)
5364 MLX5_TXOFF_INFO(mtv,
5365 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5366 MLX5_TXOFF_CONFIG_VLAN |
5367 MLX5_TXOFF_CONFIG_METADATA)
5369 MLX5_TXOFF_INFO(mtiv,
5370 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5371 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5372 MLX5_TXOFF_CONFIG_METADATA)
5375 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5376 MLX5_TXOFF_CONFIG_METADATA)
5378 MLX5_TXOFF_INFO(sci,
5379 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5380 MLX5_TXOFF_CONFIG_INLINE |
5381 MLX5_TXOFF_CONFIG_METADATA)
5383 MLX5_TXOFF_INFO(scv,
5384 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5385 MLX5_TXOFF_CONFIG_VLAN |
5386 MLX5_TXOFF_CONFIG_METADATA)
5388 MLX5_TXOFF_INFO(sciv,
5389 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5390 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5391 MLX5_TXOFF_CONFIG_METADATA)
5394 MLX5_TXOFF_CONFIG_INLINE |
5395 MLX5_TXOFF_CONFIG_METADATA)
5398 MLX5_TXOFF_CONFIG_VLAN |
5399 MLX5_TXOFF_CONFIG_METADATA)
5402 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5403 MLX5_TXOFF_CONFIG_METADATA)
5405 MLX5_TXOFF_INFO(none_mpw,
5406 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW |
5407 MLX5_TXOFF_CONFIG_MPW)
5409 MLX5_TXOFF_INFO(mci_mpw,
5410 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5411 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5412 MLX5_TXOFF_CONFIG_MPW)
5414 MLX5_TXOFF_INFO(mc_mpw,
5415 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_CSUM |
5416 MLX5_TXOFF_CONFIG_EMPW | MLX5_TXOFF_CONFIG_MPW)
5418 MLX5_TXOFF_INFO(i_mpw,
5419 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_EMPW |
5420 MLX5_TXOFF_CONFIG_MPW)
5424 * Configure the Tx function to use. The routine checks configured
5425 * Tx offloads for the device and selects appropriate Tx burst
5426 * routine. There are multiple Tx burst routines compiled from
5427 * the same template in the most optimal way for the dedicated
5431 * Pointer to private data structure.
5434 * Pointer to selected Tx burst function.
5437 mlx5_select_tx_function(struct rte_eth_dev *dev)
5439 struct mlx5_priv *priv = dev->data->dev_private;
5440 struct mlx5_dev_config *config = &priv->config;
5441 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5442 unsigned int diff = 0, olx = 0, i, m;
5444 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5445 MLX5_DSEG_MAX, "invalid WQE max size");
5446 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5447 "invalid WQE Control Segment size");
5448 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5449 "invalid WQE Ethernet Segment size");
5450 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5451 "invalid WQE Data Segment size");
5452 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5453 "invalid WQE size");
5455 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5456 /* We should support Multi-Segment Packets. */
5457 olx |= MLX5_TXOFF_CONFIG_MULTI;
5459 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5460 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5461 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5462 DEV_TX_OFFLOAD_IP_TNL_TSO |
5463 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5464 /* We should support TCP Send Offload. */
5465 olx |= MLX5_TXOFF_CONFIG_TSO;
5467 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5468 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5469 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5470 /* We should support Software Parser for Tunnels. */
5471 olx |= MLX5_TXOFF_CONFIG_SWP;
5473 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5474 DEV_TX_OFFLOAD_UDP_CKSUM |
5475 DEV_TX_OFFLOAD_TCP_CKSUM |
5476 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5477 /* We should support IP/TCP/UDP Checksums. */
5478 olx |= MLX5_TXOFF_CONFIG_CSUM;
5480 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5481 /* We should support VLAN insertion. */
5482 olx |= MLX5_TXOFF_CONFIG_VLAN;
5484 if (priv->txqs_n && (*priv->txqs)[0]) {
5485 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5487 if (txd->inlen_send) {
5489 * Check the data inline requirements. Data inline
5490 * is enabled on per device basis, we can check
5491 * the first Tx queue only.
5493 * If device does not support VLAN insertion in WQE
5494 * and some queues are requested to perform VLAN
5495 * insertion offload than inline must be enabled.
5497 olx |= MLX5_TXOFF_CONFIG_INLINE;
5500 if (config->mps == MLX5_MPW_ENHANCED &&
5501 config->txq_inline_min <= 0) {
5503 * The NIC supports Enhanced Multi-Packet Write
5504 * and does not require minimal inline data.
5506 olx |= MLX5_TXOFF_CONFIG_EMPW;
5508 if (rte_flow_dynf_metadata_avail()) {
5509 /* We should support Flow metadata. */
5510 olx |= MLX5_TXOFF_CONFIG_METADATA;
5512 if (config->mps == MLX5_MPW) {
5514 * The NIC supports Legacy Multi-Packet Write.
5515 * The MLX5_TXOFF_CONFIG_MPW controls the
5516 * descriptor building method in combination
5517 * with MLX5_TXOFF_CONFIG_EMPW.
5519 if (!(olx & (MLX5_TXOFF_CONFIG_TSO |
5520 MLX5_TXOFF_CONFIG_SWP |
5521 MLX5_TXOFF_CONFIG_VLAN |
5522 MLX5_TXOFF_CONFIG_METADATA)))
5523 olx |= MLX5_TXOFF_CONFIG_EMPW |
5524 MLX5_TXOFF_CONFIG_MPW;
5527 * Scan the routines table to find the minimal
5528 * satisfying routine with requested offloads.
5530 m = RTE_DIM(txoff_func);
5531 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5534 tmp = txoff_func[i].olx;
5536 /* Meets requested offloads exactly.*/
5540 if ((tmp & olx) != olx) {
5541 /* Does not meet requested offloads at all. */
5544 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5545 /* Do not enable eMPW if not configured. */
5547 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5548 /* Do not enable inlining if not configured. */
5551 * Some routine meets the requirements.
5552 * Check whether it has minimal amount
5553 * of not requested offloads.
5555 tmp = __builtin_popcountl(tmp & ~olx);
5556 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5557 /* First or better match, save and continue. */
5563 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5564 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5565 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5566 /* Lighter not requested offload. */
5571 if (m >= RTE_DIM(txoff_func)) {
5572 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5573 " for requested offloads %04X",
5574 dev->data->port_id, olx);
5577 DRV_LOG(DEBUG, "port %u has selected Tx function"
5578 " supporting offloads %04X/%04X",
5579 dev->data->port_id, olx, txoff_func[m].olx);
5580 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5581 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5582 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5583 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5584 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5585 DRV_LOG(DEBUG, "\tSWP (software parser)");
5586 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5587 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5588 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5589 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5590 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5591 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5592 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5593 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5594 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW) {
5595 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MPW)
5596 DRV_LOG(DEBUG, "\tMPW (Legacy MPW)");
5598 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5600 return txoff_func[m].func;
5604 * DPDK callback to get the TX queue information
5607 * Pointer to the device structure.
5609 * @param tx_queue_id
5610 * Tx queue identificator.
5613 * Pointer to the TX queue information structure.
5620 mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
5621 struct rte_eth_txq_info *qinfo)
5623 struct mlx5_priv *priv = dev->data->dev_private;
5624 struct mlx5_txq_data *txq = (*priv->txqs)[tx_queue_id];
5625 struct mlx5_txq_ctrl *txq_ctrl =
5626 container_of(txq, struct mlx5_txq_ctrl, txq);
5630 qinfo->nb_desc = txq->elts_s;
5631 qinfo->conf.tx_thresh.pthresh = 0;
5632 qinfo->conf.tx_thresh.hthresh = 0;
5633 qinfo->conf.tx_thresh.wthresh = 0;
5634 qinfo->conf.tx_rs_thresh = 0;
5635 qinfo->conf.tx_free_thresh = 0;
5636 qinfo->conf.tx_deferred_start = txq_ctrl ? 0 : 1;
5637 qinfo->conf.offloads = dev->data->dev_conf.txmode.offloads;
5641 * DPDK callback to get the TX packet burst mode information
5644 * Pointer to the device structure.
5646 * @param tx_queue_id
5647 * Tx queue identificatior.
5650 * Pointer to the burts mode information.
5653 * 0 as success, -EINVAL as failure.
5657 mlx5_tx_burst_mode_get(struct rte_eth_dev *dev,
5658 uint16_t tx_queue_id __rte_unused,
5659 struct rte_eth_burst_mode *mode)
5661 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst;
5662 unsigned int i, olx;
5664 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5665 if (pkt_burst == txoff_func[i].func) {
5666 olx = txoff_func[i].olx;
5667 snprintf(mode->info, sizeof(mode->info),
5669 (olx & MLX5_TXOFF_CONFIG_EMPW) ?
5670 ((olx & MLX5_TXOFF_CONFIG_MPW) ?
5671 "Legacy MPW" : "Enhanced MPW") : "No MPW",
5672 (olx & MLX5_TXOFF_CONFIG_MULTI) ?
5674 (olx & MLX5_TXOFF_CONFIG_TSO) ?
5676 (olx & MLX5_TXOFF_CONFIG_SWP) ?
5678 (olx & MLX5_TXOFF_CONFIG_CSUM) ?
5680 (olx & MLX5_TXOFF_CONFIG_INLINE) ?
5682 (olx & MLX5_TXOFF_CONFIG_VLAN) ?
5684 (olx & MLX5_TXOFF_CONFIG_METADATA) ?
5685 " + METADATA" : "");