1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015-2019 Mellanox Technologies, Ltd
12 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
14 #pragma GCC diagnostic ignored "-Wpedantic"
16 #include <infiniband/verbs.h>
17 #include <infiniband/mlx5dv.h>
19 #pragma GCC diagnostic error "-Wpedantic"
23 #include <rte_mempool.h>
24 #include <rte_prefetch.h>
25 #include <rte_common.h>
26 #include <rte_branch_prediction.h>
27 #include <rte_ether.h>
28 #include <rte_cycles.h>
31 #include "mlx5_utils.h"
32 #include "mlx5_rxtx.h"
33 #include "mlx5_autoconf.h"
34 #include "mlx5_defs.h"
37 /* TX burst subroutines return codes. */
38 enum mlx5_txcmp_code {
39 MLX5_TXCMP_CODE_EXIT = 0,
40 MLX5_TXCMP_CODE_ERROR,
41 MLX5_TXCMP_CODE_SINGLE,
42 MLX5_TXCMP_CODE_MULTI,
48 * These defines are used to configure Tx burst routine option set
49 * supported at compile time. The not specified options are optimized out
50 * out due to if conditions can be explicitly calculated at compile time.
51 * The offloads with bigger runtime check (require more CPU cycles to
52 * skip) overhead should have the bigger index - this is needed to
53 * select the better matching routine function if no exact match and
54 * some offloads are not actually requested.
56 #define MLX5_TXOFF_CONFIG_MULTI (1u << 0) /* Multi-segment packets.*/
57 #define MLX5_TXOFF_CONFIG_TSO (1u << 1) /* TCP send offload supported.*/
58 #define MLX5_TXOFF_CONFIG_SWP (1u << 2) /* Tunnels/SW Parser offloads.*/
59 #define MLX5_TXOFF_CONFIG_CSUM (1u << 3) /* Check Sums offloaded. */
60 #define MLX5_TXOFF_CONFIG_INLINE (1u << 4) /* Data inlining supported. */
61 #define MLX5_TXOFF_CONFIG_VLAN (1u << 5) /* VLAN insertion supported.*/
62 #define MLX5_TXOFF_CONFIG_METADATA (1u << 6) /* Flow metadata. */
63 #define MLX5_TXOFF_CONFIG_EMPW (1u << 8) /* Enhanced MPW supported.*/
65 /* The most common offloads groups. */
66 #define MLX5_TXOFF_CONFIG_NONE 0
67 #define MLX5_TXOFF_CONFIG_FULL (MLX5_TXOFF_CONFIG_MULTI | \
68 MLX5_TXOFF_CONFIG_TSO | \
69 MLX5_TXOFF_CONFIG_SWP | \
70 MLX5_TXOFF_CONFIG_CSUM | \
71 MLX5_TXOFF_CONFIG_INLINE | \
72 MLX5_TXOFF_CONFIG_VLAN | \
73 MLX5_TXOFF_CONFIG_METADATA)
75 #define MLX5_TXOFF_CONFIG(mask) (olx & MLX5_TXOFF_CONFIG_##mask)
77 #define MLX5_TXOFF_DECL(func, olx) \
78 static uint16_t mlx5_tx_burst_##func(void *txq, \
79 struct rte_mbuf **pkts, \
82 return mlx5_tx_burst_tmpl((struct mlx5_txq_data *)txq, \
83 pkts, pkts_n, (olx)); \
86 #define MLX5_TXOFF_INFO(func, olx) {mlx5_tx_burst_##func, olx},
88 static __rte_always_inline uint32_t
89 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
91 static __rte_always_inline int
92 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
93 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe);
95 static __rte_always_inline uint32_t
96 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe);
98 static __rte_always_inline void
99 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
100 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res);
102 static __rte_always_inline void
103 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
104 const unsigned int strd_n);
107 mlx5_queue_state_modify(struct rte_eth_dev *dev,
108 struct mlx5_mp_arg_queue_state_modify *sm);
111 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
112 volatile struct mlx5_cqe *restrict cqe,
116 mlx5_lro_update_hdr(uint8_t *restrict padd,
117 volatile struct mlx5_cqe *restrict cqe,
120 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
121 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
124 uint8_t mlx5_cksum_table[1 << 10] __rte_cache_aligned;
125 uint8_t mlx5_swp_types_table[1 << 10] __rte_cache_aligned;
128 * Build a table to translate Rx completion flags to packet type.
130 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
133 mlx5_set_ptype_table(void)
136 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
138 /* Last entry must not be overwritten, reserved for errored packet. */
139 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
140 (*p)[i] = RTE_PTYPE_UNKNOWN;
142 * The index to the array should have:
143 * bit[1:0] = l3_hdr_type
144 * bit[4:2] = l4_hdr_type
147 * bit[7] = outer_l3_type
150 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
152 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
153 RTE_PTYPE_L4_NONFRAG;
154 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
155 RTE_PTYPE_L4_NONFRAG;
157 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
159 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
162 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
164 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
166 (*p)[0x0d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
168 (*p)[0x0e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 (*p)[0x11] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
172 (*p)[0x12] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
175 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
177 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
179 /* Repeat with outer_l3_type being set. Just in case. */
180 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_L4_NONFRAG;
182 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_L4_NONFRAG;
184 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
188 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
190 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
192 (*p)[0x8d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
194 (*p)[0x8e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
196 (*p)[0x91] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
198 (*p)[0x92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
200 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
202 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
205 (*p)[0x40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
206 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
207 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
208 RTE_PTYPE_INNER_L4_NONFRAG;
209 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
210 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
211 RTE_PTYPE_INNER_L4_NONFRAG;
212 (*p)[0xc0] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
213 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
214 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
215 RTE_PTYPE_INNER_L4_NONFRAG;
216 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
217 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
218 RTE_PTYPE_INNER_L4_NONFRAG;
219 /* Tunneled - Fragmented */
220 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
221 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
222 RTE_PTYPE_INNER_L4_FRAG;
223 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
224 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
225 RTE_PTYPE_INNER_L4_FRAG;
226 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
227 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
228 RTE_PTYPE_INNER_L4_FRAG;
229 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
230 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
231 RTE_PTYPE_INNER_L4_FRAG;
233 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
234 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
235 RTE_PTYPE_INNER_L4_TCP;
236 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
237 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
238 RTE_PTYPE_INNER_L4_TCP;
239 (*p)[0x4d] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
240 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
241 RTE_PTYPE_INNER_L4_TCP;
242 (*p)[0x4e] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
243 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
244 RTE_PTYPE_INNER_L4_TCP;
245 (*p)[0x51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
246 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
247 RTE_PTYPE_INNER_L4_TCP;
248 (*p)[0x52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
249 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
250 RTE_PTYPE_INNER_L4_TCP;
251 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
252 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
253 RTE_PTYPE_INNER_L4_TCP;
254 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
255 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
256 RTE_PTYPE_INNER_L4_TCP;
257 (*p)[0xcd] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
258 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
259 RTE_PTYPE_INNER_L4_TCP;
260 (*p)[0xce] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
261 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
262 RTE_PTYPE_INNER_L4_TCP;
263 (*p)[0xd1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
264 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
265 RTE_PTYPE_INNER_L4_TCP;
266 (*p)[0xd2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
267 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
268 RTE_PTYPE_INNER_L4_TCP;
270 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
271 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
272 RTE_PTYPE_INNER_L4_UDP;
273 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
274 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
275 RTE_PTYPE_INNER_L4_UDP;
276 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
277 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
278 RTE_PTYPE_INNER_L4_UDP;
279 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
280 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
281 RTE_PTYPE_INNER_L4_UDP;
285 * Build a table to translate packet to checksum type of Verbs.
288 mlx5_set_cksum_table(void)
294 * The index should have:
295 * bit[0] = PKT_TX_TCP_SEG
296 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
297 * bit[4] = PKT_TX_IP_CKSUM
298 * bit[8] = PKT_TX_OUTER_IP_CKSUM
301 for (i = 0; i < RTE_DIM(mlx5_cksum_table); ++i) {
304 /* Tunneled packet. */
305 if (i & (1 << 8)) /* Outer IP. */
306 v |= MLX5_ETH_WQE_L3_CSUM;
307 if (i & (1 << 4)) /* Inner IP. */
308 v |= MLX5_ETH_WQE_L3_INNER_CSUM;
309 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
310 v |= MLX5_ETH_WQE_L4_INNER_CSUM;
313 if (i & (1 << 4)) /* IP. */
314 v |= MLX5_ETH_WQE_L3_CSUM;
315 if (i & (3 << 2 | 1 << 0)) /* L4 or TSO. */
316 v |= MLX5_ETH_WQE_L4_CSUM;
318 mlx5_cksum_table[i] = v;
323 * Build a table to translate packet type of mbuf to SWP type of Verbs.
326 mlx5_set_swp_types_table(void)
332 * The index should have:
333 * bit[0:1] = PKT_TX_L4_MASK
334 * bit[4] = PKT_TX_IPV6
335 * bit[8] = PKT_TX_OUTER_IPV6
336 * bit[9] = PKT_TX_OUTER_UDP
338 for (i = 0; i < RTE_DIM(mlx5_swp_types_table); ++i) {
341 v |= MLX5_ETH_WQE_L3_OUTER_IPV6;
343 v |= MLX5_ETH_WQE_L4_OUTER_UDP;
345 v |= MLX5_ETH_WQE_L3_INNER_IPV6;
346 if ((i & 3) == (PKT_TX_UDP_CKSUM >> 52))
347 v |= MLX5_ETH_WQE_L4_INNER_UDP;
348 mlx5_swp_types_table[i] = v;
353 * Set Software Parser flags and offsets in Ethernet Segment of WQE.
354 * Flags must be preliminary initialized to zero.
357 * Pointer to burst routine local context.
359 * Pointer to store Software Parser flags
361 * Configured Tx offloads mask. It is fully defined at
362 * compile time and may be used for optimization.
365 * Software Parser offsets packed in dword.
366 * Software Parser flags are set by pointer.
368 static __rte_always_inline uint32_t
369 txq_mbuf_to_swp(struct mlx5_txq_local *restrict loc,
374 unsigned int idx, off;
377 if (!MLX5_TXOFF_CONFIG(SWP))
379 ol = loc->mbuf->ol_flags;
380 tunnel = ol & PKT_TX_TUNNEL_MASK;
382 * Check whether Software Parser is required.
383 * Only customized tunnels may ask for.
385 if (likely(tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP))
388 * The index should have:
389 * bit[0:1] = PKT_TX_L4_MASK
390 * bit[4] = PKT_TX_IPV6
391 * bit[8] = PKT_TX_OUTER_IPV6
392 * bit[9] = PKT_TX_OUTER_UDP
394 idx = (ol & (PKT_TX_L4_MASK | PKT_TX_IPV6 | PKT_TX_OUTER_IPV6)) >> 52;
395 idx |= (tunnel == PKT_TX_TUNNEL_UDP) ? (1 << 9) : 0;
396 *swp_flags = mlx5_swp_types_table[idx];
398 * Set offsets for SW parser. Since ConnectX-5, SW parser just
399 * complements HW parser. SW parser starts to engage only if HW parser
400 * can't reach a header. For the older devices, HW parser will not kick
401 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
402 * should be set regardless of HW offload.
404 off = loc->mbuf->outer_l2_len;
405 if (MLX5_TXOFF_CONFIG(VLAN) && ol & PKT_TX_VLAN_PKT)
406 off += sizeof(struct rte_vlan_hdr);
407 set = (off >> 1) << 8; /* Outer L3 offset. */
408 off += loc->mbuf->outer_l3_len;
409 if (tunnel == PKT_TX_TUNNEL_UDP)
410 set |= off >> 1; /* Outer L4 offset. */
411 if (ol & (PKT_TX_IPV4 | PKT_TX_IPV6)) { /* Inner IP. */
412 const uint64_t csum = ol & PKT_TX_L4_MASK;
413 off += loc->mbuf->l2_len;
414 set |= (off >> 1) << 24; /* Inner L3 offset. */
415 if (csum == PKT_TX_TCP_CKSUM ||
416 csum == PKT_TX_UDP_CKSUM ||
417 (MLX5_TXOFF_CONFIG(TSO) && ol & PKT_TX_TCP_SEG)) {
418 off += loc->mbuf->l3_len;
419 set |= (off >> 1) << 16; /* Inner L4 offset. */
422 set = rte_cpu_to_le_32(set);
427 * Convert the Checksum offloads to Verbs.
430 * Pointer to the mbuf.
433 * Converted checksum flags.
435 static __rte_always_inline uint8_t
436 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
439 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
440 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
441 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
444 * The index should have:
445 * bit[0] = PKT_TX_TCP_SEG
446 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
447 * bit[4] = PKT_TX_IP_CKSUM
448 * bit[8] = PKT_TX_OUTER_IP_CKSUM
451 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
452 return mlx5_cksum_table[idx];
456 * Internal function to compute the number of used descriptors in an RX queue
462 * The number of used rx descriptor.
465 rx_queue_count(struct mlx5_rxq_data *rxq)
467 struct rxq_zip *zip = &rxq->zip;
468 volatile struct mlx5_cqe *cqe;
469 const unsigned int cqe_n = (1 << rxq->cqe_n);
470 const unsigned int cqe_cnt = cqe_n - 1;
474 /* if we are processing a compressed cqe */
476 used = zip->cqe_cnt - zip->ca;
482 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
483 while (check_cqe(cqe, cqe_n, cq_ci) != MLX5_CQE_STATUS_HW_OWN) {
487 op_own = cqe->op_own;
488 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
489 n = rte_be_to_cpu_32(cqe->byte_cnt);
494 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
496 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
501 * DPDK callback to check the status of a rx descriptor.
506 * The index of the descriptor in the ring.
509 * The status of the tx descriptor.
512 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
514 struct mlx5_rxq_data *rxq = rx_queue;
515 struct mlx5_rxq_ctrl *rxq_ctrl =
516 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
517 struct rte_eth_dev *dev = ETH_DEV(rxq_ctrl->priv);
519 if (dev->rx_pkt_burst != mlx5_rx_burst) {
523 if (offset >= (1 << rxq->elts_n)) {
527 if (offset < rx_queue_count(rxq))
528 return RTE_ETH_RX_DESC_DONE;
529 return RTE_ETH_RX_DESC_AVAIL;
533 * DPDK callback to get the number of used descriptors in a RX queue
536 * Pointer to the device structure.
542 * The number of used rx descriptor.
543 * -EINVAL if the queue is invalid
546 mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
548 struct mlx5_priv *priv = dev->data->dev_private;
549 struct mlx5_rxq_data *rxq;
551 if (dev->rx_pkt_burst != mlx5_rx_burst) {
555 rxq = (*priv->rxqs)[rx_queue_id];
560 return rx_queue_count(rxq);
563 #define MLX5_SYSTEM_LOG_DIR "/var/log"
565 * Dump debug information to log file.
570 * If not NULL this string is printed as a header to the output
571 * and the output will be in hexadecimal view.
573 * This is the buffer address to print out.
575 * The number of bytes to dump out.
578 mlx5_dump_debug_information(const char *fname, const char *hex_title,
579 const void *buf, unsigned int hex_len)
583 MKSTR(path, "%s/%s", MLX5_SYSTEM_LOG_DIR, fname);
584 fd = fopen(path, "a+");
586 DRV_LOG(WARNING, "cannot open %s for debug dump\n",
588 MKSTR(path2, "./%s", fname);
589 fd = fopen(path2, "a+");
591 DRV_LOG(ERR, "cannot open %s for debug dump\n",
595 DRV_LOG(INFO, "New debug dump in file %s\n", path2);
597 DRV_LOG(INFO, "New debug dump in file %s\n", path);
600 rte_hexdump(fd, hex_title, buf, hex_len);
602 fprintf(fd, "%s", (const char *)buf);
603 fprintf(fd, "\n\n\n");
608 * Move QP from error state to running state and initialize indexes.
611 * Pointer to TX queue control structure.
614 * 0 on success, else -1.
617 tx_recover_qp(struct mlx5_txq_ctrl *txq_ctrl)
619 struct mlx5_mp_arg_queue_state_modify sm = {
621 .queue_id = txq_ctrl->txq.idx,
624 if (mlx5_queue_state_modify(ETH_DEV(txq_ctrl->priv), &sm))
626 txq_ctrl->txq.wqe_ci = 0;
627 txq_ctrl->txq.wqe_pi = 0;
628 txq_ctrl->txq.elts_comp = 0;
632 /* Return 1 if the error CQE is signed otherwise, sign it and return 0. */
634 check_err_cqe_seen(volatile struct mlx5_err_cqe *err_cqe)
636 static const uint8_t magic[] = "seen";
640 for (i = 0; i < sizeof(magic); ++i)
641 if (!ret || err_cqe->rsvd1[i] != magic[i]) {
643 err_cqe->rsvd1[i] = magic[i];
652 * Pointer to TX queue structure.
654 * Pointer to the error CQE.
657 * Negative value if queue recovery failed,
658 * the last Tx buffer element to free otherwise.
661 mlx5_tx_error_cqe_handle(struct mlx5_txq_data *restrict txq,
662 volatile struct mlx5_err_cqe *err_cqe)
664 if (err_cqe->syndrome != MLX5_CQE_SYNDROME_WR_FLUSH_ERR) {
665 const uint16_t wqe_m = ((1 << txq->wqe_n) - 1);
666 struct mlx5_txq_ctrl *txq_ctrl =
667 container_of(txq, struct mlx5_txq_ctrl, txq);
668 uint16_t new_wqe_pi = rte_be_to_cpu_16(err_cqe->wqe_counter);
669 int seen = check_err_cqe_seen(err_cqe);
671 if (!seen && txq_ctrl->dump_file_n <
672 txq_ctrl->priv->config.max_dump_files_num) {
673 MKSTR(err_str, "Unexpected CQE error syndrome "
674 "0x%02x CQN = %u SQN = %u wqe_counter = %u "
675 "wq_ci = %u cq_ci = %u", err_cqe->syndrome,
676 txq->cqe_s, txq->qp_num_8s >> 8,
677 rte_be_to_cpu_16(err_cqe->wqe_counter),
678 txq->wqe_ci, txq->cq_ci);
679 MKSTR(name, "dpdk_mlx5_port_%u_txq_%u_index_%u_%u",
680 PORT_ID(txq_ctrl->priv), txq->idx,
681 txq_ctrl->dump_file_n, (uint32_t)rte_rdtsc());
682 mlx5_dump_debug_information(name, NULL, err_str, 0);
683 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
684 (const void *)((uintptr_t)
688 mlx5_dump_debug_information(name, "MLX5 Error SQ:",
689 (const void *)((uintptr_t)
693 txq_ctrl->dump_file_n++;
697 * Count errors in WQEs units.
698 * Later it can be improved to count error packets,
699 * for example, by SQ parsing to find how much packets
700 * should be counted for each WQE.
702 txq->stats.oerrors += ((txq->wqe_ci & wqe_m) -
704 if (tx_recover_qp(txq_ctrl) == 0) {
706 /* Release all the remaining buffers. */
707 return txq->elts_head;
709 /* Recovering failed - try again later on the same WQE. */
714 /* Do not release buffers. */
715 return txq->elts_tail;
719 * Translate RX completion flags to packet type.
722 * Pointer to RX queue structure.
726 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
729 * Packet type for struct rte_mbuf.
731 static inline uint32_t
732 rxq_cq_to_pkt_type(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
735 uint8_t pinfo = cqe->pkt_info;
736 uint16_t ptype = cqe->hdr_type_etc;
739 * The index to the array should have:
740 * bit[1:0] = l3_hdr_type
741 * bit[4:2] = l4_hdr_type
744 * bit[7] = outer_l3_type
746 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
747 return mlx5_ptype_table[idx] | rxq->tunnel * !!(idx & (1 << 6));
751 * Initialize Rx WQ and indexes.
754 * Pointer to RX queue structure.
757 mlx5_rxq_initialize(struct mlx5_rxq_data *rxq)
759 const unsigned int wqe_n = 1 << rxq->elts_n;
762 for (i = 0; (i != wqe_n); ++i) {
763 volatile struct mlx5_wqe_data_seg *scat;
767 if (mlx5_rxq_mprq_enabled(rxq)) {
768 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[i];
770 scat = &((volatile struct mlx5_wqe_mprq *)
772 addr = (uintptr_t)mlx5_mprq_buf_addr(buf,
773 1 << rxq->strd_num_n);
774 byte_count = (1 << rxq->strd_sz_n) *
775 (1 << rxq->strd_num_n);
777 struct rte_mbuf *buf = (*rxq->elts)[i];
779 scat = &((volatile struct mlx5_wqe_data_seg *)
781 addr = rte_pktmbuf_mtod(buf, uintptr_t);
782 byte_count = DATA_LEN(buf);
784 /* scat->addr must be able to store a pointer. */
785 assert(sizeof(scat->addr) >= sizeof(uintptr_t));
786 *scat = (struct mlx5_wqe_data_seg){
787 .addr = rte_cpu_to_be_64(addr),
788 .byte_count = rte_cpu_to_be_32(byte_count),
789 .lkey = mlx5_rx_addr2mr(rxq, addr),
792 rxq->consumed_strd = 0;
793 rxq->decompressed = 0;
795 rxq->zip = (struct rxq_zip){
798 /* Update doorbell counter. */
799 rxq->rq_ci = wqe_n >> rxq->sges_n;
801 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
805 * Modify a Verbs/DevX queue state.
806 * This must be called from the primary process.
809 * Pointer to Ethernet device.
811 * State modify request parameters.
814 * 0 in case of success else non-zero value and rte_errno is set.
817 mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
818 const struct mlx5_mp_arg_queue_state_modify *sm)
821 struct mlx5_priv *priv = dev->data->dev_private;
824 struct mlx5_rxq_data *rxq = (*priv->rxqs)[sm->queue_id];
825 struct mlx5_rxq_ctrl *rxq_ctrl =
826 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
828 if (rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_IBV) {
829 struct ibv_wq_attr mod = {
830 .attr_mask = IBV_WQ_ATTR_STATE,
831 .wq_state = sm->state,
834 ret = mlx5_glue->modify_wq(rxq_ctrl->obj->wq, &mod);
835 } else { /* rxq_ctrl->obj->type == MLX5_RXQ_OBJ_TYPE_DEVX_RQ. */
836 struct mlx5_devx_modify_rq_attr rq_attr;
838 memset(&rq_attr, 0, sizeof(rq_attr));
839 if (sm->state == IBV_WQS_RESET) {
840 rq_attr.rq_state = MLX5_RQC_STATE_ERR;
841 rq_attr.state = MLX5_RQC_STATE_RST;
842 } else if (sm->state == IBV_WQS_RDY) {
843 rq_attr.rq_state = MLX5_RQC_STATE_RST;
844 rq_attr.state = MLX5_RQC_STATE_RDY;
845 } else if (sm->state == IBV_WQS_ERR) {
846 rq_attr.rq_state = MLX5_RQC_STATE_RDY;
847 rq_attr.state = MLX5_RQC_STATE_ERR;
849 ret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq,
853 DRV_LOG(ERR, "Cannot change Rx WQ state to %u - %s\n",
854 sm->state, strerror(errno));
859 struct mlx5_txq_data *txq = (*priv->txqs)[sm->queue_id];
860 struct mlx5_txq_ctrl *txq_ctrl =
861 container_of(txq, struct mlx5_txq_ctrl, txq);
862 struct ibv_qp_attr mod = {
863 .qp_state = IBV_QPS_RESET,
864 .port_num = (uint8_t)priv->ibv_port,
866 struct ibv_qp *qp = txq_ctrl->ibv->qp;
868 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
870 DRV_LOG(ERR, "Cannot change the Tx QP state to RESET "
871 "%s\n", strerror(errno));
875 mod.qp_state = IBV_QPS_INIT;
876 ret = mlx5_glue->modify_qp(qp, &mod,
877 (IBV_QP_STATE | IBV_QP_PORT));
879 DRV_LOG(ERR, "Cannot change Tx QP state to INIT %s\n",
884 mod.qp_state = IBV_QPS_RTR;
885 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
887 DRV_LOG(ERR, "Cannot change Tx QP state to RTR %s\n",
892 mod.qp_state = IBV_QPS_RTS;
893 ret = mlx5_glue->modify_qp(qp, &mod, IBV_QP_STATE);
895 DRV_LOG(ERR, "Cannot change Tx QP state to RTS %s\n",
905 * Modify a Verbs queue state.
908 * Pointer to Ethernet device.
910 * State modify request parameters.
913 * 0 in case of success else non-zero value.
916 mlx5_queue_state_modify(struct rte_eth_dev *dev,
917 struct mlx5_mp_arg_queue_state_modify *sm)
921 switch (rte_eal_process_type()) {
922 case RTE_PROC_PRIMARY:
923 ret = mlx5_queue_state_modify_primary(dev, sm);
925 case RTE_PROC_SECONDARY:
926 ret = mlx5_mp_req_queue_state_modify(dev, sm);
936 * The function inserts the RQ state to reset when the first error CQE is
937 * shown, then drains the CQ by the caller function loop. When the CQ is empty,
938 * it moves the RQ state to ready and initializes the RQ.
939 * Next CQE identification and error counting are in the caller responsibility.
942 * Pointer to RX queue structure.
943 * @param[in] mbuf_prepare
944 * Whether to prepare mbufs for the RQ.
947 * -1 in case of recovery error, otherwise the CQE status.
950 mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t mbuf_prepare)
952 const uint16_t cqe_n = 1 << rxq->cqe_n;
953 const uint16_t cqe_mask = cqe_n - 1;
954 const unsigned int wqe_n = 1 << rxq->elts_n;
955 struct mlx5_rxq_ctrl *rxq_ctrl =
956 container_of(rxq, struct mlx5_rxq_ctrl, rxq);
958 volatile struct mlx5_cqe *cqe;
959 volatile struct mlx5_err_cqe *err_cqe;
961 .cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_mask],
963 struct mlx5_mp_arg_queue_state_modify sm;
966 switch (rxq->err_state) {
967 case MLX5_RXQ_ERR_STATE_NO_ERROR:
968 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_RESET;
970 case MLX5_RXQ_ERR_STATE_NEED_RESET:
972 sm.queue_id = rxq->idx;
973 sm.state = IBV_WQS_RESET;
974 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv), &sm))
976 if (rxq_ctrl->dump_file_n <
977 rxq_ctrl->priv->config.max_dump_files_num) {
978 MKSTR(err_str, "Unexpected CQE error syndrome "
979 "0x%02x CQN = %u RQN = %u wqe_counter = %u"
980 " rq_ci = %u cq_ci = %u", u.err_cqe->syndrome,
981 rxq->cqn, rxq_ctrl->wqn,
982 rte_be_to_cpu_16(u.err_cqe->wqe_counter),
983 rxq->rq_ci << rxq->sges_n, rxq->cq_ci);
984 MKSTR(name, "dpdk_mlx5_port_%u_rxq_%u_%u",
985 rxq->port_id, rxq->idx, (uint32_t)rte_rdtsc());
986 mlx5_dump_debug_information(name, NULL, err_str, 0);
987 mlx5_dump_debug_information(name, "MLX5 Error CQ:",
988 (const void *)((uintptr_t)
990 sizeof(*u.cqe) * cqe_n);
991 mlx5_dump_debug_information(name, "MLX5 Error RQ:",
992 (const void *)((uintptr_t)
995 rxq_ctrl->dump_file_n++;
997 rxq->err_state = MLX5_RXQ_ERR_STATE_NEED_READY;
999 case MLX5_RXQ_ERR_STATE_NEED_READY:
1000 ret = check_cqe(u.cqe, cqe_n, rxq->cq_ci);
1001 if (ret == MLX5_CQE_STATUS_HW_OWN) {
1003 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1006 * The RQ consumer index must be zeroed while moving
1007 * from RESET state to RDY state.
1009 *rxq->rq_db = rte_cpu_to_be_32(0);
1012 sm.queue_id = rxq->idx;
1013 sm.state = IBV_WQS_RDY;
1014 if (mlx5_queue_state_modify(ETH_DEV(rxq_ctrl->priv),
1018 const uint16_t q_mask = wqe_n - 1;
1020 struct rte_mbuf **elt;
1022 unsigned int n = wqe_n - (rxq->rq_ci -
1025 for (i = 0; i < (int)n; ++i) {
1026 elt_idx = (rxq->rq_ci + i) & q_mask;
1027 elt = &(*rxq->elts)[elt_idx];
1028 *elt = rte_mbuf_raw_alloc(rxq->mp);
1030 for (i--; i >= 0; --i) {
1031 elt_idx = (rxq->rq_ci +
1035 rte_pktmbuf_free_seg
1042 mlx5_rxq_initialize(rxq);
1043 rxq->err_state = MLX5_RXQ_ERR_STATE_NO_ERROR;
1052 * Get size of the next packet for a given CQE. For compressed CQEs, the
1053 * consumer index is updated only once all packets of the current one have
1057 * Pointer to RX queue.
1061 * Store pointer to mini-CQE if compressed. Otherwise, the pointer is not
1065 * 0 in case of empty CQE, otherwise the packet size in bytes.
1068 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1069 uint16_t cqe_cnt, volatile struct mlx5_mini_cqe8 **mcqe)
1071 struct rxq_zip *zip = &rxq->zip;
1072 uint16_t cqe_n = cqe_cnt + 1;
1078 /* Process compressed data in the CQE and mini arrays. */
1080 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1081 (volatile struct mlx5_mini_cqe8 (*)[8])
1082 (uintptr_t)(&(*rxq->cqes)[zip->ca &
1085 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1086 *mcqe = &(*mc)[zip->ai & 7];
1087 if ((++zip->ai & 7) == 0) {
1088 /* Invalidate consumed CQEs */
1091 while (idx != end) {
1092 (*rxq->cqes)[idx & cqe_cnt].op_own =
1093 MLX5_CQE_INVALIDATE;
1097 * Increment consumer index to skip the number
1098 * of CQEs consumed. Hardware leaves holes in
1099 * the CQ ring for software use.
1104 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1105 /* Invalidate the rest */
1109 while (idx != end) {
1110 (*rxq->cqes)[idx & cqe_cnt].op_own =
1111 MLX5_CQE_INVALIDATE;
1114 rxq->cq_ci = zip->cq_ci;
1118 * No compressed data, get next CQE and verify if it is
1125 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1126 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
1127 if (unlikely(ret == MLX5_CQE_STATUS_ERR ||
1129 ret = mlx5_rx_err_handle(rxq, 0);
1130 if (ret == MLX5_CQE_STATUS_HW_OWN ||
1138 op_own = cqe->op_own;
1139 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1140 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1141 (volatile struct mlx5_mini_cqe8 (*)[8])
1142 (uintptr_t)(&(*rxq->cqes)
1146 /* Fix endianness. */
1147 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1149 * Current mini array position is the one
1150 * returned by check_cqe64().
1152 * If completion comprises several mini arrays,
1153 * as a special case the second one is located
1154 * 7 CQEs after the initial CQE instead of 8
1155 * for subsequent ones.
1157 zip->ca = rxq->cq_ci;
1158 zip->na = zip->ca + 7;
1159 /* Compute the next non compressed CQE. */
1161 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1162 /* Get packet size to return. */
1163 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1166 /* Prefetch all to be invalidated */
1169 while (idx != end) {
1170 rte_prefetch0(&(*rxq->cqes)[(idx) &
1175 len = rte_be_to_cpu_32(cqe->byte_cnt);
1178 if (unlikely(rxq->err_state)) {
1179 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1180 ++rxq->stats.idropped;
1188 * Translate RX completion flags to offload flags.
1194 * Offload flags (ol_flags) for struct rte_mbuf.
1196 static inline uint32_t
1197 rxq_cq_to_ol_flags(volatile struct mlx5_cqe *cqe)
1199 uint32_t ol_flags = 0;
1200 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1204 MLX5_CQE_RX_L3_HDR_VALID,
1205 PKT_RX_IP_CKSUM_GOOD) |
1207 MLX5_CQE_RX_L4_HDR_VALID,
1208 PKT_RX_L4_CKSUM_GOOD);
1213 * Fill in mbuf fields from RX completion flags.
1214 * Note that pkt->ol_flags should be initialized outside of this function.
1217 * Pointer to RX queue.
1222 * @param rss_hash_res
1223 * Packet RSS Hash result.
1226 rxq_cq_to_mbuf(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt,
1227 volatile struct mlx5_cqe *cqe, uint32_t rss_hash_res)
1229 /* Update packet information. */
1230 pkt->packet_type = rxq_cq_to_pkt_type(rxq, cqe);
1231 if (rss_hash_res && rxq->rss_hash) {
1232 pkt->hash.rss = rss_hash_res;
1233 pkt->ol_flags |= PKT_RX_RSS_HASH;
1235 if (rxq->mark && MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1236 pkt->ol_flags |= PKT_RX_FDIR;
1237 if (cqe->sop_drop_qpn !=
1238 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1239 uint32_t mark = cqe->sop_drop_qpn;
1241 pkt->ol_flags |= PKT_RX_FDIR_ID;
1242 pkt->hash.fdir.hi = mlx5_flow_mark_get(mark);
1246 pkt->ol_flags |= rxq_cq_to_ol_flags(cqe);
1247 if (rxq->vlan_strip &&
1248 (cqe->hdr_type_etc & rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1249 pkt->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
1250 pkt->vlan_tci = rte_be_to_cpu_16(cqe->vlan_info);
1252 if (rxq->hw_timestamp) {
1253 pkt->timestamp = rte_be_to_cpu_64(cqe->timestamp);
1254 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1259 * DPDK callback for RX.
1262 * Generic pointer to RX queue structure.
1264 * Array to store received packets.
1266 * Maximum number of packets in array.
1269 * Number of packets successfully received (<= pkts_n).
1272 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1274 struct mlx5_rxq_data *rxq = dpdk_rxq;
1275 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1276 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1277 const unsigned int sges_n = rxq->sges_n;
1278 struct rte_mbuf *pkt = NULL;
1279 struct rte_mbuf *seg = NULL;
1280 volatile struct mlx5_cqe *cqe =
1281 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1283 unsigned int rq_ci = rxq->rq_ci << sges_n;
1284 int len = 0; /* keep its value across iterations. */
1287 unsigned int idx = rq_ci & wqe_cnt;
1288 volatile struct mlx5_wqe_data_seg *wqe =
1289 &((volatile struct mlx5_wqe_data_seg *)rxq->wqes)[idx];
1290 struct rte_mbuf *rep = (*rxq->elts)[idx];
1291 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1292 uint32_t rss_hash_res;
1300 rep = rte_mbuf_raw_alloc(rxq->mp);
1301 if (unlikely(rep == NULL)) {
1302 ++rxq->stats.rx_nombuf;
1305 * no buffers before we even started,
1306 * bail out silently.
1310 while (pkt != seg) {
1311 assert(pkt != (*rxq->elts)[idx]);
1315 rte_mbuf_raw_free(pkt);
1321 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1322 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt, &mcqe);
1324 rte_mbuf_raw_free(rep);
1328 assert(len >= (rxq->crc_present << 2));
1330 /* If compressed, take hash result from mini-CQE. */
1331 rss_hash_res = rte_be_to_cpu_32(mcqe == NULL ?
1333 mcqe->rx_hash_result);
1334 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1335 if (rxq->crc_present)
1336 len -= RTE_ETHER_CRC_LEN;
1338 if (cqe->lro_num_seg > 1) {
1340 (rte_pktmbuf_mtod(pkt, uint8_t *), cqe,
1342 pkt->ol_flags |= PKT_RX_LRO;
1343 pkt->tso_segsz = len / cqe->lro_num_seg;
1346 DATA_LEN(rep) = DATA_LEN(seg);
1347 PKT_LEN(rep) = PKT_LEN(seg);
1348 SET_DATA_OFF(rep, DATA_OFF(seg));
1349 PORT(rep) = PORT(seg);
1350 (*rxq->elts)[idx] = rep;
1352 * Fill NIC descriptor with the new buffer. The lkey and size
1353 * of the buffers are already known, only the buffer address
1356 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1357 /* If there's only one MR, no need to replace LKey in WQE. */
1358 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1359 wqe->lkey = mlx5_rx_mb2mr(rxq, rep);
1360 if (len > DATA_LEN(seg)) {
1361 len -= DATA_LEN(seg);
1366 DATA_LEN(seg) = len;
1367 #ifdef MLX5_PMD_SOFT_COUNTERS
1368 /* Increment bytes counter. */
1369 rxq->stats.ibytes += PKT_LEN(pkt);
1371 /* Return packet. */
1376 /* Align consumer index to the next stride. */
1381 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1383 /* Update the consumer index. */
1384 rxq->rq_ci = rq_ci >> sges_n;
1386 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1388 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1389 #ifdef MLX5_PMD_SOFT_COUNTERS
1390 /* Increment packets counter. */
1391 rxq->stats.ipackets += i;
1397 * Update LRO packet TCP header.
1398 * The HW LRO feature doesn't update the TCP header after coalescing the
1399 * TCP segments but supplies information in CQE to fill it by SW.
1402 * Pointer to the TCP header.
1404 * Pointer to the completion entry..
1406 * The L3 pseudo-header checksum.
1409 mlx5_lro_update_tcp_hdr(struct rte_tcp_hdr *restrict tcp,
1410 volatile struct mlx5_cqe *restrict cqe,
1413 uint8_t l4_type = (rte_be_to_cpu_16(cqe->hdr_type_etc) &
1414 MLX5_CQE_L4_TYPE_MASK) >> MLX5_CQE_L4_TYPE_SHIFT;
1416 * The HW calculates only the TCP payload checksum, need to complete
1417 * the TCP header checksum and the L3 pseudo-header checksum.
1419 uint32_t csum = phcsum + cqe->csum;
1421 if (l4_type == MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK ||
1422 l4_type == MLX5_L4_HDR_TYPE_TCP_WITH_ACL) {
1423 tcp->tcp_flags |= RTE_TCP_ACK_FLAG;
1424 tcp->recv_ack = cqe->lro_ack_seq_num;
1425 tcp->rx_win = cqe->lro_tcp_win;
1427 if (cqe->lro_tcppsh_abort_dupack & MLX5_CQE_LRO_PUSH_MASK)
1428 tcp->tcp_flags |= RTE_TCP_PSH_FLAG;
1430 csum += rte_raw_cksum(tcp, (tcp->data_off & 0xF) * 4);
1431 csum = ((csum & 0xffff0000) >> 16) + (csum & 0xffff);
1432 csum = (~csum) & 0xffff;
1439 * Update LRO packet headers.
1440 * The HW LRO feature doesn't update the L3/TCP headers after coalescing the
1441 * TCP segments but supply information in CQE to fill it by SW.
1444 * The packet address.
1446 * Pointer to the completion entry..
1448 * The packet length.
1451 mlx5_lro_update_hdr(uint8_t *restrict padd,
1452 volatile struct mlx5_cqe *restrict cqe,
1456 struct rte_ether_hdr *eth;
1457 struct rte_vlan_hdr *vlan;
1458 struct rte_ipv4_hdr *ipv4;
1459 struct rte_ipv6_hdr *ipv6;
1460 struct rte_tcp_hdr *tcp;
1465 uint16_t proto = h.eth->ether_type;
1469 while (proto == RTE_BE16(RTE_ETHER_TYPE_VLAN) ||
1470 proto == RTE_BE16(RTE_ETHER_TYPE_QINQ)) {
1471 proto = h.vlan->eth_proto;
1474 if (proto == RTE_BE16(RTE_ETHER_TYPE_IPV4)) {
1475 h.ipv4->time_to_live = cqe->lro_min_ttl;
1476 h.ipv4->total_length = rte_cpu_to_be_16(len - (h.hdr - padd));
1477 h.ipv4->hdr_checksum = 0;
1478 h.ipv4->hdr_checksum = rte_ipv4_cksum(h.ipv4);
1479 phcsum = rte_ipv4_phdr_cksum(h.ipv4, 0);
1482 h.ipv6->hop_limits = cqe->lro_min_ttl;
1483 h.ipv6->payload_len = rte_cpu_to_be_16(len - (h.hdr - padd) -
1485 phcsum = rte_ipv6_phdr_cksum(h.ipv6, 0);
1488 mlx5_lro_update_tcp_hdr(h.tcp, cqe, phcsum);
1492 mlx5_mprq_buf_free_cb(void *addr __rte_unused, void *opaque)
1494 struct mlx5_mprq_buf *buf = opaque;
1496 if (rte_atomic16_read(&buf->refcnt) == 1) {
1497 rte_mempool_put(buf->mp, buf);
1498 } else if (rte_atomic16_add_return(&buf->refcnt, -1) == 0) {
1499 rte_atomic16_set(&buf->refcnt, 1);
1500 rte_mempool_put(buf->mp, buf);
1505 mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf)
1507 mlx5_mprq_buf_free_cb(NULL, buf);
1511 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx,
1512 const unsigned int strd_n)
1514 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
1515 volatile struct mlx5_wqe_data_seg *wqe =
1516 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
1519 assert(rep != NULL);
1520 /* Replace MPRQ buf. */
1521 (*rxq->mprq_bufs)[rq_idx] = rep;
1523 addr = mlx5_mprq_buf_addr(rep, strd_n);
1524 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
1525 /* If there's only one MR, no need to replace LKey in WQE. */
1526 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
1527 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
1528 /* Stash a mbuf for next replacement. */
1529 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
1530 rxq->mprq_repl = rep;
1532 rxq->mprq_repl = NULL;
1536 * DPDK callback for RX with Multi-Packet RQ support.
1539 * Generic pointer to RX queue structure.
1541 * Array to store received packets.
1543 * Maximum number of packets in array.
1546 * Number of packets successfully received (<= pkts_n).
1549 mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1551 struct mlx5_rxq_data *rxq = dpdk_rxq;
1552 const unsigned int strd_n = 1 << rxq->strd_num_n;
1553 const unsigned int strd_sz = 1 << rxq->strd_sz_n;
1554 const unsigned int strd_shift =
1555 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
1556 const unsigned int cq_mask = (1 << rxq->cqe_n) - 1;
1557 const unsigned int wq_mask = (1 << rxq->elts_n) - 1;
1558 volatile struct mlx5_cqe *cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1560 uint32_t rq_ci = rxq->rq_ci;
1561 uint16_t consumed_strd = rxq->consumed_strd;
1562 uint16_t headroom_sz = rxq->strd_headroom_en * RTE_PKTMBUF_HEADROOM;
1563 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1565 while (i < pkts_n) {
1566 struct rte_mbuf *pkt;
1574 volatile struct mlx5_mini_cqe8 *mcqe = NULL;
1575 uint32_t rss_hash_res = 0;
1576 uint8_t lro_num_seg;
1578 if (consumed_strd == strd_n) {
1579 /* Replace WQE only if the buffer is still in use. */
1580 if (rte_atomic16_read(&buf->refcnt) > 1) {
1581 mprq_buf_replace(rxq, rq_ci & wq_mask, strd_n);
1582 /* Release the old buffer. */
1583 mlx5_mprq_buf_free(buf);
1584 } else if (unlikely(rxq->mprq_repl == NULL)) {
1585 struct mlx5_mprq_buf *rep;
1588 * Currently, the MPRQ mempool is out of buffer
1589 * and doing memcpy regardless of the size of Rx
1590 * packet. Retry allocation to get back to
1593 if (!rte_mempool_get(rxq->mprq_mp,
1595 rxq->mprq_repl = rep;
1597 /* Advance to the next WQE. */
1600 buf = (*rxq->mprq_bufs)[rq_ci & wq_mask];
1602 cqe = &(*rxq->cqes)[rxq->cq_ci & cq_mask];
1603 ret = mlx5_rx_poll_len(rxq, cqe, cq_mask, &mcqe);
1607 strd_cnt = (byte_cnt & MLX5_MPRQ_STRIDE_NUM_MASK) >>
1608 MLX5_MPRQ_STRIDE_NUM_SHIFT;
1610 consumed_strd += strd_cnt;
1611 if (byte_cnt & MLX5_MPRQ_FILLER_MASK)
1614 rss_hash_res = rte_be_to_cpu_32(cqe->rx_hash_res);
1615 strd_idx = rte_be_to_cpu_16(cqe->wqe_counter);
1617 /* mini-CQE for MPRQ doesn't have hash result. */
1618 strd_idx = rte_be_to_cpu_16(mcqe->stride_idx);
1620 assert(strd_idx < strd_n);
1621 assert(!((rte_be_to_cpu_16(cqe->wqe_id) ^ rq_ci) & wq_mask));
1622 lro_num_seg = cqe->lro_num_seg;
1624 * Currently configured to receive a packet per a stride. But if
1625 * MTU is adjusted through kernel interface, device could
1626 * consume multiple strides without raising an error. In this
1627 * case, the packet should be dropped because it is bigger than
1628 * the max_rx_pkt_len.
1630 if (unlikely(!lro_num_seg && strd_cnt > 1)) {
1631 ++rxq->stats.idropped;
1634 pkt = rte_pktmbuf_alloc(rxq->mp);
1635 if (unlikely(pkt == NULL)) {
1636 ++rxq->stats.rx_nombuf;
1639 len = (byte_cnt & MLX5_MPRQ_LEN_MASK) >> MLX5_MPRQ_LEN_SHIFT;
1640 assert((int)len >= (rxq->crc_present << 2));
1641 if (rxq->crc_present)
1642 len -= RTE_ETHER_CRC_LEN;
1643 offset = strd_idx * strd_sz + strd_shift;
1644 addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
1646 * Memcpy packets to the target mbuf if:
1647 * - The size of packet is smaller than mprq_max_memcpy_len.
1648 * - Out of buffer in the Mempool for Multi-Packet RQ.
1650 if (len <= rxq->mprq_max_memcpy_len || rxq->mprq_repl == NULL) {
1652 * When memcpy'ing packet due to out-of-buffer, the
1653 * packet must be smaller than the target mbuf.
1655 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1656 rte_pktmbuf_free_seg(pkt);
1657 ++rxq->stats.idropped;
1660 rte_memcpy(rte_pktmbuf_mtod(pkt, void *), addr, len);
1661 DATA_LEN(pkt) = len;
1663 rte_iova_t buf_iova;
1664 struct rte_mbuf_ext_shared_info *shinfo;
1665 uint16_t buf_len = strd_cnt * strd_sz;
1668 /* Increment the refcnt of the whole chunk. */
1669 rte_atomic16_add_return(&buf->refcnt, 1);
1670 assert((uint16_t)rte_atomic16_read(&buf->refcnt) <=
1672 buf_addr = RTE_PTR_SUB(addr, headroom_sz);
1674 * MLX5 device doesn't use iova but it is necessary in a
1675 * case where the Rx packet is transmitted via a
1678 buf_iova = rte_mempool_virt2iova(buf) +
1679 RTE_PTR_DIFF(buf_addr, buf);
1680 shinfo = &buf->shinfos[strd_idx];
1681 rte_mbuf_ext_refcnt_set(shinfo, 1);
1683 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
1684 * attaching the stride to mbuf and more offload flags
1685 * will be added below by calling rxq_cq_to_mbuf().
1686 * Other fields will be overwritten.
1688 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
1690 /* Set mbuf head-room. */
1691 pkt->data_off = headroom_sz;
1692 assert(pkt->ol_flags == EXT_ATTACHED_MBUF);
1694 * Prevent potential overflow due to MTU change through
1697 if (unlikely(rte_pktmbuf_tailroom(pkt) < len)) {
1698 rte_pktmbuf_free_seg(pkt);
1699 ++rxq->stats.idropped;
1702 DATA_LEN(pkt) = len;
1704 * LRO packet may consume all the stride memory, in this
1705 * case packet head-room space is not guaranteed so must
1706 * to add an empty mbuf for the head-room.
1708 if (!rxq->strd_headroom_en) {
1709 struct rte_mbuf *headroom_mbuf =
1710 rte_pktmbuf_alloc(rxq->mp);
1712 if (unlikely(headroom_mbuf == NULL)) {
1713 rte_pktmbuf_free_seg(pkt);
1714 ++rxq->stats.rx_nombuf;
1717 PORT(pkt) = rxq->port_id;
1718 NEXT(headroom_mbuf) = pkt;
1719 pkt = headroom_mbuf;
1723 rxq_cq_to_mbuf(rxq, pkt, cqe, rss_hash_res);
1724 if (lro_num_seg > 1) {
1725 mlx5_lro_update_hdr(addr, cqe, len);
1726 pkt->ol_flags |= PKT_RX_LRO;
1727 pkt->tso_segsz = strd_sz;
1730 PORT(pkt) = rxq->port_id;
1731 #ifdef MLX5_PMD_SOFT_COUNTERS
1732 /* Increment bytes counter. */
1733 rxq->stats.ibytes += PKT_LEN(pkt);
1735 /* Return packet. */
1739 /* Update the consumer indexes. */
1740 rxq->consumed_strd = consumed_strd;
1742 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1743 if (rq_ci != rxq->rq_ci) {
1746 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1748 #ifdef MLX5_PMD_SOFT_COUNTERS
1749 /* Increment packets counter. */
1750 rxq->stats.ipackets += i;
1756 * Dummy DPDK callback for TX.
1758 * This function is used to temporarily replace the real callback during
1759 * unsafe control operations on the queue, or in case of error.
1762 * Generic pointer to TX queue structure.
1764 * Packets to transmit.
1766 * Number of packets in array.
1769 * Number of packets successfully transmitted (<= pkts_n).
1772 removed_tx_burst(void *dpdk_txq __rte_unused,
1773 struct rte_mbuf **pkts __rte_unused,
1774 uint16_t pkts_n __rte_unused)
1781 * Dummy DPDK callback for RX.
1783 * This function is used to temporarily replace the real callback during
1784 * unsafe control operations on the queue, or in case of error.
1787 * Generic pointer to RX queue structure.
1789 * Array to store received packets.
1791 * Maximum number of packets in array.
1794 * Number of packets successfully received (<= pkts_n).
1797 removed_rx_burst(void *dpdk_txq __rte_unused,
1798 struct rte_mbuf **pkts __rte_unused,
1799 uint16_t pkts_n __rte_unused)
1806 * Vectorized Rx/Tx routines are not compiled in when required vector
1807 * instructions are not supported on a target architecture. The following null
1808 * stubs are needed for linkage when those are not included outside of this file
1809 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1813 mlx5_rx_burst_vec(void *dpdk_txq __rte_unused,
1814 struct rte_mbuf **pkts __rte_unused,
1815 uint16_t pkts_n __rte_unused)
1821 mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq __rte_unused)
1827 mlx5_check_vec_rx_support(struct rte_eth_dev *dev __rte_unused)
1833 * Free the mbufs from the linear array of pointers.
1836 * Pointer to array of packets to be free.
1838 * Number of packets to be freed.
1840 * Configured Tx offloads mask. It is fully defined at
1841 * compile time and may be used for optimization.
1843 static __rte_always_inline void
1844 mlx5_tx_free_mbuf(struct rte_mbuf **restrict pkts,
1845 unsigned int pkts_n,
1846 unsigned int olx __rte_unused)
1848 struct rte_mempool *pool = NULL;
1849 struct rte_mbuf **p_free = NULL;
1850 struct rte_mbuf *mbuf;
1851 unsigned int n_free = 0;
1854 * The implemented algorithm eliminates
1855 * copying pointers to temporary array
1856 * for rte_mempool_put_bulk() calls.
1863 * Decrement mbuf reference counter, detach
1864 * indirect and external buffers if needed.
1866 mbuf = rte_pktmbuf_prefree_seg(*pkts);
1867 if (likely(mbuf != NULL)) {
1868 assert(mbuf == *pkts);
1869 if (likely(n_free != 0)) {
1870 if (unlikely(pool != mbuf->pool))
1871 /* From different pool. */
1874 /* Start new scan array. */
1881 if (unlikely(pkts_n == 0)) {
1887 * This happens if mbuf is still referenced.
1888 * We can't put it back to the pool, skip.
1892 if (unlikely(n_free != 0))
1893 /* There is some array to free.*/
1895 if (unlikely(pkts_n == 0))
1896 /* Last mbuf, nothing to free. */
1902 * This loop is implemented to avoid multiple
1903 * inlining of rte_mempool_put_bulk().
1909 * Free the array of pre-freed mbufs
1910 * belonging to the same memory pool.
1912 rte_mempool_put_bulk(pool, (void *)p_free, n_free);
1913 if (unlikely(mbuf != NULL)) {
1914 /* There is the request to start new scan. */
1919 if (likely(pkts_n != 0))
1922 * This is the last mbuf to be freed.
1923 * Do one more loop iteration to complete.
1924 * This is rare case of the last unique mbuf.
1929 if (likely(pkts_n == 0))
1938 * Free the mbuf from the elts ring buffer till new tail.
1941 * Pointer to Tx queue structure.
1943 * Index in elts to free up to, becomes new elts tail.
1945 * Configured Tx offloads mask. It is fully defined at
1946 * compile time and may be used for optimization.
1948 static __rte_always_inline void
1949 mlx5_tx_free_elts(struct mlx5_txq_data *restrict txq,
1951 unsigned int olx __rte_unused)
1953 uint16_t n_elts = tail - txq->elts_tail;
1956 assert(n_elts <= txq->elts_s);
1958 * Implement a loop to support ring buffer wraparound
1959 * with single inlining of mlx5_tx_free_mbuf().
1964 part = txq->elts_s - (txq->elts_tail & txq->elts_m);
1965 part = RTE_MIN(part, n_elts);
1967 assert(part <= txq->elts_s);
1968 mlx5_tx_free_mbuf(&txq->elts[txq->elts_tail & txq->elts_m],
1970 txq->elts_tail += part;
1976 * Store the mbuf being sent into elts ring buffer.
1977 * On Tx completion these mbufs will be freed.
1980 * Pointer to Tx queue structure.
1982 * Pointer to array of packets to be stored.
1984 * Number of packets to be stored.
1986 * Configured Tx offloads mask. It is fully defined at
1987 * compile time and may be used for optimization.
1989 static __rte_always_inline void
1990 mlx5_tx_copy_elts(struct mlx5_txq_data *restrict txq,
1991 struct rte_mbuf **restrict pkts,
1992 unsigned int pkts_n,
1993 unsigned int olx __rte_unused)
1996 struct rte_mbuf **elts = (struct rte_mbuf **)txq->elts;
2000 part = txq->elts_s - (txq->elts_head & txq->elts_m);
2002 assert(part <= txq->elts_s);
2003 /* This code is a good candidate for vectorizing with SIMD. */
2004 rte_memcpy((void *)(elts + (txq->elts_head & txq->elts_m)),
2006 RTE_MIN(part, pkts_n) * sizeof(struct rte_mbuf *));
2007 txq->elts_head += pkts_n;
2008 if (unlikely(part < pkts_n))
2009 /* The copy is wrapping around the elts array. */
2010 rte_memcpy((void *)elts, (void *)(pkts + part),
2011 (pkts_n - part) * sizeof(struct rte_mbuf *));
2015 * Update completion queue consuming index via doorbell
2016 * and flush the completed data buffers.
2019 * Pointer to TX queue structure.
2020 * @param valid CQE pointer
2021 * if not NULL update txq->wqe_pi and flush the buffers
2023 * if not negative - flush the buffers till this index.
2025 * Configured Tx offloads mask. It is fully defined at
2026 * compile time and may be used for optimization.
2028 static __rte_always_inline void
2029 mlx5_tx_comp_flush(struct mlx5_txq_data *restrict txq,
2030 volatile struct mlx5_cqe *last_cqe,
2032 unsigned int olx __rte_unused)
2036 if (likely(last_cqe != NULL)) {
2037 txq->wqe_pi = rte_be_to_cpu_16(last_cqe->wqe_counter);
2038 tail = ((volatile struct mlx5_wqe_cseg *)
2039 (txq->wqes + (txq->wqe_pi & txq->wqe_m)))->misc;
2040 } else if (itail >= 0) {
2041 tail = (uint16_t)itail;
2045 rte_compiler_barrier();
2046 *txq->cq_db = rte_cpu_to_be_32(txq->cq_ci);
2047 if (likely(tail != txq->elts_tail)) {
2048 mlx5_tx_free_elts(txq, tail, olx);
2049 assert(tail == txq->elts_tail);
2054 * Manage TX completions. This routine checks the CQ for
2055 * arrived CQEs, deduces the last accomplished WQE in SQ,
2056 * updates SQ producing index and frees all completed mbufs.
2059 * Pointer to TX queue structure.
2061 * Configured Tx offloads mask. It is fully defined at
2062 * compile time and may be used for optimization.
2064 * NOTE: not inlined intentionally, it makes tx_burst
2065 * routine smaller, simple and faster - from experiments.
2068 mlx5_tx_handle_completion(struct mlx5_txq_data *restrict txq,
2069 unsigned int olx __rte_unused)
2071 unsigned int count = MLX5_TX_COMP_MAX_CQE;
2072 volatile struct mlx5_cqe *last_cqe = NULL;
2075 static_assert(MLX5_CQE_STATUS_HW_OWN < 0, "Must be negative value");
2076 static_assert(MLX5_CQE_STATUS_SW_OWN < 0, "Must be negative value");
2078 volatile struct mlx5_cqe *cqe;
2080 cqe = &txq->cqes[txq->cq_ci & txq->cqe_m];
2081 ret = check_cqe(cqe, txq->cqe_s, txq->cq_ci);
2082 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
2083 if (likely(ret != MLX5_CQE_STATUS_ERR)) {
2084 /* No new CQEs in completion queue. */
2085 assert(ret == MLX5_CQE_STATUS_HW_OWN);
2089 * Some error occurred, try to restart.
2090 * We have no barrier after WQE related Doorbell
2091 * written, make sure all writes are completed
2092 * here, before we might perform SQ reset.
2095 ret = mlx5_tx_error_cqe_handle
2096 (txq, (volatile struct mlx5_err_cqe *)cqe);
2098 * Flush buffers, update consuming index
2099 * if recovery succeeded. Otherwise
2100 * just try to recover later.
2105 /* Normal transmit completion. */
2113 * We have to restrict the amount of processed CQEs
2114 * in one tx_burst routine call. The CQ may be large
2115 * and many CQEs may be updated by the NIC in one
2116 * transaction. Buffers freeing is time consuming,
2117 * multiple iterations may introduce significant
2121 mlx5_tx_comp_flush(txq, last_cqe, ret, olx);
2125 * Check if the completion request flag should be set in the last WQE.
2126 * Both pushed mbufs and WQEs are monitored and the completion request
2127 * flag is set if any of thresholds is reached.
2130 * Pointer to TX queue structure.
2132 * Pointer to burst routine local context.
2134 * Configured Tx offloads mask. It is fully defined at
2135 * compile time and may be used for optimization.
2137 static __rte_always_inline void
2138 mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
2139 struct mlx5_txq_local *restrict loc,
2142 uint16_t head = txq->elts_head;
2145 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc->pkts_sent - loc->pkts_copy;
2147 if ((uint16_t)(head - txq->elts_comp) >= MLX5_TX_COMP_THRESH ||
2148 (MLX5_TXOFF_CONFIG(INLINE) &&
2149 (uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
2150 volatile struct mlx5_wqe *last = loc->wqe_last;
2152 txq->elts_comp = head;
2153 if (MLX5_TXOFF_CONFIG(INLINE))
2154 txq->wqe_comp = txq->wqe_ci;
2155 /* Request unconditional completion on last WQE. */
2156 last->cseg.flags = RTE_BE32(MLX5_COMP_ALWAYS <<
2157 MLX5_COMP_MODE_OFFSET);
2158 /* Save elts_head in unused "immediate" field of WQE. */
2159 last->cseg.misc = head;
2161 * A CQE slot must always be available. Count the
2162 * issued CEQ "always" request instead of production
2163 * index due to here can be CQE with errors and
2164 * difference with ci may become inconsistent.
2166 assert(txq->cqe_s > ++txq->cq_pi);
2171 * DPDK callback to check the status of a tx descriptor.
2176 * The index of the descriptor in the ring.
2179 * The status of the tx descriptor.
2182 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
2184 struct mlx5_txq_data *restrict txq = tx_queue;
2187 mlx5_tx_handle_completion(txq, 0);
2188 used = txq->elts_head - txq->elts_tail;
2190 return RTE_ETH_TX_DESC_FULL;
2191 return RTE_ETH_TX_DESC_DONE;
2195 * Build the Control Segment with specified opcode:
2196 * - MLX5_OPCODE_SEND
2197 * - MLX5_OPCODE_ENHANCED_MPSW
2201 * Pointer to TX queue structure.
2203 * Pointer to burst routine local context.
2205 * Pointer to WQE to fill with built Control Segment.
2207 * Supposed length of WQE in segments.
2209 * SQ WQE opcode to put into Control Segment.
2211 * Configured Tx offloads mask. It is fully defined at
2212 * compile time and may be used for optimization.
2214 static __rte_always_inline void
2215 mlx5_tx_cseg_init(struct mlx5_txq_data *restrict txq,
2216 struct mlx5_txq_local *restrict loc __rte_unused,
2217 struct mlx5_wqe *restrict wqe,
2219 unsigned int opcode,
2220 unsigned int olx __rte_unused)
2222 struct mlx5_wqe_cseg *restrict cs = &wqe->cseg;
2224 cs->opcode = rte_cpu_to_be_32((txq->wqe_ci << 8) | opcode);
2225 cs->sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
2226 cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR <<
2227 MLX5_COMP_MODE_OFFSET);
2228 cs->misc = RTE_BE32(0);
2232 * Build the Ethernet Segment without inlined data.
2233 * Supports Software Parser, Checksums and VLAN
2234 * insertion Tx offload features.
2237 * Pointer to TX queue structure.
2239 * Pointer to burst routine local context.
2241 * Pointer to WQE to fill with built Ethernet Segment.
2243 * Configured Tx offloads mask. It is fully defined at
2244 * compile time and may be used for optimization.
2246 static __rte_always_inline void
2247 mlx5_tx_eseg_none(struct mlx5_txq_data *restrict txq __rte_unused,
2248 struct mlx5_txq_local *restrict loc,
2249 struct mlx5_wqe *restrict wqe,
2252 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2256 * Calculate and set check sum flags first, dword field
2257 * in segment may be shared with Software Parser flags.
2259 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2260 es->flags = rte_cpu_to_le_32(csum);
2262 * Calculate and set Software Parser offsets and flags.
2263 * These flags a set for custom UDP and IP tunnel packets.
2265 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2266 /* Fill metadata field if needed. */
2267 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2268 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2269 loc->mbuf->tx_metadata : 0 : 0;
2270 /* Engage VLAN tag insertion feature if requested. */
2271 if (MLX5_TXOFF_CONFIG(VLAN) &&
2272 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
2274 * We should get here only if device support
2275 * this feature correctly.
2277 assert(txq->vlan_en);
2278 es->inline_hdr = rte_cpu_to_be_32(MLX5_ETH_WQE_VLAN_INSERT |
2279 loc->mbuf->vlan_tci);
2281 es->inline_hdr = RTE_BE32(0);
2286 * Build the Ethernet Segment with minimal inlined data
2287 * of MLX5_ESEG_MIN_INLINE_SIZE bytes length. This is
2288 * used to fill the gap in single WQEBB WQEs.
2289 * Supports Software Parser, Checksums and VLAN
2290 * insertion Tx offload features.
2293 * Pointer to TX queue structure.
2295 * Pointer to burst routine local context.
2297 * Pointer to WQE to fill with built Ethernet Segment.
2299 * Length of VLAN tag insertion if any.
2301 * Configured Tx offloads mask. It is fully defined at
2302 * compile time and may be used for optimization.
2304 static __rte_always_inline void
2305 mlx5_tx_eseg_dmin(struct mlx5_txq_data *restrict txq __rte_unused,
2306 struct mlx5_txq_local *restrict loc,
2307 struct mlx5_wqe *restrict wqe,
2311 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2313 uint8_t *psrc, *pdst;
2316 * Calculate and set check sum flags first, dword field
2317 * in segment may be shared with Software Parser flags.
2319 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2320 es->flags = rte_cpu_to_le_32(csum);
2322 * Calculate and set Software Parser offsets and flags.
2323 * These flags a set for custom UDP and IP tunnel packets.
2325 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2326 /* Fill metadata field if needed. */
2327 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2328 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2329 loc->mbuf->tx_metadata : 0 : 0;
2330 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2332 sizeof(rte_v128u32_t)),
2333 "invalid Ethernet Segment data size");
2334 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2336 sizeof(struct rte_vlan_hdr) +
2337 2 * RTE_ETHER_ADDR_LEN),
2338 "invalid Ethernet Segment data size");
2339 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2340 es->inline_hdr_sz = RTE_BE16(MLX5_ESEG_MIN_INLINE_SIZE);
2341 es->inline_data = *(unaligned_uint16_t *)psrc;
2342 psrc += sizeof(uint16_t);
2343 pdst = (uint8_t *)(es + 1);
2344 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2345 /* Implement VLAN tag insertion as part inline data. */
2346 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2347 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2348 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2349 /* Insert VLAN ethertype + VLAN tag. */
2350 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2351 ((RTE_ETHER_TYPE_VLAN << 16) |
2352 loc->mbuf->vlan_tci);
2353 pdst += sizeof(struct rte_vlan_hdr);
2354 /* Copy the rest two bytes from packet data. */
2355 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2356 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2358 /* Fill the gap in the title WQEBB with inline data. */
2359 rte_mov16(pdst, psrc);
2364 * Build the Ethernet Segment with entire packet
2365 * data inlining. Checks the boundary of WQEBB and
2366 * ring buffer wrapping, supports Software Parser,
2367 * Checksums and VLAN insertion Tx offload features.
2370 * Pointer to TX queue structure.
2372 * Pointer to burst routine local context.
2374 * Pointer to WQE to fill with built Ethernet Segment.
2376 * Length of VLAN tag insertion if any.
2378 * Length of data to inline (VLAN included, if any).
2380 * TSO flag, set mss field from the packet.
2382 * Configured Tx offloads mask. It is fully defined at
2383 * compile time and may be used for optimization.
2386 * Pointer to the next Data Segment (aligned and wrapped around).
2388 static __rte_always_inline struct mlx5_wqe_dseg *
2389 mlx5_tx_eseg_data(struct mlx5_txq_data *restrict txq,
2390 struct mlx5_txq_local *restrict loc,
2391 struct mlx5_wqe *restrict wqe,
2397 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2399 uint8_t *psrc, *pdst;
2403 * Calculate and set check sum flags first, dword field
2404 * in segment may be shared with Software Parser flags.
2406 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2409 csum |= loc->mbuf->tso_segsz;
2410 es->flags = rte_cpu_to_be_32(csum);
2412 es->flags = rte_cpu_to_le_32(csum);
2415 * Calculate and set Software Parser offsets and flags.
2416 * These flags a set for custom UDP and IP tunnel packets.
2418 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2419 /* Fill metadata field if needed. */
2420 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2421 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2422 loc->mbuf->tx_metadata : 0 : 0;
2423 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2425 sizeof(rte_v128u32_t)),
2426 "invalid Ethernet Segment data size");
2427 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2429 sizeof(struct rte_vlan_hdr) +
2430 2 * RTE_ETHER_ADDR_LEN),
2431 "invalid Ethernet Segment data size");
2432 psrc = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
2433 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2434 es->inline_data = *(unaligned_uint16_t *)psrc;
2435 psrc += sizeof(uint16_t);
2436 pdst = (uint8_t *)(es + 1);
2437 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2438 /* Implement VLAN tag insertion as part inline data. */
2439 memcpy(pdst, psrc, 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t));
2440 pdst += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2441 psrc += 2 * RTE_ETHER_ADDR_LEN - sizeof(uint16_t);
2442 /* Insert VLAN ethertype + VLAN tag. */
2443 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2444 ((RTE_ETHER_TYPE_VLAN << 16) |
2445 loc->mbuf->vlan_tci);
2446 pdst += sizeof(struct rte_vlan_hdr);
2447 /* Copy the rest two bytes from packet data. */
2448 assert(pdst == RTE_PTR_ALIGN(pdst, sizeof(uint16_t)));
2449 *(uint16_t *)pdst = *(unaligned_uint16_t *)psrc;
2450 psrc += sizeof(uint16_t);
2452 /* Fill the gap in the title WQEBB with inline data. */
2453 rte_mov16(pdst, psrc);
2454 psrc += sizeof(rte_v128u32_t);
2456 pdst = (uint8_t *)(es + 2);
2457 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2458 assert(pdst < (uint8_t *)txq->wqes_end);
2459 inlen -= MLX5_ESEG_MIN_INLINE_SIZE;
2461 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2462 return (struct mlx5_wqe_dseg *)pdst;
2465 * The WQEBB space availability is checked by caller.
2466 * Here we should be aware of WQE ring buffer wraparound only.
2468 part = (uint8_t *)txq->wqes_end - pdst;
2469 part = RTE_MIN(part, inlen);
2471 rte_memcpy(pdst, psrc, part);
2473 if (likely(!inlen)) {
2475 * If return value is not used by the caller
2476 * the code below will be optimized out.
2479 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2480 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2481 pdst = (uint8_t *)txq->wqes;
2482 return (struct mlx5_wqe_dseg *)pdst;
2484 pdst = (uint8_t *)txq->wqes;
2491 * Copy data from chain of mbuf to the specified linear buffer.
2492 * Checksums and VLAN insertion Tx offload features. If data
2493 * from some mbuf copied completely this mbuf is freed. Local
2494 * structure is used to keep the byte stream state.
2497 * Pointer to the destination linear buffer.
2499 * Pointer to burst routine local context.
2501 * Length of data to be copied.
2503 * Configured Tx offloads mask. It is fully defined at
2504 * compile time and may be used for optimization.
2506 static __rte_always_inline void
2507 mlx5_tx_mseg_memcpy(uint8_t *pdst,
2508 struct mlx5_txq_local *restrict loc,
2510 unsigned int olx __rte_unused)
2512 struct rte_mbuf *mbuf;
2513 unsigned int part, dlen;
2518 /* Allow zero length packets, must check first. */
2519 dlen = rte_pktmbuf_data_len(loc->mbuf);
2520 if (dlen <= loc->mbuf_off) {
2521 /* Exhausted packet, just free. */
2523 loc->mbuf = mbuf->next;
2524 rte_pktmbuf_free_seg(mbuf);
2526 assert(loc->mbuf_nseg > 1);
2531 dlen -= loc->mbuf_off;
2532 psrc = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2534 part = RTE_MIN(len, dlen);
2535 rte_memcpy(pdst, psrc, part);
2536 loc->mbuf_off += part;
2539 if (loc->mbuf_off >= rte_pktmbuf_data_len(loc->mbuf)) {
2541 /* Exhausted packet, just free. */
2543 loc->mbuf = mbuf->next;
2544 rte_pktmbuf_free_seg(mbuf);
2546 assert(loc->mbuf_nseg >= 1);
2556 * Build the Ethernet Segment with inlined data from
2557 * multi-segment packet. Checks the boundary of WQEBB
2558 * and ring buffer wrapping, supports Software Parser,
2559 * Checksums and VLAN insertion Tx offload features.
2562 * Pointer to TX queue structure.
2564 * Pointer to burst routine local context.
2566 * Pointer to WQE to fill with built Ethernet Segment.
2568 * Length of VLAN tag insertion if any.
2570 * Length of data to inline (VLAN included, if any).
2572 * TSO flag, set mss field from the packet.
2574 * Configured Tx offloads mask. It is fully defined at
2575 * compile time and may be used for optimization.
2578 * Pointer to the next Data Segment (aligned and
2579 * possible NOT wrapped around - caller should do
2580 * wrapping check on its own).
2582 static __rte_always_inline struct mlx5_wqe_dseg *
2583 mlx5_tx_eseg_mdat(struct mlx5_txq_data *restrict txq,
2584 struct mlx5_txq_local *restrict loc,
2585 struct mlx5_wqe *restrict wqe,
2591 struct mlx5_wqe_eseg *restrict es = &wqe->eseg;
2597 * Calculate and set check sum flags first, uint32_t field
2598 * in segment may be shared with Software Parser flags.
2600 csum = MLX5_TXOFF_CONFIG(CSUM) ? txq_ol_cksum_to_cs(loc->mbuf) : 0;
2603 csum |= loc->mbuf->tso_segsz;
2604 es->flags = rte_cpu_to_be_32(csum);
2606 es->flags = rte_cpu_to_le_32(csum);
2609 * Calculate and set Software Parser offsets and flags.
2610 * These flags a set for custom UDP and IP tunnel packets.
2612 es->swp_offs = txq_mbuf_to_swp(loc, &es->swp_flags, olx);
2613 /* Fill metadata field if needed. */
2614 es->metadata = MLX5_TXOFF_CONFIG(METADATA) ?
2615 loc->mbuf->ol_flags & PKT_TX_METADATA ?
2616 loc->mbuf->tx_metadata : 0 : 0;
2617 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2619 sizeof(rte_v128u32_t)),
2620 "invalid Ethernet Segment data size");
2621 static_assert(MLX5_ESEG_MIN_INLINE_SIZE ==
2623 sizeof(struct rte_vlan_hdr) +
2624 2 * RTE_ETHER_ADDR_LEN),
2625 "invalid Ethernet Segment data size");
2626 assert(inlen >= MLX5_ESEG_MIN_INLINE_SIZE);
2627 es->inline_hdr_sz = rte_cpu_to_be_16(inlen);
2628 pdst = (uint8_t *)&es->inline_data;
2629 if (MLX5_TXOFF_CONFIG(VLAN) && vlan) {
2630 /* Implement VLAN tag insertion as part inline data. */
2631 mlx5_tx_mseg_memcpy(pdst, loc, 2 * RTE_ETHER_ADDR_LEN, olx);
2632 pdst += 2 * RTE_ETHER_ADDR_LEN;
2633 *(unaligned_uint32_t *)pdst = rte_cpu_to_be_32
2634 ((RTE_ETHER_TYPE_VLAN << 16) |
2635 loc->mbuf->vlan_tci);
2636 pdst += sizeof(struct rte_vlan_hdr);
2637 inlen -= 2 * RTE_ETHER_ADDR_LEN + sizeof(struct rte_vlan_hdr);
2639 assert(pdst < (uint8_t *)txq->wqes_end);
2641 * The WQEBB space availability is checked by caller.
2642 * Here we should be aware of WQE ring buffer wraparound only.
2644 part = (uint8_t *)txq->wqes_end - pdst;
2645 part = RTE_MIN(part, inlen);
2648 mlx5_tx_mseg_memcpy(pdst, loc, part, olx);
2650 if (likely(!inlen)) {
2652 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2653 return (struct mlx5_wqe_dseg *)pdst;
2655 pdst = (uint8_t *)txq->wqes;
2661 * Build the Data Segment of pointer type.
2664 * Pointer to TX queue structure.
2666 * Pointer to burst routine local context.
2668 * Pointer to WQE to fill with built Data Segment.
2670 * Data buffer to point.
2672 * Data buffer length.
2674 * Configured Tx offloads mask. It is fully defined at
2675 * compile time and may be used for optimization.
2677 static __rte_always_inline void
2678 mlx5_tx_dseg_ptr(struct mlx5_txq_data *restrict txq,
2679 struct mlx5_txq_local *restrict loc,
2680 struct mlx5_wqe_dseg *restrict dseg,
2683 unsigned int olx __rte_unused)
2687 dseg->bcount = rte_cpu_to_be_32(len);
2688 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2689 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2693 * Build the Data Segment of pointer type or inline
2694 * if data length is less than buffer in minimal
2695 * Data Segment size.
2698 * Pointer to TX queue structure.
2700 * Pointer to burst routine local context.
2702 * Pointer to WQE to fill with built Data Segment.
2704 * Data buffer to point.
2706 * Data buffer length.
2708 * Configured Tx offloads mask. It is fully defined at
2709 * compile time and may be used for optimization.
2711 static __rte_always_inline void
2712 mlx5_tx_dseg_iptr(struct mlx5_txq_data *restrict txq,
2713 struct mlx5_txq_local *restrict loc,
2714 struct mlx5_wqe_dseg *restrict dseg,
2717 unsigned int olx __rte_unused)
2723 if (len > MLX5_DSEG_MIN_INLINE_SIZE) {
2724 dseg->bcount = rte_cpu_to_be_32(len);
2725 dseg->lkey = mlx5_tx_mb2mr(txq, loc->mbuf);
2726 dseg->pbuf = rte_cpu_to_be_64((uintptr_t)buf);
2730 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2731 /* Unrolled implementation of generic rte_memcpy. */
2732 dst = (uintptr_t)&dseg->inline_data[0];
2733 src = (uintptr_t)buf;
2734 #ifdef RTE_ARCH_STRICT_ALIGN
2735 memcpy(dst, src, len);
2738 *(uint64_t *)dst = *(uint64_t *)src;
2739 dst += sizeof(uint64_t);
2740 src += sizeof(uint64_t);
2743 *(uint32_t *)dst = *(uint32_t *)src;
2744 dst += sizeof(uint32_t);
2745 src += sizeof(uint32_t);
2748 *(uint16_t *)dst = *(uint16_t *)src;
2749 dst += sizeof(uint16_t);
2750 src += sizeof(uint16_t);
2753 *(uint8_t *)dst = *(uint8_t *)src;
2758 * Build the Data Segment of inlined data from single
2759 * segment packet, no VLAN insertion.
2762 * Pointer to TX queue structure.
2764 * Pointer to burst routine local context.
2766 * Pointer to WQE to fill with built Data Segment.
2768 * Data buffer to point.
2770 * Data buffer length.
2772 * Configured Tx offloads mask. It is fully defined at
2773 * compile time and may be used for optimization.
2776 * Pointer to the next Data Segment after inlined data.
2777 * Ring buffer wraparound check is needed. We do not
2778 * do it here because it may not be needed for the
2779 * last packet in the eMPW session.
2781 static __rte_always_inline struct mlx5_wqe_dseg *
2782 mlx5_tx_dseg_empw(struct mlx5_txq_data *restrict txq,
2783 struct mlx5_txq_local *restrict loc __rte_unused,
2784 struct mlx5_wqe_dseg *restrict dseg,
2787 unsigned int olx __rte_unused)
2792 dseg->bcount = rte_cpu_to_be_32(len | MLX5_ETH_WQE_DATA_INLINE);
2793 pdst = &dseg->inline_data[0];
2795 * The WQEBB space availability is checked by caller.
2796 * Here we should be aware of WQE ring buffer wraparound only.
2798 part = (uint8_t *)txq->wqes_end - pdst;
2799 part = RTE_MIN(part, len);
2801 rte_memcpy(pdst, buf, part);
2805 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2806 /* Note: no final wraparound check here. */
2807 return (struct mlx5_wqe_dseg *)pdst;
2809 pdst = (uint8_t *)txq->wqes;
2816 * Build the Data Segment of inlined data from single
2817 * segment packet with VLAN insertion.
2820 * Pointer to TX queue structure.
2822 * Pointer to burst routine local context.
2824 * Pointer to the dseg fill with built Data Segment.
2826 * Data buffer to point.
2828 * Data buffer length.
2830 * Configured Tx offloads mask. It is fully defined at
2831 * compile time and may be used for optimization.
2834 * Pointer to the next Data Segment after inlined data.
2835 * Ring buffer wraparound check is needed.
2837 static __rte_always_inline struct mlx5_wqe_dseg *
2838 mlx5_tx_dseg_vlan(struct mlx5_txq_data *restrict txq,
2839 struct mlx5_txq_local *restrict loc __rte_unused,
2840 struct mlx5_wqe_dseg *restrict dseg,
2843 unsigned int olx __rte_unused)
2849 assert(len > MLX5_ESEG_MIN_INLINE_SIZE);
2850 static_assert(MLX5_DSEG_MIN_INLINE_SIZE ==
2851 (2 * RTE_ETHER_ADDR_LEN),
2852 "invalid Data Segment data size");
2853 dseg->bcount = rte_cpu_to_be_32((len + sizeof(struct rte_vlan_hdr)) |
2854 MLX5_ETH_WQE_DATA_INLINE);
2855 pdst = &dseg->inline_data[0];
2856 memcpy(pdst, buf, MLX5_DSEG_MIN_INLINE_SIZE);
2857 buf += MLX5_DSEG_MIN_INLINE_SIZE;
2858 pdst += MLX5_DSEG_MIN_INLINE_SIZE;
2859 /* Insert VLAN ethertype + VLAN tag. Pointer is aligned. */
2860 assert(pdst == RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE));
2861 *(uint32_t *)pdst = rte_cpu_to_be_32((RTE_ETHER_TYPE_VLAN << 16) |
2862 loc->mbuf->vlan_tci);
2863 pdst += sizeof(struct rte_vlan_hdr);
2864 if (unlikely(pdst >= (uint8_t *)txq->wqes_end))
2865 pdst = (uint8_t *)txq->wqes;
2867 * The WQEBB space availability is checked by caller.
2868 * Here we should be aware of WQE ring buffer wraparound only.
2870 part = (uint8_t *)txq->wqes_end - pdst;
2871 part = RTE_MIN(part, len);
2873 rte_memcpy(pdst, buf, part);
2877 pdst = RTE_PTR_ALIGN(pdst, MLX5_WSEG_SIZE);
2878 /* Note: no final wraparound check here. */
2879 return (struct mlx5_wqe_dseg *)pdst;
2881 pdst = (uint8_t *)txq->wqes;
2888 * Build the Ethernet Segment with optionally inlined data with
2889 * VLAN insertion and following Data Segments (if any) from
2890 * multi-segment packet. Used by ordinary send and TSO.
2893 * Pointer to TX queue structure.
2895 * Pointer to burst routine local context.
2897 * Pointer to WQE to fill with built Ethernet/Data Segments.
2899 * Length of VLAN header to insert, 0 means no VLAN insertion.
2901 * Data length to inline. For TSO this parameter specifies
2902 * exact value, for ordinary send routine can be aligned by
2903 * caller to provide better WQE space saving and data buffer
2904 * start address alignment. This length includes VLAN header
2907 * Zero means ordinary send, inlined data can be extended,
2908 * otherwise this is TSO, inlined data length is fixed.
2910 * Configured Tx offloads mask. It is fully defined at
2911 * compile time and may be used for optimization.
2914 * Actual size of built WQE in segments.
2916 static __rte_always_inline unsigned int
2917 mlx5_tx_mseg_build(struct mlx5_txq_data *restrict txq,
2918 struct mlx5_txq_local *restrict loc,
2919 struct mlx5_wqe *restrict wqe,
2923 unsigned int olx __rte_unused)
2925 struct mlx5_wqe_dseg *restrict dseg;
2928 assert((rte_pktmbuf_pkt_len(loc->mbuf) + vlan) >= inlen);
2929 loc->mbuf_nseg = NB_SEGS(loc->mbuf);
2932 dseg = mlx5_tx_eseg_mdat(txq, loc, wqe, vlan, inlen, tso, olx);
2933 if (!loc->mbuf_nseg)
2936 * There are still some mbuf remaining, not inlined.
2937 * The first mbuf may be partially inlined and we
2938 * must process the possible non-zero data offset.
2940 if (loc->mbuf_off) {
2945 * Exhausted packets must be dropped before.
2946 * Non-zero offset means there are some data
2947 * remained in the packet.
2949 assert(loc->mbuf_off < rte_pktmbuf_data_len(loc->mbuf));
2950 assert(rte_pktmbuf_data_len(loc->mbuf));
2951 dptr = rte_pktmbuf_mtod_offset(loc->mbuf, uint8_t *,
2953 dlen = rte_pktmbuf_data_len(loc->mbuf) - loc->mbuf_off;
2955 * Build the pointer/minimal data Data Segment.
2956 * Do ring buffer wrapping check in advance.
2958 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2959 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2960 mlx5_tx_dseg_iptr(txq, loc, dseg, dptr, dlen, olx);
2961 /* Store the mbuf to be freed on completion. */
2962 assert(loc->elts_free);
2963 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2966 if (--loc->mbuf_nseg == 0)
2968 loc->mbuf = loc->mbuf->next;
2972 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
2973 struct rte_mbuf *mbuf;
2975 /* Zero length segment found, just skip. */
2977 loc->mbuf = loc->mbuf->next;
2978 rte_pktmbuf_free_seg(mbuf);
2979 if (--loc->mbuf_nseg == 0)
2982 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
2983 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
2986 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
2987 rte_pktmbuf_data_len(loc->mbuf), olx);
2988 assert(loc->elts_free);
2989 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
2992 if (--loc->mbuf_nseg == 0)
2994 loc->mbuf = loc->mbuf->next;
2999 /* Calculate actual segments used from the dseg pointer. */
3000 if ((uintptr_t)wqe < (uintptr_t)dseg)
3001 ds = ((uintptr_t)dseg - (uintptr_t)wqe) / MLX5_WSEG_SIZE;
3003 ds = (((uintptr_t)dseg - (uintptr_t)wqe) +
3004 txq->wqe_s * MLX5_WQE_SIZE) / MLX5_WSEG_SIZE;
3009 * Tx one packet function for multi-segment TSO. Supports all
3010 * types of Tx offloads, uses MLX5_OPCODE_TSO to build WQEs,
3011 * sends one packet per WQE.
3013 * This routine is responsible for storing processed mbuf
3014 * into elts ring buffer and update elts_head.
3017 * Pointer to TX queue structure.
3019 * Pointer to burst routine local context.
3021 * Configured Tx offloads mask. It is fully defined at
3022 * compile time and may be used for optimization.
3025 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3026 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3027 * Local context variables partially updated.
3029 static __rte_always_inline enum mlx5_txcmp_code
3030 mlx5_tx_packet_multi_tso(struct mlx5_txq_data *restrict txq,
3031 struct mlx5_txq_local *restrict loc,
3034 struct mlx5_wqe *restrict wqe;
3035 unsigned int ds, dlen, inlen, ntcp, vlan = 0;
3038 * Calculate data length to be inlined to estimate
3039 * the required space in WQE ring buffer.
3041 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3042 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3043 vlan = sizeof(struct rte_vlan_hdr);
3044 inlen = loc->mbuf->l2_len + vlan +
3045 loc->mbuf->l3_len + loc->mbuf->l4_len;
3046 if (unlikely((!inlen || !loc->mbuf->tso_segsz)))
3047 return MLX5_TXCMP_CODE_ERROR;
3048 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3049 inlen += loc->mbuf->outer_l2_len + loc->mbuf->outer_l3_len;
3050 /* Packet must contain all TSO headers. */
3051 if (unlikely(inlen > MLX5_MAX_TSO_HEADER ||
3052 inlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3053 inlen > (dlen + vlan)))
3054 return MLX5_TXCMP_CODE_ERROR;
3055 assert(inlen >= txq->inlen_mode);
3057 * Check whether there are enough free WQEBBs:
3059 * - Ethernet Segment
3060 * - First Segment of inlined Ethernet data
3061 * - ... data continued ...
3062 * - Data Segments of pointer/min inline type
3064 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3065 MLX5_ESEG_MIN_INLINE_SIZE +
3067 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3068 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3069 return MLX5_TXCMP_CODE_EXIT;
3070 /* Check for maximal WQE size. */
3071 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3072 return MLX5_TXCMP_CODE_ERROR;
3073 #ifdef MLX5_PMD_SOFT_COUNTERS
3074 /* Update sent data bytes/packets counters. */
3075 ntcp = (dlen - (inlen - vlan) + loc->mbuf->tso_segsz - 1) /
3076 loc->mbuf->tso_segsz;
3078 * One will be added for mbuf itself
3079 * at the end of the mlx5_tx_burst from
3080 * loc->pkts_sent field.
3083 txq->stats.opackets += ntcp;
3084 txq->stats.obytes += dlen + vlan + ntcp * inlen;
3086 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3087 loc->wqe_last = wqe;
3088 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_TSO, olx);
3089 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 1, olx);
3090 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3091 txq->wqe_ci += (ds + 3) / 4;
3092 loc->wqe_free -= (ds + 3) / 4;
3093 /* Request CQE generation if limits are reached. */
3094 mlx5_tx_request_completion(txq, loc, olx);
3095 return MLX5_TXCMP_CODE_MULTI;
3099 * Tx one packet function for multi-segment SEND. Supports all
3100 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3101 * sends one packet per WQE, without any data inlining in
3104 * This routine is responsible for storing processed mbuf
3105 * into elts ring buffer and update elts_head.
3108 * Pointer to TX queue structure.
3110 * Pointer to burst routine local context.
3112 * Configured Tx offloads mask. It is fully defined at
3113 * compile time and may be used for optimization.
3116 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3117 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3118 * Local context variables partially updated.
3120 static __rte_always_inline enum mlx5_txcmp_code
3121 mlx5_tx_packet_multi_send(struct mlx5_txq_data *restrict txq,
3122 struct mlx5_txq_local *restrict loc,
3125 struct mlx5_wqe_dseg *restrict dseg;
3126 struct mlx5_wqe *restrict wqe;
3127 unsigned int ds, nseg;
3129 assert(NB_SEGS(loc->mbuf) > 1);
3131 * No inline at all, it means the CPU cycles saving
3132 * is prioritized at configuration, we should not
3133 * copy any packet data to WQE.
3135 nseg = NB_SEGS(loc->mbuf);
3137 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3138 return MLX5_TXCMP_CODE_EXIT;
3139 /* Check for maximal WQE size. */
3140 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3141 return MLX5_TXCMP_CODE_ERROR;
3143 * Some Tx offloads may cause an error if
3144 * packet is not long enough, check against
3145 * assumed minimal length.
3147 if (rte_pktmbuf_pkt_len(loc->mbuf) <= MLX5_ESEG_MIN_INLINE_SIZE)
3148 return MLX5_TXCMP_CODE_ERROR;
3149 #ifdef MLX5_PMD_SOFT_COUNTERS
3150 /* Update sent data bytes counter. */
3151 txq->stats.obytes += rte_pktmbuf_pkt_len(loc->mbuf);
3152 if (MLX5_TXOFF_CONFIG(VLAN) &&
3153 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3154 txq->stats.obytes += sizeof(struct rte_vlan_hdr);
3157 * SEND WQE, one WQEBB:
3158 * - Control Segment, SEND opcode
3159 * - Ethernet Segment, optional VLAN, no inline
3160 * - Data Segments, pointer only type
3162 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3163 loc->wqe_last = wqe;
3164 mlx5_tx_cseg_init(txq, loc, wqe, ds, MLX5_OPCODE_SEND, olx);
3165 mlx5_tx_eseg_none(txq, loc, wqe, olx);
3166 dseg = &wqe->dseg[0];
3168 if (unlikely(!rte_pktmbuf_data_len(loc->mbuf))) {
3169 struct rte_mbuf *mbuf;
3172 * Zero length segment found, have to
3173 * correct total size of WQE in segments.
3174 * It is supposed to be rare occasion, so
3175 * in normal case (no zero length segments)
3176 * we avoid extra writing to the Control
3180 wqe->cseg.sq_ds -= RTE_BE32(1);
3182 loc->mbuf = mbuf->next;
3183 rte_pktmbuf_free_seg(mbuf);
3189 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3190 rte_pktmbuf_data_len(loc->mbuf), olx);
3191 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3196 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3197 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3198 loc->mbuf = loc->mbuf->next;
3201 txq->wqe_ci += (ds + 3) / 4;
3202 loc->wqe_free -= (ds + 3) / 4;
3203 /* Request CQE generation if limits are reached. */
3204 mlx5_tx_request_completion(txq, loc, olx);
3205 return MLX5_TXCMP_CODE_MULTI;
3209 * Tx one packet function for multi-segment SEND. Supports all
3210 * types of Tx offloads, uses MLX5_OPCODE_SEND to build WQEs,
3211 * sends one packet per WQE, with data inlining in
3212 * Ethernet Segment and minimal Data Segments.
3214 * This routine is responsible for storing processed mbuf
3215 * into elts ring buffer and update elts_head.
3218 * Pointer to TX queue structure.
3220 * Pointer to burst routine local context.
3222 * Configured Tx offloads mask. It is fully defined at
3223 * compile time and may be used for optimization.
3226 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3227 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3228 * Local context variables partially updated.
3230 static __rte_always_inline enum mlx5_txcmp_code
3231 mlx5_tx_packet_multi_inline(struct mlx5_txq_data *restrict txq,
3232 struct mlx5_txq_local *restrict loc,
3235 struct mlx5_wqe *restrict wqe;
3236 unsigned int ds, inlen, dlen, vlan = 0;
3238 assert(MLX5_TXOFF_CONFIG(INLINE));
3239 assert(NB_SEGS(loc->mbuf) > 1);
3241 * First calculate data length to be inlined
3242 * to estimate the required space for WQE.
3244 dlen = rte_pktmbuf_pkt_len(loc->mbuf);
3245 if (MLX5_TXOFF_CONFIG(VLAN) && loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
3246 vlan = sizeof(struct rte_vlan_hdr);
3247 inlen = dlen + vlan;
3248 /* Check against minimal length. */
3249 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
3250 return MLX5_TXCMP_CODE_ERROR;
3251 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
3252 if (inlen > txq->inlen_send) {
3253 struct rte_mbuf *mbuf;
3258 * Packet length exceeds the allowed inline
3259 * data length, check whether the minimal
3260 * inlining is required.
3262 if (txq->inlen_mode) {
3263 assert(txq->inlen_mode >= MLX5_ESEG_MIN_INLINE_SIZE);
3264 assert(txq->inlen_mode <= txq->inlen_send);
3265 inlen = txq->inlen_mode;
3267 if (!vlan || txq->vlan_en) {
3269 * VLAN insertion will be done inside by HW.
3270 * It is not utmost effective - VLAN flag is
3271 * checked twice, but we should proceed the
3272 * inlining length correctly and take into
3273 * account the VLAN header being inserted.
3275 return mlx5_tx_packet_multi_send
3278 inlen = MLX5_ESEG_MIN_INLINE_SIZE;
3281 * Now we know the minimal amount of data is requested
3282 * to inline. Check whether we should inline the buffers
3283 * from the chain beginning to eliminate some mbufs.
3286 nxlen = rte_pktmbuf_data_len(mbuf);
3287 if (unlikely(nxlen <= txq->inlen_send)) {
3288 /* We can inline first mbuf at least. */
3289 if (nxlen < inlen) {
3292 /* Scan mbufs till inlen filled. */
3297 nxlen = rte_pktmbuf_data_len(mbuf);
3299 } while (unlikely(nxlen < inlen));
3300 if (unlikely(nxlen > txq->inlen_send)) {
3301 /* We cannot inline entire mbuf. */
3302 smlen = inlen - smlen;
3303 start = rte_pktmbuf_mtod_offset
3304 (mbuf, uintptr_t, smlen);
3311 /* There should be not end of packet. */
3313 nxlen = inlen + rte_pktmbuf_data_len(mbuf);
3314 } while (unlikely(nxlen < txq->inlen_send));
3316 start = rte_pktmbuf_mtod(mbuf, uintptr_t);
3318 * Check whether we can do inline to align start
3319 * address of data buffer to cacheline.
3322 start = (~start + 1) & (RTE_CACHE_LINE_SIZE - 1);
3323 if (unlikely(start)) {
3325 if (start <= txq->inlen_send)
3330 * Check whether there are enough free WQEBBs:
3332 * - Ethernet Segment
3333 * - First Segment of inlined Ethernet data
3334 * - ... data continued ...
3335 * - Data Segments of pointer/min inline type
3337 * Estimate the number of Data Segments conservatively,
3338 * supposing no any mbufs is being freed during inlining.
3340 assert(inlen <= txq->inlen_send);
3341 ds = NB_SEGS(loc->mbuf) + 2 + (inlen -
3342 MLX5_ESEG_MIN_INLINE_SIZE +
3344 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3345 if (unlikely(loc->wqe_free < ((ds + 3) / 4)))
3346 return MLX5_TXCMP_CODE_EXIT;
3347 /* Check for maximal WQE size. */
3348 if (unlikely((MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE) < ((ds + 3) / 4)))
3349 return MLX5_TXCMP_CODE_ERROR;
3350 #ifdef MLX5_PMD_SOFT_COUNTERS
3351 /* Update sent data bytes/packets counters. */
3352 txq->stats.obytes += dlen + vlan;
3354 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3355 loc->wqe_last = wqe;
3356 mlx5_tx_cseg_init(txq, loc, wqe, 0, MLX5_OPCODE_SEND, olx);
3357 ds = mlx5_tx_mseg_build(txq, loc, wqe, vlan, inlen, 0, olx);
3358 wqe->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3359 txq->wqe_ci += (ds + 3) / 4;
3360 loc->wqe_free -= (ds + 3) / 4;
3361 /* Request CQE generation if limits are reached. */
3362 mlx5_tx_request_completion(txq, loc, olx);
3363 return MLX5_TXCMP_CODE_MULTI;
3367 * Tx burst function for multi-segment packets. Supports all
3368 * types of Tx offloads, uses MLX5_OPCODE_SEND/TSO to build WQEs,
3369 * sends one packet per WQE. Function stops sending if it
3370 * encounters the single-segment packet.
3372 * This routine is responsible for storing processed mbuf
3373 * into elts ring buffer and update elts_head.
3376 * Pointer to TX queue structure.
3378 * Packets to transmit.
3380 * Number of packets in array.
3382 * Pointer to burst routine local context.
3384 * Configured Tx offloads mask. It is fully defined at
3385 * compile time and may be used for optimization.
3388 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3389 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3390 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3391 * MLX5_TXCMP_CODE_TSO - TSO single-segment packet encountered.
3392 * Local context variables updated.
3394 static __rte_always_inline enum mlx5_txcmp_code
3395 mlx5_tx_burst_mseg(struct mlx5_txq_data *restrict txq,
3396 struct rte_mbuf **restrict pkts,
3397 unsigned int pkts_n,
3398 struct mlx5_txq_local *restrict loc,
3401 assert(loc->elts_free && loc->wqe_free);
3402 assert(pkts_n > loc->pkts_sent);
3403 pkts += loc->pkts_sent + 1;
3404 pkts_n -= loc->pkts_sent;
3406 enum mlx5_txcmp_code ret;
3408 assert(NB_SEGS(loc->mbuf) > 1);
3410 * Estimate the number of free elts quickly but
3411 * conservatively. Some segment may be fully inlined
3412 * and freed, ignore this here - precise estimation
3415 if (loc->elts_free < NB_SEGS(loc->mbuf))
3416 return MLX5_TXCMP_CODE_EXIT;
3417 if (MLX5_TXOFF_CONFIG(TSO) &&
3418 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)) {
3419 /* Proceed with multi-segment TSO. */
3420 ret = mlx5_tx_packet_multi_tso(txq, loc, olx);
3421 } else if (MLX5_TXOFF_CONFIG(INLINE)) {
3422 /* Proceed with multi-segment SEND with inlining. */
3423 ret = mlx5_tx_packet_multi_inline(txq, loc, olx);
3425 /* Proceed with multi-segment SEND w/o inlining. */
3426 ret = mlx5_tx_packet_multi_send(txq, loc, olx);
3428 if (ret == MLX5_TXCMP_CODE_EXIT)
3429 return MLX5_TXCMP_CODE_EXIT;
3430 if (ret == MLX5_TXCMP_CODE_ERROR)
3431 return MLX5_TXCMP_CODE_ERROR;
3432 /* WQE is built, go to the next packet. */
3435 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3436 return MLX5_TXCMP_CODE_EXIT;
3437 loc->mbuf = *pkts++;
3439 rte_prefetch0(*pkts);
3440 if (likely(NB_SEGS(loc->mbuf) > 1))
3442 /* Here ends the series of multi-segment packets. */
3443 if (MLX5_TXOFF_CONFIG(TSO) &&
3444 unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3445 return MLX5_TXCMP_CODE_TSO;
3446 return MLX5_TXCMP_CODE_SINGLE;
3452 * Tx burst function for single-segment packets with TSO.
3453 * Supports all types of Tx offloads, except multi-packets.
3454 * Uses MLX5_OPCODE_TSO to build WQEs, sends one packet per WQE.
3455 * Function stops sending if it encounters the multi-segment
3456 * packet or packet without TSO requested.
3458 * The routine is responsible for storing processed mbuf
3459 * into elts ring buffer and update elts_head if inline
3460 * offloads is requested due to possible early freeing
3461 * of the inlined mbufs (can not store pkts array in elts
3465 * Pointer to TX queue structure.
3467 * Packets to transmit.
3469 * Number of packets in array.
3471 * Pointer to burst routine local context.
3473 * Configured Tx offloads mask. It is fully defined at
3474 * compile time and may be used for optimization.
3477 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3478 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3479 * MLX5_TXCMP_CODE_SINGLE - single-segment packet encountered.
3480 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3481 * Local context variables updated.
3483 static __rte_always_inline enum mlx5_txcmp_code
3484 mlx5_tx_burst_tso(struct mlx5_txq_data *restrict txq,
3485 struct rte_mbuf **restrict pkts,
3486 unsigned int pkts_n,
3487 struct mlx5_txq_local *restrict loc,
3490 assert(loc->elts_free && loc->wqe_free);
3491 assert(pkts_n > loc->pkts_sent);
3492 pkts += loc->pkts_sent + 1;
3493 pkts_n -= loc->pkts_sent;
3495 struct mlx5_wqe_dseg *restrict dseg;
3496 struct mlx5_wqe *restrict wqe;
3497 unsigned int ds, dlen, hlen, ntcp, vlan = 0;
3500 assert(NB_SEGS(loc->mbuf) == 1);
3501 dlen = rte_pktmbuf_data_len(loc->mbuf);
3502 if (MLX5_TXOFF_CONFIG(VLAN) &&
3503 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
3504 vlan = sizeof(struct rte_vlan_hdr);
3507 * First calculate the WQE size to check
3508 * whether we have enough space in ring buffer.
3510 hlen = loc->mbuf->l2_len + vlan +
3511 loc->mbuf->l3_len + loc->mbuf->l4_len;
3512 if (unlikely((!hlen || !loc->mbuf->tso_segsz)))
3513 return MLX5_TXCMP_CODE_ERROR;
3514 if (loc->mbuf->ol_flags & PKT_TX_TUNNEL_MASK)
3515 hlen += loc->mbuf->outer_l2_len +
3516 loc->mbuf->outer_l3_len;
3517 /* Segment must contain all TSO headers. */
3518 if (unlikely(hlen > MLX5_MAX_TSO_HEADER ||
3519 hlen <= MLX5_ESEG_MIN_INLINE_SIZE ||
3520 hlen > (dlen + vlan)))
3521 return MLX5_TXCMP_CODE_ERROR;
3523 * Check whether there are enough free WQEBBs:
3525 * - Ethernet Segment
3526 * - First Segment of inlined Ethernet data
3527 * - ... data continued ...
3528 * - Finishing Data Segment of pointer type
3530 ds = 4 + (hlen - MLX5_ESEG_MIN_INLINE_SIZE +
3531 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
3532 if (loc->wqe_free < ((ds + 3) / 4))
3533 return MLX5_TXCMP_CODE_EXIT;
3534 #ifdef MLX5_PMD_SOFT_COUNTERS
3535 /* Update sent data bytes/packets counters. */
3536 ntcp = (dlen + vlan - hlen +
3537 loc->mbuf->tso_segsz - 1) /
3538 loc->mbuf->tso_segsz;
3540 * One will be added for mbuf itself at the end
3541 * of the mlx5_tx_burst from loc->pkts_sent field.
3544 txq->stats.opackets += ntcp;
3545 txq->stats.obytes += dlen + vlan + ntcp * hlen;
3548 * Build the TSO WQE:
3550 * - Ethernet Segment with hlen bytes inlined
3551 * - Data Segment of pointer type
3553 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3554 loc->wqe_last = wqe;
3555 mlx5_tx_cseg_init(txq, loc, wqe, ds,
3556 MLX5_OPCODE_TSO, olx);
3557 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan, hlen, 1, olx);
3558 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) + hlen - vlan;
3559 dlen -= hlen - vlan;
3560 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
3562 * WQE is built, update the loop parameters
3563 * and go to the next packet.
3565 txq->wqe_ci += (ds + 3) / 4;
3566 loc->wqe_free -= (ds + 3) / 4;
3567 if (MLX5_TXOFF_CONFIG(INLINE))
3568 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
3572 /* Request CQE generation if limits are reached. */
3573 mlx5_tx_request_completion(txq, loc, olx);
3574 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3575 return MLX5_TXCMP_CODE_EXIT;
3576 loc->mbuf = *pkts++;
3578 rte_prefetch0(*pkts);
3579 if (MLX5_TXOFF_CONFIG(MULTI) &&
3580 unlikely(NB_SEGS(loc->mbuf) > 1))
3581 return MLX5_TXCMP_CODE_MULTI;
3582 if (unlikely(!(loc->mbuf->ol_flags & PKT_TX_TCP_SEG)))
3583 return MLX5_TXCMP_CODE_SINGLE;
3584 /* Continue with the next TSO packet. */
3590 * Analyze the packet and select the best method to send.
3593 * Pointer to TX queue structure.
3595 * Pointer to burst routine local context.
3597 * Configured Tx offloads mask. It is fully defined at
3598 * compile time and may be used for optimization.
3600 * The predefined flag whether do complete check for
3601 * multi-segment packets and TSO.
3604 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3605 * MLX5_TXCMP_CODE_TSO - TSO required, use TSO/LSO.
3606 * MLX5_TXCMP_CODE_SINGLE - single-segment packet, use SEND.
3607 * MLX5_TXCMP_CODE_EMPW - single-segment packet, use MPW.
3609 static __rte_always_inline enum mlx5_txcmp_code
3610 mlx5_tx_able_to_empw(struct mlx5_txq_data *restrict txq,
3611 struct mlx5_txq_local *restrict loc,
3615 /* Check for multi-segment packet. */
3617 MLX5_TXOFF_CONFIG(MULTI) &&
3618 unlikely(NB_SEGS(loc->mbuf) > 1))
3619 return MLX5_TXCMP_CODE_MULTI;
3620 /* Check for TSO packet. */
3622 MLX5_TXOFF_CONFIG(TSO) &&
3623 unlikely(loc->mbuf->ol_flags & PKT_TX_TCP_SEG))
3624 return MLX5_TXCMP_CODE_TSO;
3625 /* Check if eMPW is enabled at all. */
3626 if (!MLX5_TXOFF_CONFIG(EMPW))
3627 return MLX5_TXCMP_CODE_SINGLE;
3628 /* Check if eMPW can be engaged. */
3629 if (MLX5_TXOFF_CONFIG(VLAN) &&
3630 unlikely(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) &&
3631 (!MLX5_TXOFF_CONFIG(INLINE) ||
3632 unlikely((rte_pktmbuf_data_len(loc->mbuf) +
3633 sizeof(struct rte_vlan_hdr)) > txq->inlen_empw))) {
3635 * eMPW does not support VLAN insertion offload,
3636 * we have to inline the entire packet but
3637 * packet is too long for inlining.
3639 return MLX5_TXCMP_CODE_SINGLE;
3641 return MLX5_TXCMP_CODE_EMPW;
3645 * Check the next packet attributes to match with the eMPW batch ones.
3648 * Pointer to TX queue structure.
3650 * Pointer to Ethernet Segment of eMPW batch.
3652 * Pointer to burst routine local context.
3654 * Configured Tx offloads mask. It is fully defined at
3655 * compile time and may be used for optimization.
3658 * true - packet match with eMPW batch attributes.
3659 * false - no match, eMPW should be restarted.
3661 static __rte_always_inline bool
3662 mlx5_tx_match_empw(struct mlx5_txq_data *restrict txq __rte_unused,
3663 struct mlx5_wqe_eseg *restrict es,
3664 struct mlx5_txq_local *restrict loc,
3667 uint8_t swp_flags = 0;
3669 /* Compare the checksum flags, if any. */
3670 if (MLX5_TXOFF_CONFIG(CSUM) &&
3671 txq_ol_cksum_to_cs(loc->mbuf) != es->cs_flags)
3673 /* Compare the Software Parser offsets and flags. */
3674 if (MLX5_TXOFF_CONFIG(SWP) &&
3675 (es->swp_offs != txq_mbuf_to_swp(loc, &swp_flags, olx) ||
3676 es->swp_flags != swp_flags))
3678 /* Fill metadata field if needed. */
3679 if (MLX5_TXOFF_CONFIG(METADATA) &&
3680 es->metadata != (loc->mbuf->ol_flags & PKT_TX_METADATA ?
3681 loc->mbuf->tx_metadata : 0))
3683 /* There must be no VLAN packets in eMPW loop. */
3684 if (MLX5_TXOFF_CONFIG(VLAN))
3685 assert(!(loc->mbuf->ol_flags & PKT_TX_VLAN_PKT));
3690 * Update send loop variables and WQE for eMPW loop
3691 * without data inlining. Number of Data Segments is
3692 * equal to the number of sent packets.
3695 * Pointer to TX queue structure.
3697 * Pointer to burst routine local context.
3699 * Number of packets/Data Segments/Packets.
3701 * Accumulated statistics, bytes sent
3703 * Configured Tx offloads mask. It is fully defined at
3704 * compile time and may be used for optimization.
3707 * true - packet match with eMPW batch attributes.
3708 * false - no match, eMPW should be restarted.
3710 static __rte_always_inline void
3711 mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
3712 struct mlx5_txq_local *restrict loc,
3717 assert(!MLX5_TXOFF_CONFIG(INLINE));
3718 #ifdef MLX5_PMD_SOFT_COUNTERS
3719 /* Update sent data bytes counter. */
3720 txq->stats.obytes += slen;
3724 loc->elts_free -= ds;
3725 loc->pkts_sent += ds;
3727 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | ds);
3728 txq->wqe_ci += (ds + 3) / 4;
3729 loc->wqe_free -= (ds + 3) / 4;
3730 /* Request CQE generation if limits are reached. */
3731 mlx5_tx_request_completion(txq, loc, olx);
3735 * Update send loop variables and WQE for eMPW loop
3736 * with data inlining. Gets the size of pushed descriptors
3737 * and data to the WQE.
3740 * Pointer to TX queue structure.
3742 * Pointer to burst routine local context.
3744 * Total size of descriptor/data in bytes.
3746 * Accumulated statistics, data bytes sent.
3748 * Configured Tx offloads mask. It is fully defined at
3749 * compile time and may be used for optimization.
3752 * true - packet match with eMPW batch attributes.
3753 * false - no match, eMPW should be restarted.
3755 static __rte_always_inline void
3756 mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
3757 struct mlx5_txq_local *restrict loc,
3760 unsigned int olx __rte_unused)
3762 assert(MLX5_TXOFF_CONFIG(INLINE));
3763 assert((len % MLX5_WSEG_SIZE) == 0);
3764 #ifdef MLX5_PMD_SOFT_COUNTERS
3765 /* Update sent data bytes counter. */
3766 txq->stats.obytes += slen;
3770 len = len / MLX5_WSEG_SIZE + 2;
3771 loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
3772 txq->wqe_ci += (len + 3) / 4;
3773 loc->wqe_free -= (len + 3) / 4;
3774 /* Request CQE generation if limits are reached. */
3775 mlx5_tx_request_completion(txq, loc, olx);
3779 * The set of Tx burst functions for single-segment packets
3780 * without TSO and with Multi-Packet Writing feature support.
3781 * Supports all types of Tx offloads, except multi-packets
3784 * Uses MLX5_OPCODE_EMPW to build WQEs if possible and sends
3785 * as many packet per WQE as it can. If eMPW is not configured
3786 * or packet can not be sent with eMPW (VLAN insertion) the
3787 * ordinary SEND opcode is used and only one packet placed
3790 * Functions stop sending if it encounters the multi-segment
3791 * packet or packet with TSO requested.
3793 * The routines are responsible for storing processed mbuf
3794 * into elts ring buffer and update elts_head if inlining
3795 * offload is requested. Otherwise the copying mbufs to elts
3796 * can be postponed and completed at the end of burst routine.
3799 * Pointer to TX queue structure.
3801 * Packets to transmit.
3803 * Number of packets in array.
3805 * Pointer to burst routine local context.
3807 * Configured Tx offloads mask. It is fully defined at
3808 * compile time and may be used for optimization.
3811 * MLX5_TXCMP_CODE_EXIT - sending is done or impossible.
3812 * MLX5_TXCMP_CODE_ERROR - some unrecoverable error occurred.
3813 * MLX5_TXCMP_CODE_MULTI - multi-segment packet encountered.
3814 * MLX5_TXCMP_CODE_TSO - TSO packet encountered.
3815 * MLX5_TXCMP_CODE_SINGLE - used inside functions set.
3816 * MLX5_TXCMP_CODE_EMPW - used inside functions set.
3818 * Local context variables updated.
3821 * The routine sends packets with MLX5_OPCODE_EMPW
3822 * without inlining, this is dedicated optimized branch.
3823 * No VLAN insertion is supported.
3825 static __rte_always_inline enum mlx5_txcmp_code
3826 mlx5_tx_burst_empw_simple(struct mlx5_txq_data *restrict txq,
3827 struct rte_mbuf **restrict pkts,
3828 unsigned int pkts_n,
3829 struct mlx5_txq_local *restrict loc,
3833 * Subroutine is the part of mlx5_tx_burst_single()
3834 * and sends single-segment packet with eMPW opcode
3835 * without data inlining.
3837 assert(!MLX5_TXOFF_CONFIG(INLINE));
3838 assert(MLX5_TXOFF_CONFIG(EMPW));
3839 assert(loc->elts_free && loc->wqe_free);
3840 assert(pkts_n > loc->pkts_sent);
3841 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
3842 pkts += loc->pkts_sent + 1;
3843 pkts_n -= loc->pkts_sent;
3845 struct mlx5_wqe_dseg *restrict dseg;
3846 struct mlx5_wqe_eseg *restrict eseg;
3847 enum mlx5_txcmp_code ret;
3848 unsigned int part, loop;
3849 unsigned int slen = 0;
3852 part = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
3853 if (unlikely(loc->elts_free < part)) {
3854 /* We have no enough elts to save all mbufs. */
3855 if (unlikely(loc->elts_free < MLX5_EMPW_MIN_PACKETS))
3856 return MLX5_TXCMP_CODE_EXIT;
3857 /* But we still able to send at least minimal eMPW. */
3858 part = loc->elts_free;
3860 /* Check whether we have enough WQEs */
3861 if (unlikely(loc->wqe_free < ((2 + part + 3) / 4))) {
3862 if (unlikely(loc->wqe_free <
3863 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
3864 return MLX5_TXCMP_CODE_EXIT;
3865 part = (loc->wqe_free * 4) - 2;
3867 if (likely(part > 1))
3868 rte_prefetch0(*pkts);
3869 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
3871 * Build eMPW title WQEBB:
3872 * - Control Segment, eMPW opcode
3873 * - Ethernet Segment, no inline
3875 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, part + 2,
3876 MLX5_OPCODE_ENHANCED_MPSW, olx);
3877 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
3878 olx & ~MLX5_TXOFF_CONFIG_VLAN);
3879 eseg = &loc->wqe_last->eseg;
3880 dseg = &loc->wqe_last->dseg[0];
3883 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
3884 #ifdef MLX5_PMD_SOFT_COUNTERS
3885 /* Update sent data bytes counter. */
3890 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
3892 if (unlikely(--loop == 0))
3894 loc->mbuf = *pkts++;
3895 if (likely(loop > 1))
3896 rte_prefetch0(*pkts);
3897 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3899 * Unroll the completion code to avoid
3900 * returning variable value - it results in
3901 * unoptimized sequent checking in caller.
3903 if (ret == MLX5_TXCMP_CODE_MULTI) {
3905 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3906 if (unlikely(!loc->elts_free ||
3908 return MLX5_TXCMP_CODE_EXIT;
3909 return MLX5_TXCMP_CODE_MULTI;
3911 if (ret == MLX5_TXCMP_CODE_TSO) {
3913 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3914 if (unlikely(!loc->elts_free ||
3916 return MLX5_TXCMP_CODE_EXIT;
3917 return MLX5_TXCMP_CODE_TSO;
3919 if (ret == MLX5_TXCMP_CODE_SINGLE) {
3921 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3922 if (unlikely(!loc->elts_free ||
3924 return MLX5_TXCMP_CODE_EXIT;
3925 return MLX5_TXCMP_CODE_SINGLE;
3927 if (ret != MLX5_TXCMP_CODE_EMPW) {
3930 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3931 return MLX5_TXCMP_CODE_ERROR;
3934 * Check whether packet parameters coincide
3935 * within assumed eMPW batch:
3936 * - check sum settings
3938 * - software parser settings
3940 if (!mlx5_tx_match_empw(txq, eseg, loc, olx)) {
3943 mlx5_tx_sdone_empw(txq, loc, part, slen, olx);
3944 if (unlikely(!loc->elts_free ||
3946 return MLX5_TXCMP_CODE_EXIT;
3950 /* Packet attributes match, continue the same eMPW. */
3952 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
3953 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
3955 /* eMPW is built successfully, update loop parameters. */
3957 assert(pkts_n >= part);
3958 #ifdef MLX5_PMD_SOFT_COUNTERS
3959 /* Update sent data bytes counter. */
3960 txq->stats.obytes += slen;
3962 loc->elts_free -= part;
3963 loc->pkts_sent += part;
3964 txq->wqe_ci += (2 + part + 3) / 4;
3965 loc->wqe_free -= (2 + part + 3) / 4;
3967 /* Request CQE generation if limits are reached. */
3968 mlx5_tx_request_completion(txq, loc, olx);
3969 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
3970 return MLX5_TXCMP_CODE_EXIT;
3971 loc->mbuf = *pkts++;
3972 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
3973 if (unlikely(ret != MLX5_TXCMP_CODE_EMPW))
3975 /* Continue sending eMPW batches. */
3981 * The routine sends packets with MLX5_OPCODE_EMPW
3982 * with inlining, optionally supports VLAN insertion.
3984 static __rte_always_inline enum mlx5_txcmp_code
3985 mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
3986 struct rte_mbuf **restrict pkts,
3987 unsigned int pkts_n,
3988 struct mlx5_txq_local *restrict loc,
3992 * Subroutine is the part of mlx5_tx_burst_single()
3993 * and sends single-segment packet with eMPW opcode
3994 * with data inlining.
3996 assert(MLX5_TXOFF_CONFIG(INLINE));
3997 assert(MLX5_TXOFF_CONFIG(EMPW));
3998 assert(loc->elts_free && loc->wqe_free);
3999 assert(pkts_n > loc->pkts_sent);
4000 static_assert(MLX5_EMPW_MIN_PACKETS >= 2, "invalid min size");
4001 pkts += loc->pkts_sent + 1;
4002 pkts_n -= loc->pkts_sent;
4004 struct mlx5_wqe_dseg *restrict dseg;
4005 struct mlx5_wqe_eseg *restrict eseg;
4006 enum mlx5_txcmp_code ret;
4007 unsigned int room, part, nlim;
4008 unsigned int slen = 0;
4011 * Limits the amount of packets in one WQE
4012 * to improve CQE latency generation.
4014 nlim = RTE_MIN(pkts_n, MLX5_EMPW_MAX_PACKETS);
4015 /* Check whether we have minimal amount WQEs */
4016 if (unlikely(loc->wqe_free <
4017 ((2 + MLX5_EMPW_MIN_PACKETS + 3) / 4)))
4018 return MLX5_TXCMP_CODE_EXIT;
4019 if (likely(pkts_n > 1))
4020 rte_prefetch0(*pkts);
4021 loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4023 * Build eMPW title WQEBB:
4024 * - Control Segment, eMPW opcode, zero DS
4025 * - Ethernet Segment, no inline
4027 mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
4028 MLX5_OPCODE_ENHANCED_MPSW, olx);
4029 mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
4030 olx & ~MLX5_TXOFF_CONFIG_VLAN);
4031 eseg = &loc->wqe_last->eseg;
4032 dseg = &loc->wqe_last->dseg[0];
4033 room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
4034 loc->wqe_free) * MLX5_WQE_SIZE -
4035 MLX5_WQE_CSEG_SIZE -
4037 /* Build WQE till we have space, packets and resources. */
4040 uint32_t dlen = rte_pktmbuf_data_len(loc->mbuf);
4041 uint8_t *dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *);
4044 assert(room >= MLX5_WQE_DSEG_SIZE);
4045 assert((room % MLX5_WQE_DSEG_SIZE) == 0);
4046 assert((uintptr_t)dseg < (uintptr_t)txq->wqes_end);
4048 * Some Tx offloads may cause an error if
4049 * packet is not long enough, check against
4050 * assumed minimal length.
4052 if (unlikely(dlen <= MLX5_ESEG_MIN_INLINE_SIZE)) {
4054 if (unlikely(!part))
4055 return MLX5_TXCMP_CODE_ERROR;
4057 * We have some successfully built
4058 * packet Data Segments to send.
4060 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4061 return MLX5_TXCMP_CODE_ERROR;
4063 /* Inline or not inline - that's the Question. */
4064 if (dlen > txq->inlen_empw)
4066 /* Inline entire packet, optional VLAN insertion. */
4067 tlen = sizeof(dseg->bcount) + dlen;
4068 if (MLX5_TXOFF_CONFIG(VLAN) &&
4069 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4071 * The packet length must be checked in
4072 * mlx5_tx_able_to_empw() and packet
4073 * fits into inline length guaranteed.
4075 assert((dlen + sizeof(struct rte_vlan_hdr)) <=
4077 tlen += sizeof(struct rte_vlan_hdr);
4080 dseg = mlx5_tx_dseg_vlan(txq, loc, dseg,
4082 #ifdef MLX5_PMD_SOFT_COUNTERS
4083 /* Update sent data bytes counter. */
4084 slen += sizeof(struct rte_vlan_hdr);
4089 dseg = mlx5_tx_dseg_empw(txq, loc, dseg,
4092 tlen = RTE_ALIGN(tlen, MLX5_WSEG_SIZE);
4093 assert(room >= tlen);
4096 * Packet data are completely inlined,
4097 * free the packet immediately.
4099 rte_pktmbuf_free_seg(loc->mbuf);
4103 * Not inlinable VLAN packets are
4104 * proceeded outside of this routine.
4106 assert(room >= MLX5_WQE_DSEG_SIZE);
4107 if (MLX5_TXOFF_CONFIG(VLAN))
4108 assert(!(loc->mbuf->ol_flags &
4110 mlx5_tx_dseg_ptr(txq, loc, dseg, dptr, dlen, olx);
4111 /* We have to store mbuf in elts.*/
4112 txq->elts[txq->elts_head++ & txq->elts_m] = loc->mbuf;
4113 room -= MLX5_WQE_DSEG_SIZE;
4114 /* Ring buffer wraparound is checked at the loop end.*/
4117 #ifdef MLX5_PMD_SOFT_COUNTERS
4118 /* Update sent data bytes counter. */
4124 if (unlikely(!pkts_n || !loc->elts_free)) {
4126 * We have no resources/packets to
4127 * continue build descriptors.
4130 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4131 return MLX5_TXCMP_CODE_EXIT;
4133 loc->mbuf = *pkts++;
4134 if (likely(pkts_n > 1))
4135 rte_prefetch0(*pkts);
4136 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4138 * Unroll the completion code to avoid
4139 * returning variable value - it results in
4140 * unoptimized sequent checking in caller.
4142 if (ret == MLX5_TXCMP_CODE_MULTI) {
4144 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4145 if (unlikely(!loc->elts_free ||
4147 return MLX5_TXCMP_CODE_EXIT;
4148 return MLX5_TXCMP_CODE_MULTI;
4150 if (ret == MLX5_TXCMP_CODE_TSO) {
4152 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4153 if (unlikely(!loc->elts_free ||
4155 return MLX5_TXCMP_CODE_EXIT;
4156 return MLX5_TXCMP_CODE_TSO;
4158 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4160 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4161 if (unlikely(!loc->elts_free ||
4163 return MLX5_TXCMP_CODE_EXIT;
4164 return MLX5_TXCMP_CODE_SINGLE;
4166 if (ret != MLX5_TXCMP_CODE_EMPW) {
4169 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4170 return MLX5_TXCMP_CODE_ERROR;
4172 /* Check if we have minimal room left. */
4174 if (unlikely(!nlim || room < MLX5_WQE_DSEG_SIZE))
4177 * Check whether packet parameters coincide
4178 * within assumed eMPW batch:
4179 * - check sum settings
4181 * - software parser settings
4183 if (!mlx5_tx_match_empw(txq, eseg, loc, olx))
4185 /* Packet attributes match, continue the same eMPW. */
4186 if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
4187 dseg = (struct mlx5_wqe_dseg *)txq->wqes;
4190 * We get here to close an existing eMPW
4191 * session and start the new one.
4195 if (unlikely(!part))
4196 return MLX5_TXCMP_CODE_EXIT;
4197 mlx5_tx_idone_empw(txq, loc, part, slen, olx);
4198 if (unlikely(!loc->elts_free ||
4200 return MLX5_TXCMP_CODE_EXIT;
4201 /* Continue the loop with new eMPW session. */
4207 * The routine sends packets with ordinary MLX5_OPCODE_SEND.
4208 * Data inlining and VLAN insertion are supported.
4210 static __rte_always_inline enum mlx5_txcmp_code
4211 mlx5_tx_burst_single_send(struct mlx5_txq_data *restrict txq,
4212 struct rte_mbuf **restrict pkts,
4213 unsigned int pkts_n,
4214 struct mlx5_txq_local *restrict loc,
4218 * Subroutine is the part of mlx5_tx_burst_single()
4219 * and sends single-segment packet with SEND opcode.
4221 assert(loc->elts_free && loc->wqe_free);
4222 assert(pkts_n > loc->pkts_sent);
4223 pkts += loc->pkts_sent + 1;
4224 pkts_n -= loc->pkts_sent;
4226 struct mlx5_wqe *restrict wqe;
4227 enum mlx5_txcmp_code ret;
4229 assert(NB_SEGS(loc->mbuf) == 1);
4230 if (MLX5_TXOFF_CONFIG(INLINE)) {
4231 unsigned int inlen, vlan = 0;
4233 inlen = rte_pktmbuf_data_len(loc->mbuf);
4234 if (MLX5_TXOFF_CONFIG(VLAN) &&
4235 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT) {
4236 vlan = sizeof(struct rte_vlan_hdr);
4238 static_assert((sizeof(struct rte_vlan_hdr) +
4239 sizeof(struct rte_ether_hdr)) ==
4240 MLX5_ESEG_MIN_INLINE_SIZE,
4241 "invalid min inline data size");
4244 * If inlining is enabled at configuration time
4245 * the limit must be not less than minimal size.
4246 * Otherwise we would do extra check for data
4247 * size to avoid crashes due to length overflow.
4249 assert(txq->inlen_send >= MLX5_ESEG_MIN_INLINE_SIZE);
4250 if (inlen <= txq->inlen_send) {
4251 unsigned int seg_n, wqe_n;
4253 rte_prefetch0(rte_pktmbuf_mtod
4254 (loc->mbuf, uint8_t *));
4255 /* Check against minimal length. */
4256 if (inlen <= MLX5_ESEG_MIN_INLINE_SIZE)
4257 return MLX5_TXCMP_CODE_ERROR;
4259 * Completely inlined packet data WQE:
4260 * - Control Segment, SEND opcode
4261 * - Ethernet Segment, no VLAN insertion
4262 * - Data inlined, VLAN optionally inserted
4263 * - Alignment to MLX5_WSEG_SIZE
4264 * Have to estimate amount of WQEBBs
4266 seg_n = (inlen + 3 * MLX5_WSEG_SIZE -
4267 MLX5_ESEG_MIN_INLINE_SIZE +
4268 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4269 /* Check if there are enough WQEBBs. */
4270 wqe_n = (seg_n + 3) / 4;
4271 if (wqe_n > loc->wqe_free)
4272 return MLX5_TXCMP_CODE_EXIT;
4273 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4274 loc->wqe_last = wqe;
4275 mlx5_tx_cseg_init(txq, loc, wqe, seg_n,
4276 MLX5_OPCODE_SEND, olx);
4277 mlx5_tx_eseg_data(txq, loc, wqe,
4278 vlan, inlen, 0, olx);
4279 txq->wqe_ci += wqe_n;
4280 loc->wqe_free -= wqe_n;
4282 * Packet data are completely inlined,
4283 * free the packet immediately.
4285 rte_pktmbuf_free_seg(loc->mbuf);
4286 } else if (!MLX5_TXOFF_CONFIG(EMPW) &&
4289 * If minimal inlining is requested the eMPW
4290 * feature should be disabled due to data is
4291 * inlined into Ethernet Segment, which can
4292 * not contain inlined data for eMPW due to
4293 * segment shared for all packets.
4295 struct mlx5_wqe_dseg *restrict dseg;
4300 * The inline-mode settings require
4301 * to inline the specified amount of
4302 * data bytes to the Ethernet Segment.
4303 * We should check the free space in
4304 * WQE ring buffer to inline partially.
4306 assert(txq->inlen_send >= txq->inlen_mode);
4307 assert(inlen > txq->inlen_mode);
4308 assert(txq->inlen_mode >=
4309 MLX5_ESEG_MIN_INLINE_SIZE);
4311 * Check whether there are enough free WQEBBs:
4313 * - Ethernet Segment
4314 * - First Segment of inlined Ethernet data
4315 * - ... data continued ...
4316 * - Finishing Data Segment of pointer type
4318 ds = (MLX5_WQE_CSEG_SIZE +
4319 MLX5_WQE_ESEG_SIZE +
4320 MLX5_WQE_DSEG_SIZE +
4322 MLX5_ESEG_MIN_INLINE_SIZE +
4323 MLX5_WQE_DSEG_SIZE +
4324 MLX5_WSEG_SIZE - 1) / MLX5_WSEG_SIZE;
4325 if (loc->wqe_free < ((ds + 3) / 4))
4326 return MLX5_TXCMP_CODE_EXIT;
4328 * Build the ordinary SEND WQE:
4330 * - Ethernet Segment, inline inlen_mode bytes
4331 * - Data Segment of pointer type
4333 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4334 loc->wqe_last = wqe;
4335 mlx5_tx_cseg_init(txq, loc, wqe, ds,
4336 MLX5_OPCODE_SEND, olx);
4337 dseg = mlx5_tx_eseg_data(txq, loc, wqe, vlan,
4340 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4341 txq->inlen_mode - vlan;
4342 inlen -= txq->inlen_mode;
4343 mlx5_tx_dseg_ptr(txq, loc, dseg,
4346 * WQE is built, update the loop parameters
4347 * and got to the next packet.
4349 txq->wqe_ci += (ds + 3) / 4;
4350 loc->wqe_free -= (ds + 3) / 4;
4351 /* We have to store mbuf in elts.*/
4352 assert(MLX5_TXOFF_CONFIG(INLINE));
4353 txq->elts[txq->elts_head++ & txq->elts_m] =
4361 * Partially inlined packet data WQE, we have
4362 * some space in title WQEBB, we can fill it
4363 * with some packet data. It takes one WQEBB,
4364 * it is available, no extra space check:
4365 * - Control Segment, SEND opcode
4366 * - Ethernet Segment, no VLAN insertion
4367 * - MLX5_ESEG_MIN_INLINE_SIZE bytes of Data
4368 * - Data Segment, pointer type
4370 * We also get here if VLAN insertion is not
4371 * supported by HW, the inline is enabled.
4373 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4374 loc->wqe_last = wqe;
4375 mlx5_tx_cseg_init(txq, loc, wqe, 4,
4376 MLX5_OPCODE_SEND, olx);
4377 mlx5_tx_eseg_dmin(txq, loc, wqe, vlan, olx);
4378 dptr = rte_pktmbuf_mtod(loc->mbuf, uint8_t *) +
4379 MLX5_ESEG_MIN_INLINE_SIZE - vlan;
4381 * The length check is performed above, by
4382 * comparing with txq->inlen_send. We should
4383 * not get overflow here.
4385 assert(inlen > MLX5_ESEG_MIN_INLINE_SIZE);
4386 dlen = inlen - MLX5_ESEG_MIN_INLINE_SIZE;
4387 mlx5_tx_dseg_ptr(txq, loc, &wqe->dseg[1],
4391 /* We have to store mbuf in elts.*/
4392 assert(MLX5_TXOFF_CONFIG(INLINE));
4393 txq->elts[txq->elts_head++ & txq->elts_m] =
4397 #ifdef MLX5_PMD_SOFT_COUNTERS
4398 /* Update sent data bytes counter. */
4399 txq->stats.obytes += vlan +
4400 rte_pktmbuf_data_len(loc->mbuf);
4404 * No inline at all, it means the CPU cycles saving
4405 * is prioritized at configuration, we should not
4406 * copy any packet data to WQE.
4408 * SEND WQE, one WQEBB:
4409 * - Control Segment, SEND opcode
4410 * - Ethernet Segment, optional VLAN, no inline
4411 * - Data Segment, pointer type
4413 wqe = txq->wqes + (txq->wqe_ci & txq->wqe_m);
4414 loc->wqe_last = wqe;
4415 mlx5_tx_cseg_init(txq, loc, wqe, 3,
4416 MLX5_OPCODE_SEND, olx);
4417 mlx5_tx_eseg_none(txq, loc, wqe, olx);
4419 (txq, loc, &wqe->dseg[0],
4420 rte_pktmbuf_mtod(loc->mbuf, uint8_t *),
4421 rte_pktmbuf_data_len(loc->mbuf), olx);
4425 * We should not store mbuf pointer in elts
4426 * if no inlining is configured, this is done
4427 * by calling routine in a batch copy.
4429 assert(!MLX5_TXOFF_CONFIG(INLINE));
4431 #ifdef MLX5_PMD_SOFT_COUNTERS
4432 /* Update sent data bytes counter. */
4433 txq->stats.obytes += rte_pktmbuf_data_len(loc->mbuf);
4434 if (MLX5_TXOFF_CONFIG(VLAN) &&
4435 loc->mbuf->ol_flags & PKT_TX_VLAN_PKT)
4436 txq->stats.obytes +=
4437 sizeof(struct rte_vlan_hdr);
4442 /* Request CQE generation if limits are reached. */
4443 mlx5_tx_request_completion(txq, loc, olx);
4444 if (unlikely(!pkts_n || !loc->elts_free || !loc->wqe_free))
4445 return MLX5_TXCMP_CODE_EXIT;
4446 loc->mbuf = *pkts++;
4448 rte_prefetch0(*pkts);
4449 ret = mlx5_tx_able_to_empw(txq, loc, olx, true);
4450 if (unlikely(ret != MLX5_TXCMP_CODE_SINGLE))
4456 static __rte_always_inline enum mlx5_txcmp_code
4457 mlx5_tx_burst_single(struct mlx5_txq_data *restrict txq,
4458 struct rte_mbuf **restrict pkts,
4459 unsigned int pkts_n,
4460 struct mlx5_txq_local *restrict loc,
4463 enum mlx5_txcmp_code ret;
4465 ret = mlx5_tx_able_to_empw(txq, loc, olx, false);
4466 if (ret == MLX5_TXCMP_CODE_SINGLE)
4468 assert(ret == MLX5_TXCMP_CODE_EMPW);
4470 /* Optimize for inline/no inline eMPW send. */
4471 ret = (MLX5_TXOFF_CONFIG(INLINE)) ?
4472 mlx5_tx_burst_empw_inline
4473 (txq, pkts, pkts_n, loc, olx) :
4474 mlx5_tx_burst_empw_simple
4475 (txq, pkts, pkts_n, loc, olx);
4476 if (ret != MLX5_TXCMP_CODE_SINGLE)
4478 /* The resources to send one packet should remain. */
4479 assert(loc->elts_free && loc->wqe_free);
4481 ret = mlx5_tx_burst_single_send(txq, pkts, pkts_n, loc, olx);
4482 assert(ret != MLX5_TXCMP_CODE_SINGLE);
4483 if (ret != MLX5_TXCMP_CODE_EMPW)
4485 /* The resources to send one packet should remain. */
4486 assert(loc->elts_free && loc->wqe_free);
4491 * DPDK Tx callback template. This is configured template
4492 * used to generate routines optimized for specified offload setup.
4493 * One of this generated functions is chosen at SQ configuration
4497 * Generic pointer to TX queue structure.
4499 * Packets to transmit.
4501 * Number of packets in array.
4503 * Configured offloads mask, presents the bits of MLX5_TXOFF_CONFIG_xxx
4504 * values. Should be static to take compile time static configuration
4508 * Number of packets successfully transmitted (<= pkts_n).
4510 static __rte_always_inline uint16_t
4511 mlx5_tx_burst_tmpl(struct mlx5_txq_data *restrict txq,
4512 struct rte_mbuf **restrict pkts,
4516 struct mlx5_txq_local loc;
4517 enum mlx5_txcmp_code ret;
4520 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4521 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4522 if (unlikely(!pkts_n))
4526 loc.wqe_last = NULL;
4529 loc.pkts_loop = loc.pkts_sent;
4531 * Check if there are some CQEs, if any:
4532 * - process an encountered errors
4533 * - process the completed WQEs
4534 * - free related mbufs
4535 * - doorbell the NIC about processed CQEs
4537 rte_prefetch0(*(pkts + loc.pkts_sent));
4538 mlx5_tx_handle_completion(txq, olx);
4540 * Calculate the number of available resources - elts and WQEs.
4541 * There are two possible different scenarios:
4542 * - no data inlining into WQEs, one WQEBB may contains upto
4543 * four packets, in this case elts become scarce resource
4544 * - data inlining into WQEs, one packet may require multiple
4545 * WQEBBs, the WQEs become the limiting factor.
4547 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4548 loc.elts_free = txq->elts_s -
4549 (uint16_t)(txq->elts_head - txq->elts_tail);
4550 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4551 loc.wqe_free = txq->wqe_s -
4552 (uint16_t)(txq->wqe_ci - txq->wqe_pi);
4553 if (unlikely(!loc.elts_free || !loc.wqe_free))
4554 return loc.pkts_sent;
4557 * Fetch the packet from array. Usually this is
4558 * the first packet in series of multi/single
4561 loc.mbuf = *(pkts + loc.pkts_sent);
4562 /* Dedicated branch for multi-segment packets. */
4563 if (MLX5_TXOFF_CONFIG(MULTI) &&
4564 unlikely(NB_SEGS(loc.mbuf) > 1)) {
4566 * Multi-segment packet encountered.
4567 * Hardware is able to process it only
4568 * with SEND/TSO opcodes, one packet
4569 * per WQE, do it in dedicated routine.
4572 assert(loc.pkts_sent >= loc.pkts_copy);
4573 part = loc.pkts_sent - loc.pkts_copy;
4574 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4576 * There are some single-segment mbufs not
4577 * stored in elts. The mbufs must be in the
4578 * same order as WQEs, so we must copy the
4579 * mbufs to elts here, before the coming
4580 * multi-segment packet mbufs is appended.
4582 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy,
4584 loc.pkts_copy = loc.pkts_sent;
4586 assert(pkts_n > loc.pkts_sent);
4587 ret = mlx5_tx_burst_mseg(txq, pkts, pkts_n, &loc, olx);
4588 if (!MLX5_TXOFF_CONFIG(INLINE))
4589 loc.pkts_copy = loc.pkts_sent;
4591 * These returned code checks are supposed
4592 * to be optimized out due to routine inlining.
4594 if (ret == MLX5_TXCMP_CODE_EXIT) {
4596 * The routine returns this code when
4597 * all packets are sent or there is no
4598 * enough resources to complete request.
4602 if (ret == MLX5_TXCMP_CODE_ERROR) {
4604 * The routine returns this code when
4605 * some error in the incoming packets
4608 txq->stats.oerrors++;
4611 if (ret == MLX5_TXCMP_CODE_SINGLE) {
4613 * The single-segment packet was encountered
4614 * in the array, try to send it with the
4615 * best optimized way, possible engaging eMPW.
4617 goto enter_send_single;
4619 if (MLX5_TXOFF_CONFIG(TSO) &&
4620 ret == MLX5_TXCMP_CODE_TSO) {
4622 * The single-segment TSO packet was
4623 * encountered in the array.
4625 goto enter_send_tso;
4627 /* We must not get here. Something is going wrong. */
4629 txq->stats.oerrors++;
4632 /* Dedicated branch for single-segment TSO packets. */
4633 if (MLX5_TXOFF_CONFIG(TSO) &&
4634 unlikely(loc.mbuf->ol_flags & PKT_TX_TCP_SEG)) {
4636 * TSO might require special way for inlining
4637 * (dedicated parameters) and is sent with
4638 * MLX5_OPCODE_TSO opcode only, provide this
4639 * in dedicated branch.
4642 assert(NB_SEGS(loc.mbuf) == 1);
4643 assert(pkts_n > loc.pkts_sent);
4644 ret = mlx5_tx_burst_tso(txq, pkts, pkts_n, &loc, olx);
4646 * These returned code checks are supposed
4647 * to be optimized out due to routine inlining.
4649 if (ret == MLX5_TXCMP_CODE_EXIT)
4651 if (ret == MLX5_TXCMP_CODE_ERROR) {
4652 txq->stats.oerrors++;
4655 if (ret == MLX5_TXCMP_CODE_SINGLE)
4656 goto enter_send_single;
4657 if (MLX5_TXOFF_CONFIG(MULTI) &&
4658 ret == MLX5_TXCMP_CODE_MULTI) {
4660 * The multi-segment packet was
4661 * encountered in the array.
4663 goto enter_send_multi;
4665 /* We must not get here. Something is going wrong. */
4667 txq->stats.oerrors++;
4671 * The dedicated branch for the single-segment packets
4672 * without TSO. Often these ones can be sent using
4673 * MLX5_OPCODE_EMPW with multiple packets in one WQE.
4674 * The routine builds the WQEs till it encounters
4675 * the TSO or multi-segment packet (in case if these
4676 * offloads are requested at SQ configuration time).
4679 assert(pkts_n > loc.pkts_sent);
4680 ret = mlx5_tx_burst_single(txq, pkts, pkts_n, &loc, olx);
4682 * These returned code checks are supposed
4683 * to be optimized out due to routine inlining.
4685 if (ret == MLX5_TXCMP_CODE_EXIT)
4687 if (ret == MLX5_TXCMP_CODE_ERROR) {
4688 txq->stats.oerrors++;
4691 if (MLX5_TXOFF_CONFIG(MULTI) &&
4692 ret == MLX5_TXCMP_CODE_MULTI) {
4694 * The multi-segment packet was
4695 * encountered in the array.
4697 goto enter_send_multi;
4699 if (MLX5_TXOFF_CONFIG(TSO) &&
4700 ret == MLX5_TXCMP_CODE_TSO) {
4702 * The single-segment TSO packet was
4703 * encountered in the array.
4705 goto enter_send_tso;
4707 /* We must not get here. Something is going wrong. */
4709 txq->stats.oerrors++;
4713 * Main Tx loop is completed, do the rest:
4714 * - set completion request if thresholds are reached
4715 * - doorbell the hardware
4716 * - copy the rest of mbufs to elts (if any)
4718 assert(MLX5_TXOFF_CONFIG(INLINE) || loc.pkts_sent >= loc.pkts_copy);
4719 /* Take a shortcut if nothing is sent. */
4720 if (unlikely(loc.pkts_sent == loc.pkts_loop))
4721 return loc.pkts_sent;
4723 * Ring QP doorbell immediately after WQE building completion
4724 * to improve latencies. The pure software related data treatment
4725 * can be completed after doorbell. Tx CQEs for this SQ are
4726 * processed in this thread only by the polling.
4728 mlx5_tx_dbrec_cond_wmb(txq, loc.wqe_last, 0);
4729 /* Not all of the mbufs may be stored into elts yet. */
4730 part = MLX5_TXOFF_CONFIG(INLINE) ? 0 : loc.pkts_sent - loc.pkts_copy;
4731 if (!MLX5_TXOFF_CONFIG(INLINE) && part) {
4733 * There are some single-segment mbufs not stored in elts.
4734 * It can be only if the last packet was single-segment.
4735 * The copying is gathered into one place due to it is
4736 * a good opportunity to optimize that with SIMD.
4737 * Unfortunately if inlining is enabled the gaps in
4738 * pointer array may happen due to early freeing of the
4741 mlx5_tx_copy_elts(txq, pkts + loc.pkts_copy, part, olx);
4742 loc.pkts_copy = loc.pkts_sent;
4744 #ifdef MLX5_PMD_SOFT_COUNTERS
4745 /* Increment sent packets counter. */
4746 txq->stats.opackets += loc.pkts_sent;
4748 assert(txq->elts_s >= (uint16_t)(txq->elts_head - txq->elts_tail));
4749 assert(txq->wqe_s >= (uint16_t)(txq->wqe_ci - txq->wqe_pi));
4750 if (pkts_n > loc.pkts_sent) {
4752 * If burst size is large there might be no enough CQE
4753 * fetched from completion queue and no enough resources
4754 * freed to send all the packets.
4758 return loc.pkts_sent;
4761 /* Generate routines with Enhanced Multi-Packet Write support. */
4762 MLX5_TXOFF_DECL(full_empw,
4763 MLX5_TXOFF_CONFIG_FULL | MLX5_TXOFF_CONFIG_EMPW)
4765 MLX5_TXOFF_DECL(none_empw,
4766 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4768 MLX5_TXOFF_DECL(md_empw,
4769 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4771 MLX5_TXOFF_DECL(mt_empw,
4772 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4773 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4775 MLX5_TXOFF_DECL(mtsc_empw,
4776 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4777 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4778 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4780 MLX5_TXOFF_DECL(mti_empw,
4781 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4782 MLX5_TXOFF_CONFIG_INLINE |
4783 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4785 MLX5_TXOFF_DECL(mtv_empw,
4786 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4787 MLX5_TXOFF_CONFIG_VLAN |
4788 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4790 MLX5_TXOFF_DECL(mtiv_empw,
4791 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4792 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4793 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4795 MLX5_TXOFF_DECL(sc_empw,
4796 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4797 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4799 MLX5_TXOFF_DECL(sci_empw,
4800 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4801 MLX5_TXOFF_CONFIG_INLINE |
4802 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4804 MLX5_TXOFF_DECL(scv_empw,
4805 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4806 MLX5_TXOFF_CONFIG_VLAN |
4807 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4809 MLX5_TXOFF_DECL(sciv_empw,
4810 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4811 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4812 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4814 MLX5_TXOFF_DECL(i_empw,
4815 MLX5_TXOFF_CONFIG_INLINE |
4816 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4818 MLX5_TXOFF_DECL(v_empw,
4819 MLX5_TXOFF_CONFIG_VLAN |
4820 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4822 MLX5_TXOFF_DECL(iv_empw,
4823 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4824 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4826 /* Generate routines without Enhanced Multi-Packet Write support. */
4827 MLX5_TXOFF_DECL(full,
4828 MLX5_TXOFF_CONFIG_FULL)
4830 MLX5_TXOFF_DECL(none,
4831 MLX5_TXOFF_CONFIG_NONE)
4834 MLX5_TXOFF_CONFIG_METADATA)
4837 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4838 MLX5_TXOFF_CONFIG_METADATA)
4840 MLX5_TXOFF_DECL(mtsc,
4841 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4842 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4843 MLX5_TXOFF_CONFIG_METADATA)
4845 MLX5_TXOFF_DECL(mti,
4846 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4847 MLX5_TXOFF_CONFIG_INLINE |
4848 MLX5_TXOFF_CONFIG_METADATA)
4851 MLX5_TXOFF_DECL(mtv,
4852 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4853 MLX5_TXOFF_CONFIG_VLAN |
4854 MLX5_TXOFF_CONFIG_METADATA)
4857 MLX5_TXOFF_DECL(mtiv,
4858 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4859 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4860 MLX5_TXOFF_CONFIG_METADATA)
4863 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4864 MLX5_TXOFF_CONFIG_METADATA)
4866 MLX5_TXOFF_DECL(sci,
4867 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4868 MLX5_TXOFF_CONFIG_INLINE |
4869 MLX5_TXOFF_CONFIG_METADATA)
4872 MLX5_TXOFF_DECL(scv,
4873 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4874 MLX5_TXOFF_CONFIG_VLAN |
4875 MLX5_TXOFF_CONFIG_METADATA)
4878 MLX5_TXOFF_DECL(sciv,
4879 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4880 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4881 MLX5_TXOFF_CONFIG_METADATA)
4884 MLX5_TXOFF_CONFIG_INLINE |
4885 MLX5_TXOFF_CONFIG_METADATA)
4888 MLX5_TXOFF_CONFIG_VLAN |
4889 MLX5_TXOFF_CONFIG_METADATA)
4892 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4893 MLX5_TXOFF_CONFIG_METADATA)
4896 * Array of declared and compiled Tx burst function and corresponding
4897 * supported offloads set. The array is used to select the Tx burst
4898 * function for specified offloads set at Tx queue configuration time.
4901 eth_tx_burst_t func;
4904 MLX5_TXOFF_INFO(full_empw,
4905 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4906 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4907 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4908 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4910 MLX5_TXOFF_INFO(none_empw,
4911 MLX5_TXOFF_CONFIG_NONE | MLX5_TXOFF_CONFIG_EMPW)
4913 MLX5_TXOFF_INFO(md_empw,
4914 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4916 MLX5_TXOFF_INFO(mt_empw,
4917 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4918 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4920 MLX5_TXOFF_INFO(mtsc_empw,
4921 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4922 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4923 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4925 MLX5_TXOFF_INFO(mti_empw,
4926 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4927 MLX5_TXOFF_CONFIG_INLINE |
4928 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4930 MLX5_TXOFF_INFO(mtv_empw,
4931 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4932 MLX5_TXOFF_CONFIG_VLAN |
4933 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4935 MLX5_TXOFF_INFO(mtiv_empw,
4936 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4937 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4938 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4940 MLX5_TXOFF_INFO(sc_empw,
4941 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4942 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4944 MLX5_TXOFF_INFO(sci_empw,
4945 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4946 MLX5_TXOFF_CONFIG_INLINE |
4947 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4949 MLX5_TXOFF_INFO(scv_empw,
4950 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4951 MLX5_TXOFF_CONFIG_VLAN |
4952 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4954 MLX5_TXOFF_INFO(sciv_empw,
4955 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4956 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4957 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4959 MLX5_TXOFF_INFO(i_empw,
4960 MLX5_TXOFF_CONFIG_INLINE |
4961 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4963 MLX5_TXOFF_INFO(v_empw,
4964 MLX5_TXOFF_CONFIG_VLAN |
4965 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4967 MLX5_TXOFF_INFO(iv_empw,
4968 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4969 MLX5_TXOFF_CONFIG_METADATA | MLX5_TXOFF_CONFIG_EMPW)
4971 MLX5_TXOFF_INFO(full,
4972 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4973 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4974 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
4975 MLX5_TXOFF_CONFIG_METADATA)
4977 MLX5_TXOFF_INFO(none,
4978 MLX5_TXOFF_CONFIG_NONE)
4981 MLX5_TXOFF_CONFIG_METADATA)
4984 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4985 MLX5_TXOFF_CONFIG_METADATA)
4987 MLX5_TXOFF_INFO(mtsc,
4988 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4989 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
4990 MLX5_TXOFF_CONFIG_METADATA)
4992 MLX5_TXOFF_INFO(mti,
4993 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
4994 MLX5_TXOFF_CONFIG_INLINE |
4995 MLX5_TXOFF_CONFIG_METADATA)
4998 MLX5_TXOFF_INFO(mtv,
4999 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5000 MLX5_TXOFF_CONFIG_VLAN |
5001 MLX5_TXOFF_CONFIG_METADATA)
5003 MLX5_TXOFF_INFO(mtiv,
5004 MLX5_TXOFF_CONFIG_MULTI | MLX5_TXOFF_CONFIG_TSO |
5005 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5006 MLX5_TXOFF_CONFIG_METADATA)
5009 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5010 MLX5_TXOFF_CONFIG_METADATA)
5012 MLX5_TXOFF_INFO(sci,
5013 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5014 MLX5_TXOFF_CONFIG_INLINE |
5015 MLX5_TXOFF_CONFIG_METADATA)
5017 MLX5_TXOFF_INFO(scv,
5018 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5019 MLX5_TXOFF_CONFIG_VLAN |
5020 MLX5_TXOFF_CONFIG_METADATA)
5022 MLX5_TXOFF_INFO(sciv,
5023 MLX5_TXOFF_CONFIG_SWP | MLX5_TXOFF_CONFIG_CSUM |
5024 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5025 MLX5_TXOFF_CONFIG_METADATA)
5028 MLX5_TXOFF_CONFIG_INLINE |
5029 MLX5_TXOFF_CONFIG_METADATA)
5032 MLX5_TXOFF_CONFIG_VLAN |
5033 MLX5_TXOFF_CONFIG_METADATA)
5036 MLX5_TXOFF_CONFIG_INLINE | MLX5_TXOFF_CONFIG_VLAN |
5037 MLX5_TXOFF_CONFIG_METADATA)
5041 * Configure the Tx function to use. The routine checks configured
5042 * Tx offloads for the device and selects appropriate Tx burst
5043 * routine. There are multiple Tx burst routines compiled from
5044 * the same template in the most optimal way for the dedicated
5048 * Pointer to private data structure.
5051 * Pointer to selected Tx burst function.
5054 mlx5_select_tx_function(struct rte_eth_dev *dev)
5056 struct mlx5_priv *priv = dev->data->dev_private;
5057 struct mlx5_dev_config *config = &priv->config;
5058 uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
5059 unsigned int diff = 0, olx = 0, i, m;
5061 static_assert(MLX5_WQE_SIZE_MAX / MLX5_WSEG_SIZE <=
5062 MLX5_DSEG_MAX, "invalid WQE max size");
5063 static_assert(MLX5_WQE_CSEG_SIZE == MLX5_WSEG_SIZE,
5064 "invalid WQE Control Segment size");
5065 static_assert(MLX5_WQE_ESEG_SIZE == MLX5_WSEG_SIZE,
5066 "invalid WQE Ethernet Segment size");
5067 static_assert(MLX5_WQE_DSEG_SIZE == MLX5_WSEG_SIZE,
5068 "invalid WQE Data Segment size");
5069 static_assert(MLX5_WQE_SIZE == 4 * MLX5_WSEG_SIZE,
5070 "invalid WQE size");
5072 if (tx_offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
5073 /* We should support Multi-Segment Packets. */
5074 olx |= MLX5_TXOFF_CONFIG_MULTI;
5076 if (tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
5077 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
5078 DEV_TX_OFFLOAD_GRE_TNL_TSO |
5079 DEV_TX_OFFLOAD_IP_TNL_TSO |
5080 DEV_TX_OFFLOAD_UDP_TNL_TSO)) {
5081 /* We should support TCP Send Offload. */
5082 olx |= MLX5_TXOFF_CONFIG_TSO;
5084 if (tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
5085 DEV_TX_OFFLOAD_UDP_TNL_TSO |
5086 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5087 /* We should support Software Parser for Tunnels. */
5088 olx |= MLX5_TXOFF_CONFIG_SWP;
5090 if (tx_offloads & (DEV_TX_OFFLOAD_IPV4_CKSUM |
5091 DEV_TX_OFFLOAD_UDP_CKSUM |
5092 DEV_TX_OFFLOAD_TCP_CKSUM |
5093 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM)) {
5094 /* We should support IP/TCP/UDP Checksums. */
5095 olx |= MLX5_TXOFF_CONFIG_CSUM;
5097 if (tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT) {
5098 /* We should support VLAN insertion. */
5099 olx |= MLX5_TXOFF_CONFIG_VLAN;
5101 if (priv->txqs_n && (*priv->txqs)[0]) {
5102 struct mlx5_txq_data *txd = (*priv->txqs)[0];
5104 if (txd->inlen_send) {
5106 * Check the data inline requirements. Data inline
5107 * is enabled on per device basis, we can check
5108 * the first Tx queue only.
5110 * If device does not support VLAN insertion in WQE
5111 * and some queues are requested to perform VLAN
5112 * insertion offload than inline must be enabled.
5114 olx |= MLX5_TXOFF_CONFIG_INLINE;
5117 if (config->mps == MLX5_MPW_ENHANCED &&
5118 config->txq_inline_min <= 0) {
5120 * The NIC supports Enhanced Multi-Packet Write.
5121 * We do not support legacy MPW due to its
5122 * hardware related problems, so we just ignore
5123 * legacy MLX5_MPW settings. There should be no
5124 * minimal required inline data.
5126 olx |= MLX5_TXOFF_CONFIG_EMPW;
5128 if (tx_offloads & DEV_TX_OFFLOAD_MATCH_METADATA) {
5129 /* We should support Flow metadata. */
5130 olx |= MLX5_TXOFF_CONFIG_METADATA;
5133 * Scan the routines table to find the minimal
5134 * satisfying routine with requested offloads.
5136 m = RTE_DIM(txoff_func);
5137 for (i = 0; i < RTE_DIM(txoff_func); i++) {
5140 tmp = txoff_func[i].olx;
5142 /* Meets requested offloads exactly.*/
5146 if ((tmp & olx) != olx) {
5147 /* Does not meet requested offloads at all. */
5150 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_EMPW)
5151 /* Do not enable eMPW if not configured. */
5153 if ((olx ^ tmp) & MLX5_TXOFF_CONFIG_INLINE)
5154 /* Do not enable inlining if not configured. */
5157 * Some routine meets the requirements.
5158 * Check whether it has minimal amount
5159 * of not requested offloads.
5161 tmp = __builtin_popcountl(tmp & ~olx);
5162 if (m >= RTE_DIM(txoff_func) || tmp < diff) {
5163 /* First or better match, save and continue. */
5169 tmp = txoff_func[i].olx ^ txoff_func[m].olx;
5170 if (__builtin_ffsl(txoff_func[i].olx & ~tmp) <
5171 __builtin_ffsl(txoff_func[m].olx & ~tmp)) {
5172 /* Lighter not requested offload. */
5177 if (m >= RTE_DIM(txoff_func)) {
5178 DRV_LOG(DEBUG, "port %u has no selected Tx function"
5179 " for requested offloads %04X",
5180 dev->data->port_id, olx);
5183 DRV_LOG(DEBUG, "port %u has selected Tx function"
5184 " supporting offloads %04X/%04X",
5185 dev->data->port_id, olx, txoff_func[m].olx);
5186 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_MULTI)
5187 DRV_LOG(DEBUG, "\tMULTI (multi segment)");
5188 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_TSO)
5189 DRV_LOG(DEBUG, "\tTSO (TCP send offload)");
5190 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_SWP)
5191 DRV_LOG(DEBUG, "\tSWP (software parser)");
5192 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_CSUM)
5193 DRV_LOG(DEBUG, "\tCSUM (checksum offload)");
5194 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_INLINE)
5195 DRV_LOG(DEBUG, "\tINLIN (inline data)");
5196 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_VLAN)
5197 DRV_LOG(DEBUG, "\tVLANI (VLAN insertion)");
5198 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_METADATA)
5199 DRV_LOG(DEBUG, "\tMETAD (tx Flow metadata)");
5200 if (txoff_func[m].olx & MLX5_TXOFF_CONFIG_EMPW)
5201 DRV_LOG(DEBUG, "\tEMPW (Enhanced MPW)");
5202 return txoff_func[m].func;