4 * Copyright 2015 6WIND S.A.
5 * Copyright 2015 Mellanox.
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8 * modification, are permitted provided that the following conditions
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19 * from this software without specific prior written permission.
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23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
42 #pragma GCC diagnostic ignored "-Wpedantic"
44 #include <infiniband/verbs.h>
45 #include <infiniband/mlx5dv.h>
47 #pragma GCC diagnostic error "-Wpedantic"
51 #include <rte_mempool.h>
52 #include <rte_prefetch.h>
53 #include <rte_common.h>
54 #include <rte_branch_prediction.h>
55 #include <rte_ether.h>
58 #include "mlx5_utils.h"
59 #include "mlx5_rxtx.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 static __rte_always_inline uint32_t
65 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe);
67 static __rte_always_inline int
68 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
69 uint16_t cqe_cnt, uint32_t *rss_hash);
71 static __rte_always_inline uint32_t
72 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe);
74 uint32_t mlx5_ptype_table[] __rte_cache_aligned = {
75 [0xff] = RTE_PTYPE_ALL_MASK, /* Last entry for errored packet. */
79 * Build a table to translate Rx completion flags to packet type.
81 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
84 mlx5_set_ptype_table(void)
87 uint32_t (*p)[RTE_DIM(mlx5_ptype_table)] = &mlx5_ptype_table;
89 /* Last entry must not be overwritten, reserved for errored packet. */
90 for (i = 0; i < RTE_DIM(mlx5_ptype_table) - 1; ++i)
91 (*p)[i] = RTE_PTYPE_UNKNOWN;
93 * The index to the array should have:
94 * bit[1:0] = l3_hdr_type
95 * bit[4:2] = l4_hdr_type
98 * bit[7] = outer_l3_type
101 (*p)[0x00] = RTE_PTYPE_L2_ETHER;
103 (*p)[0x01] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
104 RTE_PTYPE_L4_NONFRAG;
105 (*p)[0x02] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
106 RTE_PTYPE_L4_NONFRAG;
108 (*p)[0x21] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
110 (*p)[0x22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
113 (*p)[0x05] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
115 (*p)[0x06] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
118 (*p)[0x09] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
120 (*p)[0x0a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
122 /* Repeat with outer_l3_type being set. Just in case. */
123 (*p)[0x81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
124 RTE_PTYPE_L4_NONFRAG;
125 (*p)[0x82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
126 RTE_PTYPE_L4_NONFRAG;
127 (*p)[0xa1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
129 (*p)[0xa2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
131 (*p)[0x85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
133 (*p)[0x86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
135 (*p)[0x89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
137 (*p)[0x8a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
140 (*p)[0x41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
141 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
142 RTE_PTYPE_INNER_L4_NONFRAG;
143 (*p)[0x42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
144 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
145 RTE_PTYPE_INNER_L4_NONFRAG;
146 (*p)[0xc1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
147 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
148 RTE_PTYPE_INNER_L4_NONFRAG;
149 (*p)[0xc2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
150 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
151 RTE_PTYPE_INNER_L4_NONFRAG;
152 /* Tunneled - Fragmented */
153 (*p)[0x61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
154 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
155 RTE_PTYPE_INNER_L4_FRAG;
156 (*p)[0x62] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
157 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
158 RTE_PTYPE_INNER_L4_FRAG;
159 (*p)[0xe1] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
160 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
161 RTE_PTYPE_INNER_L4_FRAG;
162 (*p)[0xe2] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
163 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
164 RTE_PTYPE_INNER_L4_FRAG;
166 (*p)[0x45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
167 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
168 RTE_PTYPE_INNER_L4_TCP;
169 (*p)[0x46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
170 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
171 RTE_PTYPE_INNER_L4_TCP;
172 (*p)[0xc5] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
173 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
174 RTE_PTYPE_INNER_L4_TCP;
175 (*p)[0xc6] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
176 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
177 RTE_PTYPE_INNER_L4_TCP;
179 (*p)[0x49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
180 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
181 RTE_PTYPE_INNER_L4_UDP;
182 (*p)[0x4a] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
183 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
184 RTE_PTYPE_INNER_L4_UDP;
185 (*p)[0xc9] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
186 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
187 RTE_PTYPE_INNER_L4_UDP;
188 (*p)[0xca] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
189 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
190 RTE_PTYPE_INNER_L4_UDP;
194 * Return the size of tailroom of WQ.
197 * Pointer to TX queue structure.
199 * Pointer to tail of WQ.
205 tx_mlx5_wq_tailroom(struct mlx5_txq_data *txq, void *addr)
208 tailroom = (uintptr_t)(txq->wqes) +
209 (1 << txq->wqe_n) * MLX5_WQE_SIZE -
215 * Copy data to tailroom of circular queue.
218 * Pointer to destination.
222 * Number of bytes to copy.
224 * Pointer to head of queue.
226 * Size of tailroom from dst.
229 * Pointer after copied data.
232 mlx5_copy_to_wq(void *dst, const void *src, size_t n,
233 void *base, size_t tailroom)
238 rte_memcpy(dst, src, tailroom);
239 rte_memcpy(base, (void *)((uintptr_t)src + tailroom),
241 ret = (uint8_t *)base + n - tailroom;
243 rte_memcpy(dst, src, n);
244 ret = (n == tailroom) ? base : (uint8_t *)dst + n;
250 * DPDK callback to check the status of a tx descriptor.
255 * The index of the descriptor in the ring.
258 * The status of the tx descriptor.
261 mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset)
263 struct mlx5_txq_data *txq = tx_queue;
266 mlx5_tx_complete(txq);
267 used = txq->elts_head - txq->elts_tail;
269 return RTE_ETH_TX_DESC_FULL;
270 return RTE_ETH_TX_DESC_DONE;
274 * DPDK callback to check the status of a rx descriptor.
279 * The index of the descriptor in the ring.
282 * The status of the tx descriptor.
285 mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset)
287 struct mlx5_rxq_data *rxq = rx_queue;
288 struct rxq_zip *zip = &rxq->zip;
289 volatile struct mlx5_cqe *cqe;
290 const unsigned int cqe_n = (1 << rxq->cqe_n);
291 const unsigned int cqe_cnt = cqe_n - 1;
295 /* if we are processing a compressed cqe */
297 used = zip->cqe_cnt - zip->ca;
303 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
304 while (check_cqe(cqe, cqe_n, cq_ci) == 0) {
308 op_own = cqe->op_own;
309 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED)
310 n = rte_be_to_cpu_32(cqe->byte_cnt);
315 cqe = &(*rxq->cqes)[cq_ci & cqe_cnt];
317 used = RTE_MIN(used, (1U << rxq->elts_n) - 1);
319 return RTE_ETH_RX_DESC_DONE;
320 return RTE_ETH_RX_DESC_AVAIL;
324 * DPDK callback for TX.
327 * Generic pointer to TX queue structure.
329 * Packets to transmit.
331 * Number of packets in array.
334 * Number of packets successfully transmitted (<= pkts_n).
337 mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
339 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
340 uint16_t elts_head = txq->elts_head;
341 const uint16_t elts_n = 1 << txq->elts_n;
342 const uint16_t elts_m = elts_n - 1;
349 volatile struct mlx5_wqe_ctrl *last_wqe = NULL;
350 unsigned int segs_n = 0;
351 const unsigned int max_inline = txq->max_inline;
353 if (unlikely(!pkts_n))
355 /* Prefetch first packet cacheline. */
356 rte_prefetch0(*pkts);
357 /* Start processing. */
358 mlx5_tx_complete(txq);
359 max_elts = (elts_n - (elts_head - txq->elts_tail));
360 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
361 if (unlikely(!max_wqe))
364 struct rte_mbuf *buf = NULL;
366 volatile struct mlx5_wqe_v *wqe = NULL;
367 volatile rte_v128u32_t *dseg = NULL;
370 unsigned int sg = 0; /* counter of additional segs attached. */
372 uint16_t pkt_inline_sz = MLX5_WQE_DWORD_SIZE + 2;
373 uint16_t tso_header_sz = 0;
377 uint16_t tso_segsz = 0;
378 #ifdef MLX5_PMD_SOFT_COUNTERS
379 uint32_t total_length = 0;
384 segs_n = buf->nb_segs;
386 * Make sure there is enough room to store this packet and
387 * that one ring entry remains unused.
390 if (max_elts < segs_n)
394 if (unlikely(--max_wqe == 0))
396 wqe = (volatile struct mlx5_wqe_v *)
397 tx_mlx5_wqe(txq, txq->wqe_ci);
398 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
400 rte_prefetch0(*(pkts + 1));
401 addr = rte_pktmbuf_mtod(buf, uintptr_t);
402 length = DATA_LEN(buf);
403 ehdr = (((uint8_t *)addr)[1] << 8) |
404 ((uint8_t *)addr)[0];
405 #ifdef MLX5_PMD_SOFT_COUNTERS
406 total_length = length;
408 if (length < (MLX5_WQE_DWORD_SIZE + 2)) {
409 txq->stats.oerrors++;
412 /* Update element. */
413 (*txq->elts)[elts_head & elts_m] = buf;
414 /* Prefetch next buffer data. */
417 rte_pktmbuf_mtod(*(pkts + 1), volatile void *));
418 cs_flags = txq_ol_cksum_to_cs(txq, buf);
419 raw = ((uint8_t *)(uintptr_t)wqe) + 2 * MLX5_WQE_DWORD_SIZE;
420 /* Replace the Ethernet type by the VLAN if necessary. */
421 if (buf->ol_flags & PKT_TX_VLAN_PKT) {
422 uint32_t vlan = rte_cpu_to_be_32(0x81000000 |
424 unsigned int len = 2 * ETHER_ADDR_LEN - 2;
428 /* Copy Destination and source mac address. */
429 memcpy((uint8_t *)raw, ((uint8_t *)addr), len);
431 memcpy((uint8_t *)raw + len, &vlan, sizeof(vlan));
432 /* Copy missing two bytes to end the DSeg. */
433 memcpy((uint8_t *)raw + len + sizeof(vlan),
434 ((uint8_t *)addr) + len, 2);
438 memcpy((uint8_t *)raw, ((uint8_t *)addr) + 2,
439 MLX5_WQE_DWORD_SIZE);
440 length -= pkt_inline_sz;
441 addr += pkt_inline_sz;
443 raw += MLX5_WQE_DWORD_SIZE;
445 tso = buf->ol_flags & PKT_TX_TCP_SEG;
447 uintptr_t end = (uintptr_t)
448 (((uintptr_t)txq->wqes) +
452 uint8_t vlan_sz = (buf->ol_flags &
453 PKT_TX_VLAN_PKT) ? 4 : 0;
454 const uint64_t is_tunneled =
457 PKT_TX_TUNNEL_VXLAN);
459 tso_header_sz = buf->l2_len + vlan_sz +
460 buf->l3_len + buf->l4_len;
461 tso_segsz = buf->tso_segsz;
462 if (unlikely(tso_segsz == 0)) {
463 txq->stats.oerrors++;
466 if (is_tunneled && txq->tunnel_en) {
467 tso_header_sz += buf->outer_l2_len +
469 cs_flags |= MLX5_ETH_WQE_L4_INNER_CSUM;
471 cs_flags |= MLX5_ETH_WQE_L4_CSUM;
473 if (unlikely(tso_header_sz >
474 MLX5_MAX_TSO_HEADER)) {
475 txq->stats.oerrors++;
478 copy_b = tso_header_sz - pkt_inline_sz;
479 /* First seg must contain all headers. */
480 assert(copy_b <= length);
482 ((end - (uintptr_t)raw) > copy_b)) {
483 uint16_t n = (MLX5_WQE_DS(copy_b) -
486 if (unlikely(max_wqe < n))
489 rte_memcpy((void *)raw,
490 (void *)addr, copy_b);
493 /* Include padding for TSO header. */
494 copy_b = MLX5_WQE_DS(copy_b) *
496 pkt_inline_sz += copy_b;
500 wqe->ctrl = (rte_v128u32_t){
509 #ifdef MLX5_PMD_SOFT_COUNTERS
517 /* Inline if enough room. */
518 if (max_inline || tso) {
520 uintptr_t end = (uintptr_t)
521 (((uintptr_t)txq->wqes) +
522 (1 << txq->wqe_n) * MLX5_WQE_SIZE);
523 unsigned int inline_room = max_inline *
524 RTE_CACHE_LINE_SIZE -
525 (pkt_inline_sz - 2) -
531 addr_end = RTE_ALIGN_FLOOR(addr + inline_room,
532 RTE_CACHE_LINE_SIZE);
533 copy_b = (addr_end > addr) ?
534 RTE_MIN((addr_end - addr), length) : 0;
535 if (copy_b && ((end - (uintptr_t)raw) > copy_b)) {
537 * One Dseg remains in the current WQE. To
538 * keep the computation positive, it is
539 * removed after the bytes to Dseg conversion.
541 uint16_t n = (MLX5_WQE_DS(copy_b) - 1 + 3) / 4;
543 if (unlikely(max_wqe < n))
547 inl = rte_cpu_to_be_32(copy_b |
549 rte_memcpy((void *)raw,
550 (void *)&inl, sizeof(inl));
552 pkt_inline_sz += sizeof(inl);
554 rte_memcpy((void *)raw, (void *)addr, copy_b);
557 pkt_inline_sz += copy_b;
560 * 2 DWORDs consumed by the WQE header + ETH segment +
561 * the size of the inline part of the packet.
563 ds = 2 + MLX5_WQE_DS(pkt_inline_sz - 2);
565 if (ds % (MLX5_WQE_SIZE /
566 MLX5_WQE_DWORD_SIZE) == 0) {
567 if (unlikely(--max_wqe == 0))
569 dseg = (volatile rte_v128u32_t *)
570 tx_mlx5_wqe(txq, txq->wqe_ci +
573 dseg = (volatile rte_v128u32_t *)
575 (ds * MLX5_WQE_DWORD_SIZE));
578 } else if (!segs_n) {
582 inline_room -= copy_b;
586 addr = rte_pktmbuf_mtod(buf, uintptr_t);
587 length = DATA_LEN(buf);
588 #ifdef MLX5_PMD_SOFT_COUNTERS
589 total_length += length;
591 (*txq->elts)[++elts_head & elts_m] = buf;
596 * No inline has been done in the packet, only the
597 * Ethernet Header as been stored.
599 dseg = (volatile rte_v128u32_t *)
600 ((uintptr_t)wqe + (3 * MLX5_WQE_DWORD_SIZE));
603 /* Add the remaining packet as a simple ds. */
604 addr = rte_cpu_to_be_64(addr);
605 *dseg = (rte_v128u32_t){
606 rte_cpu_to_be_32(length),
607 mlx5_tx_mb2mr(txq, buf),
620 * Spill on next WQE when the current one does not have
621 * enough room left. Size of WQE must a be a multiple
622 * of data segment size.
624 assert(!(MLX5_WQE_SIZE % MLX5_WQE_DWORD_SIZE));
625 if (!(ds % (MLX5_WQE_SIZE / MLX5_WQE_DWORD_SIZE))) {
626 if (unlikely(--max_wqe == 0))
628 dseg = (volatile rte_v128u32_t *)
629 tx_mlx5_wqe(txq, txq->wqe_ci + ds / 4);
630 rte_prefetch0(tx_mlx5_wqe(txq,
631 txq->wqe_ci + ds / 4 + 1));
638 length = DATA_LEN(buf);
639 #ifdef MLX5_PMD_SOFT_COUNTERS
640 total_length += length;
642 /* Store segment information. */
643 addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(buf, uintptr_t));
644 *dseg = (rte_v128u32_t){
645 rte_cpu_to_be_32(length),
646 mlx5_tx_mb2mr(txq, buf),
650 (*txq->elts)[++elts_head & elts_m] = buf;
654 if (ds > MLX5_DSEG_MAX) {
655 txq->stats.oerrors++;
662 /* Initialize known and common part of the WQE structure. */
664 wqe->ctrl = (rte_v128u32_t){
665 rte_cpu_to_be_32((txq->wqe_ci << 8) |
667 rte_cpu_to_be_32(txq->qp_num_8s | ds),
671 wqe->eseg = (rte_v128u32_t){
673 cs_flags | (rte_cpu_to_be_16(tso_segsz) << 16),
675 (ehdr << 16) | rte_cpu_to_be_16(tso_header_sz),
678 wqe->ctrl = (rte_v128u32_t){
679 rte_cpu_to_be_32((txq->wqe_ci << 8) |
681 rte_cpu_to_be_32(txq->qp_num_8s | ds),
685 wqe->eseg = (rte_v128u32_t){
689 (ehdr << 16) | rte_cpu_to_be_16(pkt_inline_sz),
693 txq->wqe_ci += (ds + 3) / 4;
694 /* Save the last successful WQE for completion request */
695 last_wqe = (volatile struct mlx5_wqe_ctrl *)wqe;
696 #ifdef MLX5_PMD_SOFT_COUNTERS
697 /* Increment sent bytes counter. */
698 txq->stats.obytes += total_length;
700 } while (i < pkts_n);
701 /* Take a shortcut if nothing must be sent. */
702 if (unlikely((i + k) == 0))
704 txq->elts_head += (i + j);
705 /* Check whether completion threshold has been reached. */
706 comp = txq->elts_comp + i + j + k;
707 if (comp >= MLX5_TX_COMP_THRESH) {
708 /* Request completion on last WQE. */
709 last_wqe->ctrl2 = rte_cpu_to_be_32(8);
710 /* Save elts_head in unused "immediate" field of WQE. */
711 last_wqe->ctrl3 = txq->elts_head;
714 txq->elts_comp = comp;
716 #ifdef MLX5_PMD_SOFT_COUNTERS
717 /* Increment sent packets counter. */
718 txq->stats.opackets += i;
720 /* Ring QP doorbell. */
721 mlx5_tx_dbrec(txq, (volatile struct mlx5_wqe *)last_wqe);
726 * Open a MPW session.
729 * Pointer to TX queue structure.
731 * Pointer to MPW session structure.
736 mlx5_mpw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, uint32_t length)
738 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
739 volatile struct mlx5_wqe_data_seg (*dseg)[MLX5_MPW_DSEG_MAX] =
740 (volatile struct mlx5_wqe_data_seg (*)[])
741 tx_mlx5_wqe(txq, idx + 1);
743 mpw->state = MLX5_MPW_STATE_OPENED;
747 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
748 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
749 mpw->wqe->eseg.inline_hdr_sz = 0;
750 mpw->wqe->eseg.rsvd0 = 0;
751 mpw->wqe->eseg.rsvd1 = 0;
752 mpw->wqe->eseg.rsvd2 = 0;
753 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
756 mpw->wqe->ctrl[2] = 0;
757 mpw->wqe->ctrl[3] = 0;
758 mpw->data.dseg[0] = (volatile struct mlx5_wqe_data_seg *)
759 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
760 mpw->data.dseg[1] = (volatile struct mlx5_wqe_data_seg *)
761 (((uintptr_t)mpw->wqe) + (3 * MLX5_WQE_DWORD_SIZE));
762 mpw->data.dseg[2] = &(*dseg)[0];
763 mpw->data.dseg[3] = &(*dseg)[1];
764 mpw->data.dseg[4] = &(*dseg)[2];
768 * Close a MPW session.
771 * Pointer to TX queue structure.
773 * Pointer to MPW session structure.
776 mlx5_mpw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
778 unsigned int num = mpw->pkts_n;
781 * Store size in multiple of 16 bytes. Control and Ethernet segments
784 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s | (2 + num));
785 mpw->state = MLX5_MPW_STATE_CLOSED;
790 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
791 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
795 * DPDK callback for TX with MPW support.
798 * Generic pointer to TX queue structure.
800 * Packets to transmit.
802 * Number of packets in array.
805 * Number of packets successfully transmitted (<= pkts_n).
808 mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
810 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
811 uint16_t elts_head = txq->elts_head;
812 const uint16_t elts_n = 1 << txq->elts_n;
813 const uint16_t elts_m = elts_n - 1;
819 struct mlx5_mpw mpw = {
820 .state = MLX5_MPW_STATE_CLOSED,
823 if (unlikely(!pkts_n))
825 /* Prefetch first packet cacheline. */
826 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
827 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
828 /* Start processing. */
829 mlx5_tx_complete(txq);
830 max_elts = (elts_n - (elts_head - txq->elts_tail));
831 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
832 if (unlikely(!max_wqe))
835 struct rte_mbuf *buf = *(pkts++);
837 unsigned int segs_n = buf->nb_segs;
841 * Make sure there is enough room to store this packet and
842 * that one ring entry remains unused.
845 if (max_elts < segs_n)
847 /* Do not bother with large packets MPW cannot handle. */
848 if (segs_n > MLX5_MPW_DSEG_MAX) {
849 txq->stats.oerrors++;
854 cs_flags = txq_ol_cksum_to_cs(txq, buf);
855 /* Retrieve packet information. */
856 length = PKT_LEN(buf);
858 /* Start new session if packet differs. */
859 if ((mpw.state == MLX5_MPW_STATE_OPENED) &&
860 ((mpw.len != length) ||
862 (mpw.wqe->eseg.cs_flags != cs_flags)))
863 mlx5_mpw_close(txq, &mpw);
864 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
866 * Multi-Packet WQE consumes at most two WQE.
867 * mlx5_mpw_new() expects to be able to use such
870 if (unlikely(max_wqe < 2))
873 mlx5_mpw_new(txq, &mpw, length);
874 mpw.wqe->eseg.cs_flags = cs_flags;
876 /* Multi-segment packets must be alone in their MPW. */
877 assert((segs_n == 1) || (mpw.pkts_n == 0));
878 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
882 volatile struct mlx5_wqe_data_seg *dseg;
886 (*txq->elts)[elts_head++ & elts_m] = buf;
887 dseg = mpw.data.dseg[mpw.pkts_n];
888 addr = rte_pktmbuf_mtod(buf, uintptr_t);
889 *dseg = (struct mlx5_wqe_data_seg){
890 .byte_count = rte_cpu_to_be_32(DATA_LEN(buf)),
891 .lkey = mlx5_tx_mb2mr(txq, buf),
892 .addr = rte_cpu_to_be_64(addr),
894 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
895 length += DATA_LEN(buf);
901 assert(length == mpw.len);
902 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
903 mlx5_mpw_close(txq, &mpw);
904 #ifdef MLX5_PMD_SOFT_COUNTERS
905 /* Increment sent bytes counter. */
906 txq->stats.obytes += length;
910 /* Take a shortcut if nothing must be sent. */
911 if (unlikely(i == 0))
913 /* Check whether completion threshold has been reached. */
914 /* "j" includes both packets and segments. */
915 comp = txq->elts_comp + j;
916 if (comp >= MLX5_TX_COMP_THRESH) {
917 volatile struct mlx5_wqe *wqe = mpw.wqe;
919 /* Request completion on last WQE. */
920 wqe->ctrl[2] = rte_cpu_to_be_32(8);
921 /* Save elts_head in unused "immediate" field of WQE. */
922 wqe->ctrl[3] = elts_head;
925 txq->elts_comp = comp;
927 #ifdef MLX5_PMD_SOFT_COUNTERS
928 /* Increment sent packets counter. */
929 txq->stats.opackets += i;
931 /* Ring QP doorbell. */
932 if (mpw.state == MLX5_MPW_STATE_OPENED)
933 mlx5_mpw_close(txq, &mpw);
934 mlx5_tx_dbrec(txq, mpw.wqe);
935 txq->elts_head = elts_head;
940 * Open a MPW inline session.
943 * Pointer to TX queue structure.
945 * Pointer to MPW session structure.
950 mlx5_mpw_inline_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw,
953 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
954 struct mlx5_wqe_inl_small *inl;
956 mpw->state = MLX5_MPW_INL_STATE_OPENED;
960 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
961 mpw->wqe->ctrl[0] = rte_cpu_to_be_32((MLX5_OPC_MOD_MPW << 24) |
964 mpw->wqe->ctrl[2] = 0;
965 mpw->wqe->ctrl[3] = 0;
966 mpw->wqe->eseg.mss = rte_cpu_to_be_16(length);
967 mpw->wqe->eseg.inline_hdr_sz = 0;
968 mpw->wqe->eseg.cs_flags = 0;
969 mpw->wqe->eseg.rsvd0 = 0;
970 mpw->wqe->eseg.rsvd1 = 0;
971 mpw->wqe->eseg.rsvd2 = 0;
972 inl = (struct mlx5_wqe_inl_small *)
973 (((uintptr_t)mpw->wqe) + 2 * MLX5_WQE_DWORD_SIZE);
974 mpw->data.raw = (uint8_t *)&inl->raw;
978 * Close a MPW inline session.
981 * Pointer to TX queue structure.
983 * Pointer to MPW session structure.
986 mlx5_mpw_inline_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
989 struct mlx5_wqe_inl_small *inl = (struct mlx5_wqe_inl_small *)
990 (((uintptr_t)mpw->wqe) + (2 * MLX5_WQE_DWORD_SIZE));
992 size = MLX5_WQE_SIZE - MLX5_MWQE64_INL_DATA + mpw->total_len;
994 * Store size in multiple of 16 bytes. Control and Ethernet segments
997 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
999 mpw->state = MLX5_MPW_STATE_CLOSED;
1000 inl->byte_cnt = rte_cpu_to_be_32(mpw->total_len | MLX5_INLINE_SEG);
1001 txq->wqe_ci += (size + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1005 * DPDK callback for TX with MPW inline support.
1008 * Generic pointer to TX queue structure.
1010 * Packets to transmit.
1012 * Number of packets in array.
1015 * Number of packets successfully transmitted (<= pkts_n).
1018 mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
1021 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1022 uint16_t elts_head = txq->elts_head;
1023 const uint16_t elts_n = 1 << txq->elts_n;
1024 const uint16_t elts_m = elts_n - 1;
1030 unsigned int inline_room = txq->max_inline * RTE_CACHE_LINE_SIZE;
1031 struct mlx5_mpw mpw = {
1032 .state = MLX5_MPW_STATE_CLOSED,
1035 * Compute the maximum number of WQE which can be consumed by inline
1038 * - 1 control segment,
1039 * - 1 Ethernet segment,
1040 * - N Dseg from the inline request.
1042 const unsigned int wqe_inl_n =
1043 ((2 * MLX5_WQE_DWORD_SIZE +
1044 txq->max_inline * RTE_CACHE_LINE_SIZE) +
1045 RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE;
1047 if (unlikely(!pkts_n))
1049 /* Prefetch first packet cacheline. */
1050 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci));
1051 rte_prefetch0(tx_mlx5_wqe(txq, txq->wqe_ci + 1));
1052 /* Start processing. */
1053 mlx5_tx_complete(txq);
1054 max_elts = (elts_n - (elts_head - txq->elts_tail));
1056 struct rte_mbuf *buf = *(pkts++);
1059 unsigned int segs_n = buf->nb_segs;
1063 * Make sure there is enough room to store this packet and
1064 * that one ring entry remains unused.
1067 if (max_elts < segs_n)
1069 /* Do not bother with large packets MPW cannot handle. */
1070 if (segs_n > MLX5_MPW_DSEG_MAX) {
1071 txq->stats.oerrors++;
1077 * Compute max_wqe in case less WQE were consumed in previous
1080 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1081 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1082 /* Retrieve packet information. */
1083 length = PKT_LEN(buf);
1084 /* Start new session if packet differs. */
1085 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1086 if ((mpw.len != length) ||
1088 (mpw.wqe->eseg.cs_flags != cs_flags))
1089 mlx5_mpw_close(txq, &mpw);
1090 } else if (mpw.state == MLX5_MPW_INL_STATE_OPENED) {
1091 if ((mpw.len != length) ||
1093 (length > inline_room) ||
1094 (mpw.wqe->eseg.cs_flags != cs_flags)) {
1095 mlx5_mpw_inline_close(txq, &mpw);
1097 txq->max_inline * RTE_CACHE_LINE_SIZE;
1100 if (mpw.state == MLX5_MPW_STATE_CLOSED) {
1101 if ((segs_n != 1) ||
1102 (length > inline_room)) {
1104 * Multi-Packet WQE consumes at most two WQE.
1105 * mlx5_mpw_new() expects to be able to use
1108 if (unlikely(max_wqe < 2))
1111 mlx5_mpw_new(txq, &mpw, length);
1112 mpw.wqe->eseg.cs_flags = cs_flags;
1114 if (unlikely(max_wqe < wqe_inl_n))
1116 max_wqe -= wqe_inl_n;
1117 mlx5_mpw_inline_new(txq, &mpw, length);
1118 mpw.wqe->eseg.cs_flags = cs_flags;
1121 /* Multi-segment packets must be alone in their MPW. */
1122 assert((segs_n == 1) || (mpw.pkts_n == 0));
1123 if (mpw.state == MLX5_MPW_STATE_OPENED) {
1124 assert(inline_room ==
1125 txq->max_inline * RTE_CACHE_LINE_SIZE);
1126 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1130 volatile struct mlx5_wqe_data_seg *dseg;
1133 (*txq->elts)[elts_head++ & elts_m] = buf;
1134 dseg = mpw.data.dseg[mpw.pkts_n];
1135 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1136 *dseg = (struct mlx5_wqe_data_seg){
1138 rte_cpu_to_be_32(DATA_LEN(buf)),
1139 .lkey = mlx5_tx_mb2mr(txq, buf),
1140 .addr = rte_cpu_to_be_64(addr),
1142 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1143 length += DATA_LEN(buf);
1149 assert(length == mpw.len);
1150 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX)
1151 mlx5_mpw_close(txq, &mpw);
1155 assert(mpw.state == MLX5_MPW_INL_STATE_OPENED);
1156 assert(length <= inline_room);
1157 assert(length == DATA_LEN(buf));
1158 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1159 (*txq->elts)[elts_head++ & elts_m] = buf;
1160 /* Maximum number of bytes before wrapping. */
1161 max = ((((uintptr_t)(txq->wqes)) +
1164 (uintptr_t)mpw.data.raw);
1166 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1169 mpw.data.raw = (volatile void *)txq->wqes;
1170 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1171 (void *)(addr + max),
1173 mpw.data.raw += length - max;
1175 rte_memcpy((void *)(uintptr_t)mpw.data.raw,
1181 (volatile void *)txq->wqes;
1183 mpw.data.raw += length;
1186 mpw.total_len += length;
1188 if (mpw.pkts_n == MLX5_MPW_DSEG_MAX) {
1189 mlx5_mpw_inline_close(txq, &mpw);
1191 txq->max_inline * RTE_CACHE_LINE_SIZE;
1193 inline_room -= length;
1196 #ifdef MLX5_PMD_SOFT_COUNTERS
1197 /* Increment sent bytes counter. */
1198 txq->stats.obytes += length;
1202 /* Take a shortcut if nothing must be sent. */
1203 if (unlikely(i == 0))
1205 /* Check whether completion threshold has been reached. */
1206 /* "j" includes both packets and segments. */
1207 comp = txq->elts_comp + j;
1208 if (comp >= MLX5_TX_COMP_THRESH) {
1209 volatile struct mlx5_wqe *wqe = mpw.wqe;
1211 /* Request completion on last WQE. */
1212 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1213 /* Save elts_head in unused "immediate" field of WQE. */
1214 wqe->ctrl[3] = elts_head;
1217 txq->elts_comp = comp;
1219 #ifdef MLX5_PMD_SOFT_COUNTERS
1220 /* Increment sent packets counter. */
1221 txq->stats.opackets += i;
1223 /* Ring QP doorbell. */
1224 if (mpw.state == MLX5_MPW_INL_STATE_OPENED)
1225 mlx5_mpw_inline_close(txq, &mpw);
1226 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1227 mlx5_mpw_close(txq, &mpw);
1228 mlx5_tx_dbrec(txq, mpw.wqe);
1229 txq->elts_head = elts_head;
1234 * Open an Enhanced MPW session.
1237 * Pointer to TX queue structure.
1239 * Pointer to MPW session structure.
1244 mlx5_empw_new(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw, int padding)
1246 uint16_t idx = txq->wqe_ci & ((1 << txq->wqe_n) - 1);
1248 mpw->state = MLX5_MPW_ENHANCED_STATE_OPENED;
1250 mpw->total_len = sizeof(struct mlx5_wqe);
1251 mpw->wqe = (volatile struct mlx5_wqe *)tx_mlx5_wqe(txq, idx);
1253 rte_cpu_to_be_32((MLX5_OPC_MOD_ENHANCED_MPSW << 24) |
1254 (txq->wqe_ci << 8) |
1255 MLX5_OPCODE_ENHANCED_MPSW);
1256 mpw->wqe->ctrl[2] = 0;
1257 mpw->wqe->ctrl[3] = 0;
1258 memset((void *)(uintptr_t)&mpw->wqe->eseg, 0, MLX5_WQE_DWORD_SIZE);
1259 if (unlikely(padding)) {
1260 uintptr_t addr = (uintptr_t)(mpw->wqe + 1);
1262 /* Pad the first 2 DWORDs with zero-length inline header. */
1263 *(volatile uint32_t *)addr = rte_cpu_to_be_32(MLX5_INLINE_SEG);
1264 *(volatile uint32_t *)(addr + MLX5_WQE_DWORD_SIZE) =
1265 rte_cpu_to_be_32(MLX5_INLINE_SEG);
1266 mpw->total_len += 2 * MLX5_WQE_DWORD_SIZE;
1267 /* Start from the next WQEBB. */
1268 mpw->data.raw = (volatile void *)(tx_mlx5_wqe(txq, idx + 1));
1270 mpw->data.raw = (volatile void *)(mpw->wqe + 1);
1275 * Close an Enhanced MPW session.
1278 * Pointer to TX queue structure.
1280 * Pointer to MPW session structure.
1283 * Number of consumed WQEs.
1285 static inline uint16_t
1286 mlx5_empw_close(struct mlx5_txq_data *txq, struct mlx5_mpw *mpw)
1290 /* Store size in multiple of 16 bytes. Control and Ethernet segments
1293 mpw->wqe->ctrl[1] = rte_cpu_to_be_32(txq->qp_num_8s |
1294 MLX5_WQE_DS(mpw->total_len));
1295 mpw->state = MLX5_MPW_STATE_CLOSED;
1296 ret = (mpw->total_len + (MLX5_WQE_SIZE - 1)) / MLX5_WQE_SIZE;
1302 * DPDK callback for TX with Enhanced MPW support.
1305 * Generic pointer to TX queue structure.
1307 * Packets to transmit.
1309 * Number of packets in array.
1312 * Number of packets successfully transmitted (<= pkts_n).
1315 mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1317 struct mlx5_txq_data *txq = (struct mlx5_txq_data *)dpdk_txq;
1318 uint16_t elts_head = txq->elts_head;
1319 const uint16_t elts_n = 1 << txq->elts_n;
1320 const uint16_t elts_m = elts_n - 1;
1325 unsigned int max_inline = txq->max_inline * RTE_CACHE_LINE_SIZE;
1326 unsigned int mpw_room = 0;
1327 unsigned int inl_pad = 0;
1329 struct mlx5_mpw mpw = {
1330 .state = MLX5_MPW_STATE_CLOSED,
1333 if (unlikely(!pkts_n))
1335 /* Start processing. */
1336 mlx5_tx_complete(txq);
1337 max_elts = (elts_n - (elts_head - txq->elts_tail));
1338 /* A CQE slot must always be available. */
1339 assert((1u << txq->cqe_n) - (txq->cq_pi - txq->cq_ci));
1340 max_wqe = (1u << txq->wqe_n) - (txq->wqe_ci - txq->wqe_pi);
1341 if (unlikely(!max_wqe))
1344 struct rte_mbuf *buf = *(pkts++);
1347 unsigned int do_inline = 0; /* Whether inline is possible. */
1349 unsigned int segs_n = buf->nb_segs;
1353 * Make sure there is enough room to store this packet and
1354 * that one ring entry remains unused.
1357 if (max_elts - j < segs_n)
1359 /* Do not bother with large packets MPW cannot handle. */
1360 if (segs_n > MLX5_MPW_DSEG_MAX) {
1361 txq->stats.oerrors++;
1364 cs_flags = txq_ol_cksum_to_cs(txq, buf);
1365 /* Retrieve packet information. */
1366 length = PKT_LEN(buf);
1367 /* Start new session if:
1368 * - multi-segment packet
1369 * - no space left even for a dseg
1370 * - next packet can be inlined with a new WQE
1372 * It can't be MLX5_MPW_STATE_OPENED as always have a single
1375 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED) {
1376 if ((segs_n != 1) ||
1377 (inl_pad + sizeof(struct mlx5_wqe_data_seg) >
1379 (length <= txq->inline_max_packet_sz &&
1380 inl_pad + sizeof(inl_hdr) + length >
1382 (mpw.wqe->eseg.cs_flags != cs_flags))
1383 max_wqe -= mlx5_empw_close(txq, &mpw);
1385 if (unlikely(mpw.state == MLX5_MPW_STATE_CLOSED)) {
1386 if (unlikely(segs_n != 1)) {
1387 /* Fall back to legacy MPW.
1388 * A MPW session consumes 2 WQEs at most to
1389 * include MLX5_MPW_DSEG_MAX pointers.
1391 if (unlikely(max_wqe < 2))
1393 mlx5_mpw_new(txq, &mpw, length);
1395 /* In Enhanced MPW, inline as much as the budget
1396 * is allowed. The remaining space is to be
1397 * filled with dsegs. If the title WQEBB isn't
1398 * padded, it will have 2 dsegs there.
1400 mpw_room = RTE_MIN(MLX5_WQE_SIZE_MAX,
1401 (max_inline ? max_inline :
1402 pkts_n * MLX5_WQE_DWORD_SIZE) +
1404 if (unlikely(max_wqe * MLX5_WQE_SIZE <
1407 /* Don't pad the title WQEBB to not waste WQ. */
1408 mlx5_empw_new(txq, &mpw, 0);
1409 mpw_room -= mpw.total_len;
1412 length <= txq->inline_max_packet_sz &&
1413 sizeof(inl_hdr) + length <= mpw_room &&
1416 mpw.wqe->eseg.cs_flags = cs_flags;
1418 /* Evaluate whether the next packet can be inlined.
1419 * Inlininig is possible when:
1420 * - length is less than configured value
1421 * - length fits for remaining space
1422 * - not required to fill the title WQEBB with dsegs
1425 length <= txq->inline_max_packet_sz &&
1426 inl_pad + sizeof(inl_hdr) + length <=
1428 (!txq->mpw_hdr_dseg ||
1429 mpw.total_len >= MLX5_WQE_SIZE);
1431 /* Multi-segment packets must be alone in their MPW. */
1432 assert((segs_n == 1) || (mpw.pkts_n == 0));
1433 if (unlikely(mpw.state == MLX5_MPW_STATE_OPENED)) {
1434 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1438 volatile struct mlx5_wqe_data_seg *dseg;
1441 (*txq->elts)[elts_head++ & elts_m] = buf;
1442 dseg = mpw.data.dseg[mpw.pkts_n];
1443 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1444 *dseg = (struct mlx5_wqe_data_seg){
1445 .byte_count = rte_cpu_to_be_32(
1447 .lkey = mlx5_tx_mb2mr(txq, buf),
1448 .addr = rte_cpu_to_be_64(addr),
1450 #if defined(MLX5_PMD_SOFT_COUNTERS) || !defined(NDEBUG)
1451 length += DATA_LEN(buf);
1457 /* A multi-segmented packet takes one MPW session.
1458 * TODO: Pack more multi-segmented packets if possible.
1460 mlx5_mpw_close(txq, &mpw);
1465 } else if (do_inline) {
1466 /* Inline packet into WQE. */
1469 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1470 assert(length == DATA_LEN(buf));
1471 inl_hdr = rte_cpu_to_be_32(length | MLX5_INLINE_SEG);
1472 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1473 mpw.data.raw = (volatile void *)
1474 ((uintptr_t)mpw.data.raw + inl_pad);
1475 max = tx_mlx5_wq_tailroom(txq,
1476 (void *)(uintptr_t)mpw.data.raw);
1477 /* Copy inline header. */
1478 mpw.data.raw = (volatile void *)
1480 (void *)(uintptr_t)mpw.data.raw,
1483 (void *)(uintptr_t)txq->wqes,
1485 max = tx_mlx5_wq_tailroom(txq,
1486 (void *)(uintptr_t)mpw.data.raw);
1487 /* Copy packet data. */
1488 mpw.data.raw = (volatile void *)
1490 (void *)(uintptr_t)mpw.data.raw,
1493 (void *)(uintptr_t)txq->wqes,
1496 mpw.total_len += (inl_pad + sizeof(inl_hdr) + length);
1497 /* No need to get completion as the entire packet is
1498 * copied to WQ. Free the buf right away.
1500 rte_pktmbuf_free_seg(buf);
1501 mpw_room -= (inl_pad + sizeof(inl_hdr) + length);
1502 /* Add pad in the next packet if any. */
1503 inl_pad = (((uintptr_t)mpw.data.raw +
1504 (MLX5_WQE_DWORD_SIZE - 1)) &
1505 ~(MLX5_WQE_DWORD_SIZE - 1)) -
1506 (uintptr_t)mpw.data.raw;
1508 /* No inline. Load a dseg of packet pointer. */
1509 volatile rte_v128u32_t *dseg;
1511 assert(mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED);
1512 assert((inl_pad + sizeof(*dseg)) <= mpw_room);
1513 assert(length == DATA_LEN(buf));
1514 if (!tx_mlx5_wq_tailroom(txq,
1515 (void *)((uintptr_t)mpw.data.raw
1517 dseg = (volatile void *)txq->wqes;
1519 dseg = (volatile void *)
1520 ((uintptr_t)mpw.data.raw +
1522 (*txq->elts)[elts_head++ & elts_m] = buf;
1523 addr = rte_pktmbuf_mtod(buf, uintptr_t);
1524 for (n = 0; n * RTE_CACHE_LINE_SIZE < length; n++)
1525 rte_prefetch2((void *)(addr +
1526 n * RTE_CACHE_LINE_SIZE));
1527 addr = rte_cpu_to_be_64(addr);
1528 *dseg = (rte_v128u32_t) {
1529 rte_cpu_to_be_32(length),
1530 mlx5_tx_mb2mr(txq, buf),
1534 mpw.data.raw = (volatile void *)(dseg + 1);
1535 mpw.total_len += (inl_pad + sizeof(*dseg));
1538 mpw_room -= (inl_pad + sizeof(*dseg));
1541 #ifdef MLX5_PMD_SOFT_COUNTERS
1542 /* Increment sent bytes counter. */
1543 txq->stats.obytes += length;
1546 } while (i < pkts_n);
1547 /* Take a shortcut if nothing must be sent. */
1548 if (unlikely(i == 0))
1550 /* Check whether completion threshold has been reached. */
1551 if (txq->elts_comp + j >= MLX5_TX_COMP_THRESH ||
1552 (uint16_t)(txq->wqe_ci - txq->mpw_comp) >=
1553 (1 << txq->wqe_n) / MLX5_TX_COMP_THRESH_INLINE_DIV) {
1554 volatile struct mlx5_wqe *wqe = mpw.wqe;
1556 /* Request completion on last WQE. */
1557 wqe->ctrl[2] = rte_cpu_to_be_32(8);
1558 /* Save elts_head in unused "immediate" field of WQE. */
1559 wqe->ctrl[3] = elts_head;
1561 txq->mpw_comp = txq->wqe_ci;
1564 txq->elts_comp += j;
1566 #ifdef MLX5_PMD_SOFT_COUNTERS
1567 /* Increment sent packets counter. */
1568 txq->stats.opackets += i;
1570 if (mpw.state == MLX5_MPW_ENHANCED_STATE_OPENED)
1571 mlx5_empw_close(txq, &mpw);
1572 else if (mpw.state == MLX5_MPW_STATE_OPENED)
1573 mlx5_mpw_close(txq, &mpw);
1574 /* Ring QP doorbell. */
1575 mlx5_tx_dbrec(txq, mpw.wqe);
1576 txq->elts_head = elts_head;
1581 * Translate RX completion flags to packet type.
1586 * @note: fix mlx5_dev_supported_ptypes_get() if any change here.
1589 * Packet type for struct rte_mbuf.
1591 static inline uint32_t
1592 rxq_cq_to_pkt_type(volatile struct mlx5_cqe *cqe)
1595 uint8_t pinfo = cqe->pkt_info;
1596 uint16_t ptype = cqe->hdr_type_etc;
1599 * The index to the array should have:
1600 * bit[1:0] = l3_hdr_type
1601 * bit[4:2] = l4_hdr_type
1604 * bit[7] = outer_l3_type
1606 idx = ((pinfo & 0x3) << 6) | ((ptype & 0xfc00) >> 10);
1607 return mlx5_ptype_table[idx];
1611 * Get size of the next packet for a given CQE. For compressed CQEs, the
1612 * consumer index is updated only once all packets of the current one have
1616 * Pointer to RX queue.
1619 * @param[out] rss_hash
1620 * Packet RSS Hash result.
1623 * Packet size in bytes (0 if there is none), -1 in case of completion
1627 mlx5_rx_poll_len(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe,
1628 uint16_t cqe_cnt, uint32_t *rss_hash)
1630 struct rxq_zip *zip = &rxq->zip;
1631 uint16_t cqe_n = cqe_cnt + 1;
1635 /* Process compressed data in the CQE and mini arrays. */
1637 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1638 (volatile struct mlx5_mini_cqe8 (*)[8])
1639 (uintptr_t)(&(*rxq->cqes)[zip->ca & cqe_cnt].pkt_info);
1641 len = rte_be_to_cpu_32((*mc)[zip->ai & 7].byte_cnt);
1642 *rss_hash = rte_be_to_cpu_32((*mc)[zip->ai & 7].rx_hash_result);
1643 if ((++zip->ai & 7) == 0) {
1644 /* Invalidate consumed CQEs */
1647 while (idx != end) {
1648 (*rxq->cqes)[idx & cqe_cnt].op_own =
1649 MLX5_CQE_INVALIDATE;
1653 * Increment consumer index to skip the number of
1654 * CQEs consumed. Hardware leaves holes in the CQ
1655 * ring for software use.
1660 if (unlikely(rxq->zip.ai == rxq->zip.cqe_cnt)) {
1661 /* Invalidate the rest */
1665 while (idx != end) {
1666 (*rxq->cqes)[idx & cqe_cnt].op_own =
1667 MLX5_CQE_INVALIDATE;
1670 rxq->cq_ci = zip->cq_ci;
1673 /* No compressed data, get next CQE and verify if it is compressed. */
1678 ret = check_cqe(cqe, cqe_n, rxq->cq_ci);
1679 if (unlikely(ret == 1))
1682 op_own = cqe->op_own;
1683 if (MLX5_CQE_FORMAT(op_own) == MLX5_COMPRESSED) {
1684 volatile struct mlx5_mini_cqe8 (*mc)[8] =
1685 (volatile struct mlx5_mini_cqe8 (*)[8])
1686 (uintptr_t)(&(*rxq->cqes)[rxq->cq_ci &
1689 /* Fix endianness. */
1690 zip->cqe_cnt = rte_be_to_cpu_32(cqe->byte_cnt);
1692 * Current mini array position is the one returned by
1695 * If completion comprises several mini arrays, as a
1696 * special case the second one is located 7 CQEs after
1697 * the initial CQE instead of 8 for subsequent ones.
1699 zip->ca = rxq->cq_ci;
1700 zip->na = zip->ca + 7;
1701 /* Compute the next non compressed CQE. */
1703 zip->cq_ci = rxq->cq_ci + zip->cqe_cnt;
1704 /* Get packet size to return. */
1705 len = rte_be_to_cpu_32((*mc)[0].byte_cnt);
1706 *rss_hash = rte_be_to_cpu_32((*mc)[0].rx_hash_result);
1708 /* Prefetch all the entries to be invalidated */
1711 while (idx != end) {
1712 rte_prefetch0(&(*rxq->cqes)[(idx) & cqe_cnt]);
1716 len = rte_be_to_cpu_32(cqe->byte_cnt);
1717 *rss_hash = rte_be_to_cpu_32(cqe->rx_hash_res);
1719 /* Error while receiving packet. */
1720 if (unlikely(MLX5_CQE_OPCODE(op_own) == MLX5_CQE_RESP_ERR))
1727 * Translate RX completion flags to offload flags.
1730 * Pointer to RX queue structure.
1735 * Offload flags (ol_flags) for struct rte_mbuf.
1737 static inline uint32_t
1738 rxq_cq_to_ol_flags(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cqe)
1740 uint32_t ol_flags = 0;
1741 uint16_t flags = rte_be_to_cpu_16(cqe->hdr_type_etc);
1745 MLX5_CQE_RX_L3_HDR_VALID,
1746 PKT_RX_IP_CKSUM_GOOD) |
1748 MLX5_CQE_RX_L4_HDR_VALID,
1749 PKT_RX_L4_CKSUM_GOOD);
1750 if ((cqe->pkt_info & MLX5_CQE_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
1753 MLX5_CQE_RX_L3_HDR_VALID,
1754 PKT_RX_IP_CKSUM_GOOD) |
1756 MLX5_CQE_RX_L4_HDR_VALID,
1757 PKT_RX_L4_CKSUM_GOOD);
1762 * DPDK callback for RX.
1765 * Generic pointer to RX queue structure.
1767 * Array to store received packets.
1769 * Maximum number of packets in array.
1772 * Number of packets successfully received (<= pkts_n).
1775 mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1777 struct mlx5_rxq_data *rxq = dpdk_rxq;
1778 const unsigned int wqe_cnt = (1 << rxq->elts_n) - 1;
1779 const unsigned int cqe_cnt = (1 << rxq->cqe_n) - 1;
1780 const unsigned int sges_n = rxq->sges_n;
1781 struct rte_mbuf *pkt = NULL;
1782 struct rte_mbuf *seg = NULL;
1783 volatile struct mlx5_cqe *cqe =
1784 &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1786 unsigned int rq_ci = rxq->rq_ci << sges_n;
1787 int len = 0; /* keep its value across iterations. */
1790 unsigned int idx = rq_ci & wqe_cnt;
1791 volatile struct mlx5_wqe_data_seg *wqe = &(*rxq->wqes)[idx];
1792 struct rte_mbuf *rep = (*rxq->elts)[idx];
1793 uint32_t rss_hash_res = 0;
1801 rep = rte_mbuf_raw_alloc(rxq->mp);
1802 if (unlikely(rep == NULL)) {
1803 ++rxq->stats.rx_nombuf;
1806 * no buffers before we even started,
1807 * bail out silently.
1811 while (pkt != seg) {
1812 assert(pkt != (*rxq->elts)[idx]);
1816 rte_mbuf_raw_free(pkt);
1822 cqe = &(*rxq->cqes)[rxq->cq_ci & cqe_cnt];
1823 len = mlx5_rx_poll_len(rxq, cqe, cqe_cnt,
1826 rte_mbuf_raw_free(rep);
1829 if (unlikely(len == -1)) {
1830 /* RX error, packet is likely too large. */
1831 rte_mbuf_raw_free(rep);
1832 ++rxq->stats.idropped;
1836 assert(len >= (rxq->crc_present << 2));
1837 /* Update packet information. */
1838 pkt->packet_type = rxq_cq_to_pkt_type(cqe);
1840 if (rss_hash_res && rxq->rss_hash) {
1841 pkt->hash.rss = rss_hash_res;
1842 pkt->ol_flags = PKT_RX_RSS_HASH;
1845 MLX5_FLOW_MARK_IS_VALID(cqe->sop_drop_qpn)) {
1846 pkt->ol_flags |= PKT_RX_FDIR;
1847 if (cqe->sop_drop_qpn !=
1848 rte_cpu_to_be_32(MLX5_FLOW_MARK_DEFAULT)) {
1849 uint32_t mark = cqe->sop_drop_qpn;
1851 pkt->ol_flags |= PKT_RX_FDIR_ID;
1853 mlx5_flow_mark_get(mark);
1856 if (rxq->csum | rxq->csum_l2tun)
1857 pkt->ol_flags |= rxq_cq_to_ol_flags(rxq, cqe);
1858 if (rxq->vlan_strip &&
1859 (cqe->hdr_type_etc &
1860 rte_cpu_to_be_16(MLX5_CQE_VLAN_STRIPPED))) {
1861 pkt->ol_flags |= PKT_RX_VLAN |
1862 PKT_RX_VLAN_STRIPPED;
1864 rte_be_to_cpu_16(cqe->vlan_info);
1866 if (rxq->hw_timestamp) {
1868 rte_be_to_cpu_64(cqe->timestamp);
1869 pkt->ol_flags |= PKT_RX_TIMESTAMP;
1871 if (rxq->crc_present)
1872 len -= ETHER_CRC_LEN;
1875 DATA_LEN(rep) = DATA_LEN(seg);
1876 PKT_LEN(rep) = PKT_LEN(seg);
1877 SET_DATA_OFF(rep, DATA_OFF(seg));
1878 PORT(rep) = PORT(seg);
1879 (*rxq->elts)[idx] = rep;
1881 * Fill NIC descriptor with the new buffer. The lkey and size
1882 * of the buffers are already known, only the buffer address
1885 wqe->addr = rte_cpu_to_be_64(rte_pktmbuf_mtod(rep, uintptr_t));
1886 if (len > DATA_LEN(seg)) {
1887 len -= DATA_LEN(seg);
1892 DATA_LEN(seg) = len;
1893 #ifdef MLX5_PMD_SOFT_COUNTERS
1894 /* Increment bytes counter. */
1895 rxq->stats.ibytes += PKT_LEN(pkt);
1897 /* Return packet. */
1903 /* Align consumer index to the next stride. */
1908 if (unlikely((i == 0) && ((rq_ci >> sges_n) == rxq->rq_ci)))
1910 /* Update the consumer index. */
1911 rxq->rq_ci = rq_ci >> sges_n;
1913 *rxq->cq_db = rte_cpu_to_be_32(rxq->cq_ci);
1915 *rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
1916 #ifdef MLX5_PMD_SOFT_COUNTERS
1917 /* Increment packets counter. */
1918 rxq->stats.ipackets += i;
1924 * Dummy DPDK callback for TX.
1926 * This function is used to temporarily replace the real callback during
1927 * unsafe control operations on the queue, or in case of error.
1930 * Generic pointer to TX queue structure.
1932 * Packets to transmit.
1934 * Number of packets in array.
1937 * Number of packets successfully transmitted (<= pkts_n).
1940 removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1949 * Dummy DPDK callback for RX.
1951 * This function is used to temporarily replace the real callback during
1952 * unsafe control operations on the queue, or in case of error.
1955 * Generic pointer to RX queue structure.
1957 * Array to store received packets.
1959 * Maximum number of packets in array.
1962 * Number of packets successfully received (<= pkts_n).
1965 removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
1974 * Vectorized Rx/Tx routines are not compiled in when required vector
1975 * instructions are not supported on a target architecture. The following null
1976 * stubs are needed for linkage when those are not included outside of this file
1977 * (e.g. mlx5_rxtx_vec_sse.c for x86).
1980 uint16_t __attribute__((weak))
1981 mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1989 uint16_t __attribute__((weak))
1990 mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
1998 uint16_t __attribute__((weak))
1999 mlx5_rx_burst_vec(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
2007 int __attribute__((weak))
2008 priv_check_raw_vec_tx_support(struct priv *priv)
2014 int __attribute__((weak))
2015 priv_check_vec_tx_support(struct priv *priv)
2021 int __attribute__((weak))
2022 rxq_check_vec_support(struct mlx5_rxq_data *rxq)
2028 int __attribute__((weak))
2029 priv_check_vec_rx_support(struct priv *priv)