1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
32 #include <rte_malloc.h>
34 #include "mlx5_utils.h"
37 #include "mlx5_autoconf.h"
38 #include "mlx5_defs.h"
40 #include "mlx5_glue.h"
42 /* Support tunnel matching. */
43 #define MLX5_FLOW_TUNNEL 8
45 struct mlx5_rxq_stats {
46 #ifdef MLX5_PMD_SOFT_COUNTERS
47 uint64_t ipackets; /**< Total of successfully received packets. */
48 uint64_t ibytes; /**< Total of successfully received bytes. */
50 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
51 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
54 struct mlx5_txq_stats {
55 #ifdef MLX5_PMD_SOFT_COUNTERS
56 uint64_t opackets; /**< Total of successfully sent packets. */
57 uint64_t obytes; /**< Total of successfully sent bytes. */
59 uint64_t oerrors; /**< Total number of failed transmitted packets. */
64 /* Compressed CQE context. */
66 uint16_t ai; /* Array index. */
67 uint16_t ca; /* Current array index. */
68 uint16_t na; /* Next array index. */
69 uint16_t cq_ci; /* The next CQE. */
70 uint32_t cqe_cnt; /* Number of CQEs. */
73 /* Multi-Packet RQ buffer header. */
74 struct mlx5_mprq_buf {
75 struct rte_mempool *mp;
76 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
77 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
78 struct rte_mbuf_ext_shared_info shinfos[];
80 * Shared information per stride.
81 * More memory will be allocated for the first stride head-room and for
84 } __rte_cache_aligned;
86 /* Get pointer to the first stride. */
87 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
88 sizeof(struct mlx5_mprq_buf) + \
90 sizeof(struct rte_mbuf_ext_shared_info) + \
91 RTE_PKTMBUF_HEADROOM))
93 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
94 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
96 enum mlx5_rxq_err_state {
97 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
98 MLX5_RXQ_ERR_STATE_NEED_RESET,
99 MLX5_RXQ_ERR_STATE_NEED_READY,
102 /* RX queue descriptor. */
103 struct mlx5_rxq_data {
104 unsigned int csum:1; /* Enable checksum offloading. */
105 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
106 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
107 unsigned int crc_present:1; /* CRC must be subtracted. */
108 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
109 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
110 unsigned int elts_n:4; /* Log 2 of Mbufs. */
111 unsigned int rss_hash:1; /* RSS hash result is enabled. */
112 unsigned int mark:1; /* Marked flow available on the queue. */
113 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
114 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
115 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
116 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
117 unsigned int strd_headroom_en:1; /* Enable mbuf headroom in MPRQ. */
118 unsigned int lro:1; /* Enable LRO. */
119 unsigned int :1; /* Remaining bits. */
120 volatile uint32_t *rq_db;
121 volatile uint32_t *cq_db;
124 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
127 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
129 struct rxq_zip zip; /* Compressed context. */
130 uint16_t decompressed;
131 /* Number of ready mbufs decompressed from the CQ. */
133 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
134 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
136 volatile struct mlx5_cqe(*cqes)[];
139 struct rte_mbuf *(*elts)[];
140 struct mlx5_mprq_buf *(*mprq_bufs)[];
142 struct rte_mempool *mp;
143 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
144 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
145 uint16_t idx; /* Queue index. */
146 struct mlx5_rxq_stats stats;
147 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
148 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
149 void *cq_uar; /* CQ user access region. */
150 uint32_t cqn; /* CQ number. */
151 uint8_t cq_arm_sn; /* CQ arm seq number. */
153 rte_spinlock_t *uar_lock_cq;
154 /* CQ (UAR) access lock required for 32bit implementations */
156 uint32_t tunnel; /* Tunnel information. */
157 } __rte_cache_aligned;
159 enum mlx5_rxq_obj_type {
160 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
161 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
162 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
163 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
167 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
168 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
171 /* Verbs/DevX Rx queue elements. */
172 struct mlx5_rxq_obj {
173 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
174 rte_atomic32_t refcnt; /* Reference counter. */
175 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
176 struct ibv_cq *cq; /* Completion Queue. */
177 enum mlx5_rxq_obj_type type;
180 struct ibv_wq *wq; /* Work Queue. */
181 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
183 struct ibv_comp_channel *channel;
186 /* RX queue control descriptor. */
187 struct mlx5_rxq_ctrl {
188 struct mlx5_rxq_data rxq; /* Data path structure. */
189 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
190 rte_atomic32_t refcnt; /* Reference counter. */
191 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
192 struct mlx5_priv *priv; /* Back pointer to private data. */
193 enum mlx5_rxq_type type; /* Rxq type. */
194 unsigned int socket; /* CPU socket ID for allocations. */
195 unsigned int irq:1; /* Whether IRQ is enabled. */
196 unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */
197 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
198 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
199 uint32_t wqn; /* WQ number. */
200 uint16_t dump_file_n; /* Number of dump files. */
201 uint32_t dbr_umem_id; /* Storing door-bell information, */
202 uint64_t dbr_offset; /* needed when freeing door-bell. */
203 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
204 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
207 enum mlx5_ind_tbl_type {
208 MLX5_IND_TBL_TYPE_IBV,
209 MLX5_IND_TBL_TYPE_DEVX,
212 /* Indirection table. */
213 struct mlx5_ind_table_obj {
214 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
215 rte_atomic32_t refcnt; /* Reference counter. */
216 enum mlx5_ind_tbl_type type;
219 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
220 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
222 uint32_t queues_n; /**< Number of queues in the list. */
223 uint16_t queues[]; /**< Queue list. */
228 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
229 rte_atomic32_t refcnt; /* Reference counter. */
230 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
233 struct ibv_qp *qp; /* Verbs queue pair. */
234 struct mlx5_devx_obj *tir; /* DevX TIR object. */
236 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
237 void *action; /* DV QP action pointer. */
239 uint64_t hash_fields; /* Verbs Hash fields. */
240 uint32_t rss_key_len; /* Hash key length in bytes. */
241 uint8_t rss_key[]; /* Hash key. */
244 /* TX queue send local data. */
246 struct mlx5_txq_local {
247 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
248 struct rte_mbuf *mbuf; /* first mbuf to process. */
249 uint16_t pkts_copy; /* packets copied to elts. */
250 uint16_t pkts_sent; /* packets sent. */
251 uint16_t pkts_loop; /* packets sent on loop entry. */
252 uint16_t elts_free; /* available elts remain. */
253 uint16_t wqe_free; /* available wqe remain. */
254 uint16_t mbuf_off; /* data offset in current mbuf. */
255 uint16_t mbuf_nseg; /* number of remaining mbuf. */
258 /* TX queue descriptor. */
260 struct mlx5_txq_data {
261 uint16_t elts_head; /* Current counter in (*elts)[]. */
262 uint16_t elts_tail; /* Counter of first element awaiting completion. */
263 uint16_t elts_comp; /* elts index since last completion request. */
264 uint16_t elts_s; /* Number of mbuf elements. */
265 uint16_t elts_m; /* Mask for mbuf elements indices. */
266 /* Fields related to elts mbuf storage. */
267 uint16_t wqe_ci; /* Consumer index for work queue. */
268 uint16_t wqe_pi; /* Producer index for work queue. */
269 uint16_t wqe_s; /* Number of WQ elements. */
270 uint16_t wqe_m; /* Mask Number for WQ elements. */
271 uint16_t wqe_comp; /* WQE index since last completion request. */
272 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
273 /* WQ related fields. */
274 uint16_t cq_ci; /* Consumer index for completion queue. */
276 uint16_t cq_pi; /* Counter of issued CQE "always" requests. */
278 uint16_t cqe_s; /* Number of CQ elements. */
279 uint16_t cqe_m; /* Mask for CQ indices. */
280 /* CQ related fields. */
281 uint16_t elts_n:4; /* elts[] length (in log2). */
282 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
283 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
284 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
285 uint16_t tunnel_en:1;
286 /* When set TX offload for tunneled packets are supported. */
287 uint16_t swp_en:1; /* Whether SW parser is enabled. */
288 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
289 uint16_t inlen_send; /* Ordinary send data inline size. */
290 uint16_t inlen_empw; /* eMPW max packet size to inline. */
291 uint16_t inlen_mode; /* Minimal data length to inline. */
292 uint32_t qp_num_8s; /* QP number shifted by 8. */
293 uint64_t offloads; /* Offloads for Tx Queue. */
294 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
295 struct mlx5_wqe *wqes; /* Work queue. */
296 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
297 volatile struct mlx5_cqe *cqes; /* Completion queue. */
298 volatile uint32_t *qp_db; /* Work queue doorbell. */
299 volatile uint32_t *cq_db; /* Completion queue doorbell. */
300 uint16_t port_id; /* Port ID of device. */
301 uint16_t idx; /* Queue index. */
302 struct mlx5_txq_stats stats; /* TX queue counters. */
304 rte_spinlock_t *uar_lock;
305 /* UAR access lock required for 32bit implementations */
307 struct rte_mbuf *elts[0];
308 /* Storage for queued packets, must be the last field. */
309 } __rte_cache_aligned;
311 enum mlx5_txq_obj_type {
312 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
313 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
314 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
318 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
319 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
322 /* Verbs/DevX Tx queue elements. */
323 struct mlx5_txq_obj {
324 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
325 rte_atomic32_t refcnt; /* Reference counter. */
326 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
327 enum mlx5_rxq_obj_type type; /* The txq object type. */
331 struct ibv_cq *cq; /* Completion Queue. */
332 struct ibv_qp *qp; /* Queue Pair. */
334 struct mlx5_devx_obj *sq; /* DevX object for Sx queue. */
338 /* TX queue control descriptor. */
339 struct mlx5_txq_ctrl {
340 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
341 rte_atomic32_t refcnt; /* Reference counter. */
342 unsigned int socket; /* CPU socket ID for allocations. */
343 enum mlx5_txq_type type; /* The txq ctrl type. */
344 unsigned int max_inline_data; /* Max inline data. */
345 unsigned int max_tso_header; /* Max TSO header size. */
346 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
347 struct mlx5_priv *priv; /* Back pointer to private data. */
348 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
349 void *bf_reg; /* BlueFlame register from Verbs. */
350 uint16_t dump_file_n; /* Number of dump files. */
351 struct mlx5_txq_data txq; /* Data path structure. */
352 /* Must be the last field in the structure, contains elts[]. */
355 #define MLX5_TX_BFREG(txq) \
356 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
360 extern uint8_t rss_hash_default_key[];
362 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
363 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
364 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
365 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
366 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
367 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
368 unsigned int socket, const struct rte_eth_rxconf *conf,
369 struct rte_mempool *mp);
370 int mlx5_rx_hairpin_queue_setup
371 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
372 const struct rte_eth_hairpin_conf *hairpin_conf);
373 void mlx5_rx_queue_release(void *dpdk_rxq);
374 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
375 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
376 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
377 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
378 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
379 enum mlx5_rxq_obj_type type);
380 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
381 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
382 uint16_t desc, unsigned int socket,
383 const struct rte_eth_rxconf *conf,
384 struct rte_mempool *mp);
385 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
386 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
387 const struct rte_eth_hairpin_conf *hairpin_conf);
388 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
389 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
390 int mlx5_rxq_verify(struct rte_eth_dev *dev);
391 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
392 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
393 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
394 const uint8_t *rss_key, uint32_t rss_key_len,
395 uint64_t hash_fields,
396 const uint16_t *queues, uint32_t queues_n,
397 int tunnel __rte_unused);
398 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
399 const uint8_t *rss_key, uint32_t rss_key_len,
400 uint64_t hash_fields,
401 const uint16_t *queues, uint32_t queues_n);
402 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
403 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
404 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
405 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
406 uint64_t mlx5_get_rx_port_offloads(void);
407 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
411 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
412 unsigned int socket, const struct rte_eth_txconf *conf);
413 void mlx5_tx_queue_release(void *dpdk_txq);
414 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
415 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx);
416 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
417 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
418 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
419 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
420 uint16_t desc, unsigned int socket,
421 const struct rte_eth_txconf *conf);
422 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
423 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
424 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
425 int mlx5_txq_verify(struct rte_eth_dev *dev);
426 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
427 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
431 extern uint32_t mlx5_ptype_table[];
432 extern uint8_t mlx5_cksum_table[];
433 extern uint8_t mlx5_swp_types_table[];
435 void mlx5_set_ptype_table(void);
436 void mlx5_set_cksum_table(void);
437 void mlx5_set_swp_types_table(void);
438 __rte_noinline int mlx5_tx_error_cqe_handle
439 (struct mlx5_txq_data *restrict txq,
440 volatile struct mlx5_err_cqe *err_cqe);
441 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
442 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
443 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
444 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
445 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
446 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
448 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
450 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
452 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
453 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
454 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
455 void mlx5_dump_debug_information(const char *path, const char *title,
456 const void *buf, unsigned int len);
457 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
458 const struct mlx5_mp_arg_queue_state_modify *sm);
460 /* Vectorized version of mlx5_rxtx.c */
461 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
462 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
463 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
468 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
469 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
470 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
471 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
472 struct rte_mempool *mp);
473 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
475 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
479 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
480 * 64bit architectures.
483 * value to write in CPU endian format.
485 * Address to write to.
487 * Address of the lock to use for that UAR access.
489 static __rte_always_inline void
490 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
491 rte_spinlock_t *lock __rte_unused)
494 *(uint64_t *)addr = val;
495 #else /* !RTE_ARCH_64 */
496 rte_spinlock_lock(lock);
497 *(uint32_t *)addr = val;
499 *((uint32_t *)addr + 1) = val >> 32;
500 rte_spinlock_unlock(lock);
505 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
506 * 64bit architectures while guaranteeing the order of execution with the
507 * code being executed.
510 * value to write in CPU endian format.
512 * Address to write to.
514 * Address of the lock to use for that UAR access.
516 static __rte_always_inline void
517 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
520 __mlx5_uar_write64_relaxed(val, addr, lock);
523 /* Assist macros, used instead of directly calling the functions they wrap. */
525 #define mlx5_uar_write64_relaxed(val, dst, lock) \
526 __mlx5_uar_write64_relaxed(val, dst, NULL)
527 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
529 #define mlx5_uar_write64_relaxed(val, dst, lock) \
530 __mlx5_uar_write64_relaxed(val, dst, lock)
531 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
535 enum mlx5_cqe_status {
536 MLX5_CQE_STATUS_SW_OWN = -1,
537 MLX5_CQE_STATUS_HW_OWN = -2,
538 MLX5_CQE_STATUS_ERR = -3,
542 * Check whether CQE is valid.
547 * Size of completion queue.
554 static __rte_always_inline enum mlx5_cqe_status
555 check_cqe(volatile struct mlx5_cqe *cqe, const uint16_t cqes_n,
558 const uint16_t idx = ci & cqes_n;
559 const uint8_t op_own = cqe->op_own;
560 const uint8_t op_owner = MLX5_CQE_OWNER(op_own);
561 const uint8_t op_code = MLX5_CQE_OPCODE(op_own);
563 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
564 return MLX5_CQE_STATUS_HW_OWN;
566 if (unlikely(op_code == MLX5_CQE_RESP_ERR ||
567 op_code == MLX5_CQE_REQ_ERR))
568 return MLX5_CQE_STATUS_ERR;
569 return MLX5_CQE_STATUS_SW_OWN;
573 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
574 * cloned mbuf is allocated is returned instead.
580 * Memory pool where data is located for given mbuf.
582 static inline struct rte_mempool *
583 mlx5_mb2mp(struct rte_mbuf *buf)
585 if (unlikely(RTE_MBUF_CLONED(buf)))
586 return rte_mbuf_from_indirect(buf)->pool;
591 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
592 * as mempool is pre-configured and static.
595 * Pointer to Rx queue structure.
600 * Searched LKey on success, UINT32_MAX on no match.
602 static __rte_always_inline uint32_t
603 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
605 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
608 /* Linear search on MR cache array. */
609 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
610 MLX5_MR_CACHE_N, addr);
611 if (likely(lkey != UINT32_MAX))
613 /* Take slower bottom-half (Binary Search) on miss. */
614 return mlx5_rx_addr2mr_bh(rxq, addr);
617 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
620 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
623 * Pointer to Tx queue structure.
628 * Searched LKey on success, UINT32_MAX on no match.
630 static __rte_always_inline uint32_t
631 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
633 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
634 uintptr_t addr = (uintptr_t)mb->buf_addr;
637 /* Check generation bit to see if there's any change on existing MRs. */
638 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
639 mlx5_mr_flush_local_cache(mr_ctrl);
640 /* Linear search on MR cache array. */
641 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
642 MLX5_MR_CACHE_N, addr);
643 if (likely(lkey != UINT32_MAX))
645 /* Take slower bottom-half on miss. */
646 return mlx5_tx_mb2mr_bh(txq, mb);
650 * Ring TX queue doorbell and flush the update if requested.
653 * Pointer to TX queue structure.
655 * Pointer to the last WQE posted in the NIC.
657 * Request for write memory barrier after BlueFlame update.
659 static __rte_always_inline void
660 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
663 uint64_t *dst = MLX5_TX_BFREG(txq);
664 volatile uint64_t *src = ((volatile uint64_t *)wqe);
667 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
668 /* Ensure ordering between DB record and BF copy. */
670 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
676 * Ring TX queue doorbell and flush the update by write memory barrier.
679 * Pointer to TX queue structure.
681 * Pointer to the last WQE posted in the NIC.
683 static __rte_always_inline void
684 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
686 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
689 #endif /* RTE_PMD_MLX5_RXTX_H_ */