1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox.
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
30 #include "mlx5_utils.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 struct mlx5_rxq_stats {
37 unsigned int idx; /**< Mapping index. */
38 #ifdef MLX5_PMD_SOFT_COUNTERS
39 uint64_t ipackets; /**< Total of successfully received packets. */
40 uint64_t ibytes; /**< Total of successfully received bytes. */
42 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
43 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
46 struct mlx5_txq_stats {
47 unsigned int idx; /**< Mapping index. */
48 #ifdef MLX5_PMD_SOFT_COUNTERS
49 uint64_t opackets; /**< Total of successfully sent packets. */
50 uint64_t obytes; /**< Total of successfully sent bytes. */
52 uint64_t oerrors; /**< Total number of failed transmitted packets. */
57 /* Memory region queue object. */
59 LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
60 rte_atomic32_t refcnt; /*<< Reference counter. */
61 uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
62 uintptr_t start; /* Start address of MR */
63 uintptr_t end; /* End address of MR */
64 struct ibv_mr *mr; /*<< Memory Region. */
65 struct rte_mempool *mp; /*<< Memory Pool. */
68 /* Compressed CQE context. */
70 uint16_t ai; /* Array index. */
71 uint16_t ca; /* Current array index. */
72 uint16_t na; /* Next array index. */
73 uint16_t cq_ci; /* The next CQE. */
74 uint32_t cqe_cnt; /* Number of CQEs. */
77 /* RX queue descriptor. */
78 struct mlx5_rxq_data {
79 unsigned int csum:1; /* Enable checksum offloading. */
80 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
81 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
82 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
83 unsigned int crc_present:1; /* CRC must be subtracted. */
84 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
85 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
86 unsigned int elts_n:4; /* Log 2 of Mbufs. */
87 unsigned int rss_hash:1; /* RSS hash result is enabled. */
88 unsigned int mark:1; /* Marked flow available on the queue. */
89 unsigned int :15; /* Remaining bits. */
90 volatile uint32_t *rq_db;
91 volatile uint32_t *cq_db;
96 volatile struct mlx5_wqe_data_seg(*wqes)[];
97 volatile struct mlx5_cqe(*cqes)[];
98 struct rxq_zip zip; /* Compressed context. */
99 struct rte_mbuf *(*elts)[];
100 struct rte_mempool *mp;
101 struct mlx5_rxq_stats stats;
102 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
103 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
104 void *cq_uar; /* CQ user access region. */
105 uint32_t cqn; /* CQ number. */
106 uint8_t cq_arm_sn; /* CQ arm seq number. */
107 } __rte_cache_aligned;
109 /* Verbs Rx queue elements. */
110 struct mlx5_rxq_ibv {
111 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
112 rte_atomic32_t refcnt; /* Reference counter. */
113 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
114 struct ibv_cq *cq; /* Completion Queue. */
115 struct ibv_wq *wq; /* Work Queue. */
116 struct ibv_comp_channel *channel;
117 struct mlx5_mr *mr; /* Memory Region (for mp). */
120 /* RX queue control descriptor. */
121 struct mlx5_rxq_ctrl {
122 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
123 rte_atomic32_t refcnt; /* Reference counter. */
124 struct priv *priv; /* Back pointer to private data. */
125 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
126 struct mlx5_rxq_data rxq; /* Data path structure. */
127 unsigned int socket; /* CPU socket ID for allocations. */
128 unsigned int irq:1; /* Whether IRQ is enabled. */
131 /* Indirection table. */
132 struct mlx5_ind_table_ibv {
133 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
134 rte_atomic32_t refcnt; /* Reference counter. */
135 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
136 uint16_t queues_n; /**< Number of queues in the list. */
137 uint16_t queues[]; /**< Queue list. */
142 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
143 rte_atomic32_t refcnt; /* Reference counter. */
144 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
145 struct ibv_qp *qp; /* Verbs queue pair. */
146 uint64_t hash_fields; /* Verbs Hash fields. */
147 uint8_t rss_key_len; /* Hash key length in bytes. */
148 uint8_t rss_key[]; /* Hash key. */
151 /* TX queue descriptor. */
153 struct mlx5_txq_data {
154 uint16_t elts_head; /* Current counter in (*elts)[]. */
155 uint16_t elts_tail; /* Counter of first element awaiting completion. */
156 uint16_t elts_comp; /* Counter since last completion request. */
157 uint16_t mpw_comp; /* WQ index since last completion request. */
158 uint16_t cq_ci; /* Consumer index for completion queue. */
160 uint16_t cq_pi; /* Producer index for completion queue. */
162 uint16_t wqe_ci; /* Consumer index for work queue. */
163 uint16_t wqe_pi; /* Producer index for work queue. */
164 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
165 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
166 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
167 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
168 uint16_t tunnel_en:1;
169 /* When set TX offload for tunneled packets are supported. */
170 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
171 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
172 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
173 uint16_t mr_cache_idx; /* Index of last hit entry. */
174 uint32_t qp_num_8s; /* QP number shifted by 8. */
175 uint64_t offloads; /* Offloads for Tx Queue. */
176 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
177 volatile void *wqes; /* Work queue (use volatile to write into). */
178 volatile uint32_t *qp_db; /* Work queue doorbell. */
179 volatile uint32_t *cq_db; /* Completion queue doorbell. */
180 volatile void *bf_reg; /* Blueflame register remapped. */
181 struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
182 struct rte_mbuf *(*elts)[]; /* TX elements. */
183 struct mlx5_txq_stats stats; /* TX queue counters. */
184 } __rte_cache_aligned;
186 /* Verbs Rx queue elements. */
187 struct mlx5_txq_ibv {
188 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
189 rte_atomic32_t refcnt; /* Reference counter. */
190 struct ibv_cq *cq; /* Completion Queue. */
191 struct ibv_qp *qp; /* Queue Pair. */
194 /* TX queue control descriptor. */
195 struct mlx5_txq_ctrl {
196 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
197 rte_atomic32_t refcnt; /* Reference counter. */
198 struct priv *priv; /* Back pointer to private data. */
199 unsigned int socket; /* CPU socket ID for allocations. */
200 unsigned int max_inline_data; /* Max inline data. */
201 unsigned int max_tso_header; /* Max TSO header size. */
202 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
203 struct mlx5_txq_data txq; /* Data path structure. */
204 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
205 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
210 extern uint8_t rss_hash_default_key[];
211 extern const size_t rss_hash_default_key_len;
213 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
214 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
215 unsigned int socket, const struct rte_eth_rxconf *conf,
216 struct rte_mempool *mp);
217 void mlx5_rx_queue_release(void *dpdk_rxq);
218 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
219 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
220 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
221 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
222 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
223 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
224 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
225 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
226 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
227 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
228 uint16_t desc, unsigned int socket,
229 const struct rte_eth_rxconf *conf,
230 struct rte_mempool *mp);
231 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
232 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
233 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
234 int mlx5_rxq_verify(struct rte_eth_dev *dev);
235 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
236 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
239 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
242 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
243 struct mlx5_ind_table_ibv *ind_tbl);
244 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
245 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev, uint8_t *rss_key,
246 uint8_t rss_key_len, uint64_t hash_fields,
247 uint16_t queues[], uint16_t queues_n);
248 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev, uint8_t *rss_key,
249 uint8_t rss_key_len, uint64_t hash_fields,
250 uint16_t queues[], uint16_t queues_n);
251 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
252 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
253 uint64_t mlx5_get_rx_port_offloads(void);
254 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
258 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
259 unsigned int socket, const struct rte_eth_txconf *conf);
260 void mlx5_tx_queue_release(void *dpdk_txq);
261 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
262 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
263 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
264 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
265 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
266 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
267 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
268 uint16_t desc, unsigned int socket,
269 const struct rte_eth_txconf *conf);
270 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
271 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
272 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
273 int mlx5_txq_verify(struct rte_eth_dev *dev);
274 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
275 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
279 extern uint32_t mlx5_ptype_table[];
281 void mlx5_set_ptype_table(void);
282 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
284 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
286 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
288 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
290 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
291 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
293 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
295 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
296 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
298 /* Vectorized version of mlx5_rxtx.c */
299 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
300 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
301 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
302 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
303 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
305 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
307 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
312 void mlx5_mp2mr_iter(struct rte_mempool *mp, void *arg);
313 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *txq,
314 struct rte_mempool *mp, unsigned int idx);
318 * Verify or set magic value in CQE.
327 check_cqe_seen(volatile struct mlx5_cqe *cqe)
329 static const uint8_t magic[] = "seen";
330 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
334 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
335 if (!ret || (*buf)[i] != magic[i]) {
337 (*buf)[i] = magic[i];
344 * Check whether CQE is valid.
349 * Size of completion queue.
354 * 0 on success, 1 on failure.
356 static __rte_always_inline int
357 check_cqe(volatile struct mlx5_cqe *cqe,
358 unsigned int cqes_n, const uint16_t ci)
360 uint16_t idx = ci & cqes_n;
361 uint8_t op_own = cqe->op_own;
362 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
363 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
365 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
366 return 1; /* No CQE. */
368 if ((op_code == MLX5_CQE_RESP_ERR) ||
369 (op_code == MLX5_CQE_REQ_ERR)) {
370 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
371 uint8_t syndrome = err_cqe->syndrome;
373 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
374 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
376 if (!check_cqe_seen(cqe)) {
377 ERROR("unexpected CQE error %u (0x%02x)"
379 op_code, op_code, syndrome);
380 rte_hexdump(stderr, "MLX5 Error CQE:",
381 (const void *)((uintptr_t)err_cqe),
385 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
386 (op_code != MLX5_CQE_REQ)) {
387 if (!check_cqe_seen(cqe)) {
388 ERROR("unexpected CQE opcode %u (0x%02x)",
390 rte_hexdump(stderr, "MLX5 CQE:",
391 (const void *)((uintptr_t)cqe),
401 * Return the address of the WQE.
404 * Pointer to TX queue structure.
406 * WQE consumer index.
411 static inline uintptr_t *
412 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
414 ci &= ((1 << txq->wqe_n) - 1);
415 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
419 * Manage TX completions.
421 * When sending a burst, mlx5_tx_burst() posts several WRs.
424 * Pointer to TX queue structure.
426 static __rte_always_inline void
427 mlx5_tx_complete(struct mlx5_txq_data *txq)
429 const uint16_t elts_n = 1 << txq->elts_n;
430 const uint16_t elts_m = elts_n - 1;
431 const unsigned int cqe_n = 1 << txq->cqe_n;
432 const unsigned int cqe_cnt = cqe_n - 1;
433 uint16_t elts_free = txq->elts_tail;
435 uint16_t cq_ci = txq->cq_ci;
436 volatile struct mlx5_cqe *cqe = NULL;
437 volatile struct mlx5_wqe_ctrl *ctrl;
438 struct rte_mbuf *m, *free[elts_n];
439 struct rte_mempool *pool = NULL;
440 unsigned int blk_n = 0;
442 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
443 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
446 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
447 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
448 if (!check_cqe_seen(cqe)) {
449 ERROR("unexpected error CQE, TX stopped");
450 rte_hexdump(stderr, "MLX5 TXQ:",
451 (const void *)((uintptr_t)txq->wqes),
459 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
460 ctrl = (volatile struct mlx5_wqe_ctrl *)
461 tx_mlx5_wqe(txq, txq->wqe_pi);
462 elts_tail = ctrl->ctrl3;
463 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
465 while (elts_free != elts_tail) {
466 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
467 if (likely(m != NULL)) {
468 if (likely(m->pool == pool)) {
471 if (likely(pool != NULL))
472 rte_mempool_put_bulk(pool,
482 rte_mempool_put_bulk(pool, (void *)free, blk_n);
484 elts_free = txq->elts_tail;
486 while (elts_free != elts_tail) {
487 memset(&(*txq->elts)[elts_free & elts_m],
489 sizeof((*txq->elts)[elts_free & elts_m]));
494 txq->elts_tail = elts_tail;
495 /* Update the consumer index. */
496 rte_compiler_barrier();
497 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
501 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
502 * the cloned mbuf is allocated is returned instead.
508 * Memory pool where data is located for given mbuf.
510 static struct rte_mempool *
511 mlx5_tx_mb2mp(struct rte_mbuf *buf)
513 if (unlikely(RTE_MBUF_INDIRECT(buf)))
514 return rte_mbuf_from_indirect(buf)->pool;
519 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
520 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
521 * remove an entry first.
524 * Pointer to TX queue structure.
526 * Memory Pool for which a Memory Region lkey must be returned.
529 * mr->lkey on success, (uint32_t)-1 on failure.
531 static __rte_always_inline uint32_t
532 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
534 uint16_t i = txq->mr_cache_idx;
535 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
538 assert(i < RTE_DIM(txq->mp2mr));
539 if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end > addr))
540 return txq->mp2mr[i]->lkey;
541 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
542 if (unlikely(txq->mp2mr[i] == NULL ||
543 txq->mp2mr[i]->mr == NULL)) {
544 /* Unknown MP, add a new MR for it. */
547 if (txq->mp2mr[i]->start <= addr &&
548 txq->mp2mr[i]->end > addr) {
549 assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
550 txq->mr_cache_idx = i;
551 return txq->mp2mr[i]->lkey;
554 mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
556 * Request the reference to use in this queue, the original one is
557 * kept by the control plane.
560 rte_atomic32_inc(&mr->refcnt);
561 txq->mr_cache_idx = i >= RTE_DIM(txq->mp2mr) ? i - 1 : i;
564 struct rte_mempool *mp = mlx5_tx_mb2mp(mb);
566 WARN("Failed to register mempool 0x%p(%s)",
567 (void *)mp, mp->name);
573 * Ring TX queue doorbell and flush the update if requested.
576 * Pointer to TX queue structure.
578 * Pointer to the last WQE posted in the NIC.
580 * Request for write memory barrier after BlueFlame update.
582 static __rte_always_inline void
583 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
586 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
587 volatile uint64_t *src = ((volatile uint64_t *)wqe);
590 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
591 /* Ensure ordering between DB record and BF copy. */
599 * Ring TX queue doorbell and flush the update by write memory barrier.
602 * Pointer to TX queue structure.
604 * Pointer to the last WQE posted in the NIC.
606 static __rte_always_inline void
607 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
609 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
613 * Convert the Checksum offloads to Verbs.
616 * Pointer to the Tx queue.
618 * Pointer to the mbuf.
621 * the converted cs_flags.
623 static __rte_always_inline uint8_t
624 txq_ol_cksum_to_cs(struct mlx5_txq_data *txq_data, struct rte_mbuf *buf)
626 uint8_t cs_flags = 0;
628 /* Should we enable HW CKSUM offload */
630 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM |
631 PKT_TX_OUTER_IP_CKSUM)) {
632 if (txq_data->tunnel_en &&
634 (PKT_TX_TUNNEL_GRE | PKT_TX_TUNNEL_VXLAN))) {
635 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
636 MLX5_ETH_WQE_L4_INNER_CSUM;
637 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
638 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
640 cs_flags = MLX5_ETH_WQE_L3_CSUM |
641 MLX5_ETH_WQE_L4_CSUM;
648 * Count the number of contiguous single segment packets.
651 * Pointer to array of packets.
656 * Number of contiguous single segment packets.
658 static __rte_always_inline unsigned int
659 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
665 /* Count the number of contiguous single segment packets. */
666 for (pos = 0; pos < pkts_n; ++pos)
667 if (NB_SEGS(pkts[pos]) > 1)
673 * Count the number of contiguous multi-segment packets.
676 * Pointer to array of packets.
681 * Number of contiguous multi-segment packets.
683 static __rte_always_inline unsigned int
684 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
690 /* Count the number of contiguous multi-segment packets. */
691 for (pos = 0; pos < pkts_n; ++pos)
692 if (NB_SEGS(pkts[pos]) == 1)
697 #endif /* RTE_PMD_MLX5_RXTX_H_ */