1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
30 #include "mlx5_utils.h"
32 #include "mlx5_autoconf.h"
33 #include "mlx5_defs.h"
36 struct mlx5_rxq_stats {
37 unsigned int idx; /**< Mapping index. */
38 #ifdef MLX5_PMD_SOFT_COUNTERS
39 uint64_t ipackets; /**< Total of successfully received packets. */
40 uint64_t ibytes; /**< Total of successfully received bytes. */
42 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
43 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
46 struct mlx5_txq_stats {
47 unsigned int idx; /**< Mapping index. */
48 #ifdef MLX5_PMD_SOFT_COUNTERS
49 uint64_t opackets; /**< Total of successfully sent packets. */
50 uint64_t obytes; /**< Total of successfully sent bytes. */
52 uint64_t oerrors; /**< Total number of failed transmitted packets. */
57 /* Memory region queue object. */
59 LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
60 rte_atomic32_t refcnt; /*<< Reference counter. */
61 uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
62 uintptr_t start; /* Start address of MR */
63 uintptr_t end; /* End address of MR */
64 struct ibv_mr *mr; /*<< Memory Region. */
65 struct rte_mempool *mp; /*<< Memory Pool. */
68 /* Compressed CQE context. */
70 uint16_t ai; /* Array index. */
71 uint16_t ca; /* Current array index. */
72 uint16_t na; /* Next array index. */
73 uint16_t cq_ci; /* The next CQE. */
74 uint32_t cqe_cnt; /* Number of CQEs. */
77 /* RX queue descriptor. */
78 struct mlx5_rxq_data {
79 unsigned int csum:1; /* Enable checksum offloading. */
80 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
81 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
82 unsigned int crc_present:1; /* CRC must be subtracted. */
83 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
84 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
85 unsigned int elts_n:4; /* Log 2 of Mbufs. */
86 unsigned int rss_hash:1; /* RSS hash result is enabled. */
87 unsigned int mark:1; /* Marked flow available on the queue. */
88 unsigned int :15; /* Remaining bits. */
89 volatile uint32_t *rq_db;
90 volatile uint32_t *cq_db;
95 volatile struct mlx5_wqe_data_seg(*wqes)[];
96 volatile struct mlx5_cqe(*cqes)[];
97 struct rxq_zip zip; /* Compressed context. */
98 struct rte_mbuf *(*elts)[];
99 struct rte_mempool *mp;
100 struct mlx5_rxq_stats stats;
101 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
102 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
103 void *cq_uar; /* CQ user access region. */
104 uint32_t cqn; /* CQ number. */
105 uint8_t cq_arm_sn; /* CQ arm seq number. */
106 uint32_t tunnel; /* Tunnel information. */
107 } __rte_cache_aligned;
109 /* Verbs Rx queue elements. */
110 struct mlx5_rxq_ibv {
111 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
112 rte_atomic32_t refcnt; /* Reference counter. */
113 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
114 struct ibv_cq *cq; /* Completion Queue. */
115 struct ibv_wq *wq; /* Work Queue. */
116 struct ibv_comp_channel *channel;
117 struct mlx5_mr *mr; /* Memory Region (for mp). */
120 /* RX queue control descriptor. */
121 struct mlx5_rxq_ctrl {
122 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
123 rte_atomic32_t refcnt; /* Reference counter. */
124 struct priv *priv; /* Back pointer to private data. */
125 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
126 struct mlx5_rxq_data rxq; /* Data path structure. */
127 unsigned int socket; /* CPU socket ID for allocations. */
128 uint32_t tunnel_types[16]; /* Tunnel type counter. */
129 unsigned int irq:1; /* Whether IRQ is enabled. */
130 uint16_t idx; /* Queue index. */
133 /* Indirection table. */
134 struct mlx5_ind_table_ibv {
135 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
136 rte_atomic32_t refcnt; /* Reference counter. */
137 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
138 uint32_t queues_n; /**< Number of queues in the list. */
139 uint16_t queues[]; /**< Queue list. */
144 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
145 rte_atomic32_t refcnt; /* Reference counter. */
146 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
147 struct ibv_qp *qp; /* Verbs queue pair. */
148 uint64_t hash_fields; /* Verbs Hash fields. */
149 uint32_t tunnel; /* Tunnel type. */
150 uint32_t rss_key_len; /* Hash key length in bytes. */
151 uint8_t rss_key[]; /* Hash key. */
154 /* TX queue descriptor. */
156 struct mlx5_txq_data {
157 uint16_t elts_head; /* Current counter in (*elts)[]. */
158 uint16_t elts_tail; /* Counter of first element awaiting completion. */
159 uint16_t elts_comp; /* Counter since last completion request. */
160 uint16_t mpw_comp; /* WQ index since last completion request. */
161 uint16_t cq_ci; /* Consumer index for completion queue. */
163 uint16_t cq_pi; /* Producer index for completion queue. */
165 uint16_t wqe_ci; /* Consumer index for work queue. */
166 uint16_t wqe_pi; /* Producer index for work queue. */
167 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
168 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
169 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
170 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
171 uint16_t tunnel_en:1;
172 /* When set TX offload for tunneled packets are supported. */
173 uint16_t swp_en:1; /* Whether SW parser is enabled. */
174 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
175 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
176 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
177 uint16_t mr_cache_idx; /* Index of last hit entry. */
178 uint32_t qp_num_8s; /* QP number shifted by 8. */
179 uint64_t offloads; /* Offloads for Tx Queue. */
180 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
181 volatile void *wqes; /* Work queue (use volatile to write into). */
182 volatile uint32_t *qp_db; /* Work queue doorbell. */
183 volatile uint32_t *cq_db; /* Completion queue doorbell. */
184 volatile void *bf_reg; /* Blueflame register remapped. */
185 struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
186 struct rte_mbuf *(*elts)[]; /* TX elements. */
187 struct mlx5_txq_stats stats; /* TX queue counters. */
188 } __rte_cache_aligned;
190 /* Verbs Rx queue elements. */
191 struct mlx5_txq_ibv {
192 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
193 rte_atomic32_t refcnt; /* Reference counter. */
194 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
195 struct ibv_cq *cq; /* Completion Queue. */
196 struct ibv_qp *qp; /* Queue Pair. */
199 /* TX queue control descriptor. */
200 struct mlx5_txq_ctrl {
201 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
202 rte_atomic32_t refcnt; /* Reference counter. */
203 struct priv *priv; /* Back pointer to private data. */
204 unsigned int socket; /* CPU socket ID for allocations. */
205 unsigned int max_inline_data; /* Max inline data. */
206 unsigned int max_tso_header; /* Max TSO header size. */
207 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
208 struct mlx5_txq_data txq; /* Data path structure. */
209 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
210 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
211 uint16_t idx; /* Queue index. */
216 extern uint8_t rss_hash_default_key[];
217 extern const size_t rss_hash_default_key_len;
219 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
220 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
221 unsigned int socket, const struct rte_eth_rxconf *conf,
222 struct rte_mempool *mp);
223 void mlx5_rx_queue_release(void *dpdk_rxq);
224 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
225 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
226 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
227 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
228 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
229 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
230 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
231 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
232 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
233 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
234 uint16_t desc, unsigned int socket,
235 const struct rte_eth_rxconf *conf,
236 struct rte_mempool *mp);
237 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
238 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
239 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
240 int mlx5_rxq_verify(struct rte_eth_dev *dev);
241 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
242 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
243 const uint16_t *queues,
245 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
246 const uint16_t *queues,
248 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
249 struct mlx5_ind_table_ibv *ind_tbl);
250 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
251 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
252 const uint8_t *rss_key, uint32_t rss_key_len,
253 uint64_t hash_fields,
254 const uint16_t *queues, uint32_t queues_n,
256 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
257 const uint8_t *rss_key, uint32_t rss_key_len,
258 uint64_t hash_fields,
259 const uint16_t *queues, uint32_t queues_n,
261 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
262 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
263 uint64_t mlx5_get_rx_port_offloads(void);
264 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
268 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
269 unsigned int socket, const struct rte_eth_txconf *conf);
270 void mlx5_tx_queue_release(void *dpdk_txq);
271 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
272 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
273 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
274 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
275 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
276 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
277 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
278 uint16_t desc, unsigned int socket,
279 const struct rte_eth_txconf *conf);
280 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
281 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
282 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
283 int mlx5_txq_verify(struct rte_eth_dev *dev);
284 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
285 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
289 extern uint32_t mlx5_ptype_table[];
290 extern uint8_t mlx5_cksum_table[];
291 extern uint8_t mlx5_swp_types_table[];
293 void mlx5_set_ptype_table(void);
294 void mlx5_set_cksum_table(void);
295 void mlx5_set_swp_types_table(void);
296 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
298 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
300 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
302 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
304 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
305 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
307 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
309 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
310 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
312 /* Vectorized version of mlx5_rxtx.c */
313 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
314 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
315 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
316 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
317 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
319 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
321 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
326 void mlx5_mp2mr_iter(struct rte_mempool *mp, void *arg);
327 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *txq,
328 struct rte_mempool *mp, unsigned int idx);
332 * Verify or set magic value in CQE.
341 check_cqe_seen(volatile struct mlx5_cqe *cqe)
343 static const uint8_t magic[] = "seen";
344 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
348 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
349 if (!ret || (*buf)[i] != magic[i]) {
351 (*buf)[i] = magic[i];
358 * Check whether CQE is valid.
363 * Size of completion queue.
368 * 0 on success, 1 on failure.
370 static __rte_always_inline int
371 check_cqe(volatile struct mlx5_cqe *cqe,
372 unsigned int cqes_n, const uint16_t ci)
374 uint16_t idx = ci & cqes_n;
375 uint8_t op_own = cqe->op_own;
376 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
377 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
379 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
380 return 1; /* No CQE. */
382 if ((op_code == MLX5_CQE_RESP_ERR) ||
383 (op_code == MLX5_CQE_REQ_ERR)) {
384 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
385 uint8_t syndrome = err_cqe->syndrome;
387 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
388 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
390 if (!check_cqe_seen(cqe)) {
392 "unexpected CQE error %u (0x%02x) syndrome"
394 op_code, op_code, syndrome);
395 rte_hexdump(stderr, "MLX5 Error CQE:",
396 (const void *)((uintptr_t)err_cqe),
400 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
401 (op_code != MLX5_CQE_REQ)) {
402 if (!check_cqe_seen(cqe)) {
403 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
405 rte_hexdump(stderr, "MLX5 CQE:",
406 (const void *)((uintptr_t)cqe),
416 * Return the address of the WQE.
419 * Pointer to TX queue structure.
421 * WQE consumer index.
426 static inline uintptr_t *
427 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
429 ci &= ((1 << txq->wqe_n) - 1);
430 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
434 * Manage TX completions.
436 * When sending a burst, mlx5_tx_burst() posts several WRs.
439 * Pointer to TX queue structure.
441 static __rte_always_inline void
442 mlx5_tx_complete(struct mlx5_txq_data *txq)
444 const uint16_t elts_n = 1 << txq->elts_n;
445 const uint16_t elts_m = elts_n - 1;
446 const unsigned int cqe_n = 1 << txq->cqe_n;
447 const unsigned int cqe_cnt = cqe_n - 1;
448 uint16_t elts_free = txq->elts_tail;
450 uint16_t cq_ci = txq->cq_ci;
451 volatile struct mlx5_cqe *cqe = NULL;
452 volatile struct mlx5_wqe_ctrl *ctrl;
453 struct rte_mbuf *m, *free[elts_n];
454 struct rte_mempool *pool = NULL;
455 unsigned int blk_n = 0;
457 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
458 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
461 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
462 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
463 if (!check_cqe_seen(cqe)) {
464 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
465 rte_hexdump(stderr, "MLX5 TXQ:",
466 (const void *)((uintptr_t)txq->wqes),
474 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
475 ctrl = (volatile struct mlx5_wqe_ctrl *)
476 tx_mlx5_wqe(txq, txq->wqe_pi);
477 elts_tail = ctrl->ctrl3;
478 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
480 while (elts_free != elts_tail) {
481 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
482 if (likely(m != NULL)) {
483 if (likely(m->pool == pool)) {
486 if (likely(pool != NULL))
487 rte_mempool_put_bulk(pool,
497 rte_mempool_put_bulk(pool, (void *)free, blk_n);
499 elts_free = txq->elts_tail;
501 while (elts_free != elts_tail) {
502 memset(&(*txq->elts)[elts_free & elts_m],
504 sizeof((*txq->elts)[elts_free & elts_m]));
509 txq->elts_tail = elts_tail;
510 /* Update the consumer index. */
511 rte_compiler_barrier();
512 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
516 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
517 * the cloned mbuf is allocated is returned instead.
523 * Memory pool where data is located for given mbuf.
525 static struct rte_mempool *
526 mlx5_tx_mb2mp(struct rte_mbuf *buf)
528 if (unlikely(RTE_MBUF_INDIRECT(buf)))
529 return rte_mbuf_from_indirect(buf)->pool;
534 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
535 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
536 * remove an entry first.
539 * Pointer to TX queue structure.
541 * Memory Pool for which a Memory Region lkey must be returned.
544 * mr->lkey on success, (uint32_t)-1 on failure.
546 static __rte_always_inline uint32_t
547 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
549 uint16_t i = txq->mr_cache_idx;
550 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
553 assert(i < RTE_DIM(txq->mp2mr));
554 if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end > addr))
555 return txq->mp2mr[i]->lkey;
556 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
557 if (unlikely(txq->mp2mr[i] == NULL ||
558 txq->mp2mr[i]->mr == NULL)) {
559 /* Unknown MP, add a new MR for it. */
562 if (txq->mp2mr[i]->start <= addr &&
563 txq->mp2mr[i]->end > addr) {
564 assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
565 txq->mr_cache_idx = i;
566 return txq->mp2mr[i]->lkey;
569 mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
571 * Request the reference to use in this queue, the original one is
572 * kept by the control plane.
575 rte_atomic32_inc(&mr->refcnt);
576 txq->mr_cache_idx = i >= RTE_DIM(txq->mp2mr) ? i - 1 : i;
579 struct rte_mempool *mp = mlx5_tx_mb2mp(mb);
581 DRV_LOG(WARNING, "failed to register mempool 0x%p(%s)",
582 (void *)mp, mp->name);
588 * Ring TX queue doorbell and flush the update if requested.
591 * Pointer to TX queue structure.
593 * Pointer to the last WQE posted in the NIC.
595 * Request for write memory barrier after BlueFlame update.
597 static __rte_always_inline void
598 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
601 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
602 volatile uint64_t *src = ((volatile uint64_t *)wqe);
605 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
606 /* Ensure ordering between DB record and BF copy. */
614 * Ring TX queue doorbell and flush the update by write memory barrier.
617 * Pointer to TX queue structure.
619 * Pointer to the last WQE posted in the NIC.
621 static __rte_always_inline void
622 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
624 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
628 * Convert mbuf to Verb SWP.
631 * Pointer to the Tx queue.
633 * Pointer to the mbuf.
635 * TSO offloads enabled.
637 * VLAN offloads enabled
639 * Pointer to the SWP header offsets.
641 * Pointer to the SWP header types.
643 static __rte_always_inline void
644 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
645 uint8_t tso, uint64_t vlan,
646 uint8_t *offsets, uint8_t *swp_types)
648 uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
651 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
654 if (likely(!tunnel || !txq->swp_en ||
655 (tunnel != PKT_TX_TUNNEL_UDP && tunnel != PKT_TX_TUNNEL_IP)))
658 * The index should have:
659 * bit[0:1] = PKT_TX_L4_MASK
660 * bit[4] = PKT_TX_IPV6
661 * bit[8] = PKT_TX_OUTER_IPV6
662 * bit[9] = PKT_TX_OUTER_UDP
664 idx = (buf->ol_flags & ol_flags_mask) >> 52;
665 if (tunnel == PKT_TX_TUNNEL_UDP)
667 *swp_types = mlx5_swp_types_table[idx];
669 off = buf->outer_l2_len + (vlan ? 4 : 0); /* Outer L3 offset. */
670 if (tso || (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM))
671 offsets[1] = off >> 1;
672 off += buf->outer_l3_len; /* Outer L4 offset. */
673 if (tunnel == PKT_TX_TUNNEL_UDP)
674 offsets[0] = off >> 1;
675 off += buf->l2_len; /* Inner L3 offset. */
676 if (tso || (buf->ol_flags & PKT_TX_IP_CKSUM))
677 offsets[3] = off >> 1;
678 off += buf->l3_len; /* Inner L4 offset. */
679 if (tso || ((buf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_TCP_CKSUM) ||
680 ((buf->ol_flags & PKT_TX_L4_MASK) == PKT_TX_UDP_CKSUM))
681 offsets[2] = off >> 1;
685 * Convert the Checksum offloads to Verbs.
688 * Pointer to the mbuf.
691 * Converted checksum flags.
693 static __rte_always_inline uint8_t
694 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
697 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
698 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
699 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
702 * The index should have:
703 * bit[0] = PKT_TX_TCP_SEG
704 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
705 * bit[4] = PKT_TX_IP_CKSUM
706 * bit[8] = PKT_TX_OUTER_IP_CKSUM
709 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
710 return mlx5_cksum_table[idx];
714 * Count the number of contiguous single segment packets.
717 * Pointer to array of packets.
722 * Number of contiguous single segment packets.
724 static __rte_always_inline unsigned int
725 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
731 /* Count the number of contiguous single segment packets. */
732 for (pos = 0; pos < pkts_n; ++pos)
733 if (NB_SEGS(pkts[pos]) > 1)
739 * Count the number of contiguous multi-segment packets.
742 * Pointer to array of packets.
747 * Number of contiguous multi-segment packets.
749 static __rte_always_inline unsigned int
750 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
756 /* Count the number of contiguous multi-segment packets. */
757 for (pos = 0; pos < pkts_n; ++pos)
758 if (NB_SEGS(pkts[pos]) == 1)
763 #endif /* RTE_PMD_MLX5_RXTX_H_ */