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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
39 #include <sys/queue.h>
42 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
44 #pragma GCC diagnostic ignored "-Wpedantic"
46 #include <infiniband/verbs.h>
47 #include <infiniband/mlx5dv.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_mempool.h>
54 #include <rte_common.h>
55 #include <rte_hexdump.h>
56 #include <rte_atomic.h>
58 #include "mlx5_utils.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 struct mlx5_rxq_stats {
65 unsigned int idx; /**< Mapping index. */
66 #ifdef MLX5_PMD_SOFT_COUNTERS
67 uint64_t ipackets; /**< Total of successfully received packets. */
68 uint64_t ibytes; /**< Total of successfully received bytes. */
70 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
71 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
74 struct mlx5_txq_stats {
75 unsigned int idx; /**< Mapping index. */
76 #ifdef MLX5_PMD_SOFT_COUNTERS
77 uint64_t opackets; /**< Total of successfully sent packets. */
78 uint64_t obytes; /**< Total of successfully sent bytes. */
80 uint64_t oerrors; /**< Total number of failed transmitted packets. */
85 /* Memory region queue object. */
87 LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
88 rte_atomic32_t refcnt; /*<< Reference counter. */
89 uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
90 uintptr_t start; /* Start address of MR */
91 uintptr_t end; /* End address of MR */
92 struct ibv_mr *mr; /*<< Memory Region. */
93 struct rte_mempool *mp; /*<< Memory Pool. */
96 /* Compressed CQE context. */
98 uint16_t ai; /* Array index. */
99 uint16_t ca; /* Current array index. */
100 uint16_t na; /* Next array index. */
101 uint16_t cq_ci; /* The next CQE. */
102 uint32_t cqe_cnt; /* Number of CQEs. */
105 /* RX queue descriptor. */
106 struct mlx5_rxq_data {
107 unsigned int csum:1; /* Enable checksum offloading. */
108 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
109 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
110 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111 unsigned int crc_present:1; /* CRC must be subtracted. */
112 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114 unsigned int elts_n:4; /* Log 2 of Mbufs. */
115 unsigned int rss_hash:1; /* RSS hash result is enabled. */
116 unsigned int mark:1; /* Marked flow available on the queue. */
117 unsigned int :15; /* Remaining bits. */
118 volatile uint32_t *rq_db;
119 volatile uint32_t *cq_db;
124 volatile struct mlx5_wqe_data_seg(*wqes)[];
125 volatile struct mlx5_cqe(*cqes)[];
126 struct rxq_zip zip; /* Compressed context. */
127 struct rte_mbuf *(*elts)[];
128 struct rte_mempool *mp;
129 struct mlx5_rxq_stats stats;
130 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
131 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
132 void *cq_uar; /* CQ user access region. */
133 uint32_t cqn; /* CQ number. */
134 uint8_t cq_arm_sn; /* CQ arm seq number. */
135 } __rte_cache_aligned;
137 /* Verbs Rx queue elements. */
138 struct mlx5_rxq_ibv {
139 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
140 rte_atomic32_t refcnt; /* Reference counter. */
141 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
142 struct ibv_cq *cq; /* Completion Queue. */
143 struct ibv_wq *wq; /* Work Queue. */
144 struct ibv_comp_channel *channel;
145 struct mlx5_mr *mr; /* Memory Region (for mp). */
148 /* RX queue control descriptor. */
149 struct mlx5_rxq_ctrl {
150 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
151 rte_atomic32_t refcnt; /* Reference counter. */
152 struct priv *priv; /* Back pointer to private data. */
153 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
154 struct mlx5_rxq_data rxq; /* Data path structure. */
155 unsigned int socket; /* CPU socket ID for allocations. */
156 unsigned int irq:1; /* Whether IRQ is enabled. */
159 /* Indirection table. */
160 struct mlx5_ind_table_ibv {
161 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
162 rte_atomic32_t refcnt; /* Reference counter. */
163 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
164 uint16_t queues_n; /**< Number of queues in the list. */
165 uint16_t queues[]; /**< Queue list. */
170 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
171 rte_atomic32_t refcnt; /* Reference counter. */
172 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
173 struct ibv_qp *qp; /* Verbs queue pair. */
174 uint64_t hash_fields; /* Verbs Hash fields. */
175 uint8_t rss_key_len; /* Hash key length in bytes. */
176 uint8_t rss_key[]; /* Hash key. */
179 /* TX queue descriptor. */
181 struct mlx5_txq_data {
182 uint16_t elts_head; /* Current counter in (*elts)[]. */
183 uint16_t elts_tail; /* Counter of first element awaiting completion. */
184 uint16_t elts_comp; /* Counter since last completion request. */
185 uint16_t mpw_comp; /* WQ index since last completion request. */
186 uint16_t cq_ci; /* Consumer index for completion queue. */
188 uint16_t cq_pi; /* Producer index for completion queue. */
190 uint16_t wqe_ci; /* Consumer index for work queue. */
191 uint16_t wqe_pi; /* Producer index for work queue. */
192 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
193 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
194 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
195 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
196 uint16_t tunnel_en:1;
197 /* When set TX offload for tunneled packets are supported. */
198 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
199 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
200 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
201 uint16_t mr_cache_idx; /* Index of last hit entry. */
202 uint32_t qp_num_8s; /* QP number shifted by 8. */
203 uint64_t offloads; /* Offloads for Tx Queue. */
204 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
205 volatile void *wqes; /* Work queue (use volatile to write into). */
206 volatile uint32_t *qp_db; /* Work queue doorbell. */
207 volatile uint32_t *cq_db; /* Completion queue doorbell. */
208 volatile void *bf_reg; /* Blueflame register remapped. */
209 struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
210 struct rte_mbuf *(*elts)[]; /* TX elements. */
211 struct mlx5_txq_stats stats; /* TX queue counters. */
212 } __rte_cache_aligned;
214 /* Verbs Rx queue elements. */
215 struct mlx5_txq_ibv {
216 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
217 rte_atomic32_t refcnt; /* Reference counter. */
218 struct ibv_cq *cq; /* Completion Queue. */
219 struct ibv_qp *qp; /* Queue Pair. */
222 /* TX queue control descriptor. */
223 struct mlx5_txq_ctrl {
224 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
225 rte_atomic32_t refcnt; /* Reference counter. */
226 struct priv *priv; /* Back pointer to private data. */
227 unsigned int socket; /* CPU socket ID for allocations. */
228 unsigned int max_inline_data; /* Max inline data. */
229 unsigned int max_tso_header; /* Max TSO header size. */
230 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
231 struct mlx5_txq_data txq; /* Data path structure. */
232 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
233 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
238 extern uint8_t rss_hash_default_key[];
239 extern const size_t rss_hash_default_key_len;
241 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *);
242 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
243 const struct rte_eth_rxconf *, struct rte_mempool *);
244 void mlx5_rx_queue_release(void *);
245 int priv_rx_intr_vec_enable(struct priv *priv);
246 void priv_rx_intr_vec_disable(struct priv *priv);
247 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
248 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
249 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_new(struct priv *, uint16_t);
250 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_get(struct priv *, uint16_t);
251 int mlx5_priv_rxq_ibv_release(struct priv *, struct mlx5_rxq_ibv *);
252 int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *);
253 int mlx5_priv_rxq_ibv_verify(struct priv *);
254 struct mlx5_rxq_ctrl *mlx5_priv_rxq_new(struct priv *, uint16_t,
255 uint16_t, unsigned int,
256 const struct rte_eth_rxconf *,
257 struct rte_mempool *);
258 struct mlx5_rxq_ctrl *mlx5_priv_rxq_get(struct priv *, uint16_t);
259 int mlx5_priv_rxq_release(struct priv *, uint16_t);
260 int mlx5_priv_rxq_releasable(struct priv *, uint16_t);
261 int mlx5_priv_rxq_verify(struct priv *);
262 int rxq_alloc_elts(struct mlx5_rxq_ctrl *);
263 struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_new(struct priv *,
266 struct mlx5_ind_table_ibv *mlx5_priv_ind_table_ibv_get(struct priv *,
269 int mlx5_priv_ind_table_ibv_release(struct priv *, struct mlx5_ind_table_ibv *);
270 int mlx5_priv_ind_table_ibv_verify(struct priv *);
271 struct mlx5_hrxq *mlx5_priv_hrxq_new(struct priv *, uint8_t *, uint8_t,
272 uint64_t, uint16_t [], uint16_t);
273 struct mlx5_hrxq *mlx5_priv_hrxq_get(struct priv *, uint8_t *, uint8_t,
274 uint64_t, uint16_t [], uint16_t);
275 int mlx5_priv_hrxq_release(struct priv *, struct mlx5_hrxq *);
276 int mlx5_priv_hrxq_ibv_verify(struct priv *);
277 uint64_t mlx5_priv_get_rx_port_offloads(struct priv *);
278 uint64_t mlx5_priv_get_rx_queue_offloads(struct priv *);
282 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
283 const struct rte_eth_txconf *);
284 void mlx5_tx_queue_release(void *);
285 int priv_tx_uar_remap(struct priv *priv, int fd);
286 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_new(struct priv *, uint16_t);
287 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_get(struct priv *, uint16_t);
288 int mlx5_priv_txq_ibv_release(struct priv *, struct mlx5_txq_ibv *);
289 int mlx5_priv_txq_ibv_releasable(struct priv *, struct mlx5_txq_ibv *);
290 int mlx5_priv_txq_ibv_verify(struct priv *);
291 struct mlx5_txq_ctrl *mlx5_priv_txq_new(struct priv *, uint16_t,
292 uint16_t, unsigned int,
293 const struct rte_eth_txconf *);
294 struct mlx5_txq_ctrl *mlx5_priv_txq_get(struct priv *, uint16_t);
295 int mlx5_priv_txq_release(struct priv *, uint16_t);
296 int mlx5_priv_txq_releasable(struct priv *, uint16_t);
297 int mlx5_priv_txq_verify(struct priv *);
298 void txq_alloc_elts(struct mlx5_txq_ctrl *);
299 uint64_t mlx5_priv_get_tx_port_offloads(struct priv *);
303 extern uint32_t mlx5_ptype_table[];
305 void mlx5_set_ptype_table(void);
306 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
307 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
308 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
309 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
310 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
311 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
312 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
313 int mlx5_rx_descriptor_status(void *, uint16_t);
314 int mlx5_tx_descriptor_status(void *, uint16_t);
316 /* Vectorized version of mlx5_rxtx.c */
317 int priv_check_raw_vec_tx_support(struct priv *, struct rte_eth_dev *);
318 int priv_check_vec_tx_support(struct priv *, struct rte_eth_dev *);
319 int rxq_check_vec_support(struct mlx5_rxq_data *);
320 int priv_check_vec_rx_support(struct priv *);
321 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
322 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
323 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
327 void mlx5_mp2mr_iter(struct rte_mempool *, void *);
328 struct mlx5_mr *priv_txq_mp2mr_reg(struct priv *priv, struct mlx5_txq_data *,
329 struct rte_mempool *, unsigned int);
330 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
335 * Verify or set magic value in CQE.
344 check_cqe_seen(volatile struct mlx5_cqe *cqe)
346 static const uint8_t magic[] = "seen";
347 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
351 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
352 if (!ret || (*buf)[i] != magic[i]) {
354 (*buf)[i] = magic[i];
361 * Check whether CQE is valid.
366 * Size of completion queue.
371 * 0 on success, 1 on failure.
373 static __rte_always_inline int
374 check_cqe(volatile struct mlx5_cqe *cqe,
375 unsigned int cqes_n, const uint16_t ci)
377 uint16_t idx = ci & cqes_n;
378 uint8_t op_own = cqe->op_own;
379 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
380 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
382 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
383 return 1; /* No CQE. */
385 if ((op_code == MLX5_CQE_RESP_ERR) ||
386 (op_code == MLX5_CQE_REQ_ERR)) {
387 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
388 uint8_t syndrome = err_cqe->syndrome;
390 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
391 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
393 if (!check_cqe_seen(cqe)) {
394 ERROR("unexpected CQE error %u (0x%02x)"
396 op_code, op_code, syndrome);
397 rte_hexdump(stderr, "MLX5 Error CQE:",
398 (const void *)((uintptr_t)err_cqe),
402 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
403 (op_code != MLX5_CQE_REQ)) {
404 if (!check_cqe_seen(cqe)) {
405 ERROR("unexpected CQE opcode %u (0x%02x)",
407 rte_hexdump(stderr, "MLX5 CQE:",
408 (const void *)((uintptr_t)cqe),
418 * Return the address of the WQE.
421 * Pointer to TX queue structure.
423 * WQE consumer index.
428 static inline uintptr_t *
429 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
431 ci &= ((1 << txq->wqe_n) - 1);
432 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
436 * Manage TX completions.
438 * When sending a burst, mlx5_tx_burst() posts several WRs.
441 * Pointer to TX queue structure.
443 static __rte_always_inline void
444 mlx5_tx_complete(struct mlx5_txq_data *txq)
446 const uint16_t elts_n = 1 << txq->elts_n;
447 const uint16_t elts_m = elts_n - 1;
448 const unsigned int cqe_n = 1 << txq->cqe_n;
449 const unsigned int cqe_cnt = cqe_n - 1;
450 uint16_t elts_free = txq->elts_tail;
452 uint16_t cq_ci = txq->cq_ci;
453 volatile struct mlx5_cqe *cqe = NULL;
454 volatile struct mlx5_wqe_ctrl *ctrl;
455 struct rte_mbuf *m, *free[elts_n];
456 struct rte_mempool *pool = NULL;
457 unsigned int blk_n = 0;
459 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
460 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
463 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
464 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
465 if (!check_cqe_seen(cqe)) {
466 ERROR("unexpected error CQE, TX stopped");
467 rte_hexdump(stderr, "MLX5 TXQ:",
468 (const void *)((uintptr_t)txq->wqes),
476 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
477 ctrl = (volatile struct mlx5_wqe_ctrl *)
478 tx_mlx5_wqe(txq, txq->wqe_pi);
479 elts_tail = ctrl->ctrl3;
480 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
482 while (elts_free != elts_tail) {
483 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
484 if (likely(m != NULL)) {
485 if (likely(m->pool == pool)) {
488 if (likely(pool != NULL))
489 rte_mempool_put_bulk(pool,
499 rte_mempool_put_bulk(pool, (void *)free, blk_n);
501 elts_free = txq->elts_tail;
503 while (elts_free != elts_tail) {
504 memset(&(*txq->elts)[elts_free & elts_m],
506 sizeof((*txq->elts)[elts_free & elts_m]));
511 txq->elts_tail = elts_tail;
512 /* Update the consumer index. */
513 rte_compiler_barrier();
514 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
518 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
519 * the cloned mbuf is allocated is returned instead.
525 * Memory pool where data is located for given mbuf.
527 static struct rte_mempool *
528 mlx5_tx_mb2mp(struct rte_mbuf *buf)
530 if (unlikely(RTE_MBUF_INDIRECT(buf)))
531 return rte_mbuf_from_indirect(buf)->pool;
536 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
537 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
538 * remove an entry first.
541 * Pointer to TX queue structure.
543 * Memory Pool for which a Memory Region lkey must be returned.
546 * mr->lkey on success, (uint32_t)-1 on failure.
548 static __rte_always_inline uint32_t
549 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
551 uint16_t i = txq->mr_cache_idx;
552 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
555 assert(i < RTE_DIM(txq->mp2mr));
556 if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end > addr))
557 return txq->mp2mr[i]->lkey;
558 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
559 if (unlikely(txq->mp2mr[i] == NULL ||
560 txq->mp2mr[i]->mr == NULL)) {
561 /* Unknown MP, add a new MR for it. */
564 if (txq->mp2mr[i]->start <= addr &&
565 txq->mp2mr[i]->end > addr) {
566 assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
567 txq->mr_cache_idx = i;
568 return txq->mp2mr[i]->lkey;
571 mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
573 * Request the reference to use in this queue, the original one is
574 * kept by the control plane.
577 rte_atomic32_inc(&mr->refcnt);
578 txq->mr_cache_idx = i >= RTE_DIM(txq->mp2mr) ? i - 1 : i;
581 struct rte_mempool *mp = mlx5_tx_mb2mp(mb);
583 WARN("Failed to register mempool 0x%p(%s)",
584 (void *)mp, mp->name);
590 * Ring TX queue doorbell and flush the update if requested.
593 * Pointer to TX queue structure.
595 * Pointer to the last WQE posted in the NIC.
597 * Request for write memory barrier after BlueFlame update.
599 static __rte_always_inline void
600 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
603 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
604 volatile uint64_t *src = ((volatile uint64_t *)wqe);
607 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
608 /* Ensure ordering between DB record and BF copy. */
616 * Ring TX queue doorbell and flush the update by write memory barrier.
619 * Pointer to TX queue structure.
621 * Pointer to the last WQE posted in the NIC.
623 static __rte_always_inline void
624 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
626 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
630 * Convert the Checksum offloads to Verbs.
633 * Pointer to the Tx queue.
635 * Pointer to the mbuf.
638 * the converted cs_flags.
640 static __rte_always_inline uint8_t
641 txq_ol_cksum_to_cs(struct mlx5_txq_data *txq_data, struct rte_mbuf *buf)
643 uint8_t cs_flags = 0;
645 /* Should we enable HW CKSUM offload */
647 (PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM |
648 PKT_TX_OUTER_IP_CKSUM)) {
649 if (txq_data->tunnel_en &&
651 (PKT_TX_TUNNEL_GRE | PKT_TX_TUNNEL_VXLAN))) {
652 cs_flags = MLX5_ETH_WQE_L3_INNER_CSUM |
653 MLX5_ETH_WQE_L4_INNER_CSUM;
654 if (buf->ol_flags & PKT_TX_OUTER_IP_CKSUM)
655 cs_flags |= MLX5_ETH_WQE_L3_CSUM;
657 cs_flags = MLX5_ETH_WQE_L3_CSUM |
658 MLX5_ETH_WQE_L4_CSUM;
665 * Count the number of contiguous single segment packets.
668 * Pointer to array of packets.
673 * Number of contiguous single segment packets.
675 static __rte_always_inline unsigned int
676 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
682 /* Count the number of contiguous single segment packets. */
683 for (pos = 0; pos < pkts_n; ++pos)
684 if (NB_SEGS(pkts[pos]) > 1)
690 * Count the number of contiguous multi-segment packets.
693 * Pointer to array of packets.
698 * Number of contiguous multi-segment packets.
700 static __rte_always_inline unsigned int
701 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
707 /* Count the number of contiguous multi-segment packets. */
708 for (pos = 0; pos < pkts_n; ++pos)
709 if (NB_SEGS(pkts[pos]) == 1)
714 #endif /* RTE_PMD_MLX5_RXTX_H_ */