1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 #include <rte_mempool.h>
15 #include <rte_common.h>
16 #include <rte_hexdump.h>
17 #include <rte_atomic.h>
18 #include <rte_spinlock.h>
20 #include <rte_bus_pci.h>
21 #include <rte_malloc.h>
22 #include <rte_cycles.h>
24 #include <mlx5_glue.h>
26 #include <mlx5_common.h>
27 #include <mlx5_common_mr.h>
29 #include "mlx5_defs.h"
30 #include "mlx5_utils.h"
32 #include "mlx5_autoconf.h"
34 /* Support tunnel matching. */
35 #define MLX5_FLOW_TUNNEL 10
37 /* Mbuf dynamic flag offset for inline. */
38 extern uint64_t rte_net_mlx5_dynf_inline_mask;
40 struct mlx5_rxq_stats {
41 #ifdef MLX5_PMD_SOFT_COUNTERS
42 uint64_t ipackets; /**< Total of successfully received packets. */
43 uint64_t ibytes; /**< Total of successfully received bytes. */
45 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
46 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
49 struct mlx5_txq_stats {
50 #ifdef MLX5_PMD_SOFT_COUNTERS
51 uint64_t opackets; /**< Total of successfully sent packets. */
52 uint64_t obytes; /**< Total of successfully sent bytes. */
54 uint64_t oerrors; /**< Total number of failed transmitted packets. */
59 /* Compressed CQE context. */
61 uint16_t ai; /* Array index. */
62 uint16_t ca; /* Current array index. */
63 uint16_t na; /* Next array index. */
64 uint16_t cq_ci; /* The next CQE. */
65 uint32_t cqe_cnt; /* Number of CQEs. */
68 /* Multi-Packet RQ buffer header. */
69 struct mlx5_mprq_buf {
70 struct rte_mempool *mp;
71 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
72 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
73 struct rte_mbuf_ext_shared_info shinfos[];
75 * Shared information per stride.
76 * More memory will be allocated for the first stride head-room and for
79 } __rte_cache_aligned;
81 /* Get pointer to the first stride. */
82 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
83 sizeof(struct mlx5_mprq_buf) + \
85 sizeof(struct rte_mbuf_ext_shared_info) + \
86 RTE_PKTMBUF_HEADROOM))
88 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
89 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
91 enum mlx5_rxq_err_state {
92 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
93 MLX5_RXQ_ERR_STATE_NEED_RESET,
94 MLX5_RXQ_ERR_STATE_NEED_READY,
97 /* RX queue descriptor. */
98 struct mlx5_rxq_data {
99 unsigned int csum:1; /* Enable checksum offloading. */
100 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
101 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
102 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
103 unsigned int crc_present:1; /* CRC must be subtracted. */
104 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
105 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
106 unsigned int elts_n:4; /* Log 2 of Mbufs. */
107 unsigned int rss_hash:1; /* RSS hash result is enabled. */
108 unsigned int mark:1; /* Marked flow available on the queue. */
109 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
110 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
111 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
112 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
113 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
114 unsigned int lro:1; /* Enable LRO. */
115 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
116 volatile uint32_t *rq_db;
117 volatile uint32_t *cq_db;
120 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
123 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
125 struct rxq_zip zip; /* Compressed context. */
126 uint16_t decompressed;
127 /* Number of ready mbufs decompressed from the CQ. */
129 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
130 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
132 volatile struct mlx5_cqe(*cqes)[];
135 struct rte_mbuf *(*elts)[];
136 struct mlx5_mprq_buf *(*mprq_bufs)[];
138 struct rte_mempool *mp;
139 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
140 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
141 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
142 uint16_t idx; /* Queue index. */
143 struct mlx5_rxq_stats stats;
144 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
145 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
146 void *cq_uar; /* CQ user access region. */
147 uint32_t cqn; /* CQ number. */
148 uint8_t cq_arm_sn; /* CQ arm seq number. */
150 rte_spinlock_t *uar_lock_cq;
151 /* CQ (UAR) access lock required for 32bit implementations */
153 uint32_t tunnel; /* Tunnel information. */
154 uint64_t flow_meta_mask;
155 int32_t flow_meta_offset;
156 } __rte_cache_aligned;
158 enum mlx5_rxq_obj_type {
159 MLX5_RXQ_OBJ_TYPE_IBV, /* mlx5_rxq_obj with ibv_wq. */
160 MLX5_RXQ_OBJ_TYPE_DEVX_RQ, /* mlx5_rxq_obj with mlx5_devx_rq. */
161 MLX5_RXQ_OBJ_TYPE_DEVX_HAIRPIN,
162 /* mlx5_rxq_obj with mlx5_devx_rq and hairpin support. */
166 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
167 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
168 MLX5_RXQ_TYPE_UNDEFINED,
171 /* Verbs/DevX Rx queue elements. */
172 struct mlx5_rxq_obj {
173 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */
174 rte_atomic32_t refcnt; /* Reference counter. */
175 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
176 struct ibv_cq *cq; /* Completion Queue. */
177 enum mlx5_rxq_obj_type type;
180 struct ibv_wq *wq; /* Work Queue. */
181 struct mlx5_devx_obj *rq; /* DevX object for Rx Queue. */
183 struct ibv_comp_channel *channel;
186 /* RX queue control descriptor. */
187 struct mlx5_rxq_ctrl {
188 struct mlx5_rxq_data rxq; /* Data path structure. */
189 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
190 rte_atomic32_t refcnt; /* Reference counter. */
191 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
192 struct mlx5_priv *priv; /* Back pointer to private data. */
193 enum mlx5_rxq_type type; /* Rxq type. */
194 unsigned int socket; /* CPU socket ID for allocations. */
195 unsigned int irq:1; /* Whether IRQ is enabled. */
196 unsigned int dbr_umem_id_valid:1; /* dbr_umem_id holds a valid value. */
197 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
198 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
199 uint32_t wqn; /* WQ number. */
200 uint16_t dump_file_n; /* Number of dump files. */
201 uint32_t dbr_umem_id; /* Storing door-bell information, */
202 uint64_t dbr_offset; /* needed when freeing door-bell. */
203 struct mlx5dv_devx_umem *wq_umem; /* WQ buffer registration info. */
204 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
207 enum mlx5_ind_tbl_type {
208 MLX5_IND_TBL_TYPE_IBV,
209 MLX5_IND_TBL_TYPE_DEVX,
212 /* Indirection table. */
213 struct mlx5_ind_table_obj {
214 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */
215 rte_atomic32_t refcnt; /* Reference counter. */
216 enum mlx5_ind_tbl_type type;
219 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
220 struct mlx5_devx_obj *rqt; /* DevX RQT object. */
222 uint32_t queues_n; /**< Number of queues in the list. */
223 uint16_t queues[]; /**< Queue list. */
228 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */
229 rte_atomic32_t refcnt; /* Reference counter. */
230 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */
233 struct ibv_qp *qp; /* Verbs queue pair. */
234 struct mlx5_devx_obj *tir; /* DevX TIR object. */
236 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
237 void *action; /* DV QP action pointer. */
239 uint64_t hash_fields; /* Verbs Hash fields. */
240 uint32_t rss_key_len; /* Hash key length in bytes. */
241 uint8_t rss_key[]; /* Hash key. */
244 /* TX queue send local data. */
246 struct mlx5_txq_local {
247 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
248 struct rte_mbuf *mbuf; /* first mbuf to process. */
249 uint16_t pkts_copy; /* packets copied to elts. */
250 uint16_t pkts_sent; /* packets sent. */
251 uint16_t pkts_loop; /* packets sent on loop entry. */
252 uint16_t elts_free; /* available elts remain. */
253 uint16_t wqe_free; /* available wqe remain. */
254 uint16_t mbuf_off; /* data offset in current mbuf. */
255 uint16_t mbuf_nseg; /* number of remaining mbuf. */
258 /* TX queue descriptor. */
260 struct mlx5_txq_data {
261 uint16_t elts_head; /* Current counter in (*elts)[]. */
262 uint16_t elts_tail; /* Counter of first element awaiting completion. */
263 uint16_t elts_comp; /* elts index since last completion request. */
264 uint16_t elts_s; /* Number of mbuf elements. */
265 uint16_t elts_m; /* Mask for mbuf elements indices. */
266 /* Fields related to elts mbuf storage. */
267 uint16_t wqe_ci; /* Consumer index for work queue. */
268 uint16_t wqe_pi; /* Producer index for work queue. */
269 uint16_t wqe_s; /* Number of WQ elements. */
270 uint16_t wqe_m; /* Mask Number for WQ elements. */
271 uint16_t wqe_comp; /* WQE index since last completion request. */
272 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
273 /* WQ related fields. */
274 uint16_t cq_ci; /* Consumer index for completion queue. */
275 uint16_t cq_pi; /* Production index for completion queue. */
276 uint16_t cqe_s; /* Number of CQ elements. */
277 uint16_t cqe_m; /* Mask for CQ indices. */
278 /* CQ related fields. */
279 uint16_t elts_n:4; /* elts[] length (in log2). */
280 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
281 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
282 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
283 uint16_t tunnel_en:1;
284 /* When set TX offload for tunneled packets are supported. */
285 uint16_t swp_en:1; /* Whether SW parser is enabled. */
286 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
287 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
288 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
289 uint16_t inlen_send; /* Ordinary send data inline size. */
290 uint16_t inlen_empw; /* eMPW max packet size to inline. */
291 uint16_t inlen_mode; /* Minimal data length to inline. */
292 uint32_t qp_num_8s; /* QP number shifted by 8. */
293 uint64_t offloads; /* Offloads for Tx Queue. */
294 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
295 struct mlx5_wqe *wqes; /* Work queue. */
296 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
297 #ifdef RTE_LIBRTE_MLX5_DEBUG
298 uint32_t *fcqs; /* Free completion queue (debug extended). */
300 uint16_t *fcqs; /* Free completion queue. */
302 volatile struct mlx5_cqe *cqes; /* Completion queue. */
303 volatile uint32_t *qp_db; /* Work queue doorbell. */
304 volatile uint32_t *cq_db; /* Completion queue doorbell. */
305 uint16_t port_id; /* Port ID of device. */
306 uint16_t idx; /* Queue index. */
307 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
308 int32_t ts_offset; /* Timestamp field dynamic offset. */
309 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
310 struct mlx5_txq_stats stats; /* TX queue counters. */
312 rte_spinlock_t *uar_lock;
313 /* UAR access lock required for 32bit implementations */
315 struct rte_mbuf *elts[0];
316 /* Storage for queued packets, must be the last field. */
317 } __rte_cache_aligned;
319 enum mlx5_txq_obj_type {
320 MLX5_TXQ_OBJ_TYPE_IBV, /* mlx5_txq_obj with ibv_wq. */
321 MLX5_TXQ_OBJ_TYPE_DEVX_SQ, /* mlx5_txq_obj with mlx5_devx_sq. */
322 MLX5_TXQ_OBJ_TYPE_DEVX_HAIRPIN,
323 /* mlx5_txq_obj with mlx5_devx_tq and hairpin support. */
327 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
328 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
331 /* Verbs/DevX Tx queue elements. */
332 struct mlx5_txq_obj {
333 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */
334 rte_atomic32_t refcnt; /* Reference counter. */
335 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
336 enum mlx5_txq_obj_type type; /* The txq object type. */
340 struct ibv_cq *cq; /* Completion Queue. */
341 struct ibv_qp *qp; /* Queue Pair. */
344 struct mlx5_devx_obj *sq;
345 /* DevX object for Sx queue. */
346 struct mlx5_devx_obj *tis; /* The TIS object. */
349 struct rte_eth_dev *dev;
350 struct mlx5_devx_obj *cq_devx;
351 struct mlx5dv_devx_umem *cq_umem;
353 int64_t cq_dbrec_offset;
354 struct mlx5_devx_dbr_page *cq_dbrec_page;
355 struct mlx5_devx_obj *sq_devx;
356 struct mlx5dv_devx_umem *sq_umem;
358 int64_t sq_dbrec_offset;
359 struct mlx5_devx_dbr_page *sq_dbrec_page;
364 /* TX queue control descriptor. */
365 struct mlx5_txq_ctrl {
366 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
367 rte_atomic32_t refcnt; /* Reference counter. */
368 unsigned int socket; /* CPU socket ID for allocations. */
369 enum mlx5_txq_type type; /* The txq ctrl type. */
370 unsigned int max_inline_data; /* Max inline data. */
371 unsigned int max_tso_header; /* Max TSO header size. */
372 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
373 struct mlx5_priv *priv; /* Back pointer to private data. */
374 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
375 void *bf_reg; /* BlueFlame register from Verbs. */
376 uint16_t dump_file_n; /* Number of dump files. */
377 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
378 struct mlx5_txq_data txq; /* Data path structure. */
379 /* Must be the last field in the structure, contains elts[]. */
382 #define MLX5_TX_BFREG(txq) \
383 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
387 extern uint8_t rss_hash_default_key[];
389 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
390 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
391 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
392 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
393 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
394 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
395 unsigned int socket, const struct rte_eth_rxconf *conf,
396 struct rte_mempool *mp);
397 int mlx5_rx_hairpin_queue_setup
398 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
399 const struct rte_eth_hairpin_conf *hairpin_conf);
400 void mlx5_rx_queue_release(void *dpdk_rxq);
401 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
402 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
403 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
404 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
405 struct mlx5_rxq_obj *mlx5_rxq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
406 enum mlx5_rxq_obj_type type);
407 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
408 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
409 uint16_t desc, unsigned int socket,
410 const struct rte_eth_rxconf *conf,
411 struct rte_mempool *mp);
412 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
413 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
414 const struct rte_eth_hairpin_conf *hairpin_conf);
415 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
416 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
417 int mlx5_rxq_verify(struct rte_eth_dev *dev);
418 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
419 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
420 uint32_t mlx5_hrxq_new(struct rte_eth_dev *dev,
421 const uint8_t *rss_key, uint32_t rss_key_len,
422 uint64_t hash_fields,
423 const uint16_t *queues, uint32_t queues_n,
424 int tunnel __rte_unused);
425 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
426 const uint8_t *rss_key, uint32_t rss_key_len,
427 uint64_t hash_fields,
428 const uint16_t *queues, uint32_t queues_n);
429 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
430 int mlx5_hrxq_verify(struct rte_eth_dev *dev);
431 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
432 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
433 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
434 uint64_t mlx5_get_rx_port_offloads(void);
435 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
436 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
441 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
442 unsigned int socket, const struct rte_eth_txconf *conf);
443 int mlx5_tx_hairpin_queue_setup
444 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
445 const struct rte_eth_hairpin_conf *hairpin_conf);
446 void mlx5_tx_queue_release(void *dpdk_txq);
447 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
448 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
449 struct mlx5_txq_obj *mlx5_txq_obj_new(struct rte_eth_dev *dev, uint16_t idx,
450 enum mlx5_txq_obj_type type);
451 struct mlx5_txq_obj *mlx5_txq_obj_get(struct rte_eth_dev *dev, uint16_t idx);
452 int mlx5_txq_obj_release(struct mlx5_txq_obj *txq_ibv);
453 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
454 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
455 uint16_t desc, unsigned int socket,
456 const struct rte_eth_txconf *conf);
457 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
458 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
459 const struct rte_eth_hairpin_conf *hairpin_conf);
460 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
461 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
462 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
463 int mlx5_txq_verify(struct rte_eth_dev *dev);
464 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
465 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
466 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
467 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
471 extern uint32_t mlx5_ptype_table[];
472 extern uint8_t mlx5_cksum_table[];
473 extern uint8_t mlx5_swp_types_table[];
475 void mlx5_set_ptype_table(void);
476 void mlx5_set_cksum_table(void);
477 void mlx5_set_swp_types_table(void);
478 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
479 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
480 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
481 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
482 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
483 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
485 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
487 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
489 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
490 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
491 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
492 void mlx5_dump_debug_information(const char *path, const char *title,
493 const void *buf, unsigned int len);
494 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
495 const struct mlx5_mp_arg_queue_state_modify *sm);
496 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
497 struct rte_eth_rxq_info *qinfo);
498 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
499 struct rte_eth_txq_info *qinfo);
500 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
501 struct rte_eth_burst_mode *mode);
502 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
503 struct rte_eth_burst_mode *mode);
505 /* Vectorized version of mlx5_rxtx.c */
506 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
507 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
508 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
513 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
514 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
515 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
516 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
517 struct rte_mempool *mp);
518 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
520 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
524 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
525 * 64bit architectures.
528 * value to write in CPU endian format.
530 * Address to write to.
532 * Address of the lock to use for that UAR access.
534 static __rte_always_inline void
535 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
536 rte_spinlock_t *lock __rte_unused)
539 *(uint64_t *)addr = val;
540 #else /* !RTE_ARCH_64 */
541 rte_spinlock_lock(lock);
542 *(uint32_t *)addr = val;
544 *((uint32_t *)addr + 1) = val >> 32;
545 rte_spinlock_unlock(lock);
550 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
551 * 64bit architectures while guaranteeing the order of execution with the
552 * code being executed.
555 * value to write in CPU endian format.
557 * Address to write to.
559 * Address of the lock to use for that UAR access.
561 static __rte_always_inline void
562 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
565 __mlx5_uar_write64_relaxed(val, addr, lock);
568 /* Assist macros, used instead of directly calling the functions they wrap. */
570 #define mlx5_uar_write64_relaxed(val, dst, lock) \
571 __mlx5_uar_write64_relaxed(val, dst, NULL)
572 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
574 #define mlx5_uar_write64_relaxed(val, dst, lock) \
575 __mlx5_uar_write64_relaxed(val, dst, lock)
576 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
580 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
581 * cloned mbuf is allocated is returned instead.
587 * Memory pool where data is located for given mbuf.
589 static inline struct rte_mempool *
590 mlx5_mb2mp(struct rte_mbuf *buf)
592 if (unlikely(RTE_MBUF_CLONED(buf)))
593 return rte_mbuf_from_indirect(buf)->pool;
598 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
599 * as mempool is pre-configured and static.
602 * Pointer to Rx queue structure.
607 * Searched LKey on success, UINT32_MAX on no match.
609 static __rte_always_inline uint32_t
610 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
612 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
615 /* Linear search on MR cache array. */
616 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
617 MLX5_MR_CACHE_N, addr);
618 if (likely(lkey != UINT32_MAX))
620 /* Take slower bottom-half (Binary Search) on miss. */
621 return mlx5_rx_addr2mr_bh(rxq, addr);
624 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
627 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
630 * Pointer to Tx queue structure.
635 * Searched LKey on success, UINT32_MAX on no match.
637 static __rte_always_inline uint32_t
638 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
640 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
641 uintptr_t addr = (uintptr_t)mb->buf_addr;
644 /* Check generation bit to see if there's any change on existing MRs. */
645 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
646 mlx5_mr_flush_local_cache(mr_ctrl);
647 /* Linear search on MR cache array. */
648 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
649 MLX5_MR_CACHE_N, addr);
650 if (likely(lkey != UINT32_MAX))
652 /* Take slower bottom-half on miss. */
653 return mlx5_tx_mb2mr_bh(txq, mb);
657 * Ring TX queue doorbell and flush the update if requested.
660 * Pointer to TX queue structure.
662 * Pointer to the last WQE posted in the NIC.
664 * Request for write memory barrier after BlueFlame update.
666 static __rte_always_inline void
667 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
670 uint64_t *dst = MLX5_TX_BFREG(txq);
671 volatile uint64_t *src = ((volatile uint64_t *)wqe);
674 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
675 /* Ensure ordering between DB record and BF copy. */
677 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
683 * Ring TX queue doorbell and flush the update by write memory barrier.
686 * Pointer to TX queue structure.
688 * Pointer to the last WQE posted in the NIC.
690 static __rte_always_inline void
691 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
693 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
697 * Convert timestamp from HW format to linear counter
698 * from Packet Pacing Clock Queue CQE timestamp format.
701 * Pointer to the device shared context. Might be needed
702 * to convert according current device configuration.
704 * Timestamp from CQE to convert.
708 static __rte_always_inline uint64_t
709 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
712 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
716 * Convert timestamp from mbuf format to linear counter
717 * of Clock Queue completions (24 bits)
720 * Pointer to the device shared context to fetch Tx
721 * packet pacing timestamp and parameters.
723 * Timestamp from mbuf to convert.
725 * positive or zero value - completion ID to wait
726 * negative value - conversion error
728 static __rte_always_inline int32_t
729 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
736 * Read atomically two uint64_t fields and compare lsb bits.
737 * It there is no match - the timestamp was updated in
738 * the service thread, data should be re-read.
740 rte_compiler_barrier();
741 ci = rte_atomic64_read(&sh->txpp.ts.ci_ts);
742 ts = rte_atomic64_read(&sh->txpp.ts.ts);
743 rte_compiler_barrier();
744 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
747 /* Perform the skew correction, positive value to send earlier. */
748 mts -= sh->txpp.skew;
750 if (unlikely(mts >= UINT64_MAX / 2)) {
751 /* We have negative integer, mts is in the past. */
752 rte_atomic32_inc(&sh->txpp.err_ts_past);
755 tick = sh->txpp.tick;
757 /* Convert delta to completions, round up. */
758 mts = (mts + tick - 1) / tick;
759 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
760 /* We have mts is too distant future. */
761 rte_atomic32_inc(&sh->txpp.err_ts_future);
764 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
766 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
770 #endif /* RTE_PMD_MLX5_RXTX_H_ */