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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
48 #pragma GCC diagnostic error "-Wpedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-Wpedantic"
56 #include <rte_mempool.h>
57 #include <rte_common.h>
59 #pragma GCC diagnostic error "-Wpedantic"
62 #include "mlx5_utils.h"
64 #include "mlx5_autoconf.h"
65 #include "mlx5_defs.h"
68 struct mlx5_rxq_stats {
69 unsigned int idx; /**< Mapping index. */
70 #ifdef MLX5_PMD_SOFT_COUNTERS
71 uint64_t ipackets; /**< Total of successfully received packets. */
72 uint64_t ibytes; /**< Total of successfully received bytes. */
74 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
75 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
78 struct mlx5_txq_stats {
79 unsigned int idx; /**< Mapping index. */
80 #ifdef MLX5_PMD_SOFT_COUNTERS
81 uint64_t opackets; /**< Total of successfully sent packets. */
82 uint64_t obytes; /**< Total of successfully sent bytes. */
84 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
87 /* Flow director queue structure. */
89 struct ibv_qp *qp; /* Associated RX QP. */
90 struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
91 struct ibv_exp_wq *wq; /* Work queue. */
92 struct ibv_cq *cq; /* Completion queue. */
97 /* Compressed CQE context. */
99 uint16_t ai; /* Array index. */
100 uint16_t ca; /* Current array index. */
101 uint16_t na; /* Next array index. */
102 uint16_t cq_ci; /* The next CQE. */
103 uint32_t cqe_cnt; /* Number of CQEs. */
106 /* RX queue descriptor. */
108 unsigned int csum:1; /* Enable checksum offloading. */
109 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
110 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
111 unsigned int crc_present:1; /* CRC must be subtracted. */
112 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
113 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
114 unsigned int elts_n:4; /* Log 2 of Mbufs. */
115 unsigned int port_id:8;
116 unsigned int rss_hash:1; /* RSS hash result is enabled. */
117 unsigned int mark:1; /* Marked flow available on the queue. */
118 unsigned int pending_err:1; /* CQE error needs to be handled. */
119 unsigned int :7; /* Remaining bits. */
120 volatile uint32_t *rq_db;
121 volatile uint32_t *cq_db;
125 volatile struct mlx5_wqe_data_seg(*wqes)[];
126 volatile struct mlx5_cqe(*cqes)[];
127 struct rxq_zip zip; /* Compressed context. */
128 struct rte_mbuf *(*elts)[];
129 struct rte_mempool *mp;
130 struct mlx5_rxq_stats stats;
131 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
132 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
133 } __rte_cache_aligned;
135 /* RX queue control descriptor. */
137 struct priv *priv; /* Back pointer to private data. */
138 struct ibv_cq *cq; /* Completion Queue. */
139 struct ibv_exp_wq *wq; /* Work Queue. */
140 struct fdir_queue *fdir_queue; /* Flow director queue. */
141 struct ibv_mr *mr; /* Memory Region (for mp). */
142 struct ibv_comp_channel *channel;
143 unsigned int socket; /* CPU socket ID for allocations. */
144 struct rxq rxq; /* Data path structure. */
147 /* Hash RX queue types. */
158 /* Flow structure with Ethernet specification. It is packed to prevent padding
159 * between attr and spec as this layout is expected by libibverbs. */
160 struct flow_attr_spec_eth {
161 struct ibv_exp_flow_attr attr;
162 struct ibv_exp_flow_spec_eth spec;
163 } __attribute__((packed));
165 /* Define a struct flow_attr_spec_eth object as an array of at least
166 * "size" bytes. Room after the first index is normally used to store
167 * extra flow specifications. */
168 #define FLOW_ATTR_SPEC_ETH(name, size) \
169 struct flow_attr_spec_eth name \
170 [((size) / sizeof(struct flow_attr_spec_eth)) + \
171 !!((size) % sizeof(struct flow_attr_spec_eth))]
173 /* Initialization data for hash RX queue. */
174 struct hash_rxq_init {
175 uint64_t hash_fields; /* Fields that participate in the hash. */
176 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
177 unsigned int flow_priority; /* Flow priority to use. */
180 enum ibv_exp_flow_spec_type type;
183 struct ibv_exp_flow_spec_tcp_udp tcp_udp;
184 struct ibv_exp_flow_spec_ipv4 ipv4;
185 struct ibv_exp_flow_spec_ipv6 ipv6;
186 struct ibv_exp_flow_spec_eth eth;
187 } flow_spec; /* Flow specification template. */
188 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
191 /* Initialization data for indirection table. */
192 struct ind_table_init {
193 unsigned int max_size; /* Maximum number of WQs. */
194 /* Hash RX queues using this table. */
195 unsigned int hash_types;
196 unsigned int hash_types_n;
199 /* Initialization data for special flows. */
200 struct special_flow_init {
201 uint8_t dst_mac_val[6];
202 uint8_t dst_mac_mask[6];
203 unsigned int hash_types;
204 unsigned int per_vlan:1;
207 enum hash_rxq_flow_type {
208 HASH_RXQ_FLOW_TYPE_PROMISC,
209 HASH_RXQ_FLOW_TYPE_ALLMULTI,
210 HASH_RXQ_FLOW_TYPE_BROADCAST,
211 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
212 HASH_RXQ_FLOW_TYPE_MAC,
216 static inline const char *
217 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
220 case HASH_RXQ_FLOW_TYPE_PROMISC:
221 return "promiscuous";
222 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
223 return "allmulticast";
224 case HASH_RXQ_FLOW_TYPE_BROADCAST:
226 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
227 return "IPv6 multicast";
228 case HASH_RXQ_FLOW_TYPE_MAC:
236 struct priv *priv; /* Back pointer to private data. */
237 struct ibv_qp *qp; /* Hash RX QP. */
238 enum hash_rxq_type type; /* Hash RX queue type. */
239 /* MAC flow steering rules, one per VLAN ID. */
240 struct ibv_exp_flow *mac_flow
241 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
242 struct ibv_exp_flow *special_flow
243 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
246 /* TX queue descriptor. */
249 uint16_t elts_head; /* Current counter in (*elts)[]. */
250 uint16_t elts_tail; /* Counter of first element awaiting completion. */
251 uint16_t elts_comp; /* Counter since last completion request. */
252 uint16_t mpw_comp; /* WQ index since last completion request. */
253 uint16_t cq_ci; /* Consumer index for completion queue. */
254 uint16_t cq_pi; /* Producer index for completion queue. */
255 uint16_t wqe_ci; /* Consumer index for work queue. */
256 uint16_t wqe_pi; /* Producer index for work queue. */
257 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
258 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
259 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
260 uint16_t inline_en:1; /* When set inline is enabled. */
261 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
262 uint16_t tunnel_en:1;
263 /* When set TX offload for tunneled packets are supported. */
264 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
265 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
266 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
267 uint32_t qp_num_8s; /* QP number shifted by 8. */
268 uint32_t flags; /* Flags for Tx Queue. */
269 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
270 volatile void *wqes; /* Work queue (use volatile to write into). */
271 volatile uint32_t *qp_db; /* Work queue doorbell. */
272 volatile uint32_t *cq_db; /* Completion queue doorbell. */
273 volatile void *bf_reg; /* Blueflame register. */
275 uintptr_t start; /* Start address of MR */
276 uintptr_t end; /* End address of MR */
277 struct ibv_mr *mr; /* Memory Region (for mp). */
278 uint32_t lkey; /* htonl(mr->lkey) */
279 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
280 uint16_t mr_cache_idx; /* Index of last hit entry. */
281 struct rte_mbuf *(*elts)[]; /* TX elements. */
282 struct mlx5_txq_stats stats; /* TX queue counters. */
283 } __rte_cache_aligned;
285 /* TX queue control descriptor. */
287 struct priv *priv; /* Back pointer to private data. */
288 struct ibv_cq *cq; /* Completion Queue. */
289 struct ibv_qp *qp; /* Queue Pair. */
290 unsigned int socket; /* CPU socket ID for allocations. */
291 struct txq txq; /* Data path structure. */
296 extern const struct hash_rxq_init hash_rxq_init[];
297 extern const unsigned int hash_rxq_init_n;
299 extern uint8_t rss_hash_default_key[];
300 extern const size_t rss_hash_default_key_len;
302 size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
303 size_t, enum hash_rxq_type);
304 int priv_create_hash_rxqs(struct priv *);
305 void priv_destroy_hash_rxqs(struct priv *);
306 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
307 int priv_rehash_flows(struct priv *);
308 void rxq_cleanup(struct rxq_ctrl *);
309 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
310 const struct rte_eth_rxconf *, struct rte_mempool *);
311 void mlx5_rx_queue_release(void *);
312 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
313 int priv_rx_intr_vec_enable(struct priv *priv);
314 void priv_rx_intr_vec_disable(struct priv *priv);
315 #ifdef HAVE_UPDATE_CQ_CI
316 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
317 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
318 #endif /* HAVE_UPDATE_CQ_CI */
322 void txq_cleanup(struct txq_ctrl *);
323 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
324 unsigned int, const struct rte_eth_txconf *);
325 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
326 const struct rte_eth_txconf *);
327 void mlx5_tx_queue_release(void *);
328 uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
332 extern uint32_t mlx5_ptype_table[];
334 void mlx5_set_ptype_table(void);
335 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
336 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
337 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
338 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
339 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
340 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
341 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
342 int mlx5_rx_descriptor_status(void *, uint16_t);
343 int mlx5_tx_descriptor_status(void *, uint16_t);
345 /* Vectorized version of mlx5_rxtx.c */
346 int priv_check_raw_vec_tx_support(struct priv *);
347 int priv_check_vec_tx_support(struct priv *);
348 int rxq_check_vec_support(struct rxq *);
349 int priv_check_vec_rx_support(struct priv *);
350 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
351 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
352 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
356 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
357 void txq_mp2mr_iter(struct rte_mempool *, void *);
358 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
362 * Verify or set magic value in CQE.
371 check_cqe_seen(volatile struct mlx5_cqe *cqe)
373 static const uint8_t magic[] = "seen";
374 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
378 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
379 if (!ret || (*buf)[i] != magic[i]) {
381 (*buf)[i] = magic[i];
388 * Check whether CQE is valid.
393 * Size of completion queue.
398 * 0 on success, 1 on failure.
400 static __rte_always_inline int
401 check_cqe(volatile struct mlx5_cqe *cqe,
402 unsigned int cqes_n, const uint16_t ci)
404 uint16_t idx = ci & cqes_n;
405 uint8_t op_own = cqe->op_own;
406 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
407 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
409 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
410 return 1; /* No CQE. */
412 if ((op_code == MLX5_CQE_RESP_ERR) ||
413 (op_code == MLX5_CQE_REQ_ERR)) {
414 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
415 uint8_t syndrome = err_cqe->syndrome;
417 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
418 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
420 if (!check_cqe_seen(cqe))
421 ERROR("unexpected CQE error %u (0x%02x)"
423 op_code, op_code, syndrome);
425 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
426 (op_code != MLX5_CQE_REQ)) {
427 if (!check_cqe_seen(cqe))
428 ERROR("unexpected CQE opcode %u (0x%02x)",
437 * Return the address of the WQE.
440 * Pointer to TX queue structure.
442 * WQE consumer index.
447 static inline uintptr_t *
448 tx_mlx5_wqe(struct txq *txq, uint16_t ci)
450 ci &= ((1 << txq->wqe_n) - 1);
451 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
455 * Manage TX completions.
457 * When sending a burst, mlx5_tx_burst() posts several WRs.
460 * Pointer to TX queue structure.
462 static __rte_always_inline void
463 mlx5_tx_complete(struct txq *txq)
465 const uint16_t elts_n = 1 << txq->elts_n;
466 const uint16_t elts_m = elts_n - 1;
467 const unsigned int cqe_n = 1 << txq->cqe_n;
468 const unsigned int cqe_cnt = cqe_n - 1;
469 uint16_t elts_free = txq->elts_tail;
471 uint16_t cq_ci = txq->cq_ci;
472 volatile struct mlx5_cqe *cqe = NULL;
473 volatile struct mlx5_wqe_ctrl *ctrl;
474 struct rte_mbuf *m, *free[elts_n];
475 struct rte_mempool *pool = NULL;
476 unsigned int blk_n = 0;
478 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
479 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
482 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
483 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
484 if (!check_cqe_seen(cqe))
485 ERROR("unexpected error CQE, TX stopped");
490 txq->wqe_pi = ntohs(cqe->wqe_counter);
491 ctrl = (volatile struct mlx5_wqe_ctrl *)
492 tx_mlx5_wqe(txq, txq->wqe_pi);
493 elts_tail = ctrl->ctrl3;
494 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
496 while (elts_free != elts_tail) {
497 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
498 if (likely(m != NULL)) {
499 if (likely(m->pool == pool)) {
502 if (likely(pool != NULL))
503 rte_mempool_put_bulk(pool,
513 rte_mempool_put_bulk(pool, (void *)free, blk_n);
515 elts_free = txq->elts_tail;
517 while (elts_free != elts_tail) {
518 memset(&(*txq->elts)[elts_free & elts_m],
520 sizeof((*txq->elts)[elts_free & elts_m]));
525 txq->elts_tail = elts_tail;
526 /* Update the consumer index. */
528 *txq->cq_db = htonl(cq_ci);
532 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
533 * the cloned mbuf is allocated is returned instead.
539 * Memory pool where data is located for given mbuf.
541 static struct rte_mempool *
542 mlx5_tx_mb2mp(struct rte_mbuf *buf)
544 if (unlikely(RTE_MBUF_INDIRECT(buf)))
545 return rte_mbuf_from_indirect(buf)->pool;
550 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
551 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
552 * remove an entry first.
555 * Pointer to TX queue structure.
557 * Memory Pool for which a Memory Region lkey must be returned.
560 * mr->lkey on success, (uint32_t)-1 on failure.
562 static __rte_always_inline uint32_t
563 mlx5_tx_mb2mr(struct txq *txq, struct rte_mbuf *mb)
565 uint16_t i = txq->mr_cache_idx;
566 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
568 assert(i < RTE_DIM(txq->mp2mr));
569 if (likely(txq->mp2mr[i].start <= addr && txq->mp2mr[i].end >= addr))
570 return txq->mp2mr[i].lkey;
571 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
572 if (unlikely(txq->mp2mr[i].mr == NULL)) {
573 /* Unknown MP, add a new MR for it. */
576 if (txq->mp2mr[i].start <= addr &&
577 txq->mp2mr[i].end >= addr) {
578 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
579 assert(htonl(txq->mp2mr[i].mr->lkey) ==
581 txq->mr_cache_idx = i;
582 return txq->mp2mr[i].lkey;
585 txq->mr_cache_idx = 0;
586 return txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
590 * Ring TX queue doorbell.
593 * Pointer to TX queue structure.
595 * Pointer to the last WQE posted in the NIC.
597 static __rte_always_inline void
598 mlx5_tx_dbrec(struct txq *txq, volatile struct mlx5_wqe *wqe)
600 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
601 volatile uint64_t *src = ((volatile uint64_t *)wqe);
604 *txq->qp_db = htonl(txq->wqe_ci);
605 /* Ensure ordering between DB record and BF copy. */
610 #endif /* RTE_PMD_MLX5_RXTX_H_ */