1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
32 #include "mlx5_utils.h"
35 #include "mlx5_autoconf.h"
36 #include "mlx5_defs.h"
39 /* Support tunnel matching. */
40 #define MLX5_FLOW_TUNNEL 5
42 struct mlx5_rxq_stats {
43 unsigned int idx; /**< Mapping index. */
44 #ifdef MLX5_PMD_SOFT_COUNTERS
45 uint64_t ipackets; /**< Total of successfully received packets. */
46 uint64_t ibytes; /**< Total of successfully received bytes. */
48 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
49 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
52 struct mlx5_txq_stats {
53 unsigned int idx; /**< Mapping index. */
54 #ifdef MLX5_PMD_SOFT_COUNTERS
55 uint64_t opackets; /**< Total of successfully sent packets. */
56 uint64_t obytes; /**< Total of successfully sent bytes. */
58 uint64_t oerrors; /**< Total number of failed transmitted packets. */
63 /* Compressed CQE context. */
65 uint16_t ai; /* Array index. */
66 uint16_t ca; /* Current array index. */
67 uint16_t na; /* Next array index. */
68 uint16_t cq_ci; /* The next CQE. */
69 uint32_t cqe_cnt; /* Number of CQEs. */
72 /* Multi-Packet RQ buffer header. */
73 struct mlx5_mprq_buf {
74 struct rte_mempool *mp;
75 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
76 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
77 } __rte_cache_aligned;
79 /* Get pointer to the first stride. */
80 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
82 /* RX queue descriptor. */
83 struct mlx5_rxq_data {
84 unsigned int csum:1; /* Enable checksum offloading. */
85 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
86 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
87 unsigned int crc_present:1; /* CRC must be subtracted. */
88 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
89 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
90 unsigned int elts_n:4; /* Log 2 of Mbufs. */
91 unsigned int rss_hash:1; /* RSS hash result is enabled. */
92 unsigned int mark:1; /* Marked flow available on the queue. */
93 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
94 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
95 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
96 unsigned int :6; /* Remaining bits. */
97 volatile uint32_t *rq_db;
98 volatile uint32_t *cq_db;
101 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
104 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
105 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
106 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
108 volatile struct mlx5_cqe(*cqes)[];
109 struct rxq_zip zip; /* Compressed context. */
112 struct rte_mbuf *(*elts)[];
113 struct mlx5_mprq_buf *(*mprq_bufs)[];
115 struct rte_mempool *mp;
116 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
117 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
118 struct mlx5_rxq_stats stats;
119 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
120 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
121 void *cq_uar; /* CQ user access region. */
122 uint32_t cqn; /* CQ number. */
123 uint8_t cq_arm_sn; /* CQ arm seq number. */
125 rte_spinlock_t *uar_lock_cq;
126 /* CQ (UAR) access lock required for 32bit implementations */
128 uint32_t tunnel; /* Tunnel information. */
129 } __rte_cache_aligned;
131 /* Verbs Rx queue elements. */
132 struct mlx5_rxq_ibv {
133 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
134 rte_atomic32_t refcnt; /* Reference counter. */
135 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
136 struct ibv_cq *cq; /* Completion Queue. */
137 struct ibv_wq *wq; /* Work Queue. */
138 struct ibv_comp_channel *channel;
141 /* RX queue control descriptor. */
142 struct mlx5_rxq_ctrl {
143 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
144 rte_atomic32_t refcnt; /* Reference counter. */
145 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
146 struct mlx5_priv *priv; /* Back pointer to private data. */
147 struct mlx5_rxq_data rxq; /* Data path structure. */
148 unsigned int socket; /* CPU socket ID for allocations. */
149 unsigned int irq:1; /* Whether IRQ is enabled. */
150 uint16_t idx; /* Queue index. */
151 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
152 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
155 /* Indirection table. */
156 struct mlx5_ind_table_ibv {
157 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
158 rte_atomic32_t refcnt; /* Reference counter. */
159 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
160 uint32_t queues_n; /**< Number of queues in the list. */
161 uint16_t queues[]; /**< Queue list. */
166 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
167 rte_atomic32_t refcnt; /* Reference counter. */
168 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
169 struct ibv_qp *qp; /* Verbs queue pair. */
170 uint64_t hash_fields; /* Verbs Hash fields. */
171 uint32_t rss_key_len; /* Hash key length in bytes. */
172 uint8_t rss_key[]; /* Hash key. */
175 /* TX queue descriptor. */
177 struct mlx5_txq_data {
178 uint16_t elts_head; /* Current counter in (*elts)[]. */
179 uint16_t elts_tail; /* Counter of first element awaiting completion. */
180 uint16_t elts_comp; /* Counter since last completion request. */
181 uint16_t mpw_comp; /* WQ index since last completion request. */
182 uint16_t cq_ci; /* Consumer index for completion queue. */
184 uint16_t cq_pi; /* Producer index for completion queue. */
186 uint16_t wqe_ci; /* Consumer index for work queue. */
187 uint16_t wqe_pi; /* Producer index for work queue. */
188 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
189 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
190 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
191 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
192 uint16_t tunnel_en:1;
193 /* When set TX offload for tunneled packets are supported. */
194 uint16_t swp_en:1; /* Whether SW parser is enabled. */
195 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
196 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
197 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
198 uint32_t qp_num_8s; /* QP number shifted by 8. */
199 uint64_t offloads; /* Offloads for Tx Queue. */
200 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
201 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
202 volatile void *wqes; /* Work queue (use volatile to write into). */
203 volatile uint32_t *qp_db; /* Work queue doorbell. */
204 volatile uint32_t *cq_db; /* Completion queue doorbell. */
205 volatile void *bf_reg; /* Blueflame register remapped. */
206 struct rte_mbuf *(*elts)[]; /* TX elements. */
207 struct mlx5_txq_stats stats; /* TX queue counters. */
209 rte_spinlock_t *uar_lock;
210 /* UAR access lock required for 32bit implementations */
212 } __rte_cache_aligned;
214 /* Verbs Rx queue elements. */
215 struct mlx5_txq_ibv {
216 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
217 rte_atomic32_t refcnt; /* Reference counter. */
218 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
219 struct ibv_cq *cq; /* Completion Queue. */
220 struct ibv_qp *qp; /* Queue Pair. */
223 /* TX queue control descriptor. */
224 struct mlx5_txq_ctrl {
225 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
226 rte_atomic32_t refcnt; /* Reference counter. */
227 unsigned int socket; /* CPU socket ID for allocations. */
228 unsigned int max_inline_data; /* Max inline data. */
229 unsigned int max_tso_header; /* Max TSO header size. */
230 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
231 struct mlx5_priv *priv; /* Back pointer to private data. */
232 struct mlx5_txq_data txq; /* Data path structure. */
233 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
234 volatile void *bf_reg_orig; /* Blueflame register from verbs. */
235 uint16_t idx; /* Queue index. */
240 extern uint8_t rss_hash_default_key[];
242 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
243 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
244 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
245 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
246 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
247 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
248 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
249 unsigned int socket, const struct rte_eth_rxconf *conf,
250 struct rte_mempool *mp);
251 void mlx5_rx_queue_release(void *dpdk_rxq);
252 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
253 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
254 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
255 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
256 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
257 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
258 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
259 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
260 struct mlx5_rxq_ibv *mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev);
261 void mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev);
262 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
263 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
264 uint16_t desc, unsigned int socket,
265 const struct rte_eth_rxconf *conf,
266 struct rte_mempool *mp);
267 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
268 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
269 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
270 int mlx5_rxq_verify(struct rte_eth_dev *dev);
271 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
272 int rxq_alloc_mprq_buf(struct mlx5_rxq_ctrl *rxq_ctrl);
273 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
274 const uint16_t *queues,
276 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
277 const uint16_t *queues,
279 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
280 struct mlx5_ind_table_ibv *ind_tbl);
281 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
282 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev);
283 void mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev);
284 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
285 const uint8_t *rss_key, uint32_t rss_key_len,
286 uint64_t hash_fields,
287 const uint16_t *queues, uint32_t queues_n,
288 int tunnel __rte_unused);
289 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
290 const uint8_t *rss_key, uint32_t rss_key_len,
291 uint64_t hash_fields,
292 const uint16_t *queues, uint32_t queues_n);
293 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
294 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
295 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
296 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
297 uint64_t mlx5_get_rx_port_offloads(void);
298 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
302 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
303 unsigned int socket, const struct rte_eth_txconf *conf);
304 void mlx5_tx_queue_release(void *dpdk_txq);
305 int mlx5_tx_uar_remap(struct rte_eth_dev *dev, int fd);
306 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
307 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
308 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
309 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
310 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
311 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
312 uint16_t desc, unsigned int socket,
313 const struct rte_eth_txconf *conf);
314 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
315 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
316 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
317 int mlx5_txq_verify(struct rte_eth_dev *dev);
318 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
319 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
323 extern uint32_t mlx5_ptype_table[];
324 extern uint8_t mlx5_cksum_table[];
325 extern uint8_t mlx5_swp_types_table[];
327 void mlx5_set_ptype_table(void);
328 void mlx5_set_cksum_table(void);
329 void mlx5_set_swp_types_table(void);
330 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
332 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
334 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
336 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
338 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
339 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
340 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
341 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
343 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
345 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
347 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
348 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
349 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
351 /* Vectorized version of mlx5_rxtx.c */
352 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
353 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
354 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
355 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
356 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
358 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
360 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
365 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
366 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
367 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
368 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
369 struct rte_mempool *mp);
372 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
373 * 64bit architectures.
376 * value to write in CPU endian format.
378 * Address to write to.
380 * Address of the lock to use for that UAR access.
382 static __rte_always_inline void
383 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
384 rte_spinlock_t *lock __rte_unused)
387 *(uint64_t *)addr = val;
388 #else /* !RTE_ARCH_64 */
389 rte_spinlock_lock(lock);
390 *(uint32_t *)addr = val;
392 *((uint32_t *)addr + 1) = val >> 32;
393 rte_spinlock_unlock(lock);
398 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
399 * 64bit architectures while guaranteeing the order of execution with the
400 * code being executed.
403 * value to write in CPU endian format.
405 * Address to write to.
407 * Address of the lock to use for that UAR access.
409 static __rte_always_inline void
410 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
413 __mlx5_uar_write64_relaxed(val, addr, lock);
416 /* Assist macros, used instead of directly calling the functions they wrap. */
418 #define mlx5_uar_write64_relaxed(val, dst, lock) \
419 __mlx5_uar_write64_relaxed(val, dst, NULL)
420 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
422 #define mlx5_uar_write64_relaxed(val, dst, lock) \
423 __mlx5_uar_write64_relaxed(val, dst, lock)
424 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
429 * Verify or set magic value in CQE.
438 check_cqe_seen(volatile struct mlx5_cqe *cqe)
440 static const uint8_t magic[] = "seen";
441 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1;
445 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
446 if (!ret || (*buf)[i] != magic[i]) {
448 (*buf)[i] = magic[i];
455 * Check whether CQE is valid.
460 * Size of completion queue.
465 * 0 on success, 1 on failure.
467 static __rte_always_inline int
468 check_cqe(volatile struct mlx5_cqe *cqe,
469 unsigned int cqes_n, const uint16_t ci)
471 uint16_t idx = ci & cqes_n;
472 uint8_t op_own = cqe->op_own;
473 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
474 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
476 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
477 return 1; /* No CQE. */
479 if ((op_code == MLX5_CQE_RESP_ERR) ||
480 (op_code == MLX5_CQE_REQ_ERR)) {
481 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
482 uint8_t syndrome = err_cqe->syndrome;
484 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
485 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
487 if (!check_cqe_seen(cqe)) {
489 "unexpected CQE error %u (0x%02x) syndrome"
491 op_code, op_code, syndrome);
492 rte_hexdump(stderr, "MLX5 Error CQE:",
493 (const void *)((uintptr_t)err_cqe),
497 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
498 (op_code != MLX5_CQE_REQ)) {
499 if (!check_cqe_seen(cqe)) {
500 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
502 rte_hexdump(stderr, "MLX5 CQE:",
503 (const void *)((uintptr_t)cqe),
513 * Return the address of the WQE.
516 * Pointer to TX queue structure.
518 * WQE consumer index.
523 static inline uintptr_t *
524 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
526 ci &= ((1 << txq->wqe_n) - 1);
527 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
531 * Manage TX completions.
533 * When sending a burst, mlx5_tx_burst() posts several WRs.
536 * Pointer to TX queue structure.
538 static __rte_always_inline void
539 mlx5_tx_complete(struct mlx5_txq_data *txq)
541 const uint16_t elts_n = 1 << txq->elts_n;
542 const uint16_t elts_m = elts_n - 1;
543 const unsigned int cqe_n = 1 << txq->cqe_n;
544 const unsigned int cqe_cnt = cqe_n - 1;
545 uint16_t elts_free = txq->elts_tail;
547 uint16_t cq_ci = txq->cq_ci;
548 volatile struct mlx5_cqe *cqe = NULL;
549 volatile struct mlx5_wqe_ctrl *ctrl;
550 struct rte_mbuf *m, *free[elts_n];
551 struct rte_mempool *pool = NULL;
552 unsigned int blk_n = 0;
554 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
555 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
558 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
559 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
560 if (!check_cqe_seen(cqe)) {
561 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
562 rte_hexdump(stderr, "MLX5 TXQ:",
563 (const void *)((uintptr_t)txq->wqes),
572 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
573 ctrl = (volatile struct mlx5_wqe_ctrl *)
574 tx_mlx5_wqe(txq, txq->wqe_pi);
575 elts_tail = ctrl->ctrl3;
576 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
578 while (elts_free != elts_tail) {
579 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
580 if (likely(m != NULL)) {
581 if (likely(m->pool == pool)) {
584 if (likely(pool != NULL))
585 rte_mempool_put_bulk(pool,
595 rte_mempool_put_bulk(pool, (void *)free, blk_n);
597 elts_free = txq->elts_tail;
599 while (elts_free != elts_tail) {
600 memset(&(*txq->elts)[elts_free & elts_m],
602 sizeof((*txq->elts)[elts_free & elts_m]));
607 txq->elts_tail = elts_tail;
608 /* Update the consumer index. */
609 rte_compiler_barrier();
610 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
614 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
615 * cloned mbuf is allocated is returned instead.
621 * Memory pool where data is located for given mbuf.
623 static inline struct rte_mempool *
624 mlx5_mb2mp(struct rte_mbuf *buf)
626 if (unlikely(RTE_MBUF_CLONED(buf)))
627 return rte_mbuf_from_indirect(buf)->pool;
632 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
633 * as mempool is pre-configured and static.
636 * Pointer to Rx queue structure.
641 * Searched LKey on success, UINT32_MAX on no match.
643 static __rte_always_inline uint32_t
644 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
646 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
649 /* Linear search on MR cache array. */
650 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
651 MLX5_MR_CACHE_N, addr);
652 if (likely(lkey != UINT32_MAX))
654 /* Take slower bottom-half (Binary Search) on miss. */
655 return mlx5_rx_addr2mr_bh(rxq, addr);
658 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
661 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
664 * Pointer to Tx queue structure.
669 * Searched LKey on success, UINT32_MAX on no match.
671 static __rte_always_inline uint32_t
672 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
674 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
675 uintptr_t addr = (uintptr_t)mb->buf_addr;
678 /* Check generation bit to see if there's any change on existing MRs. */
679 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
680 mlx5_mr_flush_local_cache(mr_ctrl);
681 /* Linear search on MR cache array. */
682 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
683 MLX5_MR_CACHE_N, addr);
684 if (likely(lkey != UINT32_MAX))
686 /* Take slower bottom-half on miss. */
687 return mlx5_tx_mb2mr_bh(txq, mb);
691 * Ring TX queue doorbell and flush the update if requested.
694 * Pointer to TX queue structure.
696 * Pointer to the last WQE posted in the NIC.
698 * Request for write memory barrier after BlueFlame update.
700 static __rte_always_inline void
701 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
704 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
705 volatile uint64_t *src = ((volatile uint64_t *)wqe);
708 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
709 /* Ensure ordering between DB record and BF copy. */
711 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
717 * Ring TX queue doorbell and flush the update by write memory barrier.
720 * Pointer to TX queue structure.
722 * Pointer to the last WQE posted in the NIC.
724 static __rte_always_inline void
725 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
727 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
731 * Convert mbuf to Verb SWP.
734 * Pointer to the Tx queue.
736 * Pointer to the mbuf.
738 * Pointer to the SWP header offsets.
740 * Pointer to the SWP header types.
742 static __rte_always_inline void
743 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
744 uint8_t *offsets, uint8_t *swp_types)
746 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
747 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
748 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
749 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
750 const uint64_t inner_ip =
751 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
752 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
757 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
758 tunnel != PKT_TX_TUNNEL_IP)))
761 * The index should have:
762 * bit[0:1] = PKT_TX_L4_MASK
763 * bit[4] = PKT_TX_IPV6
764 * bit[8] = PKT_TX_OUTER_IPV6
765 * bit[9] = PKT_TX_OUTER_UDP
767 idx = (buf->ol_flags & ol_flags_mask) >> 52;
768 if (tunnel == PKT_TX_TUNNEL_UDP)
770 *swp_types = mlx5_swp_types_table[idx];
772 * Set offsets for SW parser. Since ConnectX-5, SW parser just
773 * complements HW parser. SW parser starts to engage only if HW parser
774 * can't reach a header. For the older devices, HW parser will not kick
775 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
776 * should be set regardless of HW offload.
778 off = buf->outer_l2_len + (vlan ? sizeof(struct vlan_hdr) : 0);
779 offsets[1] = off >> 1; /* Outer L3 offset. */
780 off += buf->outer_l3_len;
781 if (tunnel == PKT_TX_TUNNEL_UDP)
782 offsets[0] = off >> 1; /* Outer L4 offset. */
785 offsets[3] = off >> 1; /* Inner L3 offset. */
786 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
787 csum_flags == PKT_TX_UDP_CKSUM) {
789 offsets[2] = off >> 1; /* Inner L4 offset. */
795 * Convert the Checksum offloads to Verbs.
798 * Pointer to the mbuf.
801 * Converted checksum flags.
803 static __rte_always_inline uint8_t
804 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
807 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
808 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
809 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
812 * The index should have:
813 * bit[0] = PKT_TX_TCP_SEG
814 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
815 * bit[4] = PKT_TX_IP_CKSUM
816 * bit[8] = PKT_TX_OUTER_IP_CKSUM
819 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
820 return mlx5_cksum_table[idx];
824 * Count the number of contiguous single segment packets.
827 * Pointer to array of packets.
832 * Number of contiguous single segment packets.
834 static __rte_always_inline unsigned int
835 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
841 /* Count the number of contiguous single segment packets. */
842 for (pos = 0; pos < pkts_n; ++pos)
843 if (NB_SEGS(pkts[pos]) > 1)
849 * Count the number of contiguous multi-segment packets.
852 * Pointer to array of packets.
857 * Number of contiguous multi-segment packets.
859 static __rte_always_inline unsigned int
860 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
866 /* Count the number of contiguous multi-segment packets. */
867 for (pos = 0; pos < pkts_n; ++pos)
868 if (NB_SEGS(pkts[pos]) == 1)
873 #endif /* RTE_PMD_MLX5_RXTX_H_ */