1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
16 #pragma GCC diagnostic ignored "-Wpedantic"
18 #include <infiniband/verbs.h>
19 #include <infiniband/mlx5dv.h>
21 #pragma GCC diagnostic error "-Wpedantic"
25 #include <rte_mempool.h>
26 #include <rte_common.h>
27 #include <rte_hexdump.h>
28 #include <rte_atomic.h>
29 #include <rte_spinlock.h>
31 #include <rte_bus_pci.h>
33 #include "mlx5_utils.h"
36 #include "mlx5_autoconf.h"
37 #include "mlx5_defs.h"
40 /* Support tunnel matching. */
41 #define MLX5_FLOW_TUNNEL 5
43 struct mlx5_rxq_stats {
44 #ifdef MLX5_PMD_SOFT_COUNTERS
45 uint64_t ipackets; /**< Total of successfully received packets. */
46 uint64_t ibytes; /**< Total of successfully received bytes. */
48 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
49 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
52 struct mlx5_txq_stats {
53 #ifdef MLX5_PMD_SOFT_COUNTERS
54 uint64_t opackets; /**< Total of successfully sent packets. */
55 uint64_t obytes; /**< Total of successfully sent bytes. */
57 uint64_t oerrors; /**< Total number of failed transmitted packets. */
62 /* Compressed CQE context. */
64 uint16_t ai; /* Array index. */
65 uint16_t ca; /* Current array index. */
66 uint16_t na; /* Next array index. */
67 uint16_t cq_ci; /* The next CQE. */
68 uint32_t cqe_cnt; /* Number of CQEs. */
71 /* Multi-Packet RQ buffer header. */
72 struct mlx5_mprq_buf {
73 struct rte_mempool *mp;
74 rte_atomic16_t refcnt; /* Atomically accessed refcnt. */
75 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
76 } __rte_cache_aligned;
78 /* Get pointer to the first stride. */
79 #define mlx5_mprq_buf_addr(ptr) ((ptr) + 1)
81 /* RX queue descriptor. */
82 struct mlx5_rxq_data {
83 unsigned int csum:1; /* Enable checksum offloading. */
84 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
85 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
86 unsigned int crc_present:1; /* CRC must be subtracted. */
87 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
88 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
89 unsigned int elts_n:4; /* Log 2 of Mbufs. */
90 unsigned int rss_hash:1; /* RSS hash result is enabled. */
91 unsigned int mark:1; /* Marked flow available on the queue. */
92 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
93 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
94 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
95 unsigned int :6; /* Remaining bits. */
96 volatile uint32_t *rq_db;
97 volatile uint32_t *cq_db;
100 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
103 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
104 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
105 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
107 volatile struct mlx5_cqe(*cqes)[];
108 struct rxq_zip zip; /* Compressed context. */
111 struct rte_mbuf *(*elts)[];
112 struct mlx5_mprq_buf *(*mprq_bufs)[];
114 struct rte_mempool *mp;
115 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
116 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
117 uint16_t idx; /* Queue index. */
118 struct mlx5_rxq_stats stats;
119 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
120 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
121 void *cq_uar; /* CQ user access region. */
122 uint32_t cqn; /* CQ number. */
123 uint8_t cq_arm_sn; /* CQ arm seq number. */
125 rte_spinlock_t *uar_lock_cq;
126 /* CQ (UAR) access lock required for 32bit implementations */
128 uint32_t tunnel; /* Tunnel information. */
129 } __rte_cache_aligned;
131 /* Verbs Rx queue elements. */
132 struct mlx5_rxq_ibv {
133 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
134 rte_atomic32_t refcnt; /* Reference counter. */
135 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
136 struct ibv_cq *cq; /* Completion Queue. */
137 struct ibv_wq *wq; /* Work Queue. */
138 struct ibv_comp_channel *channel;
141 /* RX queue control descriptor. */
142 struct mlx5_rxq_ctrl {
143 struct mlx5_rxq_data rxq; /* Data path structure. */
144 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
145 rte_atomic32_t refcnt; /* Reference counter. */
146 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
147 struct mlx5_priv *priv; /* Back pointer to private data. */
148 unsigned int socket; /* CPU socket ID for allocations. */
149 unsigned int irq:1; /* Whether IRQ is enabled. */
150 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
151 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
154 /* Indirection table. */
155 struct mlx5_ind_table_ibv {
156 LIST_ENTRY(mlx5_ind_table_ibv) next; /* Pointer to the next element. */
157 rte_atomic32_t refcnt; /* Reference counter. */
158 struct ibv_rwq_ind_table *ind_table; /**< Indirection table. */
159 uint32_t queues_n; /**< Number of queues in the list. */
160 uint16_t queues[]; /**< Queue list. */
165 LIST_ENTRY(mlx5_hrxq) next; /* Pointer to the next element. */
166 rte_atomic32_t refcnt; /* Reference counter. */
167 struct mlx5_ind_table_ibv *ind_table; /* Indirection table. */
168 struct ibv_qp *qp; /* Verbs queue pair. */
169 uint64_t hash_fields; /* Verbs Hash fields. */
170 uint32_t rss_key_len; /* Hash key length in bytes. */
171 uint8_t rss_key[]; /* Hash key. */
174 /* TX queue descriptor. */
176 struct mlx5_txq_data {
177 uint16_t elts_head; /* Current counter in (*elts)[]. */
178 uint16_t elts_tail; /* Counter of first element awaiting completion. */
179 uint16_t elts_comp; /* Counter since last completion request. */
180 uint16_t mpw_comp; /* WQ index since last completion request. */
181 uint16_t cq_ci; /* Consumer index for completion queue. */
183 uint16_t cq_pi; /* Producer index for completion queue. */
185 uint16_t wqe_ci; /* Consumer index for work queue. */
186 uint16_t wqe_pi; /* Producer index for work queue. */
187 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
188 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
189 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
190 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
191 uint16_t tunnel_en:1;
192 /* When set TX offload for tunneled packets are supported. */
193 uint16_t swp_en:1; /* Whether SW parser is enabled. */
194 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
195 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
196 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
197 uint32_t qp_num_8s; /* QP number shifted by 8. */
198 uint64_t offloads; /* Offloads for Tx Queue. */
199 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
200 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
201 volatile void *wqes; /* Work queue (use volatile to write into). */
202 volatile uint32_t *qp_db; /* Work queue doorbell. */
203 volatile uint32_t *cq_db; /* Completion queue doorbell. */
204 struct rte_mbuf *(*elts)[]; /* TX elements. */
205 uint16_t port_id; /* Port ID of device. */
206 uint16_t idx; /* Queue index. */
207 struct mlx5_txq_stats stats; /* TX queue counters. */
209 rte_spinlock_t *uar_lock;
210 /* UAR access lock required for 32bit implementations */
212 } __rte_cache_aligned;
214 /* Verbs Rx queue elements. */
215 struct mlx5_txq_ibv {
216 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
217 rte_atomic32_t refcnt; /* Reference counter. */
218 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */
219 struct ibv_cq *cq; /* Completion Queue. */
220 struct ibv_qp *qp; /* Queue Pair. */
223 /* TX queue control descriptor. */
224 struct mlx5_txq_ctrl {
225 struct mlx5_txq_data txq; /* Data path structure. */
226 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
227 rte_atomic32_t refcnt; /* Reference counter. */
228 unsigned int socket; /* CPU socket ID for allocations. */
229 unsigned int max_inline_data; /* Max inline data. */
230 unsigned int max_tso_header; /* Max TSO header size. */
231 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
232 struct mlx5_priv *priv; /* Back pointer to private data. */
233 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
234 void *bf_reg; /* BlueFlame register from Verbs. */
237 #define MLX5_TX_BFREG(txq) \
238 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
242 extern uint8_t rss_hash_default_key[];
244 int mlx5_check_mprq_support(struct rte_eth_dev *dev);
245 int mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq);
246 int mlx5_mprq_enabled(struct rte_eth_dev *dev);
247 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
248 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
249 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *rxq_ctrl);
250 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
251 unsigned int socket, const struct rte_eth_rxconf *conf,
252 struct rte_mempool *mp);
253 void mlx5_rx_queue_release(void *dpdk_rxq);
254 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
255 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
256 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
257 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
258 struct mlx5_rxq_ibv *mlx5_rxq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
259 struct mlx5_rxq_ibv *mlx5_rxq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
260 int mlx5_rxq_ibv_release(struct mlx5_rxq_ibv *rxq_ibv);
261 int mlx5_rxq_ibv_releasable(struct mlx5_rxq_ibv *rxq_ibv);
262 struct mlx5_rxq_ibv *mlx5_rxq_ibv_drop_new(struct rte_eth_dev *dev);
263 void mlx5_rxq_ibv_drop_release(struct rte_eth_dev *dev);
264 int mlx5_rxq_ibv_verify(struct rte_eth_dev *dev);
265 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
266 uint16_t desc, unsigned int socket,
267 const struct rte_eth_rxconf *conf,
268 struct rte_mempool *mp);
269 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
270 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
271 int mlx5_rxq_releasable(struct rte_eth_dev *dev, uint16_t idx);
272 int mlx5_rxq_verify(struct rte_eth_dev *dev);
273 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
274 int rxq_alloc_mprq_buf(struct mlx5_rxq_ctrl *rxq_ctrl);
275 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_new(struct rte_eth_dev *dev,
276 const uint16_t *queues,
278 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_get(struct rte_eth_dev *dev,
279 const uint16_t *queues,
281 int mlx5_ind_table_ibv_release(struct rte_eth_dev *dev,
282 struct mlx5_ind_table_ibv *ind_tbl);
283 int mlx5_ind_table_ibv_verify(struct rte_eth_dev *dev);
284 struct mlx5_ind_table_ibv *mlx5_ind_table_ibv_drop_new(struct rte_eth_dev *dev);
285 void mlx5_ind_table_ibv_drop_release(struct rte_eth_dev *dev);
286 struct mlx5_hrxq *mlx5_hrxq_new(struct rte_eth_dev *dev,
287 const uint8_t *rss_key, uint32_t rss_key_len,
288 uint64_t hash_fields,
289 const uint16_t *queues, uint32_t queues_n,
290 int tunnel __rte_unused);
291 struct mlx5_hrxq *mlx5_hrxq_get(struct rte_eth_dev *dev,
292 const uint8_t *rss_key, uint32_t rss_key_len,
293 uint64_t hash_fields,
294 const uint16_t *queues, uint32_t queues_n);
295 int mlx5_hrxq_release(struct rte_eth_dev *dev, struct mlx5_hrxq *hxrq);
296 int mlx5_hrxq_ibv_verify(struct rte_eth_dev *dev);
297 struct mlx5_hrxq *mlx5_hrxq_drop_new(struct rte_eth_dev *dev);
298 void mlx5_hrxq_drop_release(struct rte_eth_dev *dev);
299 uint64_t mlx5_get_rx_port_offloads(void);
300 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
304 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
305 unsigned int socket, const struct rte_eth_txconf *conf);
306 void mlx5_tx_queue_release(void *dpdk_txq);
307 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
308 struct mlx5_txq_ibv *mlx5_txq_ibv_new(struct rte_eth_dev *dev, uint16_t idx);
309 struct mlx5_txq_ibv *mlx5_txq_ibv_get(struct rte_eth_dev *dev, uint16_t idx);
310 int mlx5_txq_ibv_release(struct mlx5_txq_ibv *txq_ibv);
311 int mlx5_txq_ibv_releasable(struct mlx5_txq_ibv *txq_ibv);
312 int mlx5_txq_ibv_verify(struct rte_eth_dev *dev);
313 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
314 uint16_t desc, unsigned int socket,
315 const struct rte_eth_txconf *conf);
316 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
317 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
318 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
319 int mlx5_txq_verify(struct rte_eth_dev *dev);
320 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
321 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
325 extern uint32_t mlx5_ptype_table[];
326 extern uint8_t mlx5_cksum_table[];
327 extern uint8_t mlx5_swp_types_table[];
329 void mlx5_set_ptype_table(void);
330 void mlx5_set_cksum_table(void);
331 void mlx5_set_swp_types_table(void);
332 uint16_t mlx5_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
334 uint16_t mlx5_tx_burst_mpw(void *dpdk_txq, struct rte_mbuf **pkts,
336 uint16_t mlx5_tx_burst_mpw_inline(void *dpdk_txq, struct rte_mbuf **pkts,
338 uint16_t mlx5_tx_burst_empw(void *dpdk_txq, struct rte_mbuf **pkts,
340 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
341 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
342 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
343 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
345 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
347 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
349 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
350 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
351 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
353 /* Vectorized version of mlx5_rxtx.c */
354 int mlx5_check_raw_vec_tx_support(struct rte_eth_dev *dev);
355 int mlx5_check_vec_tx_support(struct rte_eth_dev *dev);
356 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
357 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
358 uint16_t mlx5_tx_burst_raw_vec(void *dpdk_txq, struct rte_mbuf **pkts,
360 uint16_t mlx5_tx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
362 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
367 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
368 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
369 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
370 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
371 struct rte_mempool *mp);
372 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
374 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
378 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
379 * 64bit architectures.
382 * value to write in CPU endian format.
384 * Address to write to.
386 * Address of the lock to use for that UAR access.
388 static __rte_always_inline void
389 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
390 rte_spinlock_t *lock __rte_unused)
393 *(uint64_t *)addr = val;
394 #else /* !RTE_ARCH_64 */
395 rte_spinlock_lock(lock);
396 *(uint32_t *)addr = val;
398 *((uint32_t *)addr + 1) = val >> 32;
399 rte_spinlock_unlock(lock);
404 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
405 * 64bit architectures while guaranteeing the order of execution with the
406 * code being executed.
409 * value to write in CPU endian format.
411 * Address to write to.
413 * Address of the lock to use for that UAR access.
415 static __rte_always_inline void
416 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
419 __mlx5_uar_write64_relaxed(val, addr, lock);
422 /* Assist macros, used instead of directly calling the functions they wrap. */
424 #define mlx5_uar_write64_relaxed(val, dst, lock) \
425 __mlx5_uar_write64_relaxed(val, dst, NULL)
426 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
428 #define mlx5_uar_write64_relaxed(val, dst, lock) \
429 __mlx5_uar_write64_relaxed(val, dst, lock)
430 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
435 * Verify or set magic value in CQE.
444 check_cqe_seen(volatile struct mlx5_cqe *cqe)
446 static const uint8_t magic[] = "seen";
447 volatile uint8_t (*buf)[sizeof(cqe->rsvd1)] = &cqe->rsvd1;
451 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
452 if (!ret || (*buf)[i] != magic[i]) {
454 (*buf)[i] = magic[i];
461 * Check whether CQE is valid.
466 * Size of completion queue.
471 * 0 on success, 1 on failure.
473 static __rte_always_inline int
474 check_cqe(volatile struct mlx5_cqe *cqe,
475 unsigned int cqes_n, const uint16_t ci)
477 uint16_t idx = ci & cqes_n;
478 uint8_t op_own = cqe->op_own;
479 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
480 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
482 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
483 return 1; /* No CQE. */
485 if ((op_code == MLX5_CQE_RESP_ERR) ||
486 (op_code == MLX5_CQE_REQ_ERR)) {
487 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
488 uint8_t syndrome = err_cqe->syndrome;
490 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
491 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
493 if (!check_cqe_seen(cqe)) {
495 "unexpected CQE error %u (0x%02x) syndrome"
497 op_code, op_code, syndrome);
498 rte_hexdump(stderr, "MLX5 Error CQE:",
499 (const void *)((uintptr_t)err_cqe),
503 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
504 (op_code != MLX5_CQE_REQ)) {
505 if (!check_cqe_seen(cqe)) {
506 DRV_LOG(ERR, "unexpected CQE opcode %u (0x%02x)",
508 rte_hexdump(stderr, "MLX5 CQE:",
509 (const void *)((uintptr_t)cqe),
519 * Return the address of the WQE.
522 * Pointer to TX queue structure.
524 * WQE consumer index.
529 static inline uintptr_t *
530 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
532 ci &= ((1 << txq->wqe_n) - 1);
533 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
537 * Manage TX completions.
539 * When sending a burst, mlx5_tx_burst() posts several WRs.
542 * Pointer to TX queue structure.
544 static __rte_always_inline void
545 mlx5_tx_complete(struct mlx5_txq_data *txq)
547 const uint16_t elts_n = 1 << txq->elts_n;
548 const uint16_t elts_m = elts_n - 1;
549 const unsigned int cqe_n = 1 << txq->cqe_n;
550 const unsigned int cqe_cnt = cqe_n - 1;
551 uint16_t elts_free = txq->elts_tail;
553 uint16_t cq_ci = txq->cq_ci;
554 volatile struct mlx5_cqe *cqe = NULL;
555 volatile struct mlx5_wqe_ctrl *ctrl;
556 struct rte_mbuf *m, *free[elts_n];
557 struct rte_mempool *pool = NULL;
558 unsigned int blk_n = 0;
560 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
561 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
564 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
565 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
566 if (!check_cqe_seen(cqe)) {
567 DRV_LOG(ERR, "unexpected error CQE, Tx stopped");
568 rte_hexdump(stderr, "MLX5 TXQ:",
569 (const void *)((uintptr_t)txq->wqes),
578 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
579 ctrl = (volatile struct mlx5_wqe_ctrl *)
580 tx_mlx5_wqe(txq, txq->wqe_pi);
581 elts_tail = ctrl->ctrl3;
582 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
584 while (elts_free != elts_tail) {
585 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
586 if (likely(m != NULL)) {
587 if (likely(m->pool == pool)) {
590 if (likely(pool != NULL))
591 rte_mempool_put_bulk(pool,
601 rte_mempool_put_bulk(pool, (void *)free, blk_n);
603 elts_free = txq->elts_tail;
605 while (elts_free != elts_tail) {
606 memset(&(*txq->elts)[elts_free & elts_m],
608 sizeof((*txq->elts)[elts_free & elts_m]));
613 txq->elts_tail = elts_tail;
614 /* Update the consumer index. */
615 rte_compiler_barrier();
616 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
620 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
621 * cloned mbuf is allocated is returned instead.
627 * Memory pool where data is located for given mbuf.
629 static inline struct rte_mempool *
630 mlx5_mb2mp(struct rte_mbuf *buf)
632 if (unlikely(RTE_MBUF_CLONED(buf)))
633 return rte_mbuf_from_indirect(buf)->pool;
638 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
639 * as mempool is pre-configured and static.
642 * Pointer to Rx queue structure.
647 * Searched LKey on success, UINT32_MAX on no match.
649 static __rte_always_inline uint32_t
650 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
652 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
655 /* Linear search on MR cache array. */
656 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
657 MLX5_MR_CACHE_N, addr);
658 if (likely(lkey != UINT32_MAX))
660 /* Take slower bottom-half (Binary Search) on miss. */
661 return mlx5_rx_addr2mr_bh(rxq, addr);
664 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
667 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
670 * Pointer to Tx queue structure.
675 * Searched LKey on success, UINT32_MAX on no match.
677 static __rte_always_inline uint32_t
678 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
680 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
681 uintptr_t addr = (uintptr_t)mb->buf_addr;
684 /* Check generation bit to see if there's any change on existing MRs. */
685 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
686 mlx5_mr_flush_local_cache(mr_ctrl);
687 /* Linear search on MR cache array. */
688 lkey = mlx5_mr_lookup_cache(mr_ctrl->cache, &mr_ctrl->mru,
689 MLX5_MR_CACHE_N, addr);
690 if (likely(lkey != UINT32_MAX))
692 /* Take slower bottom-half on miss. */
693 return mlx5_tx_mb2mr_bh(txq, mb);
697 * Ring TX queue doorbell and flush the update if requested.
700 * Pointer to TX queue structure.
702 * Pointer to the last WQE posted in the NIC.
704 * Request for write memory barrier after BlueFlame update.
706 static __rte_always_inline void
707 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
710 uint64_t *dst = MLX5_TX_BFREG(txq);
711 volatile uint64_t *src = ((volatile uint64_t *)wqe);
714 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
715 /* Ensure ordering between DB record and BF copy. */
717 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
723 * Ring TX queue doorbell and flush the update by write memory barrier.
726 * Pointer to TX queue structure.
728 * Pointer to the last WQE posted in the NIC.
730 static __rte_always_inline void
731 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
733 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
737 * Convert mbuf to Verb SWP.
740 * Pointer to the Tx queue.
742 * Pointer to the mbuf.
744 * Pointer to the SWP header offsets.
746 * Pointer to the SWP header types.
748 static __rte_always_inline void
749 txq_mbuf_to_swp(struct mlx5_txq_data *txq, struct rte_mbuf *buf,
750 uint8_t *offsets, uint8_t *swp_types)
752 const uint64_t vlan = buf->ol_flags & PKT_TX_VLAN_PKT;
753 const uint64_t tunnel = buf->ol_flags & PKT_TX_TUNNEL_MASK;
754 const uint64_t tso = buf->ol_flags & PKT_TX_TCP_SEG;
755 const uint64_t csum_flags = buf->ol_flags & PKT_TX_L4_MASK;
756 const uint64_t inner_ip =
757 buf->ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6);
758 const uint64_t ol_flags_mask = PKT_TX_L4_MASK | PKT_TX_IPV6 |
763 if (likely(!txq->swp_en || (tunnel != PKT_TX_TUNNEL_UDP &&
764 tunnel != PKT_TX_TUNNEL_IP)))
767 * The index should have:
768 * bit[0:1] = PKT_TX_L4_MASK
769 * bit[4] = PKT_TX_IPV6
770 * bit[8] = PKT_TX_OUTER_IPV6
771 * bit[9] = PKT_TX_OUTER_UDP
773 idx = (buf->ol_flags & ol_flags_mask) >> 52;
774 if (tunnel == PKT_TX_TUNNEL_UDP)
776 *swp_types = mlx5_swp_types_table[idx];
778 * Set offsets for SW parser. Since ConnectX-5, SW parser just
779 * complements HW parser. SW parser starts to engage only if HW parser
780 * can't reach a header. For the older devices, HW parser will not kick
781 * in if any of SWP offsets is set. Therefore, all of the L3 offsets
782 * should be set regardless of HW offload.
784 off = buf->outer_l2_len + (vlan ? sizeof(struct vlan_hdr) : 0);
785 offsets[1] = off >> 1; /* Outer L3 offset. */
786 off += buf->outer_l3_len;
787 if (tunnel == PKT_TX_TUNNEL_UDP)
788 offsets[0] = off >> 1; /* Outer L4 offset. */
791 offsets[3] = off >> 1; /* Inner L3 offset. */
792 if (csum_flags == PKT_TX_TCP_CKSUM || tso ||
793 csum_flags == PKT_TX_UDP_CKSUM) {
795 offsets[2] = off >> 1; /* Inner L4 offset. */
801 * Convert the Checksum offloads to Verbs.
804 * Pointer to the mbuf.
807 * Converted checksum flags.
809 static __rte_always_inline uint8_t
810 txq_ol_cksum_to_cs(struct rte_mbuf *buf)
813 uint8_t is_tunnel = !!(buf->ol_flags & PKT_TX_TUNNEL_MASK);
814 const uint64_t ol_flags_mask = PKT_TX_TCP_SEG | PKT_TX_L4_MASK |
815 PKT_TX_IP_CKSUM | PKT_TX_OUTER_IP_CKSUM;
818 * The index should have:
819 * bit[0] = PKT_TX_TCP_SEG
820 * bit[2:3] = PKT_TX_UDP_CKSUM, PKT_TX_TCP_CKSUM
821 * bit[4] = PKT_TX_IP_CKSUM
822 * bit[8] = PKT_TX_OUTER_IP_CKSUM
825 idx = ((buf->ol_flags & ol_flags_mask) >> 50) | (!!is_tunnel << 9);
826 return mlx5_cksum_table[idx];
830 * Count the number of contiguous single segment packets.
833 * Pointer to array of packets.
838 * Number of contiguous single segment packets.
840 static __rte_always_inline unsigned int
841 txq_count_contig_single_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
847 /* Count the number of contiguous single segment packets. */
848 for (pos = 0; pos < pkts_n; ++pos)
849 if (NB_SEGS(pkts[pos]) > 1)
855 * Count the number of contiguous multi-segment packets.
858 * Pointer to array of packets.
863 * Number of contiguous multi-segment packets.
865 static __rte_always_inline unsigned int
866 txq_count_contig_multi_seg(struct rte_mbuf **pkts, uint16_t pkts_n)
872 /* Count the number of contiguous multi-segment packets. */
873 for (pos = 0; pos < pkts_n; ++pos)
874 if (NB_SEGS(pkts[pos]) == 1)
879 #endif /* RTE_PMD_MLX5_RXTX_H_ */