1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2015 6WIND S.A.
3 * Copyright 2015 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_RXTX_H_
7 #define RTE_PMD_MLX5_RXTX_H_
11 #include <sys/queue.h>
14 #include <rte_mempool.h>
15 #include <rte_common.h>
16 #include <rte_hexdump.h>
17 #include <rte_spinlock.h>
19 #include <rte_bus_pci.h>
20 #include <rte_malloc.h>
21 #include <rte_cycles.h>
23 #include <mlx5_glue.h>
25 #include <mlx5_common.h>
26 #include <mlx5_common_mr.h>
28 #include "mlx5_defs.h"
29 #include "mlx5_utils.h"
31 #include "mlx5_autoconf.h"
34 /* Support tunnel matching. */
35 #define MLX5_FLOW_TUNNEL 10
37 /* Mbuf dynamic flag offset for inline. */
38 extern uint64_t rte_net_mlx5_dynf_inline_mask;
40 struct mlx5_rxq_stats {
41 #ifdef MLX5_PMD_SOFT_COUNTERS
42 uint64_t ipackets; /**< Total of successfully received packets. */
43 uint64_t ibytes; /**< Total of successfully received bytes. */
45 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
46 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
49 struct mlx5_txq_stats {
50 #ifdef MLX5_PMD_SOFT_COUNTERS
51 uint64_t opackets; /**< Total of successfully sent packets. */
52 uint64_t obytes; /**< Total of successfully sent bytes. */
54 uint64_t oerrors; /**< Total number of failed transmitted packets. */
59 /* Compressed CQE context. */
61 uint16_t ai; /* Array index. */
62 uint16_t ca; /* Current array index. */
63 uint16_t na; /* Next array index. */
64 uint16_t cq_ci; /* The next CQE. */
65 uint32_t cqe_cnt; /* Number of CQEs. */
68 /* Multi-Packet RQ buffer header. */
69 struct mlx5_mprq_buf {
70 struct rte_mempool *mp;
71 uint16_t refcnt; /* Atomically accessed refcnt. */
72 uint8_t pad[RTE_PKTMBUF_HEADROOM]; /* Headroom for the first packet. */
73 struct rte_mbuf_ext_shared_info shinfos[];
75 * Shared information per stride.
76 * More memory will be allocated for the first stride head-room and for
79 } __rte_cache_aligned;
81 /* Get pointer to the first stride. */
82 #define mlx5_mprq_buf_addr(ptr, strd_n) (RTE_PTR_ADD((ptr), \
83 sizeof(struct mlx5_mprq_buf) + \
85 sizeof(struct rte_mbuf_ext_shared_info) + \
86 RTE_PKTMBUF_HEADROOM))
88 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
89 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
91 enum mlx5_rxq_err_state {
92 MLX5_RXQ_ERR_STATE_NO_ERROR = 0,
93 MLX5_RXQ_ERR_STATE_NEED_RESET,
94 MLX5_RXQ_ERR_STATE_NEED_READY,
98 MLX5_RXQ_CODE_EXIT = 0,
100 MLX5_RXQ_CODE_DROPPED,
103 struct mlx5_eth_rxseg {
104 struct rte_mempool *mp; /**< Memory pool to allocate segment from. */
105 uint16_t length; /**< Segment data length, configures split point. */
106 uint16_t offset; /**< Data offset from beginning of mbuf data buffer. */
107 uint32_t reserved; /**< Reserved field. */
110 /* RX queue descriptor. */
111 struct mlx5_rxq_data {
112 unsigned int csum:1; /* Enable checksum offloading. */
113 unsigned int hw_timestamp:1; /* Enable HW timestamp. */
114 unsigned int rt_timestamp:1; /* Realtime timestamp format. */
115 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
116 unsigned int crc_present:1; /* CRC must be subtracted. */
117 unsigned int sges_n:3; /* Log 2 of SGEs (max buffers per packet). */
118 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
119 unsigned int elts_n:4; /* Log 2 of Mbufs. */
120 unsigned int rss_hash:1; /* RSS hash result is enabled. */
121 unsigned int mark:1; /* Marked flow available on the queue. */
122 unsigned int strd_num_n:5; /* Log 2 of the number of stride. */
123 unsigned int strd_sz_n:4; /* Log 2 of stride size. */
124 unsigned int strd_shift_en:1; /* Enable 2bytes shift on a stride. */
125 unsigned int err_state:2; /* enum mlx5_rxq_err_state. */
126 unsigned int strd_scatter_en:1; /* Scattered packets from a stride. */
127 unsigned int lro:1; /* Enable LRO. */
128 unsigned int dynf_meta:1; /* Dynamic metadata is configured. */
129 unsigned int mcqe_format:3; /* Dynamic metadata is configured. */
130 volatile uint32_t *rq_db;
131 volatile uint32_t *cq_db;
135 uint16_t consumed_strd; /* Number of consumed strides in WQE. */
138 uint16_t rq_repl_thresh; /* Threshold for buffer replenishment. */
141 struct rxq_zip zip; /* Compressed context. */
142 uint16_t decompressed;
143 /* Number of ready mbufs decompressed from the CQ. */
145 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
146 uint16_t mprq_max_memcpy_len; /* Maximum size of packet to memcpy. */
148 volatile struct mlx5_cqe(*cqes)[];
149 struct rte_mbuf *(*elts)[];
150 struct mlx5_mprq_buf *(*mprq_bufs)[];
151 struct rte_mempool *mp;
152 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */
153 struct mlx5_mprq_buf *mprq_repl; /* Stashed mbuf for replenish. */
154 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
155 uint16_t idx; /* Queue index. */
156 struct mlx5_rxq_stats stats;
157 rte_xmm_t mbuf_initializer; /* Default rearm/flags for vectorized Rx. */
158 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
159 void *cq_uar; /* Verbs CQ user access region. */
160 uint32_t cqn; /* CQ number. */
161 uint8_t cq_arm_sn; /* CQ arm seq number. */
163 rte_spinlock_t *uar_lock_cq;
164 /* CQ (UAR) access lock required for 32bit implementations */
166 uint32_t tunnel; /* Tunnel information. */
167 int timestamp_offset; /* Dynamic mbuf field for timestamp. */
168 uint64_t timestamp_rx_flag; /* Dynamic mbuf flag for timestamp. */
169 uint64_t flow_meta_mask;
170 int32_t flow_meta_offset;
171 uint32_t rxseg_n; /* Number of split segment descriptions. */
172 struct mlx5_eth_rxseg rxseg[MLX5_MAX_RXQ_NSEG];
173 /* Buffer split segment descriptions - sizes, offsets, pools. */
174 } __rte_cache_aligned;
177 MLX5_RXQ_TYPE_STANDARD, /* Standard Rx queue. */
178 MLX5_RXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
179 MLX5_RXQ_TYPE_UNDEFINED,
182 /* RX queue control descriptor. */
183 struct mlx5_rxq_ctrl {
184 struct mlx5_rxq_data rxq; /* Data path structure. */
185 LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */
186 uint32_t refcnt; /* Reference counter. */
187 struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */
188 struct mlx5_priv *priv; /* Back pointer to private data. */
189 enum mlx5_rxq_type type; /* Rxq type. */
190 unsigned int socket; /* CPU socket ID for allocations. */
191 unsigned int irq:1; /* Whether IRQ is enabled. */
192 uint32_t flow_mark_n; /* Number of Mark/Flag flows using this Queue. */
193 uint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */
194 uint32_t wqn; /* WQ number. */
195 uint16_t dump_file_n; /* Number of dump files. */
196 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
197 uint32_t hairpin_status; /* Hairpin binding status. */
200 /* TX queue send local data. */
202 struct mlx5_txq_local {
203 struct mlx5_wqe *wqe_last; /* last sent WQE pointer. */
204 struct rte_mbuf *mbuf; /* first mbuf to process. */
205 uint16_t pkts_copy; /* packets copied to elts. */
206 uint16_t pkts_sent; /* packets sent. */
207 uint16_t pkts_loop; /* packets sent on loop entry. */
208 uint16_t elts_free; /* available elts remain. */
209 uint16_t wqe_free; /* available wqe remain. */
210 uint16_t mbuf_off; /* data offset in current mbuf. */
211 uint16_t mbuf_nseg; /* number of remaining mbuf. */
212 uint16_t mbuf_free; /* number of inline mbufs to free. */
215 /* TX queue descriptor. */
217 struct mlx5_txq_data {
218 uint16_t elts_head; /* Current counter in (*elts)[]. */
219 uint16_t elts_tail; /* Counter of first element awaiting completion. */
220 uint16_t elts_comp; /* elts index since last completion request. */
221 uint16_t elts_s; /* Number of mbuf elements. */
222 uint16_t elts_m; /* Mask for mbuf elements indices. */
223 /* Fields related to elts mbuf storage. */
224 uint16_t wqe_ci; /* Consumer index for work queue. */
225 uint16_t wqe_pi; /* Producer index for work queue. */
226 uint16_t wqe_s; /* Number of WQ elements. */
227 uint16_t wqe_m; /* Mask Number for WQ elements. */
228 uint16_t wqe_comp; /* WQE index since last completion request. */
229 uint16_t wqe_thres; /* WQE threshold to request completion in CQ. */
230 /* WQ related fields. */
231 uint16_t cq_ci; /* Consumer index for completion queue. */
232 uint16_t cq_pi; /* Production index for completion queue. */
233 uint16_t cqe_s; /* Number of CQ elements. */
234 uint16_t cqe_m; /* Mask for CQ indices. */
235 /* CQ related fields. */
236 uint16_t elts_n:4; /* elts[] length (in log2). */
237 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
238 uint16_t wqe_n:4; /* Number of WQ elements (in log2). */
239 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
240 uint16_t tunnel_en:1;
241 /* When set TX offload for tunneled packets are supported. */
242 uint16_t swp_en:1; /* Whether SW parser is enabled. */
243 uint16_t vlan_en:1; /* VLAN insertion in WQE is supported. */
244 uint16_t db_nc:1; /* Doorbell mapped to non-cached region. */
245 uint16_t db_heu:1; /* Doorbell heuristic write barrier. */
246 uint16_t fast_free:1; /* mbuf fast free on Tx is enabled. */
247 uint16_t inlen_send; /* Ordinary send data inline size. */
248 uint16_t inlen_empw; /* eMPW max packet size to inline. */
249 uint16_t inlen_mode; /* Minimal data length to inline. */
250 uint32_t qp_num_8s; /* QP number shifted by 8. */
251 uint64_t offloads; /* Offloads for Tx Queue. */
252 struct mlx5_mr_ctrl mr_ctrl; /* MR control descriptor. */
253 struct mlx5_wqe *wqes; /* Work queue. */
254 struct mlx5_wqe *wqes_end; /* Work queue array limit. */
255 #ifdef RTE_LIBRTE_MLX5_DEBUG
256 uint32_t *fcqs; /* Free completion queue (debug extended). */
258 uint16_t *fcqs; /* Free completion queue. */
260 volatile struct mlx5_cqe *cqes; /* Completion queue. */
261 volatile uint32_t *qp_db; /* Work queue doorbell. */
262 volatile uint32_t *cq_db; /* Completion queue doorbell. */
263 uint16_t port_id; /* Port ID of device. */
264 uint16_t idx; /* Queue index. */
265 uint64_t ts_mask; /* Timestamp flag dynamic mask. */
266 int32_t ts_offset; /* Timestamp field dynamic offset. */
267 struct mlx5_dev_ctx_shared *sh; /* Shared context. */
268 struct mlx5_txq_stats stats; /* TX queue counters. */
270 rte_spinlock_t *uar_lock;
271 /* UAR access lock required for 32bit implementations */
273 struct rte_mbuf *elts[0];
274 /* Storage for queued packets, must be the last field. */
275 } __rte_cache_aligned;
278 MLX5_TXQ_TYPE_STANDARD, /* Standard Tx queue. */
279 MLX5_TXQ_TYPE_HAIRPIN, /* Hairpin Rx queue. */
282 /* TX queue control descriptor. */
283 struct mlx5_txq_ctrl {
284 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
285 uint32_t refcnt; /* Reference counter. */
286 unsigned int socket; /* CPU socket ID for allocations. */
287 enum mlx5_txq_type type; /* The txq ctrl type. */
288 unsigned int max_inline_data; /* Max inline data. */
289 unsigned int max_tso_header; /* Max TSO header size. */
290 struct mlx5_txq_obj *obj; /* Verbs/DevX queue object. */
291 struct mlx5_priv *priv; /* Back pointer to private data. */
292 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
293 void *bf_reg; /* BlueFlame register from Verbs. */
294 uint16_t dump_file_n; /* Number of dump files. */
295 struct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */
296 uint32_t hairpin_status; /* Hairpin binding status. */
297 struct mlx5_txq_data txq; /* Data path structure. */
298 /* Must be the last field in the structure, contains elts[]. */
301 #define MLX5_TX_BFREG(txq) \
302 (MLX5_PROC_PRIV((txq)->port_id)->uar_table[(txq)->idx])
306 extern uint8_t rss_hash_default_key[];
308 unsigned int mlx5_rxq_cqe_num(struct mlx5_rxq_data *rxq_data);
309 int mlx5_mprq_free_mp(struct rte_eth_dev *dev);
310 int mlx5_mprq_alloc_mp(struct rte_eth_dev *dev);
311 int mlx5_rx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
312 int mlx5_rx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
313 int mlx5_rx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
314 int mlx5_rx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
315 int mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
316 unsigned int socket, const struct rte_eth_rxconf *conf,
317 struct rte_mempool *mp);
318 int mlx5_rx_hairpin_queue_setup
319 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
320 const struct rte_eth_hairpin_conf *hairpin_conf);
321 void mlx5_rx_queue_release(void *dpdk_rxq);
322 int mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev);
323 void mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev);
324 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
325 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
326 int mlx5_rxq_obj_verify(struct rte_eth_dev *dev);
327 struct mlx5_rxq_ctrl *mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx,
328 uint16_t desc, unsigned int socket,
329 const struct rte_eth_rxconf *conf,
330 const struct rte_eth_rxseg_split *rx_seg,
332 struct mlx5_rxq_ctrl *mlx5_rxq_hairpin_new
333 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
334 const struct rte_eth_hairpin_conf *hairpin_conf);
335 struct mlx5_rxq_ctrl *mlx5_rxq_get(struct rte_eth_dev *dev, uint16_t idx);
336 int mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx);
337 int mlx5_rxq_verify(struct rte_eth_dev *dev);
338 int rxq_alloc_elts(struct mlx5_rxq_ctrl *rxq_ctrl);
339 int mlx5_ind_table_obj_verify(struct rte_eth_dev *dev);
340 struct mlx5_ind_table_obj *mlx5_ind_table_obj_get(struct rte_eth_dev *dev,
341 const uint16_t *queues,
343 int mlx5_ind_table_obj_release(struct rte_eth_dev *dev,
344 struct mlx5_ind_table_obj *ind_tbl,
346 int mlx5_ind_table_obj_setup(struct rte_eth_dev *dev,
347 struct mlx5_ind_table_obj *ind_tbl);
348 int mlx5_ind_table_obj_modify(struct rte_eth_dev *dev,
349 struct mlx5_ind_table_obj *ind_tbl,
350 uint16_t *queues, const uint32_t queues_n,
352 struct mlx5_cache_entry *mlx5_hrxq_create_cb(struct mlx5_cache_list *list,
353 struct mlx5_cache_entry *entry __rte_unused, void *cb_ctx);
354 int mlx5_hrxq_match_cb(struct mlx5_cache_list *list,
355 struct mlx5_cache_entry *entry,
357 void mlx5_hrxq_remove_cb(struct mlx5_cache_list *list,
358 struct mlx5_cache_entry *entry);
359 uint32_t mlx5_hrxq_get(struct rte_eth_dev *dev,
360 struct mlx5_flow_rss_desc *rss_desc);
361 int mlx5_hrxq_release(struct rte_eth_dev *dev, uint32_t hxrq_idx);
362 uint32_t mlx5_hrxq_verify(struct rte_eth_dev *dev);
365 enum mlx5_rxq_type mlx5_rxq_get_type(struct rte_eth_dev *dev, uint16_t idx);
366 const struct rte_eth_hairpin_conf *mlx5_rxq_get_hairpin_conf
367 (struct rte_eth_dev *dev, uint16_t idx);
368 struct mlx5_hrxq *mlx5_drop_action_create(struct rte_eth_dev *dev);
369 void mlx5_drop_action_destroy(struct rte_eth_dev *dev);
370 uint64_t mlx5_get_rx_port_offloads(void);
371 uint64_t mlx5_get_rx_queue_offloads(struct rte_eth_dev *dev);
372 void mlx5_rxq_timestamp_set(struct rte_eth_dev *dev);
373 int mlx5_hrxq_modify(struct rte_eth_dev *dev, uint32_t hxrq_idx,
374 const uint8_t *rss_key, uint32_t rss_key_len,
375 uint64_t hash_fields,
376 const uint16_t *queues, uint32_t queues_n);
380 int mlx5_tx_queue_start(struct rte_eth_dev *dev, uint16_t queue_id);
381 int mlx5_tx_queue_stop(struct rte_eth_dev *dev, uint16_t queue_id);
382 int mlx5_tx_queue_start_primary(struct rte_eth_dev *dev, uint16_t queue_id);
383 int mlx5_tx_queue_stop_primary(struct rte_eth_dev *dev, uint16_t queue_id);
384 int mlx5_tx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
385 unsigned int socket, const struct rte_eth_txconf *conf);
386 int mlx5_tx_hairpin_queue_setup
387 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
388 const struct rte_eth_hairpin_conf *hairpin_conf);
389 void mlx5_tx_queue_release(void *dpdk_txq);
390 void txq_uar_init(struct mlx5_txq_ctrl *txq_ctrl);
391 int mlx5_tx_uar_init_secondary(struct rte_eth_dev *dev, int fd);
392 void mlx5_tx_uar_uninit_secondary(struct rte_eth_dev *dev);
393 int mlx5_txq_obj_verify(struct rte_eth_dev *dev);
394 struct mlx5_txq_ctrl *mlx5_txq_new(struct rte_eth_dev *dev, uint16_t idx,
395 uint16_t desc, unsigned int socket,
396 const struct rte_eth_txconf *conf);
397 struct mlx5_txq_ctrl *mlx5_txq_hairpin_new
398 (struct rte_eth_dev *dev, uint16_t idx, uint16_t desc,
399 const struct rte_eth_hairpin_conf *hairpin_conf);
400 struct mlx5_txq_ctrl *mlx5_txq_get(struct rte_eth_dev *dev, uint16_t idx);
401 int mlx5_txq_release(struct rte_eth_dev *dev, uint16_t idx);
402 int mlx5_txq_releasable(struct rte_eth_dev *dev, uint16_t idx);
403 int mlx5_txq_verify(struct rte_eth_dev *dev);
404 void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl);
405 void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl);
406 uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev);
407 void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev);
411 extern uint32_t mlx5_ptype_table[];
412 extern uint8_t mlx5_cksum_table[];
413 extern uint8_t mlx5_swp_types_table[];
415 void mlx5_set_ptype_table(void);
416 void mlx5_set_cksum_table(void);
417 void mlx5_set_swp_types_table(void);
418 uint16_t mlx5_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
419 void mlx5_rxq_initialize(struct mlx5_rxq_data *rxq);
420 __rte_noinline int mlx5_rx_err_handle(struct mlx5_rxq_data *rxq, uint8_t vec);
421 void mlx5_mprq_buf_free_cb(void *addr, void *opaque);
422 void mlx5_mprq_buf_free(struct mlx5_mprq_buf *buf);
423 uint16_t mlx5_rx_burst_mprq(void *dpdk_rxq, struct rte_mbuf **pkts,
425 uint16_t removed_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts,
427 uint16_t removed_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts,
429 int mlx5_rx_descriptor_status(void *rx_queue, uint16_t offset);
430 int mlx5_tx_descriptor_status(void *tx_queue, uint16_t offset);
431 uint32_t mlx5_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id);
432 void mlx5_dump_debug_information(const char *path, const char *title,
433 const void *buf, unsigned int len);
434 int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
435 const struct mlx5_mp_arg_queue_state_modify *sm);
436 void mlx5_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
437 struct rte_eth_rxq_info *qinfo);
438 void mlx5_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
439 struct rte_eth_txq_info *qinfo);
440 int mlx5_rx_burst_mode_get(struct rte_eth_dev *dev, uint16_t rx_queue_id,
441 struct rte_eth_burst_mode *mode);
442 int mlx5_tx_burst_mode_get(struct rte_eth_dev *dev, uint16_t tx_queue_id,
443 struct rte_eth_burst_mode *mode);
445 /* Vectorized version of mlx5_rxtx.c */
446 int mlx5_rxq_check_vec_support(struct mlx5_rxq_data *rxq_data);
447 int mlx5_check_vec_rx_support(struct rte_eth_dev *dev);
448 uint16_t mlx5_rx_burst_vec(void *dpdk_txq, struct rte_mbuf **pkts,
450 uint16_t mlx5_rx_burst_mprq_vec(void *dpdk_txq, struct rte_mbuf **pkts,
455 void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
456 uint32_t mlx5_rx_addr2mr_bh(struct mlx5_rxq_data *rxq, uintptr_t addr);
457 uint32_t mlx5_tx_mb2mr_bh(struct mlx5_txq_data *txq, struct rte_mbuf *mb);
458 uint32_t mlx5_tx_update_ext_mp(struct mlx5_txq_data *txq, uintptr_t addr,
459 struct rte_mempool *mp);
460 int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
462 int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
466 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
467 * 64bit architectures.
470 * value to write in CPU endian format.
472 * Address to write to.
474 * Address of the lock to use for that UAR access.
476 static __rte_always_inline void
477 __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
478 rte_spinlock_t *lock __rte_unused)
481 *(uint64_t *)addr = val;
482 #else /* !RTE_ARCH_64 */
483 rte_spinlock_lock(lock);
484 *(uint32_t *)addr = val;
486 *((uint32_t *)addr + 1) = val >> 32;
487 rte_spinlock_unlock(lock);
492 * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
493 * 64bit architectures while guaranteeing the order of execution with the
494 * code being executed.
497 * value to write in CPU endian format.
499 * Address to write to.
501 * Address of the lock to use for that UAR access.
503 static __rte_always_inline void
504 __mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
507 __mlx5_uar_write64_relaxed(val, addr, lock);
510 /* Assist macros, used instead of directly calling the functions they wrap. */
512 #define mlx5_uar_write64_relaxed(val, dst, lock) \
513 __mlx5_uar_write64_relaxed(val, dst, NULL)
514 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, NULL)
516 #define mlx5_uar_write64_relaxed(val, dst, lock) \
517 __mlx5_uar_write64_relaxed(val, dst, lock)
518 #define mlx5_uar_write64(val, dst, lock) __mlx5_uar_write64(val, dst, lock)
522 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
523 * cloned mbuf is allocated is returned instead.
529 * Memory pool where data is located for given mbuf.
531 static inline struct rte_mempool *
532 mlx5_mb2mp(struct rte_mbuf *buf)
534 if (unlikely(RTE_MBUF_CLONED(buf)))
535 return rte_mbuf_from_indirect(buf)->pool;
540 * Query LKey from a packet buffer for Rx. No need to flush local caches for Rx
541 * as mempool is pre-configured and static.
544 * Pointer to Rx queue structure.
549 * Searched LKey on success, UINT32_MAX on no match.
551 static __rte_always_inline uint32_t
552 mlx5_rx_addr2mr(struct mlx5_rxq_data *rxq, uintptr_t addr)
554 struct mlx5_mr_ctrl *mr_ctrl = &rxq->mr_ctrl;
557 /* Linear search on MR cache array. */
558 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
559 MLX5_MR_CACHE_N, addr);
560 if (likely(lkey != UINT32_MAX))
562 /* Take slower bottom-half (Binary Search) on miss. */
563 return mlx5_rx_addr2mr_bh(rxq, addr);
566 #define mlx5_rx_mb2mr(rxq, mb) mlx5_rx_addr2mr(rxq, (uintptr_t)((mb)->buf_addr))
569 * Query LKey from a packet buffer for Tx. If not found, add the mempool.
572 * Pointer to Tx queue structure.
577 * Searched LKey on success, UINT32_MAX on no match.
579 static __rte_always_inline uint32_t
580 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
582 struct mlx5_mr_ctrl *mr_ctrl = &txq->mr_ctrl;
583 uintptr_t addr = (uintptr_t)mb->buf_addr;
586 /* Check generation bit to see if there's any change on existing MRs. */
587 if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
588 mlx5_mr_flush_local_cache(mr_ctrl);
589 /* Linear search on MR cache array. */
590 lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
591 MLX5_MR_CACHE_N, addr);
592 if (likely(lkey != UINT32_MAX))
594 /* Take slower bottom-half on miss. */
595 return mlx5_tx_mb2mr_bh(txq, mb);
599 * Ring TX queue doorbell and flush the update if requested.
602 * Pointer to TX queue structure.
604 * Pointer to the last WQE posted in the NIC.
606 * Request for write memory barrier after BlueFlame update.
608 static __rte_always_inline void
609 mlx5_tx_dbrec_cond_wmb(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe,
612 uint64_t *dst = MLX5_TX_BFREG(txq);
613 volatile uint64_t *src = ((volatile uint64_t *)wqe);
616 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
617 /* Ensure ordering between DB record and BF copy. */
619 mlx5_uar_write64_relaxed(*src, dst, txq->uar_lock);
625 * Ring TX queue doorbell and flush the update by write memory barrier.
628 * Pointer to TX queue structure.
630 * Pointer to the last WQE posted in the NIC.
632 static __rte_always_inline void
633 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
635 mlx5_tx_dbrec_cond_wmb(txq, wqe, 1);
639 * Convert timestamp from HW format to linear counter
640 * from Packet Pacing Clock Queue CQE timestamp format.
643 * Pointer to the device shared context. Might be needed
644 * to convert according current device configuration.
646 * Timestamp from CQE to convert.
650 static __rte_always_inline uint64_t
651 mlx5_txpp_convert_rx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t ts)
654 return (ts & UINT32_MAX) + (ts >> 32) * NS_PER_S;
658 * Convert timestamp from mbuf format to linear counter
659 * of Clock Queue completions (24 bits)
662 * Pointer to the device shared context to fetch Tx
663 * packet pacing timestamp and parameters.
665 * Timestamp from mbuf to convert.
667 * positive or zero value - completion ID to wait
668 * negative value - conversion error
670 static __rte_always_inline int32_t
671 mlx5_txpp_convert_tx_ts(struct mlx5_dev_ctx_shared *sh, uint64_t mts)
678 * Read atomically two uint64_t fields and compare lsb bits.
679 * It there is no match - the timestamp was updated in
680 * the service thread, data should be re-read.
682 rte_compiler_barrier();
683 ci = __atomic_load_n(&sh->txpp.ts.ci_ts, __ATOMIC_RELAXED);
684 ts = __atomic_load_n(&sh->txpp.ts.ts, __ATOMIC_RELAXED);
685 rte_compiler_barrier();
686 if (!((ts ^ ci) << (64 - MLX5_CQ_INDEX_WIDTH)))
689 /* Perform the skew correction, positive value to send earlier. */
690 mts -= sh->txpp.skew;
692 if (unlikely(mts >= UINT64_MAX / 2)) {
693 /* We have negative integer, mts is in the past. */
694 __atomic_fetch_add(&sh->txpp.err_ts_past,
695 1, __ATOMIC_RELAXED);
698 tick = sh->txpp.tick;
700 /* Convert delta to completions, round up. */
701 mts = (mts + tick - 1) / tick;
702 if (unlikely(mts >= (1 << MLX5_CQ_INDEX_WIDTH) / 2 - 1)) {
703 /* We have mts is too distant future. */
704 __atomic_fetch_add(&sh->txpp.err_ts_future,
705 1, __ATOMIC_RELAXED);
708 mts <<= 64 - MLX5_CQ_INDEX_WIDTH;
710 ci >>= 64 - MLX5_CQ_INDEX_WIDTH;
715 * Set timestamp in mbuf dynamic field.
718 * Structure to write into.
720 * Dynamic field offset in mbuf structure.
724 static __rte_always_inline void
725 mlx5_timestamp_set(struct rte_mbuf *mbuf, int offset,
726 rte_mbuf_timestamp_t timestamp)
728 *RTE_MBUF_DYNFIELD(mbuf, offset, rte_mbuf_timestamp_t *) = timestamp;
732 * Replace MPRQ buffer.
735 * Pointer to Rx queue structure.
737 * RQ index to replace.
739 static __rte_always_inline void
740 mprq_buf_replace(struct mlx5_rxq_data *rxq, uint16_t rq_idx)
742 const uint32_t strd_n = 1 << rxq->strd_num_n;
743 struct mlx5_mprq_buf *rep = rxq->mprq_repl;
744 volatile struct mlx5_wqe_data_seg *wqe =
745 &((volatile struct mlx5_wqe_mprq *)rxq->wqes)[rq_idx].dseg;
746 struct mlx5_mprq_buf *buf = (*rxq->mprq_bufs)[rq_idx];
749 if (__atomic_load_n(&buf->refcnt, __ATOMIC_RELAXED) > 1) {
750 MLX5_ASSERT(rep != NULL);
751 /* Replace MPRQ buf. */
752 (*rxq->mprq_bufs)[rq_idx] = rep;
754 addr = mlx5_mprq_buf_addr(rep, strd_n);
755 wqe->addr = rte_cpu_to_be_64((uintptr_t)addr);
756 /* If there's only one MR, no need to replace LKey in WQE. */
757 if (unlikely(mlx5_mr_btree_len(&rxq->mr_ctrl.cache_bh) > 1))
758 wqe->lkey = mlx5_rx_addr2mr(rxq, (uintptr_t)addr);
759 /* Stash a mbuf for next replacement. */
760 if (likely(!rte_mempool_get(rxq->mprq_mp, (void **)&rep)))
761 rxq->mprq_repl = rep;
763 rxq->mprq_repl = NULL;
764 /* Release the old buffer. */
765 mlx5_mprq_buf_free(buf);
766 } else if (unlikely(rxq->mprq_repl == NULL)) {
767 struct mlx5_mprq_buf *rep;
770 * Currently, the MPRQ mempool is out of buffer
771 * and doing memcpy regardless of the size of Rx
772 * packet. Retry allocation to get back to
775 if (!rte_mempool_get(rxq->mprq_mp, (void **)&rep))
776 rxq->mprq_repl = rep;
781 * Attach or copy MPRQ buffer content to a packet.
784 * Pointer to Rx queue structure.
786 * Pointer to a packet to fill.
790 * Pointer to a MPRQ buffer to take the data from.
792 * Stride index to start from.
794 * Number of strides to consume.
796 static __rte_always_inline enum mlx5_rqx_code
797 mprq_buf_to_pkt(struct mlx5_rxq_data *rxq, struct rte_mbuf *pkt, uint32_t len,
798 struct mlx5_mprq_buf *buf, uint16_t strd_idx, uint16_t strd_cnt)
800 const uint32_t strd_n = 1 << rxq->strd_num_n;
801 const uint16_t strd_sz = 1 << rxq->strd_sz_n;
802 const uint16_t strd_shift =
803 MLX5_MPRQ_STRIDE_SHIFT_BYTE * rxq->strd_shift_en;
804 const int32_t hdrm_overlap =
805 len + RTE_PKTMBUF_HEADROOM - strd_cnt * strd_sz;
806 const uint32_t offset = strd_idx * strd_sz + strd_shift;
807 void *addr = RTE_PTR_ADD(mlx5_mprq_buf_addr(buf, strd_n), offset);
810 * Memcpy packets to the target mbuf if:
811 * - The size of packet is smaller than mprq_max_memcpy_len.
812 * - Out of buffer in the Mempool for Multi-Packet RQ.
813 * - The packet's stride overlaps a headroom and scatter is off.
815 if (len <= rxq->mprq_max_memcpy_len ||
816 rxq->mprq_repl == NULL ||
817 (hdrm_overlap > 0 && !rxq->strd_scatter_en)) {
819 (uint32_t)(pkt->buf_len - RTE_PKTMBUF_HEADROOM))) {
820 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
823 } else if (rxq->strd_scatter_en) {
824 struct rte_mbuf *prev = pkt;
825 uint32_t seg_len = RTE_MIN(len, (uint32_t)
826 (pkt->buf_len - RTE_PKTMBUF_HEADROOM));
827 uint32_t rem_len = len - seg_len;
829 rte_memcpy(rte_pktmbuf_mtod(pkt, void *),
831 DATA_LEN(pkt) = seg_len;
833 struct rte_mbuf *next =
834 rte_pktmbuf_alloc(rxq->mp);
836 if (unlikely(next == NULL))
837 return MLX5_RXQ_CODE_NOMBUF;
839 SET_DATA_OFF(next, 0);
840 addr = RTE_PTR_ADD(addr, seg_len);
841 seg_len = RTE_MIN(rem_len, (uint32_t)
842 (next->buf_len - RTE_PKTMBUF_HEADROOM));
844 (rte_pktmbuf_mtod(next, void *),
846 DATA_LEN(next) = seg_len;
852 return MLX5_RXQ_CODE_DROPPED;
856 struct rte_mbuf_ext_shared_info *shinfo;
857 uint16_t buf_len = strd_cnt * strd_sz;
860 /* Increment the refcnt of the whole chunk. */
861 __atomic_add_fetch(&buf->refcnt, 1, __ATOMIC_RELAXED);
862 MLX5_ASSERT(__atomic_load_n(&buf->refcnt,
863 __ATOMIC_RELAXED) <= strd_n + 1);
864 buf_addr = RTE_PTR_SUB(addr, RTE_PKTMBUF_HEADROOM);
866 * MLX5 device doesn't use iova but it is necessary in a
867 * case where the Rx packet is transmitted via a
870 buf_iova = rte_mempool_virt2iova(buf) +
871 RTE_PTR_DIFF(buf_addr, buf);
872 shinfo = &buf->shinfos[strd_idx];
873 rte_mbuf_ext_refcnt_set(shinfo, 1);
875 * EXT_ATTACHED_MBUF will be set to pkt->ol_flags when
876 * attaching the stride to mbuf and more offload flags
877 * will be added below by calling rxq_cq_to_mbuf().
878 * Other fields will be overwritten.
880 rte_pktmbuf_attach_extbuf(pkt, buf_addr, buf_iova,
882 /* Set mbuf head-room. */
883 SET_DATA_OFF(pkt, RTE_PKTMBUF_HEADROOM);
884 MLX5_ASSERT(pkt->ol_flags == EXT_ATTACHED_MBUF);
885 MLX5_ASSERT(rte_pktmbuf_tailroom(pkt) >=
886 len - (hdrm_overlap > 0 ? hdrm_overlap : 0));
889 * Copy the last fragment of a packet (up to headroom
890 * size bytes) in case there is a stride overlap with
891 * a next packet's headroom. Allocate a separate mbuf
892 * to store this fragment and link it. Scatter is on.
894 if (hdrm_overlap > 0) {
895 MLX5_ASSERT(rxq->strd_scatter_en);
896 struct rte_mbuf *seg =
897 rte_pktmbuf_alloc(rxq->mp);
899 if (unlikely(seg == NULL))
900 return MLX5_RXQ_CODE_NOMBUF;
901 SET_DATA_OFF(seg, 0);
902 rte_memcpy(rte_pktmbuf_mtod(seg, void *),
903 RTE_PTR_ADD(addr, len - hdrm_overlap),
905 DATA_LEN(seg) = hdrm_overlap;
906 DATA_LEN(pkt) = len - hdrm_overlap;
911 return MLX5_RXQ_CODE_EXIT;
915 * Check whether Multi-Packet RQ can be enabled for the device.
918 * Pointer to Ethernet device.
921 * 1 if supported, negative errno value if not.
923 static __rte_always_inline int
924 mlx5_check_mprq_support(struct rte_eth_dev *dev)
926 struct mlx5_priv *priv = dev->data->dev_private;
928 if (priv->config.mprq.enabled &&
929 priv->rxqs_n >= priv->config.mprq.min_rxqs_num)
935 * Check whether Multi-Packet RQ is enabled for the Rx queue.
938 * Pointer to receive queue structure.
941 * 0 if disabled, otherwise enabled.
943 static __rte_always_inline int
944 mlx5_rxq_mprq_enabled(struct mlx5_rxq_data *rxq)
946 return rxq->strd_num_n > 0;
950 * Check whether Multi-Packet RQ is enabled for the device.
953 * Pointer to Ethernet device.
956 * 0 if disabled, otherwise enabled.
958 static __rte_always_inline int
959 mlx5_mprq_enabled(struct rte_eth_dev *dev)
961 struct mlx5_priv *priv = dev->data->dev_private;
966 if (mlx5_check_mprq_support(dev) < 0)
968 /* All the configured queues should be enabled. */
969 for (i = 0; i < priv->rxqs_n; ++i) {
970 struct mlx5_rxq_data *rxq = (*priv->rxqs)[i];
971 struct mlx5_rxq_ctrl *rxq_ctrl = container_of
972 (rxq, struct mlx5_rxq_ctrl, rxq);
974 if (rxq == NULL || rxq_ctrl->type != MLX5_RXQ_TYPE_STANDARD)
977 if (mlx5_rxq_mprq_enabled(rxq))
980 /* Multi-Packet RQ can't be partially configured. */
981 MLX5_ASSERT(n == 0 || n == n_ibv);
984 #endif /* RTE_PMD_MLX5_RXTX_H_ */