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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
39 #include <sys/queue.h>
42 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
44 #pragma GCC diagnostic ignored "-Wpedantic"
46 #include <infiniband/verbs.h>
47 #include <infiniband/mlx5dv.h>
49 #pragma GCC diagnostic error "-Wpedantic"
53 #include <rte_mempool.h>
54 #include <rte_common.h>
55 #include <rte_hexdump.h>
56 #include <rte_atomic.h>
58 #include "mlx5_utils.h"
60 #include "mlx5_autoconf.h"
61 #include "mlx5_defs.h"
64 struct mlx5_rxq_stats {
65 unsigned int idx; /**< Mapping index. */
66 #ifdef MLX5_PMD_SOFT_COUNTERS
67 uint64_t ipackets; /**< Total of successfully received packets. */
68 uint64_t ibytes; /**< Total of successfully received bytes. */
70 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
71 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
74 struct mlx5_txq_stats {
75 unsigned int idx; /**< Mapping index. */
76 #ifdef MLX5_PMD_SOFT_COUNTERS
77 uint64_t opackets; /**< Total of successfully sent packets. */
78 uint64_t obytes; /**< Total of successfully sent bytes. */
80 uint64_t oerrors; /**< Total number of failed transmitted packets. */
85 /* Memory region queue object. */
87 LIST_ENTRY(mlx5_mr) next; /**< Pointer to the next element. */
88 rte_atomic32_t refcnt; /*<< Reference counter. */
89 uint32_t lkey; /*<< rte_cpu_to_be_32(mr->lkey) */
90 uintptr_t start; /* Start address of MR */
91 uintptr_t end; /* End address of MR */
92 struct ibv_mr *mr; /*<< Memory Region. */
93 struct rte_mempool *mp; /*<< Memory Pool. */
96 /* Compressed CQE context. */
98 uint16_t ai; /* Array index. */
99 uint16_t ca; /* Current array index. */
100 uint16_t na; /* Next array index. */
101 uint16_t cq_ci; /* The next CQE. */
102 uint32_t cqe_cnt; /* Number of CQEs. */
105 /* RX queue descriptor. */
106 struct mlx5_rxq_data {
107 unsigned int csum:1; /* Enable checksum offloading. */
108 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
109 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
110 unsigned int crc_present:1; /* CRC must be subtracted. */
111 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
112 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
113 unsigned int elts_n:4; /* Log 2 of Mbufs. */
114 unsigned int rss_hash:1; /* RSS hash result is enabled. */
115 unsigned int mark:1; /* Marked flow available on the queue. */
116 unsigned int pending_err:1; /* CQE error needs to be handled. */
117 unsigned int :15; /* Remaining bits. */
118 volatile uint32_t *rq_db;
119 volatile uint32_t *cq_db;
124 volatile struct mlx5_wqe_data_seg(*wqes)[];
125 volatile struct mlx5_cqe(*cqes)[];
126 struct rxq_zip zip; /* Compressed context. */
127 struct rte_mbuf *(*elts)[];
128 struct rte_mempool *mp;
129 struct mlx5_rxq_stats stats;
130 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
131 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
132 void *cq_uar; /* CQ user access region. */
133 uint32_t cqn; /* CQ number. */
134 uint8_t cq_arm_sn; /* CQ arm seq number. */
135 } __rte_cache_aligned;
137 /* Verbs Rx queue elements. */
138 struct mlx5_rxq_ibv {
139 LIST_ENTRY(mlx5_rxq_ibv) next; /* Pointer to the next element. */
140 rte_atomic32_t refcnt; /* Reference counter. */
141 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */
142 struct ibv_cq *cq; /* Completion Queue. */
143 struct ibv_wq *wq; /* Work Queue. */
144 struct ibv_comp_channel *channel;
145 struct mlx5_mr *mr; /* Memory Region (for mp). */
148 /* RX queue control descriptor. */
149 struct mlx5_rxq_ctrl {
150 struct priv *priv; /* Back pointer to private data. */
151 struct mlx5_rxq_ibv *ibv; /* Verbs elements. */
152 struct mlx5_rxq_data rxq; /* Data path structure. */
153 unsigned int socket; /* CPU socket ID for allocations. */
154 unsigned int irq:1; /* Whether IRQ is enabled. */
157 /* Hash RX queue types. */
168 /* Flow structure with Ethernet specification. It is packed to prevent padding
169 * between attr and spec as this layout is expected by libibverbs. */
170 struct flow_attr_spec_eth {
171 struct ibv_flow_attr attr;
172 struct ibv_flow_spec_eth spec;
173 } __attribute__((packed));
175 /* Define a struct flow_attr_spec_eth object as an array of at least
176 * "size" bytes. Room after the first index is normally used to store
177 * extra flow specifications. */
178 #define FLOW_ATTR_SPEC_ETH(name, size) \
179 struct flow_attr_spec_eth name \
180 [((size) / sizeof(struct flow_attr_spec_eth)) + \
181 !!((size) % sizeof(struct flow_attr_spec_eth))]
183 /* Initialization data for hash RX queue. */
184 struct hash_rxq_init {
185 uint64_t hash_fields; /* Fields that participate in the hash. */
186 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
187 unsigned int flow_priority; /* Flow priority to use. */
190 enum ibv_flow_spec_type type;
193 struct ibv_flow_spec_tcp_udp tcp_udp;
194 struct ibv_flow_spec_ipv4 ipv4;
195 struct ibv_flow_spec_ipv6 ipv6;
196 struct ibv_flow_spec_eth eth;
197 } flow_spec; /* Flow specification template. */
198 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
201 /* Initialization data for indirection table. */
202 struct ind_table_init {
203 unsigned int max_size; /* Maximum number of WQs. */
204 /* Hash RX queues using this table. */
205 unsigned int hash_types;
206 unsigned int hash_types_n;
209 /* Initialization data for special flows. */
210 struct special_flow_init {
211 uint8_t dst_mac_val[6];
212 uint8_t dst_mac_mask[6];
213 unsigned int hash_types;
214 unsigned int per_vlan:1;
217 enum hash_rxq_flow_type {
218 HASH_RXQ_FLOW_TYPE_PROMISC,
219 HASH_RXQ_FLOW_TYPE_ALLMULTI,
220 HASH_RXQ_FLOW_TYPE_BROADCAST,
221 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
222 HASH_RXQ_FLOW_TYPE_MAC,
226 static inline const char *
227 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
230 case HASH_RXQ_FLOW_TYPE_PROMISC:
231 return "promiscuous";
232 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
233 return "allmulticast";
234 case HASH_RXQ_FLOW_TYPE_BROADCAST:
236 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
237 return "IPv6 multicast";
238 case HASH_RXQ_FLOW_TYPE_MAC:
246 struct priv *priv; /* Back pointer to private data. */
247 struct ibv_qp *qp; /* Hash RX QP. */
248 enum hash_rxq_type type; /* Hash RX queue type. */
249 /* MAC flow steering rules, one per VLAN ID. */
250 struct ibv_flow *mac_flow
251 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
252 struct ibv_flow *special_flow
253 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
256 /* TX queue descriptor. */
258 struct mlx5_txq_data {
259 uint16_t elts_head; /* Current counter in (*elts)[]. */
260 uint16_t elts_tail; /* Counter of first element awaiting completion. */
261 uint16_t elts_comp; /* Counter since last completion request. */
262 uint16_t mpw_comp; /* WQ index since last completion request. */
263 uint16_t cq_ci; /* Consumer index for completion queue. */
264 uint16_t cq_pi; /* Producer index for completion queue. */
265 uint16_t wqe_ci; /* Consumer index for work queue. */
266 uint16_t wqe_pi; /* Producer index for work queue. */
267 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
268 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
269 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
270 uint16_t inline_en:1; /* When set inline is enabled. */
271 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
272 uint16_t tunnel_en:1;
273 /* When set TX offload for tunneled packets are supported. */
274 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
275 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
276 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
277 uint16_t mr_cache_idx; /* Index of last hit entry. */
278 uint32_t qp_num_8s; /* QP number shifted by 8. */
279 uint32_t flags; /* Flags for Tx Queue. */
280 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
281 volatile void *wqes; /* Work queue (use volatile to write into). */
282 volatile uint32_t *qp_db; /* Work queue doorbell. */
283 volatile uint32_t *cq_db; /* Completion queue doorbell. */
284 volatile void *bf_reg; /* Blueflame register. */
285 struct mlx5_mr *mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MR translation table. */
286 struct rte_mbuf *(*elts)[]; /* TX elements. */
287 struct mlx5_txq_stats stats; /* TX queue counters. */
288 } __rte_cache_aligned;
290 /* Verbs Rx queue elements. */
291 struct mlx5_txq_ibv {
292 LIST_ENTRY(mlx5_txq_ibv) next; /* Pointer to the next element. */
293 rte_atomic32_t refcnt; /* Reference counter. */
294 struct ibv_cq *cq; /* Completion Queue. */
295 struct ibv_qp *qp; /* Queue Pair. */
298 /* TX queue control descriptor. */
299 struct mlx5_txq_ctrl {
300 LIST_ENTRY(mlx5_txq_ctrl) next; /* Pointer to the next element. */
301 rte_atomic32_t refcnt; /* Reference counter. */
302 struct priv *priv; /* Back pointer to private data. */
303 unsigned int socket; /* CPU socket ID for allocations. */
304 unsigned int max_inline_data; /* Max inline data. */
305 unsigned int max_tso_header; /* Max TSO header size. */
306 struct mlx5_txq_ibv *ibv; /* Verbs queue object. */
307 struct mlx5_txq_data txq; /* Data path structure. */
308 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
313 extern const struct hash_rxq_init hash_rxq_init[];
314 extern const unsigned int hash_rxq_init_n;
316 extern uint8_t rss_hash_default_key[];
317 extern const size_t rss_hash_default_key_len;
319 size_t priv_flow_attr(struct priv *, struct ibv_flow_attr *,
320 size_t, enum hash_rxq_type);
321 int priv_create_hash_rxqs(struct priv *);
322 void priv_destroy_hash_rxqs(struct priv *);
323 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
324 int priv_rehash_flows(struct priv *);
325 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *);
326 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
327 const struct rte_eth_rxconf *, struct rte_mempool *);
328 void mlx5_rx_queue_release(void *);
329 int priv_rx_intr_vec_enable(struct priv *priv);
330 void priv_rx_intr_vec_disable(struct priv *priv);
331 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
332 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
333 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_new(struct priv *, uint16_t);
334 struct mlx5_rxq_ibv *mlx5_priv_rxq_ibv_get(struct priv *, uint16_t);
335 int mlx5_priv_rxq_ibv_release(struct priv *, struct mlx5_rxq_ibv *);
336 int mlx5_priv_rxq_ibv_releasable(struct priv *, struct mlx5_rxq_ibv *);
337 int mlx5_priv_rxq_ibv_verify(struct priv *);
341 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
342 const struct rte_eth_txconf *);
343 void mlx5_tx_queue_release(void *);
344 int priv_tx_uar_remap(struct priv *priv, int fd);
345 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_new(struct priv *, uint16_t);
346 struct mlx5_txq_ibv *mlx5_priv_txq_ibv_get(struct priv *, uint16_t);
347 int mlx5_priv_txq_ibv_release(struct priv *, struct mlx5_txq_ibv *);
348 int mlx5_priv_txq_ibv_releasable(struct priv *, struct mlx5_txq_ibv *);
349 int mlx5_priv_txq_ibv_verify(struct priv *);
350 struct mlx5_txq_ctrl *mlx5_priv_txq_new(struct priv *, uint16_t,
351 uint16_t, unsigned int,
352 const struct rte_eth_txconf *);
353 struct mlx5_txq_ctrl *mlx5_priv_txq_get(struct priv *, uint16_t);
354 int mlx5_priv_txq_release(struct priv *, uint16_t);
355 int mlx5_priv_txq_releasable(struct priv *, uint16_t);
356 int mlx5_priv_txq_verify(struct priv *);
357 void txq_alloc_elts(struct mlx5_txq_ctrl *);
361 extern uint32_t mlx5_ptype_table[];
363 void mlx5_set_ptype_table(void);
364 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
365 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
366 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
367 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
368 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
369 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
370 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
371 int mlx5_rx_descriptor_status(void *, uint16_t);
372 int mlx5_tx_descriptor_status(void *, uint16_t);
374 /* Vectorized version of mlx5_rxtx.c */
375 int priv_check_raw_vec_tx_support(struct priv *);
376 int priv_check_vec_tx_support(struct priv *);
377 int rxq_check_vec_support(struct mlx5_rxq_data *);
378 int priv_check_vec_rx_support(struct priv *);
379 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
380 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
381 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
385 void mlx5_mp2mr_iter(struct rte_mempool *, void *);
386 struct mlx5_mr *priv_txq_mp2mr_reg(struct priv *priv, struct mlx5_txq_data *,
387 struct rte_mempool *, unsigned int);
388 struct mlx5_mr *mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
393 * Verify or set magic value in CQE.
402 check_cqe_seen(volatile struct mlx5_cqe *cqe)
404 static const uint8_t magic[] = "seen";
405 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
409 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
410 if (!ret || (*buf)[i] != magic[i]) {
412 (*buf)[i] = magic[i];
419 * Check whether CQE is valid.
424 * Size of completion queue.
429 * 0 on success, 1 on failure.
431 static __rte_always_inline int
432 check_cqe(volatile struct mlx5_cqe *cqe,
433 unsigned int cqes_n, const uint16_t ci)
435 uint16_t idx = ci & cqes_n;
436 uint8_t op_own = cqe->op_own;
437 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
438 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
440 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
441 return 1; /* No CQE. */
443 if ((op_code == MLX5_CQE_RESP_ERR) ||
444 (op_code == MLX5_CQE_REQ_ERR)) {
445 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
446 uint8_t syndrome = err_cqe->syndrome;
448 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
449 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
451 if (!check_cqe_seen(cqe)) {
452 ERROR("unexpected CQE error %u (0x%02x)"
454 op_code, op_code, syndrome);
455 rte_hexdump(stderr, "MLX5 Error CQE:",
456 (const void *)((uintptr_t)err_cqe),
460 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
461 (op_code != MLX5_CQE_REQ)) {
462 if (!check_cqe_seen(cqe)) {
463 ERROR("unexpected CQE opcode %u (0x%02x)",
465 rte_hexdump(stderr, "MLX5 CQE:",
466 (const void *)((uintptr_t)cqe),
476 * Return the address of the WQE.
479 * Pointer to TX queue structure.
481 * WQE consumer index.
486 static inline uintptr_t *
487 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
489 ci &= ((1 << txq->wqe_n) - 1);
490 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
494 * Manage TX completions.
496 * When sending a burst, mlx5_tx_burst() posts several WRs.
499 * Pointer to TX queue structure.
501 static __rte_always_inline void
502 mlx5_tx_complete(struct mlx5_txq_data *txq)
504 const uint16_t elts_n = 1 << txq->elts_n;
505 const uint16_t elts_m = elts_n - 1;
506 const unsigned int cqe_n = 1 << txq->cqe_n;
507 const unsigned int cqe_cnt = cqe_n - 1;
508 uint16_t elts_free = txq->elts_tail;
510 uint16_t cq_ci = txq->cq_ci;
511 volatile struct mlx5_cqe *cqe = NULL;
512 volatile struct mlx5_wqe_ctrl *ctrl;
513 struct rte_mbuf *m, *free[elts_n];
514 struct rte_mempool *pool = NULL;
515 unsigned int blk_n = 0;
517 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
518 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
521 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
522 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
523 if (!check_cqe_seen(cqe)) {
524 ERROR("unexpected error CQE, TX stopped");
525 rte_hexdump(stderr, "MLX5 TXQ:",
526 (const void *)((uintptr_t)txq->wqes),
534 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
535 ctrl = (volatile struct mlx5_wqe_ctrl *)
536 tx_mlx5_wqe(txq, txq->wqe_pi);
537 elts_tail = ctrl->ctrl3;
538 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
540 while (elts_free != elts_tail) {
541 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
542 if (likely(m != NULL)) {
543 if (likely(m->pool == pool)) {
546 if (likely(pool != NULL))
547 rte_mempool_put_bulk(pool,
557 rte_mempool_put_bulk(pool, (void *)free, blk_n);
559 elts_free = txq->elts_tail;
561 while (elts_free != elts_tail) {
562 memset(&(*txq->elts)[elts_free & elts_m],
564 sizeof((*txq->elts)[elts_free & elts_m]));
569 txq->elts_tail = elts_tail;
570 /* Update the consumer index. */
572 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
576 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
577 * the cloned mbuf is allocated is returned instead.
583 * Memory pool where data is located for given mbuf.
585 static struct rte_mempool *
586 mlx5_tx_mb2mp(struct rte_mbuf *buf)
588 if (unlikely(RTE_MBUF_INDIRECT(buf)))
589 return rte_mbuf_from_indirect(buf)->pool;
594 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
595 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
596 * remove an entry first.
599 * Pointer to TX queue structure.
601 * Memory Pool for which a Memory Region lkey must be returned.
604 * mr->lkey on success, (uint32_t)-1 on failure.
606 static __rte_always_inline uint32_t
607 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
609 uint16_t i = txq->mr_cache_idx;
610 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
613 assert(i < RTE_DIM(txq->mp2mr));
614 if (likely(txq->mp2mr[i]->start <= addr && txq->mp2mr[i]->end >= addr))
615 return txq->mp2mr[i]->lkey;
616 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
617 if (unlikely(txq->mp2mr[i]->mr == NULL)) {
618 /* Unknown MP, add a new MR for it. */
621 if (txq->mp2mr[i]->start <= addr &&
622 txq->mp2mr[i]->end >= addr) {
623 assert(txq->mp2mr[i]->lkey != (uint32_t)-1);
624 assert(rte_cpu_to_be_32(txq->mp2mr[i]->mr->lkey) ==
625 txq->mp2mr[i]->lkey);
626 txq->mr_cache_idx = i;
627 return txq->mp2mr[i]->lkey;
630 txq->mr_cache_idx = 0;
631 mr = mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
633 * Request the reference to use in this queue, the original one is
634 * kept by the control plane.
637 rte_atomic32_inc(&mr->refcnt);
644 * Ring TX queue doorbell.
647 * Pointer to TX queue structure.
649 * Pointer to the last WQE posted in the NIC.
651 static __rte_always_inline void
652 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
654 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
655 volatile uint64_t *src = ((volatile uint64_t *)wqe);
658 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
659 /* Ensure ordering between DB record and BF copy. */
664 #endif /* RTE_PMD_MLX5_RXTX_H_ */