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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-pedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
58 #pragma GCC diagnostic error "-pedantic"
61 #include "mlx5_utils.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
67 struct mlx5_rxq_stats {
68 unsigned int idx; /**< Mapping index. */
69 #ifdef MLX5_PMD_SOFT_COUNTERS
70 uint64_t ipackets; /**< Total of successfully received packets. */
71 uint64_t ibytes; /**< Total of successfully received bytes. */
73 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
74 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
77 struct mlx5_txq_stats {
78 unsigned int idx; /**< Mapping index. */
79 #ifdef MLX5_PMD_SOFT_COUNTERS
80 uint64_t opackets; /**< Total of successfully sent packets. */
81 uint64_t obytes; /**< Total of successfully sent bytes. */
83 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
86 /* Flow director queue structure. */
88 struct ibv_qp *qp; /* Associated RX QP. */
89 struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
94 /* RX queue descriptor. */
96 unsigned int csum:1; /* Enable checksum offloading. */
97 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
98 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
99 unsigned int crc_present:1; /* CRC must be subtracted. */
104 volatile struct mlx5_wqe_data_seg(*wqes)[];
105 volatile struct mlx5_cqe(*cqes)[];
106 volatile uint32_t *rq_db;
107 volatile uint32_t *cq_db;
108 struct rte_mbuf *(*elts)[];
109 struct rte_mempool *mp;
110 struct mlx5_rxq_stats stats;
111 } __rte_cache_aligned;
113 /* RX queue control descriptor. */
115 struct priv *priv; /* Back pointer to private data. */
116 struct ibv_cq *cq; /* Completion Queue. */
117 struct ibv_exp_wq *wq; /* Work Queue. */
118 struct ibv_exp_res_domain *rd; /* Resource Domain. */
119 struct fdir_queue fdir_queue; /* Flow director queue. */
120 struct ibv_mr *mr; /* Memory Region (for mp). */
121 struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
122 struct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */
123 unsigned int socket; /* CPU socket ID for allocations. */
124 struct rxq rxq; /* Data path structure. */
127 /* Hash RX queue types. */
138 /* Flow structure with Ethernet specification. It is packed to prevent padding
139 * between attr and spec as this layout is expected by libibverbs. */
140 struct flow_attr_spec_eth {
141 struct ibv_exp_flow_attr attr;
142 struct ibv_exp_flow_spec_eth spec;
143 } __attribute__((packed));
145 /* Define a struct flow_attr_spec_eth object as an array of at least
146 * "size" bytes. Room after the first index is normally used to store
147 * extra flow specifications. */
148 #define FLOW_ATTR_SPEC_ETH(name, size) \
149 struct flow_attr_spec_eth name \
150 [((size) / sizeof(struct flow_attr_spec_eth)) + \
151 !!((size) % sizeof(struct flow_attr_spec_eth))]
153 /* Initialization data for hash RX queue. */
154 struct hash_rxq_init {
155 uint64_t hash_fields; /* Fields that participate in the hash. */
156 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
157 unsigned int flow_priority; /* Flow priority to use. */
160 enum ibv_exp_flow_spec_type type;
163 struct ibv_exp_flow_spec_tcp_udp tcp_udp;
164 struct ibv_exp_flow_spec_ipv4 ipv4;
165 struct ibv_exp_flow_spec_ipv6 ipv6;
166 struct ibv_exp_flow_spec_eth eth;
167 } flow_spec; /* Flow specification template. */
168 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
171 /* Initialization data for indirection table. */
172 struct ind_table_init {
173 unsigned int max_size; /* Maximum number of WQs. */
174 /* Hash RX queues using this table. */
175 unsigned int hash_types;
176 unsigned int hash_types_n;
179 /* Initialization data for special flows. */
180 struct special_flow_init {
181 uint8_t dst_mac_val[6];
182 uint8_t dst_mac_mask[6];
183 unsigned int hash_types;
184 unsigned int per_vlan:1;
187 enum hash_rxq_flow_type {
188 HASH_RXQ_FLOW_TYPE_PROMISC,
189 HASH_RXQ_FLOW_TYPE_ALLMULTI,
190 HASH_RXQ_FLOW_TYPE_BROADCAST,
191 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
192 HASH_RXQ_FLOW_TYPE_MAC,
196 static inline const char *
197 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
200 case HASH_RXQ_FLOW_TYPE_PROMISC:
201 return "promiscuous";
202 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
203 return "allmulticast";
204 case HASH_RXQ_FLOW_TYPE_BROADCAST:
206 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
207 return "IPv6 multicast";
208 case HASH_RXQ_FLOW_TYPE_MAC:
216 struct priv *priv; /* Back pointer to private data. */
217 struct ibv_qp *qp; /* Hash RX QP. */
218 enum hash_rxq_type type; /* Hash RX queue type. */
219 /* MAC flow steering rules, one per VLAN ID. */
220 struct ibv_exp_flow *mac_flow
221 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
222 struct ibv_exp_flow *special_flow
223 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
226 /* TX queue descriptor. */
228 uint16_t elts_head; /* Current index in (*elts)[]. */
229 uint16_t elts_tail; /* First element awaiting completion. */
230 uint16_t elts_comp_cd_init; /* Initial value for countdown. */
231 uint16_t elts_comp; /* Elements before asking a completion. */
232 uint16_t elts_n; /* (*elts)[] length. */
233 uint16_t cq_ci; /* Consumer index for completion queue. */
234 uint16_t cqe_n; /* Number of CQ elements. */
235 uint16_t wqe_ci; /* Consumer index for work queue. */
236 uint16_t wqe_n; /* Number of WQ elements. */
237 uint16_t bf_offset; /* Blueflame offset. */
238 uint16_t bf_buf_size; /* Blueflame size. */
239 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
240 volatile union mlx5_wqe (*wqes)[]; /* Work queue. */
241 volatile uint32_t *qp_db; /* Work queue doorbell. */
242 volatile uint32_t *cq_db; /* Completion queue doorbell. */
243 volatile void *bf_reg; /* Blueflame register. */
245 const struct rte_mempool *mp; /* Cached Memory Pool. */
246 struct ibv_mr *mr; /* Memory Region (for mp). */
247 uint32_t lkey; /* htonl(mr->lkey) */
248 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
249 struct rte_mbuf *(*elts)[]; /* TX elements. */
250 struct mlx5_txq_stats stats; /* TX queue counters. */
251 uint32_t qp_num_8s; /* QP number shifted by 8. */
252 } __rte_cache_aligned;
254 /* TX queue control descriptor. */
256 struct priv *priv; /* Back pointer to private data. */
257 struct ibv_cq *cq; /* Completion Queue. */
258 struct ibv_qp *qp; /* Queue Pair. */
259 struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
260 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
261 struct ibv_exp_res_domain *rd; /* Resource Domain. */
262 unsigned int socket; /* CPU socket ID for allocations. */
263 struct txq txq; /* Data path structure. */
268 extern const struct hash_rxq_init hash_rxq_init[];
269 extern const unsigned int hash_rxq_init_n;
271 extern uint8_t rss_hash_default_key[];
272 extern const size_t rss_hash_default_key_len;
274 size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
275 size_t, enum hash_rxq_type);
276 int priv_create_hash_rxqs(struct priv *);
277 void priv_destroy_hash_rxqs(struct priv *);
278 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
279 int priv_rehash_flows(struct priv *);
280 void rxq_cleanup(struct rxq_ctrl *);
281 int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
282 int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
283 unsigned int, const struct rte_eth_rxconf *,
284 struct rte_mempool *);
285 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
286 const struct rte_eth_rxconf *, struct rte_mempool *);
287 void mlx5_rx_queue_release(void *);
288 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
292 void txq_cleanup(struct txq_ctrl *);
293 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
294 unsigned int, const struct rte_eth_txconf *);
295 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
296 const struct rte_eth_txconf *);
297 void mlx5_tx_queue_release(void *);
298 uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
302 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
303 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
304 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
305 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
309 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
310 void txq_mp2mr_iter(struct rte_mempool *, void *);
311 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
313 #endif /* RTE_PMD_MLX5_RXTX_H_ */