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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-Wpedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5dv.h>
48 #pragma GCC diagnostic error "-Wpedantic"
52 #include <rte_mempool.h>
53 #include <rte_common.h>
54 #include <rte_hexdump.h>
56 #include "mlx5_utils.h"
58 #include "mlx5_autoconf.h"
59 #include "mlx5_defs.h"
62 struct mlx5_rxq_stats {
63 unsigned int idx; /**< Mapping index. */
64 #ifdef MLX5_PMD_SOFT_COUNTERS
65 uint64_t ipackets; /**< Total of successfully received packets. */
66 uint64_t ibytes; /**< Total of successfully received bytes. */
68 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
69 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
72 struct mlx5_txq_stats {
73 unsigned int idx; /**< Mapping index. */
74 #ifdef MLX5_PMD_SOFT_COUNTERS
75 uint64_t opackets; /**< Total of successfully sent packets. */
76 uint64_t obytes; /**< Total of successfully sent bytes. */
78 uint64_t oerrors; /**< Total number of failed transmitted packets. */
83 /* Compressed CQE context. */
85 uint16_t ai; /* Array index. */
86 uint16_t ca; /* Current array index. */
87 uint16_t na; /* Next array index. */
88 uint16_t cq_ci; /* The next CQE. */
89 uint32_t cqe_cnt; /* Number of CQEs. */
92 /* RX queue descriptor. */
93 struct mlx5_rxq_data {
94 unsigned int csum:1; /* Enable checksum offloading. */
95 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
96 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
97 unsigned int crc_present:1; /* CRC must be subtracted. */
98 unsigned int sges_n:2; /* Log 2 of SGEs (max buffers per packet). */
99 unsigned int cqe_n:4; /* Log 2 of CQ elements. */
100 unsigned int elts_n:4; /* Log 2 of Mbufs. */
101 unsigned int rss_hash:1; /* RSS hash result is enabled. */
102 unsigned int mark:1; /* Marked flow available on the queue. */
103 unsigned int pending_err:1; /* CQE error needs to be handled. */
104 unsigned int :15; /* Remaining bits. */
105 volatile uint32_t *rq_db;
106 volatile uint32_t *cq_db;
111 volatile struct mlx5_wqe_data_seg(*wqes)[];
112 volatile struct mlx5_cqe(*cqes)[];
113 struct rxq_zip zip; /* Compressed context. */
114 struct rte_mbuf *(*elts)[];
115 struct rte_mempool *mp;
116 struct mlx5_rxq_stats stats;
117 uint64_t mbuf_initializer; /* Default rearm_data for vectorized Rx. */
118 struct rte_mbuf fake_mbuf; /* elts padding for vectorized Rx. */
119 void *cq_uar; /* CQ user access region. */
120 uint32_t cqn; /* CQ number. */
121 uint8_t cq_arm_sn; /* CQ arm seq number. */
122 } __rte_cache_aligned;
124 /* RX queue control descriptor. */
125 struct mlx5_rxq_ctrl {
126 struct priv *priv; /* Back pointer to private data. */
127 struct ibv_cq *cq; /* Completion Queue. */
128 struct ibv_wq *wq; /* Work Queue. */
129 struct ibv_mr *mr; /* Memory Region (for mp). */
130 struct ibv_comp_channel *channel;
131 unsigned int socket; /* CPU socket ID for allocations. */
132 struct mlx5_rxq_data rxq; /* Data path structure. */
135 /* Hash RX queue types. */
146 /* Flow structure with Ethernet specification. It is packed to prevent padding
147 * between attr and spec as this layout is expected by libibverbs. */
148 struct flow_attr_spec_eth {
149 struct ibv_flow_attr attr;
150 struct ibv_flow_spec_eth spec;
151 } __attribute__((packed));
153 /* Define a struct flow_attr_spec_eth object as an array of at least
154 * "size" bytes. Room after the first index is normally used to store
155 * extra flow specifications. */
156 #define FLOW_ATTR_SPEC_ETH(name, size) \
157 struct flow_attr_spec_eth name \
158 [((size) / sizeof(struct flow_attr_spec_eth)) + \
159 !!((size) % sizeof(struct flow_attr_spec_eth))]
161 /* Initialization data for hash RX queue. */
162 struct hash_rxq_init {
163 uint64_t hash_fields; /* Fields that participate in the hash. */
164 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
165 unsigned int flow_priority; /* Flow priority to use. */
168 enum ibv_flow_spec_type type;
171 struct ibv_flow_spec_tcp_udp tcp_udp;
172 struct ibv_flow_spec_ipv4 ipv4;
173 struct ibv_flow_spec_ipv6 ipv6;
174 struct ibv_flow_spec_eth eth;
175 } flow_spec; /* Flow specification template. */
176 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
179 /* Initialization data for indirection table. */
180 struct ind_table_init {
181 unsigned int max_size; /* Maximum number of WQs. */
182 /* Hash RX queues using this table. */
183 unsigned int hash_types;
184 unsigned int hash_types_n;
187 /* Initialization data for special flows. */
188 struct special_flow_init {
189 uint8_t dst_mac_val[6];
190 uint8_t dst_mac_mask[6];
191 unsigned int hash_types;
192 unsigned int per_vlan:1;
195 enum hash_rxq_flow_type {
196 HASH_RXQ_FLOW_TYPE_PROMISC,
197 HASH_RXQ_FLOW_TYPE_ALLMULTI,
198 HASH_RXQ_FLOW_TYPE_BROADCAST,
199 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
200 HASH_RXQ_FLOW_TYPE_MAC,
204 static inline const char *
205 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
208 case HASH_RXQ_FLOW_TYPE_PROMISC:
209 return "promiscuous";
210 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
211 return "allmulticast";
212 case HASH_RXQ_FLOW_TYPE_BROADCAST:
214 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
215 return "IPv6 multicast";
216 case HASH_RXQ_FLOW_TYPE_MAC:
224 struct priv *priv; /* Back pointer to private data. */
225 struct ibv_qp *qp; /* Hash RX QP. */
226 enum hash_rxq_type type; /* Hash RX queue type. */
227 /* MAC flow steering rules, one per VLAN ID. */
228 struct ibv_flow *mac_flow
229 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
230 struct ibv_flow *special_flow
231 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
234 /* TX queue descriptor. */
236 struct mlx5_txq_data {
237 uint16_t elts_head; /* Current counter in (*elts)[]. */
238 uint16_t elts_tail; /* Counter of first element awaiting completion. */
239 uint16_t elts_comp; /* Counter since last completion request. */
240 uint16_t mpw_comp; /* WQ index since last completion request. */
241 uint16_t cq_ci; /* Consumer index for completion queue. */
242 uint16_t cq_pi; /* Producer index for completion queue. */
243 uint16_t wqe_ci; /* Consumer index for work queue. */
244 uint16_t wqe_pi; /* Producer index for work queue. */
245 uint16_t elts_n:4; /* (*elts)[] length (in log2). */
246 uint16_t cqe_n:4; /* Number of CQ elements (in log2). */
247 uint16_t wqe_n:4; /* Number of of WQ elements (in log2). */
248 uint16_t inline_en:1; /* When set inline is enabled. */
249 uint16_t tso_en:1; /* When set hardware TSO is enabled. */
250 uint16_t tunnel_en:1;
251 /* When set TX offload for tunneled packets are supported. */
252 uint16_t mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */
253 uint16_t max_inline; /* Multiple of RTE_CACHE_LINE_SIZE to inline. */
254 uint16_t inline_max_packet_sz; /* Max packet size for inlining. */
255 uint32_t qp_num_8s; /* QP number shifted by 8. */
256 uint32_t flags; /* Flags for Tx Queue. */
257 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
258 volatile void *wqes; /* Work queue (use volatile to write into). */
259 volatile uint32_t *qp_db; /* Work queue doorbell. */
260 volatile uint32_t *cq_db; /* Completion queue doorbell. */
261 volatile void *bf_reg; /* Blueflame register. */
263 uintptr_t start; /* Start address of MR */
264 uintptr_t end; /* End address of MR */
265 struct ibv_mr *mr; /* Memory Region (for mp). */
266 uint32_t lkey; /* rte_cpu_to_be_32(mr->lkey) */
267 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
268 uint16_t mr_cache_idx; /* Index of last hit entry. */
269 struct rte_mbuf *(*elts)[]; /* TX elements. */
270 struct mlx5_txq_stats stats; /* TX queue counters. */
271 } __rte_cache_aligned;
273 /* TX queue control descriptor. */
274 struct mlx5_txq_ctrl {
275 struct priv *priv; /* Back pointer to private data. */
276 struct ibv_cq *cq; /* Completion Queue. */
277 struct ibv_qp *qp; /* Queue Pair. */
278 unsigned int socket; /* CPU socket ID for allocations. */
279 struct mlx5_txq_data txq; /* Data path structure. */
280 off_t uar_mmap_offset; /* UAR mmap offset for non-primary process. */
285 extern const struct hash_rxq_init hash_rxq_init[];
286 extern const unsigned int hash_rxq_init_n;
288 extern uint8_t rss_hash_default_key[];
289 extern const size_t rss_hash_default_key_len;
291 size_t priv_flow_attr(struct priv *, struct ibv_flow_attr *,
292 size_t, enum hash_rxq_type);
293 int priv_create_hash_rxqs(struct priv *);
294 void priv_destroy_hash_rxqs(struct priv *);
295 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
296 int priv_rehash_flows(struct priv *);
297 void mlx5_rxq_cleanup(struct mlx5_rxq_ctrl *);
298 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
299 const struct rte_eth_rxconf *, struct rte_mempool *);
300 void mlx5_rx_queue_release(void *);
301 int priv_rx_intr_vec_enable(struct priv *priv);
302 void priv_rx_intr_vec_disable(struct priv *priv);
303 int mlx5_rx_intr_enable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
304 int mlx5_rx_intr_disable(struct rte_eth_dev *dev, uint16_t rx_queue_id);
308 void mlx5_txq_cleanup(struct mlx5_txq_ctrl *);
309 int mlx5_txq_ctrl_setup(struct rte_eth_dev *, struct mlx5_txq_ctrl *, uint16_t,
310 unsigned int, const struct rte_eth_txconf *);
311 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
312 const struct rte_eth_txconf *);
313 void mlx5_tx_queue_release(void *);
314 int priv_tx_uar_remap(struct priv *priv, int fd);
318 extern uint32_t mlx5_ptype_table[];
320 void mlx5_set_ptype_table(void);
321 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
322 uint16_t mlx5_tx_burst_mpw(void *, struct rte_mbuf **, uint16_t);
323 uint16_t mlx5_tx_burst_mpw_inline(void *, struct rte_mbuf **, uint16_t);
324 uint16_t mlx5_tx_burst_empw(void *, struct rte_mbuf **, uint16_t);
325 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
326 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
327 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
328 int mlx5_rx_descriptor_status(void *, uint16_t);
329 int mlx5_tx_descriptor_status(void *, uint16_t);
331 /* Vectorized version of mlx5_rxtx.c */
332 int priv_check_raw_vec_tx_support(struct priv *);
333 int priv_check_vec_tx_support(struct priv *);
334 int rxq_check_vec_support(struct mlx5_rxq_data *);
335 int priv_check_vec_rx_support(struct priv *);
336 uint16_t mlx5_tx_burst_raw_vec(void *, struct rte_mbuf **, uint16_t);
337 uint16_t mlx5_tx_burst_vec(void *, struct rte_mbuf **, uint16_t);
338 uint16_t mlx5_rx_burst_vec(void *, struct rte_mbuf **, uint16_t);
342 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
343 void mlx5_txq_mp2mr_iter(struct rte_mempool *, void *);
344 uint32_t mlx5_txq_mp2mr_reg(struct mlx5_txq_data *, struct rte_mempool *,
349 * Verify or set magic value in CQE.
358 check_cqe_seen(volatile struct mlx5_cqe *cqe)
360 static const uint8_t magic[] = "seen";
361 volatile uint8_t (*buf)[sizeof(cqe->rsvd0)] = &cqe->rsvd0;
365 for (i = 0; i < sizeof(magic) && i < sizeof(*buf); ++i)
366 if (!ret || (*buf)[i] != magic[i]) {
368 (*buf)[i] = magic[i];
375 * Check whether CQE is valid.
380 * Size of completion queue.
385 * 0 on success, 1 on failure.
387 static __rte_always_inline int
388 check_cqe(volatile struct mlx5_cqe *cqe,
389 unsigned int cqes_n, const uint16_t ci)
391 uint16_t idx = ci & cqes_n;
392 uint8_t op_own = cqe->op_own;
393 uint8_t op_owner = MLX5_CQE_OWNER(op_own);
394 uint8_t op_code = MLX5_CQE_OPCODE(op_own);
396 if (unlikely((op_owner != (!!(idx))) || (op_code == MLX5_CQE_INVALID)))
397 return 1; /* No CQE. */
399 if ((op_code == MLX5_CQE_RESP_ERR) ||
400 (op_code == MLX5_CQE_REQ_ERR)) {
401 volatile struct mlx5_err_cqe *err_cqe = (volatile void *)cqe;
402 uint8_t syndrome = err_cqe->syndrome;
404 if ((syndrome == MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR) ||
405 (syndrome == MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR))
407 if (!check_cqe_seen(cqe)) {
408 ERROR("unexpected CQE error %u (0x%02x)"
410 op_code, op_code, syndrome);
411 rte_hexdump(stderr, "MLX5 Error CQE:",
412 (const void *)((uintptr_t)err_cqe),
416 } else if ((op_code != MLX5_CQE_RESP_SEND) &&
417 (op_code != MLX5_CQE_REQ)) {
418 if (!check_cqe_seen(cqe)) {
419 ERROR("unexpected CQE opcode %u (0x%02x)",
421 rte_hexdump(stderr, "MLX5 CQE:",
422 (const void *)((uintptr_t)cqe),
432 * Return the address of the WQE.
435 * Pointer to TX queue structure.
437 * WQE consumer index.
442 static inline uintptr_t *
443 tx_mlx5_wqe(struct mlx5_txq_data *txq, uint16_t ci)
445 ci &= ((1 << txq->wqe_n) - 1);
446 return (uintptr_t *)((uintptr_t)txq->wqes + ci * MLX5_WQE_SIZE);
450 * Manage TX completions.
452 * When sending a burst, mlx5_tx_burst() posts several WRs.
455 * Pointer to TX queue structure.
457 static __rte_always_inline void
458 mlx5_tx_complete(struct mlx5_txq_data *txq)
460 const uint16_t elts_n = 1 << txq->elts_n;
461 const uint16_t elts_m = elts_n - 1;
462 const unsigned int cqe_n = 1 << txq->cqe_n;
463 const unsigned int cqe_cnt = cqe_n - 1;
464 uint16_t elts_free = txq->elts_tail;
466 uint16_t cq_ci = txq->cq_ci;
467 volatile struct mlx5_cqe *cqe = NULL;
468 volatile struct mlx5_wqe_ctrl *ctrl;
469 struct rte_mbuf *m, *free[elts_n];
470 struct rte_mempool *pool = NULL;
471 unsigned int blk_n = 0;
473 cqe = &(*txq->cqes)[cq_ci & cqe_cnt];
474 if (unlikely(check_cqe(cqe, cqe_n, cq_ci)))
477 if ((MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_RESP_ERR) ||
478 (MLX5_CQE_OPCODE(cqe->op_own) == MLX5_CQE_REQ_ERR)) {
479 if (!check_cqe_seen(cqe)) {
480 ERROR("unexpected error CQE, TX stopped");
481 rte_hexdump(stderr, "MLX5 TXQ:",
482 (const void *)((uintptr_t)txq->wqes),
490 txq->wqe_pi = rte_be_to_cpu_16(cqe->wqe_counter);
491 ctrl = (volatile struct mlx5_wqe_ctrl *)
492 tx_mlx5_wqe(txq, txq->wqe_pi);
493 elts_tail = ctrl->ctrl3;
494 assert((elts_tail & elts_m) < (1 << txq->wqe_n));
496 while (elts_free != elts_tail) {
497 m = rte_pktmbuf_prefree_seg((*txq->elts)[elts_free++ & elts_m]);
498 if (likely(m != NULL)) {
499 if (likely(m->pool == pool)) {
502 if (likely(pool != NULL))
503 rte_mempool_put_bulk(pool,
513 rte_mempool_put_bulk(pool, (void *)free, blk_n);
515 elts_free = txq->elts_tail;
517 while (elts_free != elts_tail) {
518 memset(&(*txq->elts)[elts_free & elts_m],
520 sizeof((*txq->elts)[elts_free & elts_m]));
525 txq->elts_tail = elts_tail;
526 /* Update the consumer index. */
528 *txq->cq_db = rte_cpu_to_be_32(cq_ci);
532 * Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which
533 * the cloned mbuf is allocated is returned instead.
539 * Memory pool where data is located for given mbuf.
541 static struct rte_mempool *
542 mlx5_tx_mb2mp(struct rte_mbuf *buf)
544 if (unlikely(RTE_MBUF_INDIRECT(buf)))
545 return rte_mbuf_from_indirect(buf)->pool;
550 * Get Memory Region (MR) <-> rte_mbuf association from txq->mp2mr[].
551 * Add MP to txq->mp2mr[] if it's not registered yet. If mp2mr[] is full,
552 * remove an entry first.
555 * Pointer to TX queue structure.
557 * Memory Pool for which a Memory Region lkey must be returned.
560 * mr->lkey on success, (uint32_t)-1 on failure.
562 static __rte_always_inline uint32_t
563 mlx5_tx_mb2mr(struct mlx5_txq_data *txq, struct rte_mbuf *mb)
565 uint16_t i = txq->mr_cache_idx;
566 uintptr_t addr = rte_pktmbuf_mtod(mb, uintptr_t);
568 assert(i < RTE_DIM(txq->mp2mr));
569 if (likely(txq->mp2mr[i].start <= addr && txq->mp2mr[i].end >= addr))
570 return txq->mp2mr[i].lkey;
571 for (i = 0; (i != RTE_DIM(txq->mp2mr)); ++i) {
572 if (unlikely(txq->mp2mr[i].mr == NULL)) {
573 /* Unknown MP, add a new MR for it. */
576 if (txq->mp2mr[i].start <= addr &&
577 txq->mp2mr[i].end >= addr) {
578 assert(txq->mp2mr[i].lkey != (uint32_t)-1);
579 assert(rte_cpu_to_be_32(txq->mp2mr[i].mr->lkey) ==
581 txq->mr_cache_idx = i;
582 return txq->mp2mr[i].lkey;
585 txq->mr_cache_idx = 0;
586 return mlx5_txq_mp2mr_reg(txq, mlx5_tx_mb2mp(mb), i);
590 * Ring TX queue doorbell.
593 * Pointer to TX queue structure.
595 * Pointer to the last WQE posted in the NIC.
597 static __rte_always_inline void
598 mlx5_tx_dbrec(struct mlx5_txq_data *txq, volatile struct mlx5_wqe *wqe)
600 uint64_t *dst = (uint64_t *)((uintptr_t)txq->bf_reg);
601 volatile uint64_t *src = ((volatile uint64_t *)wqe);
604 *txq->qp_db = rte_cpu_to_be_32(txq->wqe_ci);
605 /* Ensure ordering between DB record and BF copy. */
610 #endif /* RTE_PMD_MLX5_RXTX_H_ */