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34 #ifndef RTE_PMD_MLX5_RXTX_H_
35 #define RTE_PMD_MLX5_RXTX_H_
41 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
43 #pragma GCC diagnostic ignored "-pedantic"
45 #include <infiniband/verbs.h>
46 #include <infiniband/mlx5_hw.h>
48 #pragma GCC diagnostic error "-pedantic"
51 /* DPDK headers don't like -pedantic. */
53 #pragma GCC diagnostic ignored "-pedantic"
56 #include <rte_mempool.h>
58 #pragma GCC diagnostic error "-pedantic"
61 #include "mlx5_utils.h"
63 #include "mlx5_autoconf.h"
64 #include "mlx5_defs.h"
67 struct mlx5_rxq_stats {
68 unsigned int idx; /**< Mapping index. */
69 #ifdef MLX5_PMD_SOFT_COUNTERS
70 uint64_t ipackets; /**< Total of successfully received packets. */
71 uint64_t ibytes; /**< Total of successfully received bytes. */
73 uint64_t idropped; /**< Total of packets dropped when RX ring full. */
74 uint64_t rx_nombuf; /**< Total of RX mbuf allocation failures. */
77 struct mlx5_txq_stats {
78 unsigned int idx; /**< Mapping index. */
79 #ifdef MLX5_PMD_SOFT_COUNTERS
80 uint64_t opackets; /**< Total of successfully sent packets. */
81 uint64_t obytes; /**< Total of successfully sent bytes. */
83 uint64_t odropped; /**< Total of packets not sent when TX ring full. */
86 /* Flow director queue structure. */
88 struct ibv_qp *qp; /* Associated RX QP. */
89 struct ibv_exp_rwq_ind_table *ind_table; /* Indirection table. */
94 /* Compressed CQE context. */
96 uint16_t ai; /* Array index. */
97 uint16_t ca; /* Current array index. */
98 uint16_t na; /* Next array index. */
99 uint16_t cq_ci; /* The next CQE. */
100 uint32_t cqe_cnt; /* Number of CQEs. */
103 /* RX queue descriptor. */
105 unsigned int csum:1; /* Enable checksum offloading. */
106 unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
107 unsigned int vlan_strip:1; /* Enable VLAN stripping. */
108 unsigned int crc_present:1; /* CRC must be subtracted. */
112 uint16_t cqe_n; /* Number of CQ elements. */
114 volatile struct mlx5_wqe_data_seg(*wqes)[];
115 volatile struct mlx5_cqe(*cqes)[];
116 struct rxq_zip zip; /* Compressed context. */
117 volatile uint32_t *rq_db;
118 volatile uint32_t *cq_db;
119 struct rte_mbuf *(*elts)[];
120 struct rte_mempool *mp;
121 struct mlx5_rxq_stats stats;
122 } __rte_cache_aligned;
124 /* RX queue control descriptor. */
126 struct priv *priv; /* Back pointer to private data. */
127 struct ibv_cq *cq; /* Completion Queue. */
128 struct ibv_exp_wq *wq; /* Work Queue. */
129 struct ibv_exp_res_domain *rd; /* Resource Domain. */
130 struct fdir_queue fdir_queue; /* Flow director queue. */
131 struct ibv_mr *mr; /* Memory Region (for mp). */
132 struct ibv_exp_wq_family *if_wq; /* WQ burst interface. */
133 struct ibv_exp_cq_family_v1 *if_cq; /* CQ interface. */
134 unsigned int socket; /* CPU socket ID for allocations. */
135 struct rxq rxq; /* Data path structure. */
138 /* Hash RX queue types. */
149 /* Flow structure with Ethernet specification. It is packed to prevent padding
150 * between attr and spec as this layout is expected by libibverbs. */
151 struct flow_attr_spec_eth {
152 struct ibv_exp_flow_attr attr;
153 struct ibv_exp_flow_spec_eth spec;
154 } __attribute__((packed));
156 /* Define a struct flow_attr_spec_eth object as an array of at least
157 * "size" bytes. Room after the first index is normally used to store
158 * extra flow specifications. */
159 #define FLOW_ATTR_SPEC_ETH(name, size) \
160 struct flow_attr_spec_eth name \
161 [((size) / sizeof(struct flow_attr_spec_eth)) + \
162 !!((size) % sizeof(struct flow_attr_spec_eth))]
164 /* Initialization data for hash RX queue. */
165 struct hash_rxq_init {
166 uint64_t hash_fields; /* Fields that participate in the hash. */
167 uint64_t dpdk_rss_hf; /* Matching DPDK RSS hash fields. */
168 unsigned int flow_priority; /* Flow priority to use. */
171 enum ibv_exp_flow_spec_type type;
174 struct ibv_exp_flow_spec_tcp_udp tcp_udp;
175 struct ibv_exp_flow_spec_ipv4 ipv4;
176 struct ibv_exp_flow_spec_ipv6 ipv6;
177 struct ibv_exp_flow_spec_eth eth;
178 } flow_spec; /* Flow specification template. */
179 const struct hash_rxq_init *underlayer; /* Pointer to underlayer. */
182 /* Initialization data for indirection table. */
183 struct ind_table_init {
184 unsigned int max_size; /* Maximum number of WQs. */
185 /* Hash RX queues using this table. */
186 unsigned int hash_types;
187 unsigned int hash_types_n;
190 /* Initialization data for special flows. */
191 struct special_flow_init {
192 uint8_t dst_mac_val[6];
193 uint8_t dst_mac_mask[6];
194 unsigned int hash_types;
195 unsigned int per_vlan:1;
198 enum hash_rxq_flow_type {
199 HASH_RXQ_FLOW_TYPE_PROMISC,
200 HASH_RXQ_FLOW_TYPE_ALLMULTI,
201 HASH_RXQ_FLOW_TYPE_BROADCAST,
202 HASH_RXQ_FLOW_TYPE_IPV6MULTI,
203 HASH_RXQ_FLOW_TYPE_MAC,
207 static inline const char *
208 hash_rxq_flow_type_str(enum hash_rxq_flow_type flow_type)
211 case HASH_RXQ_FLOW_TYPE_PROMISC:
212 return "promiscuous";
213 case HASH_RXQ_FLOW_TYPE_ALLMULTI:
214 return "allmulticast";
215 case HASH_RXQ_FLOW_TYPE_BROADCAST:
217 case HASH_RXQ_FLOW_TYPE_IPV6MULTI:
218 return "IPv6 multicast";
219 case HASH_RXQ_FLOW_TYPE_MAC:
227 struct priv *priv; /* Back pointer to private data. */
228 struct ibv_qp *qp; /* Hash RX QP. */
229 enum hash_rxq_type type; /* Hash RX queue type. */
230 /* MAC flow steering rules, one per VLAN ID. */
231 struct ibv_exp_flow *mac_flow
232 [MLX5_MAX_MAC_ADDRESSES][MLX5_MAX_VLAN_IDS];
233 struct ibv_exp_flow *special_flow
234 [MLX5_MAX_SPECIAL_FLOWS][MLX5_MAX_VLAN_IDS];
237 /* TX queue descriptor. */
239 uint16_t elts_head; /* Current index in (*elts)[]. */
240 uint16_t elts_tail; /* First element awaiting completion. */
241 uint16_t elts_comp_cd_init; /* Initial value for countdown. */
242 uint16_t elts_comp; /* Elements before asking a completion. */
243 uint16_t elts_n; /* (*elts)[] length. */
244 uint16_t cq_ci; /* Consumer index for completion queue. */
245 uint16_t cqe_n; /* Number of CQ elements. */
246 uint16_t wqe_ci; /* Consumer index for work queue. */
247 uint16_t wqe_n; /* Number of WQ elements. */
248 uint16_t bf_offset; /* Blueflame offset. */
249 uint16_t bf_buf_size; /* Blueflame size. */
250 volatile struct mlx5_cqe (*cqes)[]; /* Completion queue. */
251 volatile union mlx5_wqe (*wqes)[]; /* Work queue. */
252 volatile uint32_t *qp_db; /* Work queue doorbell. */
253 volatile uint32_t *cq_db; /* Completion queue doorbell. */
254 volatile void *bf_reg; /* Blueflame register. */
256 const struct rte_mempool *mp; /* Cached Memory Pool. */
257 struct ibv_mr *mr; /* Memory Region (for mp). */
258 uint32_t lkey; /* htonl(mr->lkey) */
259 } mp2mr[MLX5_PMD_TX_MP_CACHE]; /* MP to MR translation table. */
260 struct rte_mbuf *(*elts)[]; /* TX elements. */
261 struct mlx5_txq_stats stats; /* TX queue counters. */
262 uint32_t qp_num_8s; /* QP number shifted by 8. */
263 } __rte_cache_aligned;
265 /* TX queue control descriptor. */
267 struct priv *priv; /* Back pointer to private data. */
268 struct ibv_cq *cq; /* Completion Queue. */
269 struct ibv_qp *qp; /* Queue Pair. */
270 struct ibv_exp_qp_burst_family *if_qp; /* QP burst interface. */
271 struct ibv_exp_cq_family *if_cq; /* CQ interface. */
272 struct ibv_exp_res_domain *rd; /* Resource Domain. */
273 unsigned int socket; /* CPU socket ID for allocations. */
274 struct txq txq; /* Data path structure. */
279 extern const struct hash_rxq_init hash_rxq_init[];
280 extern const unsigned int hash_rxq_init_n;
282 extern uint8_t rss_hash_default_key[];
283 extern const size_t rss_hash_default_key_len;
285 size_t priv_flow_attr(struct priv *, struct ibv_exp_flow_attr *,
286 size_t, enum hash_rxq_type);
287 int priv_create_hash_rxqs(struct priv *);
288 void priv_destroy_hash_rxqs(struct priv *);
289 int priv_allow_flow_type(struct priv *, enum hash_rxq_flow_type);
290 int priv_rehash_flows(struct priv *);
291 void rxq_cleanup(struct rxq_ctrl *);
292 int rxq_rehash(struct rte_eth_dev *, struct rxq_ctrl *);
293 int rxq_ctrl_setup(struct rte_eth_dev *, struct rxq_ctrl *, uint16_t,
294 unsigned int, const struct rte_eth_rxconf *,
295 struct rte_mempool *);
296 int mlx5_rx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
297 const struct rte_eth_rxconf *, struct rte_mempool *);
298 void mlx5_rx_queue_release(void *);
299 uint16_t mlx5_rx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
303 void txq_cleanup(struct txq_ctrl *);
304 int txq_ctrl_setup(struct rte_eth_dev *, struct txq_ctrl *, uint16_t,
305 unsigned int, const struct rte_eth_txconf *);
306 int mlx5_tx_queue_setup(struct rte_eth_dev *, uint16_t, uint16_t, unsigned int,
307 const struct rte_eth_txconf *);
308 void mlx5_tx_queue_release(void *);
309 uint16_t mlx5_tx_burst_secondary_setup(void *, struct rte_mbuf **, uint16_t);
313 uint16_t mlx5_tx_burst(void *, struct rte_mbuf **, uint16_t);
314 uint16_t mlx5_rx_burst(void *, struct rte_mbuf **, uint16_t);
315 uint16_t removed_tx_burst(void *, struct rte_mbuf **, uint16_t);
316 uint16_t removed_rx_burst(void *, struct rte_mbuf **, uint16_t);
320 struct ibv_mr *mlx5_mp2mr(struct ibv_pd *, struct rte_mempool *);
321 void txq_mp2mr_iter(struct rte_mempool *, void *);
322 uint32_t txq_mp2mr_reg(struct txq *, struct rte_mempool *, unsigned int);
324 #endif /* RTE_PMD_MLX5_RXTX_H_ */